INF4420

Phase locked loops

Spring 2012 Jrgen Andreas Michaelsen (jorgenam@ifi.uio.no)

Outline
"Linear" PLLs

Linear analysis (phase domain)

Charge pump PLLs

Delay locked loops (DLLs)

Applications


Introduction
Phase locked loops (PLLs) are versatile
building blocks found in a variety of applications

Frequency multiplication
Frequency synthesis
Clock deskew (PLL or DLL)
Clock recovery (from serial data)
Demodulation
...

Introduction
Feedback system for aligning (a fraction of) the
phase of the VCO clock with an (external)
reference clock. The VCO control voltage is
adjusted to achieve this.


Introduction
We will analyze the PLL in terms of phase. The
objective of the feedback loop, the PLL, is to
keep
ref
-
out
small and constant. In this state,
the PLL is said to be in lock.


This implies
ref
=
out
which is what we care
about in many applications.

"Linear" PLL
We will first analyze a PLL with a simple phase
detector (PD) first.

Phase
detector
Loop
filter


Phase detector
Phase is not directly observable. We have to
infer the phase difference from the output of the
oscillators.
An XOR gate can
be used as a
phase detector.

Phase detector

When
ref
and
out
is 90 out of phase, the XOR
output will have 50/50 duty cycle, and the
average output will therefore be V
dd
/ 2. If
ref

and
out
is at 0 or 180 phase difference, the
average output will be 0 or V
dd
respectively.


Phase detector

PLL with XOR PD
With the XOR PD, to generate the required V
ctl
,

ref
and
out
must be out of phase.


Loop dynamics
Linear analysis of the PLL in terms of phase, H
(s) =
out
(s) /
in
(s).

Second order TF
Natural
frequency
Damping
ratio
Generic second order
transfer function
applied to the PLL:



Loop dynamics
By choosing PLL parameters, K
VCO
, K
PD
, and

LF
, we can design
n
and , to obtain the
desired loop dynamics.
Magnitude response Step response

Large signal behaviour
An important point for PLLs is the large signal
behaviour when the system is not in lock. When
the PLL starts up,
ref
and
out
may be very
different. We must make sure that the system is
able to achieve lock. Another concern is
whether the PLL will lock to a harmonic instead.

The PLL with XOR based PD is not robust in
this case. In most applications, a so called
charge pump (CP) PLL is preferred.


Charge pump PLL
Tracks whether the reference edge or the VCO
clock edge comes first (for every period), and
adjusts the VCO control voltage accordingly to
keep the PLL in lock. When the PLL is in lock,
out and ref will be in phase.

Phase frequency
detector Loop filter
Charge
pump

Phase Frequency Detector
In the Charge Pump (CP) PLL, a more
elaborate PD with state is used, a Phase
Frequency Detector (PFD).


PDF/CP and loop filter
The PFD
generates
control
signals for
the CP to
ramp up or
down the
VCO
control
voltage.

PFD/CP gain
When the PLL is in lock, a small phase
difference between the VCO clock (out) and the
reference clock (ref) turns on the CP for a
fraction of the clock period injecting a charge
proportional to the phase error to the loop filter
every period. Looking at several periods, an
average current flows. K
PFD
is the combined
gain of the PFD and the CP:


CP loop filter
The loop filter is driven by I
avg
from the PFD/CP




In many cases, a second capacitor, C
2
, is
added in parallel to reduce glitches. C
2
is
usually chosen to be approximately 10 % of C
1

or less.

Transfer function
The open loop transfer function from
ref
to
out




The closed loop CP PLL transfer function


Transfer function
R gives rise to a zero at -1/(RC). It is required
as system would be unstable with R = 0.

Non-ideal effects in PLLs
PFD/CP will exhibit zero gain when the
phase difference is small because of finite
rise and fall times
Up/down current mismatch due to timing or
current source impedance
Jitter from power supply, coupling, electronic
noise, reference phase noise
...


Delay locked loop (DLL)
A DLL is similar to a PLL, but instead the delay
through a voltage controlled delay line (VCDL)
is locked.

Delay locked loop (DLL)
Noise (jitter) does not accumulate in the delay
line like it would in a VCO.

As there is no VCO, the order of the loop is one
less than the PLL. Stability and settling issues
are less prominent.

The DLL is not the same as a PLL and only
relevant for some PLL applications. DLLs are
usually preferred where applicable.


Frequency multiplication
Frequency multiplication is a common
application for PLLs. High speed clocks can be
generated from a stable and precise (but slow)
reference clock. N can be programmable.

Frequency demodulation
The VCO performs frequency modulation (FM).
The PLL can be used to find the inverse. The
VCO control voltage becomes the output.


Other PLL issues
We have used a continuous time analysis for
the PLL. However, the PFD samples the phase.
We approximated the PFD/CP output as an
average current.

When the deglitching capacitor, C
2
, is used, the
transfer function becomes third order. Using the
second order transfer function may not be
appropriate.

Resources
Gardner, Phaselock Techniques, Wiley, 2005

Fischette, Dennis Fischette's 1-Stop PLL
Center

Johns and Martin, Analog Integrated Circuit
Design, Wiley, 1997