Reg. No.

Question Paper Code: J7797

M.E. DEGREE EXAMINATION, JUNE 2010 Elective VLSI Design VL9261 ASIC DESIGN (Common to M.E. Applied Electronics) (Regulation 2009) Time : Three hours Answer ALL Questions

PART A (10 2 = 20 Marks) 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.

What are the different types of gate array based ASICs? Draw a circuit for a positive-enabled latch using transmission gates. List out the drawbacks of SRAM programming technology. What is metastability?

Distinguish between hard macro and soft macro. What is back annotation?

List out the objective of BIST. Define fault propagation.

Mention the objective of global routing.

What are major problems with LVS check? PART B (5 16 = 80 Marks) (6) (6) (4)

11.

(a)

(i) (ii)

Design a 4 bit carry look ahead adder. Discuss the working of Wallace tree multiplication algorithm.

(iii) Perform ( 4 ) (2) using Booths algorithm. Or (b)

1
(i)

Explain various types of programmable logic devices.

4
Or

0
(8) (10)
F = ( A B ) + (B C ) + D . Use Shannons

(ii)

Discuss the various steps involved in ASIC design flow with a neat flowchart. (8) Discuss in detail the Actel ACT logic module. Consider the function

12.

(a)

(i)

(ii)

expansion theorem to expand F with respect to B :

F = B F1 + B F2 .

1
(6)

Maximum : 100 Marks

(b)

(i)

Draw the transfer characteristics of an inverting buffer with a very high gain that has a switching threshold of 2.2 V and 300 mV hysteresis. If the center of the hysteresis shifts by 0.3 V and +0.4 V and the hysteresis varies from 260 mV to 350 mV calculate VIH(min )
and VIL (max ) . (8)

(ii) 13. (a) (i)

Write short notes on metal-metal antifuse. Compare Actel ACT1, Actel ACT2 programmable ASIC inter connect. and

Xilinx

Or (b) (i)

Explain in detail the Alteras MAX 9000 interconnect scheme and altera FLEX interconnect scheme. (10) Create a vectored instance of eight inverters inv0 through inv7. Write a netlist in internal and EDIF form and explain the contents. (6) Explain in detail the Boundary scan test.

(ii)

14.

(a)

(i) (ii)

1
2

(ii)

Write a note on low level programmable languages.

(b)

(i) (ii)

Explain steps involved in a PODEM algorithm with a suitable example. (8)

15.

(a)

(i)

Explain in detail the min-cut placement and eigenvalue placement algorithms. (10) Explain the steps involved in left edge algorithm for a two layer channel routing. (6) Or

(ii)

(b)

(i) (ii)

Write a detailed note on clock routing and power routing. Distinguish between global routing and detailed routing.

Explain in detail any two BIST architectures.

0
Or

Explain any two algorithms used for fault simulation.

0
(8) (XC 3000) (10) (6) (10) (6) (8) (10) (6)

J7797