ESc201:IntroductiontoElectronics

Combinational Circuit Design

Dr. K D K. V V. S Srivastava i t Dept. of Electrical Engineering IIT Kanpur

1

Design Flow
System Description

x y z system f

y z 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

f 0 1 0 1 0 1 0 1

Truth Table

0 0 0 0 1 1 1 1

Boolean Expression

f = x .y . z + x . y . z + x . y . z + x . y . z
Minimized Boolean Expression

f = x . z + x. z
x y y

This design approach becomes difficult to use

Gate Netlist

z x z

General Approach
Sub-Sub-system-1

S b Sub-system-1 t 1

System
Sub-system-2

Sub-system-3

There are certain sub-systems or blocks that are used quite often such as : 1. Decoders, Encoders 2 Multiplexers 2. 3. Adder/Subtractors, Multipliers 4. Comparators 5 Parity 5. P it Generators G t 6. ..

Decoders
In general maps a smaller number of inputs to a larger set of outputs
y0 A B 2-to-4 line decoder y1 y2 y3

A Y0 Y1 Y2 Y3 0 0 0 1 0 0 0 1 0 0 0 1
4

0 0 1 0 1 0 1 0 0 1 1 0

Example
M-1

M-1

M-2

2-to-4 decoder

M-2

M-3

M-3

M4 M-4

M4 M-4

Decoder with Enable Input

E B

2/4

A Y0 Y1 Y2 Y3 x 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1

y0 y1 y2

1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0

A B

y3

2/4

E B

y0 y1 y2

A Y0 Y1 Y2 Y3 x 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1
6

0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0

A B

y3

Decoder: gate Implementation

E 2/4 y0 y1 y2 A B y3

E B 0 x

A Y0 Y1 Y2 Y3 x 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1

1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0

Y0 =E.B.A ; Y1 =E.B.A ; Y2 =E.B.A ; Y3 =E.B.A

E A

E.B.A
Y0

E.B.A
Y1

E.B.A
Y2 B

E.B.A
Y3
7

A n to 2n decoder is a minterm generator

E

E .B.A
Y0

x 0 0 1 1

y min term 0 1 0 1 x.y x.y x.y x.y m0 m1 1 m2 m3

E .B.A
Y1

E .B.A
Y2 B

E .B.A
Y3

It can be used to implement any combinational circuit

B A f1 0 0 1 1 0 1 0 1 0 1 1 0

2/4 1 E y0 y1 y2

0 1 0 0 1
f

1 0

A B

y3

Implementation of a 3-variable function with a 3-to-8 decoder 1

C B A 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

f 1 0 1 0 1 0 0 0

0 0 0

1 0 0 0 0 0 0 0

Although it is easy to implement any combinational circuit with this method , it is often very inefficient in terms of gate utilization. Note that this method does not require any minimization.
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3/8 decoder using 2/4 decoders

E C B A y0 0 x x x 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 y1 y2 y3 y4 y5 y6 y7 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1

E E

2/4

y0 0 y1 1 y2 0 y3 0

0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

2/4

1 0

1 A 0 B
E 2/4

C 0

y4 0 y5 0 y6 0 y7 0

A B

E B 0 x

A Y0 Y1 Y2 Y3 x 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1
10

1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0

How many 2/4 decoders are required to implement a 4/16 decoder ?

Seven segment decoder

a f
g

a b f
g

a b f
g

a b f
g

e d

e d

e d

e d

5 5 5 5 5

D C B A 7-segment decoder (abcdefg)

5
f

0
g
11

Seven segment decoder

a f
g

D C B A 7-segment g decoder (abcdefg)

e d

output: a

BA DC 00 00 1 01 11 10 0 0 1

01 0 1 1 1

11 1 1 0 0

10 1 0 0 0

Please determine the simplified POS

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D C B A BL 7-segment decoder (abcdefg)

a = (D + B ) (C + A) (D + C + B + A )

a = DB CA D C B A

( )( )(

7449 BCD to seven segment decoder

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Encoders
An encoder performs the inverse operation of a decoder.
d3 d2 d1 d0 B A 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1

4/2 0 1 2 3 B A

0 0 0 1

d1 d0 d3d2 00 00 01 11 10 1 0

01 0

11

10 1

d1 d 0 d3d2 00 00 01 11 10 1 1

01 0

11

10 0

B = d1 d 0

A = d 2 d 0 Vacants are dont care

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Multiplexers
I0 I1

2:1 mux S

S
y

y I0 I1

0 1

I0

I0 1 I0 0 0
Y0

I1

0
15

I0 I1 I2 I3

00 01 4:1 10 mux 11
S0 S1

S1 S 0
y

y I0 I1 I2 I3

0 0 0 1 1 0 1 1
I0

S1 S0

I1

I2

I3

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Implementing Boolean expressions using Multiplexers

x2 ? ?

0 y 1

y = x1 x2 + x1 x2

x2

x1

x1 x2
0 0 1 1 0 1 0 1

y
0 1 1 0 y = x2 when x1 = 1 y = x2 when x1 = 0

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F ( x, y, z ) = (1, 2, 6, 7)
A 3 variable function can be implemented with a 4:1 mux with 2 select lines

x
0 x 1 x

z F
0 F = 0 when yz = 00 0 1 F = x when yz =01 0 1 F = 1 when yz = 10 1 0 F = x when yz = 11 1

00 01 10 11
y z

0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

1 0 1 0 1 0 1

Mux is more efficient way of implementing combinational circuits as compared to decoders. 18

Mux. expansion
E I0 I1 0 1 S y

S1 S0
E S 0 x y 0 I0 I1

y I0 I1 I2 I3

0 0 0 1 1 0 1 1

1 0 1 1

E 0 1 S0 1
I1

E 0 1 S0
0

I1

I0 I1

I2 I3

S1
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Mux. expansion
E I0 I1 0 1 S y

S1 S0
E S 0 x y 0 I0 I1

y I0 I1 I2 I3

0 0 0 1 1 0 1 1

1 0 1 1

E 0 1 S0
0

E 0 1
1 I3

I3

I0 I1

I2 I3

S0

S1
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DeMultiplexer
u-1 u-11
u-1 u-11

u-2

u-22

u-2 Mux

u-22

Demux
u-33

u-3

u-33

u-3

u-4

u-44

u-4

u-44

S1

S0 0 1 0 1

y0 D 0 0 0

y1 0 D 0 0

y2 0 0 D 0

y3 0 0 0 D
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Data S1 S0

0 1 2 3

0 0 1 1

Demultiplexer is very much like a decoder

E 2/4 y0 y1 y2 A B
E B

Data S1 S0

Dmux

0 1 2 3

y3

S1 S0 y0 y1 y2 y3 0 0 0 1 1 0 1 1
Data S0

A Y0 Y1 Y2 Y3 x 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1
Y0

I0 0 0 0 0 I1 0 0 0 0 I2 0 0 0 0 I3
E

1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0
Data
Y0
A

1 1

0
Y1

Y1

0
S1

Y2 B

Y2

0
Y3
22

Y3

Comparator

A = A3 A2 A1 A0 xi = Ai .Bi + Ai .Bi

for i = 0,1,2,3 0123

B = B3 B2 B1 B0

where xi = 1 only if the pair of bits in position i are equal (i.e., (i e if both are 1 or both are: 0) 0).

( A = B ) = x3 x2 x1 x0

all xi variable must be equal to 1

( A > B ) = A3 B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0 ( A < B ) = A3 B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0
23

( A < B ) = A3 B3 + x3 A2 B2
+ x3 x2 A1 B1 + x3 x2 x1 A0 B0

( A > B ) = A3 B3 + x3 A2 B2
+ x3 x2 A1 B1 + x3 x2 x1 A0 B0

( A = B ) = x3 x2 x1 x0

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Adder
S

a b 0 0 0 1

a b

0 0 1 0 1 0 0 1

Half Adder

1 0 1 1

S = a.b + a.b ; C = a.b

a b Cin S Cout

1 111 110 --------1101

0 0 0 0 0 0 0 1 1 0 0 1 0 1 0

Cout

F ll Add Full Adder

Cin

0 1 1 0 1 1 0 0 1 0 1 0 1 0 1

1 1 0 0 1 1 1 1 1 1

S = a.b.cin + a.b.cin + a.b.cin + a.b.cin ; Cout = a.b.cin + a.b.cin + a.b.cin + a.b.cin

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S = a.b.cin + a.b.cin + a.b.cin + a.b.cin

Cout = a.b.Cin + a.b.Cin + a.b.Cin + a.b.Cin

S = Cin ( a b)
a b Cin S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1

Cout = Cin (a.b + a.b) + a.b = Cin .(a b) + a.b

a b

ab

Cin (a b)
S

1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

Cin .(a b) a.b

Cout Cin

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4-bit Adder
S(0:3)

A 3A 2A 1A 0 B 3B 2B 1B 0 S 3S 2S 1S 0 0000 0000 0000 0001 0000 0000 0001 0001

Cout 1 0 0

C3 C2 C1

A 3 A 2 A 1A 0 B 3 B 2 B 1B 0
C 4 S 3 S 2 S 1S 0

Cout

4-bit adder

0001

A(0:3)

B(0:3)

S3 C4
FA

S2 C3
FA

S1 C2
FA

S0 C1
FA

A3

B3

A2

B2

A1

B1

A0

B0

27

Subtraction
A - B = A + 2s complement of B A - B = A + 1s complement of B+1

A B = A + B +1

FA

FA

FA

FA

B3
A3 A2

B2
A1

B1
A0

B0

1 B3 B2 B1 B0

B0 1 = B0 .1 + B0 .1 = B0
One needs add a circuit for predicting errors resulting from overflow
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Adder/Subtractor
FA FA FA FA
1

FA

FA

FA

FA

1 0

A3

A2

A1

A0 1

A3

B3

A2

B2

A1

B1

A0

B0
B3 B2 B1 B0

FA

FA

FA

FA

A3

A2

A1

A0 M=1

B3

B2

B1

B0

B0 0 = B0 .0 0 + B0 .0 0 = B0 B0 1 = B0 .1 + B0 .1 = B0

M = 0 for f Adder dd M=1

29 for Subtractor