8255A/8255A-5 PROGRAMMABLE PERIPHERAL INTERFACE

M C S - 8 5 C o m p a t i b l e 8255A-5 24 Programmable I/O Pins Completely T T L Compatible Fully Compatible with Intel M i c r o p r o c e s s o r Families Improved Timing Characteristics Direct Bit Set/Beset Capability Easing Control Application Interface Reduces System Package Count Improved DC Driving Capability Available in EXPRESS Standard Temperature Range Extended Temperature Range 40 Pin DIP Package or 44 Lead PLCC
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Tne Intel 5255A is a general purpose programmable I/O device designed for use with Intel microprocessors. It has 24 I/O pins which may be individually programmed in 2 groups of 12 and used m 3 major mooes of operation. In the first mode (MODE 0), each group of 12 I/O pins may be programmed in sets of 4 to be input or output, in MODE 1, the second mode, each group may be programmed to have 8 lines o< input or output Of the remaining 4 pins. 3 are used for handshaking and interrupt control signals. The third mooe of operation (MODE 2) is a bidirectional bus mode which uses 8 lines for a bidirectional bos, and 5 fines, borrowing one from the other group, tor handshaking.

Z31306-2

Figure 2. Pin Configuration

Figure 1. B255A Block Diagram

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8255A FUNCTIONAL DESCRIPTION General

The 8255A is a programmable peripheral interlace (PPI) device designed for use in Intel microcomputer systems. Its function is that of a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. The functional configuration of the 8255A is programmed by the system software so that normally no external logic is necessary to interlace peripheral devices or structures.

CPU Addres; and Conlrol busses and in turn, issues commands to bom of the Control Groups.

<CS)
Chip Select. A "low" on this inout pin enables the communication berween the 8255A and the CPU.

(RD)
Read. A "low" on this input pin enables the S255A to send the data or status information to the CPU or, the data bus. In essence, it allows the CPU to read from" the 8255A.

Data Bus Buffer

This 3-state bidirectional 8-bit butter is used to interface the 8255A to the system data bus. Data is transmitted or received by the butter upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer.

(WR)
Write. A "low" on this input pin enables the CPU to write data or control words into the 825 5A.

(An and A-) .Read/Write and Control Logic

The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words, ft accepts inputs from the Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word registers. They are normally connected to the least significant bits of the address bus (Ao and Aj).

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Figure 3. asSSA Block Diagram Showing Data Bus Buffer and Read/Writs Control Loqic Function*.

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8255A BASIC OPERATION

A, 0 AQ RD WR CS input O p f * t t o n (READ) 0
1

*
1

0 0

Port A Data Bus Port B Oata Bus Port C Data Bus Output Operation (WHITE)

H'.ii ol the Con'.i.il bloi ks (Grouy A and Group 8) -nicopts "commands" Irom the R:.id.'Wf*rtc Co*M'Ol -00>c. receives "control words" 'torn the internal data bus and tssuf^s !he proper commands to its associated ports. Control Group APon A and Port C upper (C7-C4) Control Group BPort 8 and Port C tower (C3-C0) The Control Word Register can Only be written into. No Read operation of the Control Word Register is allowed.

x
1

o c

0 1 0 1 X 1 X 1 1

00

Data Bus Port A Data Bus PortB Data Bus PortC Data Bus Control Disable Function

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1

o o x
1 1

o
1 0

Ports A, B, and C
The 82S5A contains three 8-bit ports (A, B, and C). All can be configured n a wide variety of functional characteristics by the system software but each has its own special features or "personaSty" to further enhance the power and flexibility of the 8255A, Port A. One 8-bit data output latch/buffer and one 8-bit data input latch. Port B. One 8-bit data input/output latch/buffer and one 8-bit data input buffer. Port C. One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-brt latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and 8.

X 1 X

X 0 1

Data Bus 3-State Illegal Condition Data Bus 3-State

(RESET)
Reset. A "high" on this input clears the control register and all ports (A, B. C) are set to the input mode.

Group A and Group B Controls

The functional configuration of each port is programmed by the systems software. In essence, the CPU "outputs" a control word to the 8255A. The control word contains information such as "mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 8255A.

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Figure 4.8225A Block Diagram Showing Group A and Group B Control Functions Pin Names
1

Pin Configuration mZ
B [
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D7-D0 RESET CS

Data Bus (Bi-Directional) Reset input Chip Select Read Input Write Input Port Address Port A (BIT) Port B (BIT) Port C (BIT) + 5 Volts 0 Volts

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231306-5

8255A OPERATIONAL DESCRIPTION Mode Selection

There are three basic mooes of operation thai can be selected by the system software

vtrw. Basic iiou". Output Mode lStrobed Inout/Outpu! Mode 2St-Oirectwnal Bus When trie reset input goes "high'" all ports will be set to the input mode (i.e.. all 24 lines will be in the high impedance state). After the reset is removed the 8255A can remain in the input mode with no additional initialization required. During the execution of the systemprogram any of the other modes may be selected using a single output instruction. This allows a single 8255A to service a variety of peripheral devices with a simple software maintenance routine. The modes for Port A and Port B can be separately defined, while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status flip-flops, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be "tailored" to almost any I/O structure. For instance; Group B can be programmed in Mode 0 to monitor simple switch closings or display computational results. Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an internjpt-driven basis.
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231306-7

Figure 6. Mode Definition Format The mode definitions and posstole mode combinations may seem confusing at first but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the 82S5A has taken into account things such as efficient PC board layout, control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins.

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Single Bit Set/Reset Feature

Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction. This feature reduces software requirements in Control-based applications.

231306-6

Figure S. Basic Mode Definitions >nd Bus Interface

8255A/8255A-5

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. 0.

This lunction allows the Programmer to aisallow or allow a specific I/O device to interrupt the CPU without atfeciing any other device in the interrupt structure.
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L
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INTE flip-ltop definition: (BIT-SET)INTE is setInterrupt enable

wmip

(BIT-RESET)INTE is RESETInterrupt disable NOTE: All Mask flip-flops are automatically reset during mode selection and device Reset.

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Operating Modes
231306-8

Figure 7. Bit Set/Reset Format When Port C is being used as status/control for Port A or B, these bits can be set or reset by using the Bit Set/Reset operation just as it they were data output ports.

MODE 0 (Basic Input/Output). This functional configuration provides simple input and output operations for each of the three ports. No "handshaking" is required, data is simply written to or read from a specified port Mode 0 Basic Functional Definitions: Two 8-bit ports and two 4-bit ports. Any port can be input or output Outputs are latched. Inputs are not latched. 16 different Input/Output configurations are possible in this Mode.

Interrupt Control Functions

When the 8255A is programmed to operate in mode 1 or mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from port C, can be inhibited or enabled by setting or resetting the associated INTE flip-flop, using the bit set/reset (unction of port C. MODE 0 (BASIC INPUT)

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MODE 0 P O R T DEFINITION A D4 0 0 0 0 0 0 0 0 D3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D, 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B Group A Group B

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0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

PortA OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT

PortC (Upper) OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT INPUT

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0 1 2 3 4 S 6 7

PortB
OUTPUT OUTPUT INPUT INPUT OUTPUT OUTPUT INPUT INPUT OUTPUT OUTPUT INPUT INPUT OUTPUT OUTPUT INPUT INPUT

PortC (Lower) OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT

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9 10 11 12 13 14 15

8255A/S255A-S

MODE CONFIGURATIONS
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231308-16

W A V E F O R M S (Continued) MODE 1 (STROBED INPUT)

MODE 1 (STROBED OUTPUT) ~ \

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NOTE: Any sequence where ?7R occurs before ACK and STB occurs before RB is permissible.
(INTR IBF K S S K 5TB RD + OSF B A S K 7KX WR)

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WRrTE TIMING

READ TIMING

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IN

National Semiconductor
NMC27C64 65,536-Bit (8k x 8) UV Erasable CMOS PROM
General Description
The NMCZ7C64 is a high-speed S4k UV erasable and electrically reprogrammable CMOS EPROM. ideally suited (or applications where fast turnaround, pattern experimentation and low power consumption are important requirements The NMCZ7C64 is designed to operate with a single + SV power supply with 5% or * tO*A tolerance. The CMOS design allows the part to operate over Extended and Military Temperature Ranges. The HMC27C6* is packaged in a 23-pin dual-in-line package with transparentfid.The transparent lid allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new partem can then be written electrically into the device by following the programming procedure. This EPROM is fabricated with National's proprietary, time proven CMOS double-poiy silicon gate technology which cbmtxries high performance and high density withtowpower consumption and excellent reliability.

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Features
Clocked sense amos tor last access time down to 150 ns Low CMOS power consumption Active Power: 55 mW max Standby Power 0.55 mW max Performance compatible to NSC800 CMOS microprocessor Single 5V power supply extended temperature range (NMC27C64QE], -40*C to +85*C. and miktary temperature range (NMC27C640M). -55"C to + T25"C, available Pin compatible with NMOS Wk EPflOMs Fast and reliable programming at Static operationno clocks required TTL. CMOS compatible inputs/outputs at THI-STATE* output Optimum EPROM lor total CMOS systems Manufacturer's identification code for automatic programming control

Block Diagram
MM. OUTPUTS 0 H ) 7

KB

OUTPUT ENAIU MO CHIP CauiE LOGIC

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OUTPUT IUTFERS

Pin Names A0-A12 CS | Addresses Chio Enable Output Enable Outputs Program No Connect

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OS O0-O7 PGM

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Functional Decagram
Program Inhibit 27C12B 2 7 C 3 2 2 7 C 1 S puts I M Z7256 VPP A12 A7 A6 AS
A4

O r o< O

2
c3 C A15 A12 A7 A6 A5 A4 A3 A2 Al AO

27128

2732

2716 I
1

NMC27C640 Ou**-tn-Ur> Package

I7C16 2716

2 7 C 3 2 27C128 27C2S8 27CS12 2732 2712J VCC 272S6 VCC A14 A13 AS A9 All 27S12 VCC A14 A13 AS A9 All OE/Vpf AIO

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A12 A7 A6 AS M A3 A2 Al AO A7 A6 AS
A4

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AS A9 VCC AS A9 A11 OS/Vpp AIO

P5J3
A13 AS AS A11

A7 A6 A5 A4 A3 A2 Al AO

til

VPP

A3 A2 A1 AO

A3 A2 A1 AO Oo 0, 02 GNO

110
A) -

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AIO

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O7

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A10

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07

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07

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07 06

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o l r . S o ( O T W > * EPflOU pn<sngaiibora* ttom > Boca uS^ctrt 10 NUCZ7C64 pu. Order Number NMC27C64Q See NS Package Number J28AQ Commercial Temp Range (0*C to + 70*C)

Parameter/Order Number NMC27C64015

- -.Access Time (ns) ISO

v c c = sv +10% Parameter/Order Number NMC27C64O150 NMC27C64O2O0 NMC27C64O250 NMC27C64O300 A c c e s s Time (ns) 150 200 250 300

Extended Temp Range ( - 4 0 " C to + 5 " C ) Vcc - SV 1 0 % Parameter/Order Number NMC27C64QE150 NMC27C840e20a Access Time (ns) ISO 200

Military Temp Range ( - 5 T C to 4- 12S*C)

Vcc - SV 1 0 %
Parameter/Order Number NMC27C64OM200 NMC27C64OM250 Access Time (ns) 20C 25C

Absolute Maximum Ratings (Note D

It Mllltary/Aeroepace apecMled devices are required, contact the National Semiconductor Sales Otfle Otatrlbutora (or availability and specliication*. Temperature Under Bias Commercial - 10*C'.o - 3C*~ Military and Extended Operating T>nc. Range Storage Temperature - ai"C to * 15CC All Input Voltages except A9 with Respect to Ground (Note 10) + 6.5V to - 0.6V All Output Voltages with Respect to Ground (Note 10) V C c ! 1.0V to GND - 0.6V Vpp Supply Voltage and A9 with Respect to Ground During Programming + 14.0V to -0.6V Vcc SuPCY Voltage with Respect to Ground Power Dissipation Lead Temperature (Soldenng. 10 s* SO flating (Mil Spec 883C. Method 30t5.2) - " I V to-0.6V ' ?'" J-V' . iCOOV

Operating Conditions (Note 7)

Temperature Range NMC27C54Q1 J, Q150. 200.250. 300 C*C to + 7<TC NMC27C64QE200 - 4C"C to + SS^C NMC27C64QM200. M250 - 55'C to + 125"C Vcc Power Supply + 5V i 10% except NMC27C64Q15 ^SVrSS

READ OPERATION DC Electrical Characteristics

Symbol | Parameter Input Load Current Output Leakage Current V c c Current (Active) TTL Inputs V c c Current (Active) CMOS Inputs V C c Current (Standby) TTL Inputs 1 V CCCurrent (Standby) ' C M O S Inputs Vpp Load Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage | lOL 2 J mA
IQH

Conditions
V I N -

Ml,,

Typ

Mai 10 10

Units jiA
^LA

ki Ko
lect (Note 9) 1CC2 (Note 9) taS8!

Vcc or GND

VouT-VccorGND.Cc-VIH C 5 - V,j_, f 5 MHz | 5

Inputs - V| H orV|i_, I/O - 0 mA Cc - GNO. f - 5 MHz Inputs - Vcc or GND. I / O = 0 mA E"-V,H

20

mA

10

mA

0.1

mA

teSK

C 5 - Vcc
VPP

0.5

100 10

|iA (A V !
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ipp VlL V|M VOL1 V 0 H1 V0L2

V

Vcc -0.1 2.0

0.8 Vcc + 1

1
2.4

0.45

- 4 0 0 uA

1
0.1 I

V
V V

IOL-0MA
I Q H " 0 MA j Vcc ~ -1

1
I

OH2

AC Electrical Characteristics
NMC27CS4Q Symbol Parameter Conditions 1S,150,E150 Min 'ACC irz Address to Output Delay Max 150 !50 60 0 60 6C 0 0 200, 2 0 0 , M200 Mln Max 200 250. U2S0 Win Max 250 250 70 0 60 60 0 0 300 Mln Max 300 300 150 j | 130 130 | ns ns ns ns ns Units

C"S - OS - V. P C M - V|H 5S - v,,.. P S M - v1H 5= - v, L . P 5 M - v,H 55 - V|L, P 5 M - V|H

5 to Output Delay 5 5 to Output Delay 0"? High to Output Fioat 5 High to Output Float

I I
i

200 60
60 60

k=E-

131
bh

o r = v!L. Fon - v,H

I Output Hold trom Addresses, i 55 = 5 5 V,L I 55 or 0 5 . Whichever I P"5M Vj

DATA TRANSISTOR BIPOLAR

TIPE
ACI26 AC127 AC12B AC132 AC187 AC 188 A0161 A0162 AFU6 ASZ15 ASZ18 BC107 BC108 BC109 BC109C BC157 BC158 BC159 BC177 BC178 BC179 BC182IU BC183(L| BC184(L| BC207 BC208 BC209 BC327 BC328 BC337 BC547 BC548 BC549 BC549C BC5S7 BC5S8 BC559 BC63S BC636 BC639 BC640 BCV71 BD139 BD140 B0262 B0263 B0266A 80681 BD682 BF11S BF173 BFI76 BF179 BF180 BF184 BF185 BF199 BFY50 BUX80 DS547 DS548 0S549 OS557 OS55B

BENTUK
TO-1 TO-1 TO-1 TO-1 TO-1 TO-1 PT1 PT1 TO-7 TO-3 TO-3 TO-1 8 TO-1 8 TO-18 TO-18 SOT-25 SOT-25 SOT-25 TO-18 TO-18 TO-18 SOT-30 |TO-92/74| SOT-30 (TO-92/741 SOT-30 TO-106 TO-106 TO-106 TO-92 (VAR| TO-92 [VAR| TO-92 IVAR} SOT-30 SOT-30 SOT-30 SOT-30 TO-92 !VAR| TO-92 |VAR| TO-92 (VAR| TO-92|74| TO-92|74| TO-92(74| TO-92(74| TO-18 TO-1 2 6 TO-1 2 6 TO-1 2 6 TO-1 2 6 TO-220 TO-126 TO-1 2 6 TO-72|28| TO-72|28| TO-39 TO-39 TO-72I25I TO-72|28| TO-72|28| TO-92 (VAR|2 TO-39 TO-3 TO-92 IVAR| TO-92 IVAR) TO-92 IVAR| TO-92 |VAR| TO-92 |VAR| TO-3 TO-220 TO-220 TO-3 TO-3 152 152-01 TO-3 TO-1 GT-3 GT-3 GT-3 GT-6 TO-1

POL MAT FG NG PG PG NG PG NG PG PG PG PG NS NS NS NS PS PS PS PS PS PS NS NS NS NS NS NS PS PS NS NS NS NS NS PS PS PS NS PS NS PS PS NS PS PS NS PS NS PS NS NS NS NS NS NS NS NS NS NS NS NS NS PS PS

Vc* 12 16 16 12 15 15 20 20 15 60 32 45 20 20 20 45 25 20 45 25 20 50 30 30 45 20 20 45 25 45 45 30 30 30 45 30 30 45 45 80 80 45 80 80 60 60 80 100 100 30 25 115 115 20 20 20 25

Vcb 32 32 32 32 25 25 32 32 32 100 100

IC RlA 100 500 1000 200 1000 1000 3000 3000 10 10A 10A 100 100 100 100 100 100 100 100 100 100 200 200 200 100 100 110 1000 500 1000

Vcn

& mA

Ht. 140 105 60-175 115 100-500 100-500 80-320 80-320 150 20-55 30110 110-450 110-800 200-800 420-800 75-260 75-500 125-500 75-260 75-500 125-500 100-480 100-850 250-850 110-220 110-800 200-800 100-600 100-600 100-600 110-800 110-800 200-800 420-800 110-330 75 125-600

s- tc
mA 2 50 300 50 300 300 500 1 1A 1A 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 100 100 100 2 2 2 2 2 2 2 150 150 150 150 10 150 150 1.5A 1.5A 3A 4A 1.5A 1 7 30 20 2 1 1 7 150

Ft 6 MHl 17 15 1 1.3 1 1 002 0015 75 02 022 300 300 300 300 150 150 150 150 150 ISO 150 150 150 150 150 150 100 100 200 300 300 300 300 150 150 150 130 130 130 SO 250 250 75 7 7 7 1 1

IC mA 10 10 10 10 10 10 300 300 1 1A 1A 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

Ptot mW 500 340 1W 216 1W 220 4W 6W

PENERAPAN
Audio driver Audio 0 / P Audio 0 / P Audio 0 / P Audio 0 / P Audio 0 / P Audio Amp. Audio A m p . H.F. A m p H.C. Sw H.C. S w S S Amp. S.S. A m p Low Noise S.S. Amp. Low Noise High G u n S.S. Amp. S S. Amp. S S Amp S.S Amp. S.S. Amp. S.S. A m p . S.S. Amp.

06 035 08 0.6 06 04 04 0.4 0.2 0.2 0.2 02 025 025 025 0 25 025 025 0 25 025 025 0.25 025 0.25 0.7 07 07 0 0 0 0 6 6 6 6

1A 200 1A 1A 1A 1A 10A 10A 100 100 100 100 100 100 100 100 100 100 10 10 10 10 10 10 500 500 500 100 100 100 100

soo

S O
30W 30W 300 300 300 300 300 300 300 300 300 300 300 300 300 300 200 200 800 500

so
30 30 30 50 30 25 50 30 25 60 45 45 50 25 25

S.S. Amp
Low S.S. S.S. Low 0/P Noise High Gain Amp. Amp Noise High Gem

G P. Amp. Sw. 0/P S.S. S.S. Low Low G.P. Amp. Amp. Noise Smell Sig Noise High Gain Small Sig.

10 10 10 10 10

800 500 500 500 500 500 500 500

50 30 30 30 50 30 30 45 45 100 100 45 100 100 60 80 80 100 100 SO 40 185 250 30 30 30

100 100

loo
100 100 100 100 1A 1A 1A 1A 200 1A 1A 4A 4A 8A 4A 4A 30 25 50 SO 20 30 30 25 1A 10A 100 100 100 100 100 15A 10A 10A 20A 20A 2A 2A 35A 10 10 SO 50 250 300

G P. Small Sig. G.P. Small Sig. Audio 0 / P Audio 0 / P Audio 0 / P Audio 0 / P G.P. G.P 0 / P G P 0/P High Gain Darl. 0 / P High Gain Oarl. 0 / P High Gain Darl. 0 / P Darlington 0 / P Darlington 0 / P V.H.F. Amp. T.V. I F . Amp. T V Video Amp. T V . Video Amp. U.H.F. A m p . H.F. Amp. H.F. Amp. H.F Amp. G.P. Deflection. High current Sw. G.P. Power S S Amp. S.S. Amp. Low Noise Small Sig S.S. Amp. S.S. Amp.

0.5 0.5 0.5 05 0.5 05 0.5 25 2.5 2

soo

500 500 500 50 500 500 1 5A 1 5A 3A

40-250 40-250 40-160 40-160 100-400 40-160 40-160 750 750 750 500 750 45-165 92 20 20 13 75-750 34-140 37. 30

500 500

50 500 500 1.5A 1.SA

230 550
120 120 675 300 220 550 60 8 300 300 300 ISO 150 4 2 2 2 2 70 70 03 75 3 05 06 0 35 01

1 5 10 10 2 1 1

1W 1W 1W 1W 350 8W 8W 36W 36W 60W 40W 40W 145 230 600 600 150 145 145 500 800 100W SOO 500 500 300 300

35
400 45 30 30 45 25

80

0.2 1.5 06 0.6 06 025 025 11

150 5A 100 100 100 100 100 4A

50

50 30 30 50 30

110-800 110-800 200-800 75-260 75-500

2 2 2 2 2 4A 4A 4A

10 10 10 10 10

MJ2955 MJE2955T MJE3055T MJ15003 MJ15004 MU9660 MU9661 OC26 0C44N 0C45 0C70 0C71 0C72 OC74N

PS PS NS NS PS PS PS PG PG PG PG PG PG PG

60 60 60 140 140 30 30 30 5 5 10 10 16 10

70 70 70 140 140 40 40 50 15 15 30 30 32 20

04 04 07

1.5A 1 5A 3A

06

300

20-70 20-100 20-100 25-150 25-150 80-400 80-400 30-100 45-225 25-125 30 30-75 45-120 60-150

500 500 SOO

350 350 1A 1 1 5 3 10 50

250 250 500 1

115W 75W 75W 2SOW .250W 1W 1W 12W 85 85 125 125 165 550

High Power 0 / P G P. Power G.P Power Hi power 0 / P Hi Power 0 / P 0/P 0/P G P 0/P R F. Amp. R.F. Amp. G P. Amp. G.P. A m p Audio 0 / P Audio 0 / P

94

FAKULTAS TEKNIK JURUSAN TEKNIK ELEKTRO UNIVERSITAS KRISTEN PETRA S U R A B A Y A tJSULAN TUGAS AKHIR Dosen Perabirabing Nama Mahasiswa Bidang Studi Nirm Mahasiswa Nrp Mahasiswa Judul Tugas Akhir Ir. Herlianto Tenggara Hendri Sutanto Elektronika 92.7.002.31073.01352 23492070 PERENCANAAN DAN PEMBUATAN EMPAT CHANNEL DENGAN JANGKA SATU MINGGU YANG DAPAT DELAPAN ACARA MENGGDNAKAN KONTROLLER 68HC11 TIMER WAKTU DIISI MIKRO

Larapiran Tugas Akhir, meliputi : 1. 2. 3. 4. 5. 6. 7. 8. Latar Belakang Pemilihan Judul Tujuan/Sasaran Ruang Lingkup Percibaliasan Metods Yang Digunakan Mata Kuliah Penunjang Uraian Singkat Jadwal Kegiatan Relevansi Surabaya, 31 Juli 1997 Mengetahui, Kepala Bidang Studi Dosen Pembimbing

(Ir. Herlianto Tenggara)

(Ir. Herlianto Tenggara)

Ketua Jurusan

( I r . Hanny H. Tuinbelaka, M.Sc.)

PERENCANAAN DAN FEMBUATAN TIMER EMPAI CHANNEL DENGAN JANGKA WAKTU SATU MINGGU YANG OAPAT DIISI SEBANYAK DELAPAN ACARA MENGGUNAKAN MIKROKONTROLLER 68HC11 1. LATAR BELAKANG PEMILIHAN JUDUL

Di

dalam

kehidupan

sehari-hari

banyak

sekali

peralatan yang memerlukan suatu pengontrolan secara otomatis baik mengenai kapan peralatan tersebut harus 'on' dan kapan peralatan tersebut harus 'off. Namun biasanya peralatan yang mempunyai kemampuan ini berharga raahal. Untuk itu alangkah baiknya bila kemampuan ini dapat kita buat sendiri dengan berbasiskan pada suatu mikrokontroller, sehingga hasil yang ingin dicapai lebih bagus dan akurat serta relatif lebih murah. Timer dihubungkan dengan berbasiskan dengan peralatan mikrokontroller yang akan dapat

dikontrol,

dimana waktu saat 'on' raaupun 'off melalui mikrokontroller tersebut. Hal ini dapat menghemat

dapat diprogram

karena peralatan yang

tidak mempunyai kemampuan seperti diatas tidak perlu diganti, hanya perlu ditambahkan suatu interfacing ke mikrokontroller yang dibuat sehingga peralatan ini

sudah dapat dikontrol layaknya suatu peralatan yang otomatis.

2. TUJUAN/SASARAN

Tujuan pembuatan Tugas Akhir merencanakan dan membuat suatu

ini adalah untuk programmable timer

empat channel dengan jangka waktu seminggu yang dapat diisi sebanyak yang delapan dapat acara berbasiskan dengan maupun mikro-

kontroller yang ingin

dihubungkan waktu
x

peralatan
y

dikontrol

on'

off-nya

secara otomatis.

3. RUANG LINGKUP PEMBAHASAN

Ruang

lingkup pembahasan dalam pembuatan Tugas

Akhir ini meliputi : perencanaan dan pembuatan perangkat mikrokontroller, pembuatan interfacing penghubung ke peralatan yang akan dikontrol, dan pembuatan

perangkat lunak.

4. METODE YANG DIGUNAKAN

Metode yang digunakan dalam pembuatan Tugas Akhir ini adalah : Studi Pustaka Pengumpulan Data

 Perencanaan Alat Pembuatan Alat Pengujian Alat Evaluasi Pembuatan Naskah TA

5. MATA KULIAH PENUNJANG

Mata kuliah penunjang dalam pembuatan Tugas Akhir ini adalah : Mikroprossessor Instrumentasi Elektronika

Elektronika Rangkaian Logika Dan Digital

6. URAIAN SINGKAT

Blok diagram

rangkaian

timer yang

akan dibuat

adalah sebagai berikut :

LCO DISPLAY DOT MftTRIX

3<~>
DATA CONTROL

DRIVER

CHANNEL 1
MCU 6BHC11 PR 8255

CHANNEL 2 CHANNEL 3 CHANNEL 4

>

KEYPAD

Sebagai referensi sinyal clock: diambil dari timer internal dalaiu mikrokontroller. Yang akan ditarapilkan pada bagian display adalah waktu saat ini (sebagai

tarapilan default) . LalLi user dapat meraprogram timer pada salah satu maupun keseluruhan 'off-nya channel dimana baik hasil

mengenai

waktu

'on' maupun

program ini direferensikan pada waktu default yang ada dan bila hasilnya sama raaka channel yang bersesuaian akan 'on' ataupun 'off. Interfacing dengan peralatan diatur melalui relay beserta rangkaian driver-nya.

Input program dikendalikan melalui bagian keypad. Dan hasil tampilan direalisasi dengan LCD dot matrix 16x1.

JADWAL KEGIATAN

KEGIATAN STUDI LITERATUR PENGUMPULAN DATA PERENCANAAN ALAT PEMBUATAN ALAT PENGUJIAN ALAT EVALUASI PEMBUATAN NASKAH TA
RELEVANSI

I
***

II
** * *** ** * ***

BULAN KE III IV
*** ***

VI

*** ***

*** ** *
*
*

* *

Programmable waktu

timer empat

channel dengan

jangka

seminggu yang berbasiskan mikrokontroller ini

dapat digunakan pada peralatan yang tidak mempunyai kontrol secara otomatis namun hendak dijalankan secara otomatis setara otomatis sehingga dengan dapat mempunyai yang kemampuan yang

peralatan

mempunyai

kontrol

built-in di dalam-nya. Untuk keperluan yang

luas maka channel dapat diperbanyak lagi sesuai dengan keinginan kita.