ABSTRACT

The project entitled Design and implementation of a Rail to Rail Class B Buffer focuses on design of class B output buffer forLCD column driver. Output Buffers are the essential part of the LCD column driver that drives the large capacitive column lines in the LCD panel along with the other drivers. This work deals with the design of a Class B buffer. The Class B buffer designed is mainly used in LCD column driver. The class B buffer provides a rail to swing (VDD to VSS) and has fast settling time. Then settling time of the buffer should the less than the scanning period of the row driver. Class B Buffer has been designed in TSMC 180nm CMOS process technology. The buffer designed does not contain any comparators thus consumes less area and has fast settling time. The project includes CMOS circuit design and simulation. Designed Buffer has a supply voltage of 2V and settling time of 1.41s for 100pF load capacitance.

TABLE OF CONTENTS

Abstract

Chapter 1: Introduction

1.1 General Introduction 1.2 Objective 1.3 Motivation 1.4 Organisation of the Report

1 4 4 5

Chapter 2: Literature Survey

Chapter 3: Overview of the Project

10

3.1 LCD Display 3.1.1 System Level Block Diagram 3.2 LCD Column Driver

10 10 12

Chapter 4: Design

14

4.1 Class B Buffer 4.2 Circuit Diagram 4.3 Circuit of Class B Buffer Using DMC

14 15 21

Chapter 5: Implementation

28

5.1 Circuit Design using H-Spice 5.1.1 Transistor Design 5.1.2 Capacitor Design
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28 29 30

5.1.3 Voltage and Current sources 5.1.4 Analysis 5.1.5 Simulation and Output

31 31 32

Chapter 6: Simulation Results

35

6.1 Transient Analysis of Class B Buffer

35

Chapter 7: Conclusion and Future Scope

42

7.1 Conclusion 7.2 Future work

42 43

References

44

Appendix

46

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LIST OF FIGURES

Fig.1.1: LCD with top polarizer removed from device and placed on top, such that the top and bottom polarizers are parallel. Fig.3.1: Block diagram of LCD system Fig.3.2: LCD column driver Fig. 3.3: The layout of column driver. Fig. 4.1: Rail-to-Rail Class-B Buffer with DC Level-Shifting Current Mirror Fig. 4.2 Circuit diagram of Rail-to-Rail Class-B Buffer with DC Level-Shifting Current Mirror Fig.4.3: The equivalent small-signal circuit of the class-B buffer shown in Fig. 4.2 using MC without feedback path. Fig. 4.4: Class-B buffer using the dc level-shifting current mirror and the distributed Miller compensation. Fig 5.1: Transistor coding in H-Spice. Fig 5.2: Capacitor coding in H-Spice. Fig 5.3: Voltage source coding in H-Spice. Fig 5.4: Transient analysis in H-Spice Fig 5.5: Hspui tool Fig 5.6: Avanwaves result browser Fig 5.7: Avanwaves output window Fig. 6.1: Measured transient responses of class-B buffers with input 2 V square wave of 12.5 kHz under the load capacitances of 10pF 35 21 30 30 31 32 32 33 34 19 15 3 10 12 13 14

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Fig. 6.2: Measured transient responses of class-B buffers with input 2 V square wave of 12.5 kHz under the load capacitances of 100pF 36

Fig. 6.3: Measured transient response of the output VOUT with a 2 V square wave VIN of 12.5 kHz for a load capacitance of 600 pF. 37

Fig. 6.4: Measured transient responses of class-B buffers with input 2 V square wave of 12.5 kHz under the load capacitances of 1200pF 38

Fig. 6.5: Measured transient response of the output VOUT with a 2 V triangular wave VIN of 2.5 kHz for a load capacitance of 1200 pF. 39

Fig. 6.4: Measured transient responses of class-B buffers with input 2 V square wave of 12.5 kHz under the load capacitances of 1200pF 40

LIST OF TABLES
Table 6.1: Simulation results Table 6.2: Simulation results of other works 41 41

LIST OF ABBREVATIONS
LCD - Liquid crystal Display IC -Integrated Circuit TFT- Thin Film Transistor CMOS- Complementary Metal Oxide Semiconductor SoC -System on Chip CRT -Cathode Ray Tube DAC -Digital to Analog Converter CBMC- Current Buffer Miller Compensation MC -Miller Compensation UGF -Unity Gain Frequency GBW -Gain Bandwidth DMC -Distributed Miller compensation PM -Phase Margin

Z Z

- Left-half-plane zero -Right-half-plane zero

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