APPLICATION

NOTE
AP-359
Novembei 1996
28F008SA
Hardware Interfacing
BRIAN DIPERT
MCD MARKFTINO APPLICATIONS
Order Number 292094-004
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COPYRIGHT INTEL CORPORATION 1996
28F008SA HARDWARE INTERFACING
CONTENTS PAGE
10 INTRODUCTION 1
20 HARDWARE INTERFACING 2
21 V
PP
(Byte WriteBlock Erase
Voltage) 2
V
PP
Generation Circuits 3
Controlling V
PP
to 28F008SA
Component(s) 3
22 RYBY (ReadyBusy) Output 4
23 RP (ResetPowerdown) Input 4
Deep Powerdown Mode 4
Write Protection 5
Reset Control 5
24 WE (Write Enable) Input 5
25 Power Supply Decoupling 5
26 High Speed Design Techniques 6
27 Example Bus Interfaces 6
CONTENTS PAGE
ADDITIONAL INFORMATION 7
APPENDIX A Intel386
TM
SL PI Bus
Interface A-1
APPENDIX B Intel486
TM
SX Local CPU
Bus Interface B-1
AP-359
10 INTRODUCTION
The 28F008SA FIashFiIe
TM
Memoiy is a veiy high
peifoimance 8 Mbit (8,388,608 bit) memoiy, oiganized
as 1 Mbyte (1,048,576 bytes) of 8 bits each. The
28F008SA contains sixteen 64 Kbyte (65,536 byte)
bIocks, each bIock sepaiateIy eiaseabIe and capabIe of
100,000 byte wiite-bIock eiase cycIes. On-chip automa-
tion diamaticaIIy simpIifies softwaie aIgoiithms, and
fiees the system miciopiocessoi to seivice highei piioi-
ity tasks duiing component data update. An enhanced
system inteiface aIIows switching the 28F008SA into a
deep poweidown mode duiing peiiods of inactivity, and
gives a haidwaie indication of the status of the inteinaI
Wiite State Machine. High-speed access time aIIows
minimaI wait-state inteifacing to miciopiocessoi buses,
and advanced packaging piovides optimum density/
in
2
.
Featuies of the 28F008SA incIude:
High-Density SymmetiicaIIy BIocked Aichitectuie:
- Sixteen 64 Kbyte BIocks
Fxtended CycIing CapabiIity
- 100,000 BIock Fiase CycIes
- 1.6 MiIIion BIock Fiase CycIes pei Chip
Automated Byte Wiite and BIock Fiase
- Command Usei Inteiface
- Status Registei
System Peifoimance Fnhancements
- RY/BY Status Output
- Fiase Suspend CapabiIity
Deep Poweidown Mode
- 0.20 mA I
CC
TypicaI
Veiy High Peifoimance Read
- 85 ns Maximum Access Time
SRAM-CompatibIe Wiite Inteiface
Haidwaie Data Piotection Featuies
- Fiase/Wiite Lockout duiing Powei Tiansitions
Industiy Standaid Packaging
- 40 Lead TSOP, 44 Lead PSOP
FTOX III NonvoIatiIe FIash Memoiy
TechnoIogy
- 12V Byte Wiite/BIock Fiase
2920941
Figure 1 The 28F008SA Revolutionizes the Architecture of Computing
1
AP-359
2920942
Figure 2 28F008SA Block Diagram
TiaditionaI system aichitectuies combine sIow, high
density nonvoIatiIe mass stoiage (such as a disk diive)
and fast, voIatiIe memoiy (such as DRAM) to fuIIy
addiess system iequiiements. As Figuie 1 iIIustiates,
fIash memoiy combines the best featuies of both the
above memoiy technoIogies, making a disk/DRAM
appioach to system aichitectuie unnecessaiy and uIti-
mateIy wastefuI. FIash memoiy is iapidIy appioaching
DRAM in both cost and peifoimance (especiaIIy in
cached systems), whiIe adding capabiIities (such as non-
voIatiIity), that DRAM cannot cIaim. The 28F008SA
wiII be the buiIding bIock memoiy of choice foi emeig-
ing computing maikets, whethei integiated in a memo-
iy caid oi disk diive foim factoi, oi iesident on the
system motheiboaid.
This appIication note discusses haidwaie inteifacing of
the 28F008SA fIash memoiy to system designs. The
28F008SA datasheet (oidei numbei 290429) is a vaIu-
abIe iefeience document, pioviding in-depth device
technicaI specifications, package pinouts and timing
wavefoims. AP-364 28F008SA Automation and AIgo-
iithms discusses in-depth opeiation of the 28F008SA
Wiite State Machine and inteinaI aIgoiithms, empha-
sizing how they inteiface to system softwaie and haid-
waie. AP-364 shouId be ieviewed in conjunction with
this appIication note and the 28F008SA datasheet foi a
compIete undeistanding of this device.
20 HARDWARE INTERFACING
Figuie 2 shows a bIock diagiam of the 28F008SA and
its inteinaI contents. The CF (chip enabIe) and OF
(output enabIe) inputs have compaiabIe enabIe and
iead functions to those of othei memoiy technoIogies
such as SRAM. SimiIaiIy, V
CC
is the component powei
suppIy (5V g10%), whiIe OND shouId be connected
to system giound. Addiess inputs aIIow the system to
seIect a specific byte foi ieading oi wiiting/eiasing, and
the 8-bit data bus tiansfeis infoimation to and fiom the
28F008SA. The othei contioI Iines (WF, RP,
RY/BY and V
PP
) aie discussed beIow.
21 V
PP
(Byte WriteBlock Erase
Voltage)
The V
PP
input suppIies high voItage to the 28F008SA
to enabIe byte wiite and bIock eiase. V
PP
is specified at
12V g5% (11.4V12.6V). Attempting to byte wiite oi
bIock eiase the 28F008SA beyond the 5% 12V toIei-
ance is not iecommended. V
PP
above 12.6V can poten-
tiaIIy iesuIt in device damage, and V
PP
beIow 11.4V
diamaticaIIy Iengthens wiite/eiase time and compio-
mises data ieIiabiIity. The 28F008SA is guaianteed to
pievent byte wiite and bIock eiase attempts with V
PP
beIow 6.5V, and in this situation it iepoits a Iow V
PP
eiioi thiough the component Status Registei (see AP-
364 oi the 28F008SA datasheet).
2
AP-359
V
PP
Generation Circuits
12V is often aIieady piesent in systems, used to powei
the haid diive, dispIay, RS-232 ciicuitiy, fIash BIOS
update, etc. If it meets the toIeiance and cuiient capa-
biIity iequiiements of the 28F008SA, such a powei sup-
pIy couId be used diiectIy as the 28F008SA update
voItage souice. Howevei, 12V is sometimes not piesent
oi otheiwise iequiied, and in such cases, the 28F008SA
V
PP
must be deiived fiom existing voItages and sup-
pIies.
FoitunateIy, fIash memoiys iapidIy incieasing popu-
Iaiity has diiven evei-impioving 12V conveitei avaiI-
abiIity in the maiket. These soIutions deiive a ieguIated
12V fiom a wide iange of input voItages, and offei vai-
ied IeveIs of integiation and cuiient deIiveiy capabiIity.
In geneiaI, the input foi 12V conveiteis shouId come
fiom the unieguIated system powei souice, paiticuIaiIy
in batteiy-poweied systems.
TabIe 1 Iists and biiefIy desciibes seveiaI 12V geneia-
tion soIutions avaiIabIe at the time this document was
pubIished. This is by no means an exhaustive Iist, and
does not iefIect any specific iecommendation by InteI
Coipoiation. Foi in-depth infoimation on powei sup-
pIy soIutions foi fIash memoiy, iefeience InteI appIica-
tion note AP-357 (oidei numbei 292092), avaiIabIe
thiough youi IocaI InteI saIes office oi distiibutoi.
Controlling V
PP
to 28F008SA Component(s)
Once 12V is avaiIabIe in the system, how is it con-
tioIIed! One appioach is to haid-wiie 12V fiom the
suppIy diiectIy to the V
PP
inputs of each 28F008SA in
the system. The advantage heie is in design simpIicity
and boaid space savings. The 28F008SA Command
Usei Inteiface aichitectuie and two-step byte wiite/
bIock eiase command sequences piovide piotection
fiom unwanted data aIteiation even with high voItage
piesent on V
PP
. AII 28F008SA functions aie disabIed
with V
CC
beIow Iockout voItage V
LKO
(2.2V), oi when
RP is at V
IL
(see section 2.3). This piovides data
piotection duiing system poweiup, when the minimaI-
Iy-Ioaded V
PP
suppIy often iamps to 12V befoie V
CC
(and theiefoie contioI inputs to the device) aie stabIe.
Foi additionaI data piotection, the system designei can
choose to make the V
PP
suppIy switchabIe via a OPIO
(OeneiaI Puipose Input/Output) Iine, enabIing 12V to
the 28F008SA onIy duiing byte wiite oi bIock eiase
attempts. A switchabIe V
PP
aIso minimizes powei con-
sumption by both the fIash memoiy components and
the 12V suppIy oi conveitei (due to efficiency Iosses).
Many 12V conveiteis integiate an FNABLF input,
eIiminating exteinaI ciicuitiy. If such an input is not
avaiIabIe, a Iow diain-souice iesistance MOSFFT
switch such as the MotoioIa MTD4P05 can be used at
the 12V suppIy output. An exampIe schematic foi this
switch is shown in Figuie 3. The caIcuIations beIow
show that the Iow diain-souice iesistance of the
MTD4P05 wiII keep a 12V input within the 5% toIei-
ance iequiied by the 28F008SA.
R
DS
e 06X
I
PP
e 60 mA
(woist case, two components being byte wiitten oi
bIock eiased)
DV
SWITCH
DROP e (60 mA c 06X) e 004V
2920943
Figure 3 V
PP
Switch Schematic
Table 1 12V Conversion Solutions for V
PP
Part Input Current
Total Est
Manufacturer
Number (V)
Package
Output
Components Cost
Needed (10K)
Maxim MAX732 4 to 75 16 SOIC 120 mA 9 $393
Linear Technology LT1110-12 45 to 55 SO8 120 mA 11 $458
Linear Technology LT1109-12 45 to 55 SO8 60 mA 8 $361
Motorola MC34063A 45 to 55 SO8 120 mA 15 $225
Maxim MAX667 121 to 165 SO8 120 mA 4 $263
Linear Technology LT1111-12 16 to 30 SO8 120 mA 7 $395
National Semiconductor LM2940CT-12 13 to 26 TO-220 1A 3 $130
3
AP-359
22 RYBY (ReadyBusy) Output
The 28F008SA offeis simiIai automated byte wiite/
bIock eiase capabiIities to those fiist seen in the
28F001BX BootbIock fIash memoiy famiIy, intioduced
by InteI in May of 1991. It enhances these capabiIities
via the RY/BY output, which piovides haidwaie in-
dication of inteinaI Wiite State Machine (WSM) opeia-
tion. RY/BY is a fuII CMOS output, constantIy diiv-
en by the 28F008SA and not tiistated if the device
CF oi OF inputs aie biought to V
IH
. RY/BYs
defauIt state aftei device poweiup is V
OH
. It tiansitions
Iow to V
OL
when a byte wiite oi bIock eiase sequence
is initiated by system softwaie, and RY/BYs iising
edge (ietuin to V
OH
) aIeits the system to byte wiite oi
bIock eiase compIetion. RY/BY aIso goes to V
OH
aftei the 28F008SA is put in Fiase Suspend oi Deep
Poweidown modes.
RY/BY is intended to inteiface the 28F008SA to a
system miciopiocessoi iising-edge-tiiggeied inteiiupt
input. In a muItipIe-chip memoiy aiiay, exteinaI
FPLD Iogic oi an inteiiupt contioIIei can be used to
combine and piioiitize RY/BYs into one system in-
teiiupt (see Figuie 4). The system can then, using a
fIash memoiy activity tabIe set up in RAM, poII the
individuaI 28F008SA Status Registeis to deteimine
which device has ietuined ieady, oi iead the
RY/BY inputs diiectIy at the FPLD, as shown.
Figuie 5 piovides an aIteinative method foi connecting
muItipIe RY/BYs to one inteiiupt input. The diode/
iesistoi combination conveits the 28F008SA fuII
CMOS output into an open-diain wiied-OR equiva-
Ient. Any RY/BY at V
OL
wiII diive the inteiiupt
input Iow, and this input is puIIed high by the iesistois
when aII RY/BYs aie at V
OH
. It is impoitant in a
design Iike this to use diodes with Iow foiwaid voItage
diops, so that the 28F008SA V
OL
(0.45V) pIus the di-
ode voItage diop is stiII Iess than oi equaI to the desti-
nation input V
IH
(0.8V). Foi the schematic shown in
Figuie 5, the equation is:
V
OL
a V
DIODE
e 045 V
MAX
a 03V e 075V
s
08V
Note that shouId the system connect RY/BY to an
inteiiupt, disabIe that inteiiupt piioi to suspending
eiase, as RY/BY wiII tiansition to V
OH
when the
device is suspended.
2920944
Figure 4 EPLD-Based RYBY Implementation
2920945
Figure 5 Wired-OR RYBY Implementation
23 RP (ResetPowerdown) Input
Deep Powerdown Mode
The RP input, when diiven to V
IL
by the system,
switches the 28F008SA into a deep poweidown mode
with negIigabIe powei consumption. This featuie inte-
giates the V
CC
powei FFT often used with Iow powei
designs. Powei consumption thiu V
CC
is typicaIIy
1 mW in deep poweidown mode. RP-Iow deseIects
the memoiy, pIaces output diiveis foi D
07
in a high-
impedence state and tuins off a majoiity of inteinaI
ciicuits. RY/BY is diiven to V
OH
whiIe in deep
poweidown mode. Depending on the fIexibiIity desiied,
system designeis can choose to put eithei the entiie
fIash device aiiay into deep poweidown mode, oi any
individuaI components via seIective input contioI. The
28F008SA iequiies a wakeup time aftei RP ie-
tuins to V
IH
befoie it can be successfuIIy wiitten
(t
PHWL
) oi outputs aie vaIid to iead attempts (t
PHQV
).
4
AP-359
Write Protection
Since RP e
V
IL
deseIects the 28F008SA, this input
can be used not onIy as a means of enteiing deep pow-
eidown mode but aIso as an active-high chip enabIe
to bIock spuiious wiites duiing system powei tian-
sitions. Figuie 6 shows one possibIe RP impIementa-
tion, contioIIed by a OPIO Iine foi powei management
and by a system POWFR OOOD foi powei sequencing
piotection. In this design, the 5V monitoiing ciicuit
begins functioning at V
CC
e
1V, and wiII enabIe the
device onIy aftei V
CC
tiansitions above 4.6V (and sys-
tem contioI signaIs aie theiefoie stabIe). As V
CC
diops
beIow 4.6V duiing system poweidown, RP piotection
is again activated.
2920946
Figure 6 RP Gating
Reset Control
RP at V
IL
iesets aII inteinaI automation within the
28F008SA as pait of the deep poweidown piocess.
Upon exit fiom deep poweidown, the 28F008SA is ie-
set to Read Aiiay mode. This functionaIity is ideaI
when the 28F008SA is the boot memoiy foi the system.
RP active tiansitions ieset the Wiite Status Machine
if system ieset occuis duiing fIash memoiy piogiam oi
eiase, and aIIow successfuI CPU ieboot.
24 WE (Write Enable) Input
When fIash memoiy is wiitten, the iesuIt can iange
fiom a 28F008SA that is pIaced in iead inteIIigent
identifiei oi iead Status Registei modes to aIteia-
tion of nonvoIatiIe fIash memoiy contents. System
haidwaie can pievent spuiious wiites to fIash memoiy
by appIication softwaie oi an opeiating system by gat-
ing the system WF to fIash memoiy components to
enabIe wiites onIy when desiied.
Figuie 7 shows a simpIe design that gates WF with a
OPIO Iine, enabIing wiites to the 28F008SA onIy when
the OPIO is a 0. The OPIO is initiaIized to 1 on
system poweiup and the BIOS, a dedicated update soft-
waie ioutine, a speciaI keyboaid sequence, switch on
the back of the system oi jumpei on the system mothei-
boaid can then contioI the OPIO. This ciicuit ensuies
that fIash memoiy contents aie as peimanent as
ROM unIess aIteiation is specificaIIy desiied.
2920947
Figure 7 WE Gating
25 Power Supply Decoupling
Both the V
CC
and V
PP
inputs to each 28F008SA
shouId be decoupIed at the package Ieads to piovide
noise immunity and suppIy cuiient foi tiansient cui-
ient spikes duiing iead, byte wiite and bIock eiase. Ad-
ditionaI buIk capacitance foi gioups of fIash memoiies
oveicomes voItage sIump caused by PC boaid tiace in-
ductances. CaIcuIations foi individuaI component and
buIk capacitois (one pei 8 devices) aie shown beIow.
Basic Fquation:
I e C dvdt
Assumptions:
I e 35 mA per device (V
CC
) therefore
I e 175 mA per device input (V
CC
)
I e 30 mA per device (V
PP
)
dv e 01V (02V peak-peak)
dt e 20 ns
Pei-Component-Input DecoupIing Capacitoi (V
CC
):
C e I dtdv e (175 mA c 20 ns)01V e 35 nF
4x margin e 4 c 35 nF e 14 nF
Standard Equivalent e 001 mF
5
AP-359
NOTE
CaIcuIations above assume that each 28F008SA is
diiving CMOS inputs (with coiiesponding high im-
pedance and negIigibIe input cuiient iequiiements). If
28F008SA outputs aie diiving non-CMOS inputs,
Iaigei pei-component capacitance may be needed to
suppIy cuiient whiIe outputs aie switching.
BuIk Capacitoi (V
CC
):
C e 10 c (Total of Decoupling Capacitors)
Bulk Capacitor (4 Mbyte array) e 10 c (8 c 001 mF)
e 08 mF
Standard Equivalent e 1 mF
Pei-Component DecoupIing Capacitoi (V
PP
):
C e I dtdv e (30 mA c 20 ns)01V e 6 nF
4x margin e 4 c 6 nF e 24 nF
Standard Equivalent e 0033 mF
26 High Speed Design Techniques
The 28F008SAs fast iead access and command wiite
specifications make it a natuiaI choice foi high pei-
foimance memoiy aiiays. The foIIowing tips wiII opti-
mize the memoiy inteiface foi optimum iead/wiite
speed. The common iecommendation in aII instances
centeis aiound minimizing fanout and capacitive bus
Ioading to aIIow highest switching speed, Iowest iise
and faII times, and theiefoie gieatest peifoimance.
Minimize addiess bus Ioading fiom the miciopioc-
essoi to the memoiy aiiay. MuItipIe addiess Iatches
feeding subsets of the aiiay speed addiess input to
each 28F008SA and CF decoding by exteinaI
Iogic.
SimiIaiIy, diive the memoiy aiiay with muItipIe
OFs and WFs. Most FPLD and disciete Iogic
timing is specified at a 30 pF Ioad, which equates to
diiving foui 28F008SA inputs at maximum input
capacitance. Anything moie than this may seveieIy
impact the Iogics piopagation deIay.
FinaIIy, iemembei that each 28F008SA, when iead,
diives not onIy the system miciopiocessoi oi tians-
ceivei but aIso any othei fIash memoiy components
connected to the common data bus. Fach 28F008SA
data output is specified at 12 pF, and the 28F008SA
iead timings aie tested at eithei 30 pF oi 100 pF of
Ioading, depending on the chosen speed bin.
Foi Iaige fIash aiiays wheie sequentiaI data can be dis-
tiibuted on many devices, haidwaie inteiIeaving pio-
vides additionaI peifoimance.
27 Example Bus Interfaces
Appendix A shows haidwaie inteiface to the In-
teI386
TM
SL PI bus, and Appendix B shows inteiface to
the InteI486
TM
SX IocaI CPU bus. Both inteifaces in-
coipoiate techniques desciibed in sections 2.12.6 of
this document. These designs aie intended to be exam-
pIes which can be modified to suit iequiiements of the
end system.
ADDITIONAL INFORMATION
Order Number
28F008SA Datasheet 290429
28F008SA-L Datasheet 290435
AP-357 Power Supply Solutions for Flash Memory 292092
AP-364 28F008SA Automation and Algorithms 292099
ER-27 The Intel 28F008SA Flash Memory 294011
ER-28 ETOX-III Flash Memory Technology 294012
REVISION HISTORY
Number Description
-003 Renamed PWD as RP to match JEDEC conventions
Updated Figure 6
Added Reset Control discussion for RP (ResetPowerdown) Input
-004 Minor changes throughout document
6
AP-359
APPENDIX A
Intel386
TM
SL PI BUS INTERFACE
2920949
NOTE
The DRAM interface is not shown for graphic simplicity
A-1
AP-359
APPENDIX B
Intel486
TM
SX LOCAL CPU BUS INTERFACE
29209410
NOTE
The DRAM interface is not shown for graphic simplicity
B-1