Exercise 5 74LS163 1x 4bit counter Synchronous design is done by having all the flip flops using the same

clock . All the output changes with each other when enabled is turned on. 74LS393 2x 4 bit counter Two of the counters inside the chip are the same and each has 4 outputs. Asynchronous design is done by using the most significant bit of the first counter as the clock for the second counter. Contains eight master-slave flip flops and additional gating 8x T flip flops 2x Gates and 8x T flip flops

Counter Design

Complexity of Implementation These have an internal carry look ahead Flip-Flops 4x JK flip-flops Logic 31x Gates & 4x JK flip-flops

Exercise 6 Because a single inverter computes the logical NOT of its input, it can be shown that the last output of a chain of an odd number of inverters is the logical NOT of the first input. This final output is asserted a finite amount of time after the first input is asserted; the feedback of this last output to the input causes oscillation. A circular chain composed of an even number of inverters cannot be used as a ring oscillator; the last output in this case is the same as the input. (Wikipedia.org)

With 11 gates the frequency of oscillation is 500Hz, and the signal is displaced by 2 full periods. Vcc of 5V, the maximum voltage attained was about 3.5V and the minimum voltage was about 0.1V.Therefore the propagation delay = ~2ms With 17 gates the propagation delay is = ~3ms. The new values for minimum and maximum voltage are Vcc = 5.9V, Vmin = 0.5V, and Vmax = 4.4V Exercise 7

The following image is of an SR latch and the corresponding truth table.

When E is high, the gated SR-latch works like a normal SR-latch and with the clock off, it latches the current state. SR latch will try to produce a high Q and a low Q at once, a race condition. The one that succeeds to change first will dominate the output. When E is low, S or R input will not affect SR-latch state, Q keeps previous output. Exercise 8 The VHDL code to implement the 7 segment display ----------------------------------------------------------------------------------- Company: -- Engineer: --- Create Date: 14:09:49 01/13/2014 -- Design Name: -- Module Name: test - Behavioral

-- Project Name: -- Target Devices: -- Tool versions: -- Description: --- Dependencies: --- Revision: -- Revision 0.01 - File Created -- Additional Comments: ----------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity test is port ( a: in std_logic; b: in std_logic; c: in std_logic; d: in std_logic; t: out std_logic; u: out std_logic; v: out std_logic; w: out std_logic; x: out std_logic; y: out std_logic; z: out std_logic ); end test; architecture Behavioral of test is begin t <= NOT(a OR c OR (NOT(b) AND NOT (d)) OR (b AND d)); u <= NOT(NOT(b) OR (c AND d) OR (NOT(c) AND NOT(d))); v <= NOT(b OR (NOT(c)) OR d); w <= NOT((NOT(b) AND NOT(d)) OR (NOT(b) AND c) OR a OR (b AND NOT(c) AND d) OR (c AND NOT(d))); x <= NOT((c AND NOT(d)) OR (NOT(b) AND NOT(d))); y <= NOT(a OR (b AND NOT(c)) OR (NOT(c) AND NOT(d)) OR (b AND NOT(d))); z <= NOT(a OR (b AND NOT(c)) OR (b and NOT(d)) OR (NOT(b) AND (c))); end Behavioral;

#### Input Pins on Nexys 3 # Switch 0 NET d LOC = T10; # Switch 1 NET c LOC = T9; # Switch 2 NET b LOC = V9; # Switch 3 NET a LOC = M8;

#### Output pins # LED 0 NET t LOC = T17; NET u LOC = T18; NET v LOC = U17; NET w LOC = U18; NET x LOC = M14; NET y LOC = N14; NET z LOC = L14;