Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 1, February 2014

EFFICIENT MULTIPLIERS FOR 1-OUT-OF-3 BINARY SIGNED-DIGIT NUMBER SYSTEM

Maryam Saremi1
1

Department of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran

ABSTRACT
This paper proposes new multipliers based on Binary Signed-Digit (BSD) operands. BSD number system has carry free capability in addition operation which causes high speed multiplication. In order to use the numbering system, BSD operand needs to be encoded into binary bits. 1-out-of-3 BSD encoding has been proposed as a subset of m-out-of-n codes which can be used for error detection and correction. However, a multiplier for 1-out-of-3 encoding has not yet been reported in the literature. In this paper, we propose three different structures for 1-out-of-3 BSD multiplication for the first time to achieve an appropriate trade-off between area, delay, and power parameters. Our target implementation platform is Application Specific Circuits (ASIC).

KEYWORDS
1-out-of-3 encoding; Binary Signed-Digit (BSD)system; BSD multiplication; Digit production; carry free addition, ASIC

1. INTRODUCTION
Multiplication is a very important operation for digital computing systems, process controllers, and signal processors [1, 2, 15]. Multiplication involves two basic steps: The first one is generation of partial products and the second step is their accumulation. Therefore, the efficiency of multiplication is improved by reducing the number of partial products or accelerating their accumulation. Besides, the performance of partial products accumulation depends on the numbering system used to represent the operands. Although, conventional weighted binary number system like two's complement representation is widely used in arithmetic units, the obtained carry propagation chain in the conventional number system increases the delay of multiplication operation. Therefore, the performance is reduced. In n-bit fast adder for conventional binary number system, ci the input carry to position i, is a function of all inputs from 0 to i, when (i=0, 1, , n-1). The dependency results in increasing the multiplication delay which is reliant on the size of the operands, in the worst case. Binary signed-digit number representation [3] is an appropriate numbering system to restrict or eliminate the carry propagation chain in addition by eliminating the dependency between output and input carries. BSD representation has been used to design high speed arithmetic circuits [5-9, 15]. To represent BSD operands they should be encoded into binary bits. Several BSD encoding schemes have been proposed in the related literatures: 2-bit encoding with twos complement representation [10-14], 2-bit encoding with posibit and negabit representation [15], and 3-bit encoding with 1-out-of-3 representation [16]. The adders and multipliers for these encodings have been presented in the state of the art papers. The 1-out-of-3 encoding scheme is a subset of m-out-of-n codes [17] and is used for error detection and correction. The authors of [18] presented constant delay adder for 1-out-of-3 encoding with capability of online error detection. The addition operation with 1-out-of-3 encoding has been described in [16]. However, the presented BSD addition algorithm for 1-outof-3 encoding seems to be faulty. In this way, we first deal with the drawback of the adder. On
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Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 1, February 2014

the other hand, a multiplier structure for 1-out-of-3 encoding has not yet been presented in the open literatures. So, we propose new multipliers based on carry free addition using 1-out-of-3 BSD system. We propose three multiplication structures for the encoding. The proposed multipliers are differently designed to obtain the desired area, speed, and power requirements. The rest of the paper is organized as follows: the next section discusses basic concepts of 1-outof-3 encoding as well as the addition method presented in [16]. In section 3, we emend the problem of the previous adder presented in [16]. The structures of the three multipliers are presented in section 4. In section 5 the synthesis results and comparisons are presented. Finally, the paper is concluded in the last section.

2. THE BINARY SIGNED-DIGIT NUMBER SYSTEM

2.1. 1-out-of-3 BSD Encoding
The radix-r signed digit number system is used to speed up the arithmetic operations by the carry limited addition capability which means the output carry signal is not dependent on the input carry signal [16]. A radix-r signed digit number X is presented in the system with n-digit as follows:

X = x 0 r 0 + x 1r 1 ++ x n 1r
n 1

n 1

= xiri
i =0

(1)

Where xi is a signed digit, r is the radix and is equal to 2 in BSD system, ri is the weight of i-th digit xi. Assuming radix-2, xi is in the range {-1, 0, 1}. Equation (1) indicates that an integer number may have more than one representation. For example, in a 4-digit BSD system, the value 6, may be represented by (0 1 1 0) BSD, (1 -1 1 0) BSD, (1 0 -1 0) BSD. The 1-out-of-3 encoding [16] scheme which is shown in Table I is utilized to represent three different binary signed digits into binary bits.
Table 1. 1-out-of-3 encoding scheme [16]

Binary BSD Digit (xi) -1 0 1 xi2 1 0 0 xi1 0 1 0 xi0 0 0 1

We employ the 1-out-of-3 encoding in order to indicate a BSD xi which is denoted as (xi2xi1xi0) with the same weight. The xi2, xi1, xi0 are called as second bit, first bit, and zero-th bit of the digit xi, respectively. The code words in this encoding are {-1, 100}, {0, 010}, and {1, 001}, have exactly 1 and two 0, s. Therefore, the presence of any other code words will show an error.
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Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 1, February 2014

2.2. Addition Structure with 1-out-of-3 BSD Encoding

Let X, Y be two integers in the n-digit 1-out-of-3 BSD number representation, and U, C and S be the intermediate sum, intermediate carry and final sum, respectively. For performing addition operation of each digit of X and Y, the following two steps are performed [16, 19, 20]. Step1: Generate The intermediate sum digit Ui and intermediate carry digit Ci signals are the i-th BSD digit of U, and C, respectively, and generated based on the 1-out-of-3 BSD addition rules shown in Table 2. Step2: Compute The final sum digit Si is the i-th BSD digit of S, computed using both the Ui and Ci-1 signals. The Ci-1 is the (i-1)-th BSD digit of C. The Ui, Ci, and Si are represented by 1-out-of-3 encoding.
S i = U i + C i 1 Si =

{1, 0,1}
Table 2. BSD Addition Rules [16]

Xi+Yi -2 -1 0 1 2

Xi-1+Yi-1 Dont care At least one is negative Non is negative Dont care At least one is negative Non is negative Dont care

Ci -1 -1 0 0 0 1 1

Ui 0 1 -1 0 1 -1 0

The following example presents the addition operation of two numbers using the 1-out-of-3 encoding and the addition rules described above: Example 1: Lets assume

X = "010001001001" = ( 7 )10 Y = "010001100010" = ( 2 )10 X +Y = ( 7 )10 + ( 2 )10 = ( 9 )10

According to the rules shown in Table II, the process of the addition is as follows:

From the above example and the BSD addition rules, the i-th final sum digit depends on the inputs in the i-th and (i-1)-th positions and is computed without carry propagation.

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Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 1, February 2014

Figure 1. BSD Adder Using BSD_FA cell

In the block diagram of BSD adder shown in Fig.1, each line denotes one BSD digit. Each BSD_FA cell has five inputs (xi, yi, xi-1, yi-1, Ci-1) and two outputs (Ci, Si). The number of inputs and outputs is tripled when using the 1-out-of-3 encoding. Then, we have 15 input bits and 6 output bits. The sign signal i.e. signi presents the sign of (xi, yi). In this adder which presented in [16] by using the signi-1 signal, the number of inputs is reduced to 10 because in this adder the xi-1 and yi-1 inputs are utilized exactly for specifying sign of (xi-1, yi-1). Fig. 2 (a), (b) shows BSD_FA cell without and with signi-1 signal, respectively. As shown in this figure, the number of inputs in the Fig. 2 (a) is 15. By using the signi-1 signal in the Fig. 2 (b), the number of inputs is reduced to 10.

Figure 2. BSD_FA cell with 1-out-of-3 Encoding

There are nine combinations for (xi+yi) as follows: -2= (100, 100), -1= {(100, 010), (010, 100)}, 0= {(010, 010), (100, 001), (001, 100)}, 1= {(001, 010), (010, 001)}, 2= (001, 001).

3. PROPOSED 1-OUT-OF-3 BSD MULTIPLICATION ALGORITHM

3.1. Digit and Partial Product Structure
Let's assume X and Y are integers in the n-digit BSD number representation. The multiplication XY can be expressed as follows:

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Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 1, February 2014

X Y =

(x 2 + x 2 + . . . + x ) (y 2 + y 2 + . . . + y )
n 1 n 2 n 1 n 2 0 n 1 n 2 n 1 n 2 0

x (y
i i =0 n 1
i =0

n 1

n 1

2n 1 + y n 2 2n 2 + . . . + y0 )

= pp i

(2)
n 1

pp i = x i ( y n 1 2

+ yn 2 2

n 2

+ . . . + y0 )

(3)

Where ppi denotes the i-th partial product. To achieve ppi, digit products xiyj (0 i, j n) should to be calculated first. The calculation is presented in the following. Let xi and yj (0 i, j n) are two digits in the 1-out-of-3 BSD number representation. Digit production of xi, yj that is (xiyj), is presented in Table 3. According to the table, there are six different combinations for (xiyj). If one of the two digits (xi or yj) is zero i.e. "010", then the result will be "010". If both digits have same sign, that is the pair (xi, yj) is one of the two cases i.e. {(001, 001) or (100, 100)}, then digit production will be "001. Finally, if both digits have opposite sign, i.e. (001, 100) or (100, 001), then digit production will be "100". Using these combinations which are presented in Table 3, the following equations can be used to describe the digit production of xi and yj.
Table 3. Digit production

xi yj Digit Production (di) 001 001 001 100 100 001 010 Dont care 010 Dont care 010 010 001 100 100 100 001 100 The three bits of the digit product di, are calculated by (4-6).
di
di di

0
1 2

= (x i
1

0 2 2 y j ) + (x i y j )
1

(4) (5)

= xi + y j = (x i 0

y j ) + (x i

yj )

(6)

3.2. Addition Tree Structure

Assuming 8-digit BSD number X and Y in 1-out-of-3 representation, there are eight partial products called pp (0), pp (1), , pp (7) according to (16). To accumulate the partial products, we propose three different addition trees to achieve the desired area, delay, and power parameters.

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Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 1, February 2014

The first structure: In the block diagram of the first structure shown in Fig. 4, each square in the partial product denotes one BSD digit with 1-out of 3 encoding. In this structure, addition is performed sequentially in eight steps. That is, pp (0) and pp (1) are accumulated first, and then the result is added to pp (2), and so on. The partial products are not aligned as shown in Fig.3. So, in addition process, one or more digits are added to zero digit. In BSD addition of a digit xi with zero is not necessarily equal to xi.

Figure 3. Generation of partial product

Figure 4. The first structure for adding partial products

So, addition with zero digit is necessary because the representation of the addition result may be different to the input representation. For example, according to table II, if xi=1 (001), yi=0 (010) and xi-1+yi-1=1 (Non is negative) i.e. sixth row of table II, the intermediate signals i.e. Ci and Ui are "001" and "100", respectively. In this case Ci is not equal with zero, therefore we can't ignore Ci. Then addition with zero digit is necessary. The circles in Fig. 3, Fig. 4 specify the addition with zero as discussed above. This addition is performed by the proposed BSD_FA0 cell as discussed in the following. For BSD_FA0 cell like BSD_FA there are five inputs (xi, yi, xi-1, yi-1, Ci-1) and two outputs (Ci, Si). The following logic equations can be used to describe the BSD_FA0 cell with the 1-out-of-3 encoding:
Sign i = x i 2

(7)

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Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 1, February 2014

The three bits of output carry digit Ci are calculated by (8-10).

Ci Ci
Ci

0 1
2

0 = (Sign i 1 x i ) = (Sign i 1 x i ) + x i + (Sign i 1 x i )

2 = (Sign i 1 x i )

(8)
1 0

(9) (10)

The three bits of the intermediate sum Ui, are calculated by (11-13).
Ui Ui 0 1 = ( Sign i 1 ) ( x i = xi 1 2 0 + xi )

(11) (12)

Ui

= ( Sign i 1 ) ( x i

2 + xi )

(13)

The final sum in position i, Si in 1-out-of-3 encoding are calculated by (14-16).

Si 0 = (U i 0 1 1 0 C i 1 ) + (U i C i 1 )

(14) (15)

Si
Si

1
2

1 1 1 = (U i C i 1 ) + (U i C i 1 )
2 2 1 = (U i C i 1 ) + (U i C i 1 ) 1

(16)

Fig. 5 shows the BSD_FA0 cell used to align the partial products which are described above.

Figure 5. BSD_FA0 Cell using 1-out-of-3 Encoding

In the first step of this structure, pp (0) and pp (1) are added together simultaneously with BSD_FA and BSD_FA0 cells and the result of this step is denoted as pp'(0). In the next step, pp (2) is added to pp'(0) according to the previous step and in next steps each newly generated product is added to the previously accumulated partial products. Therefore, the resulted sum in each step will have one digit more than the previous step. The problem of this structure is a considerable delay due to sequential addition operation of partial products which makes it improper for arithmetic units. Due to the fact that delay is an important constraint; in the following we propose two different addition trees in order to reduce the delay.

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Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 1, February 2014

The Second structure: In the second structure, addition operation of partial products is performed in three steps as shown in Fig. 6 (a). In the first step, four BSD addition operations are performed in parallel for four groups of partial products i.e. {pp (0), pp (1)}, {pp (2), pp (3)}, {pp (4), pp (5)}, {pp (6), pp (7)} utilizing BSD_FA and BSD_FA0 components. The results are denoted as pp'(0), pp'(1), pp'(2), pp'(3), respectively. In the next step, the same processes are done for the results of first step. That is (pp'(0) + pp'(1)} and {pp'(2) + pp'(3)} are performed simultaneously. The results are denoted as pp"(0) and pp"(1), respectively. In the last step, pp"(0) and pp"(1) are added together and the final sum is obtained. This structure is performed in three steps which leads to less delay in comparison to the first structure. The third structure: This structure is presented in three steps similar to the second structure as shown in Fig.6 (b). In the first step of this structure, four BSD addition operations are performed in parallel for four groups of partial products i.e. {pp (0), pp (7)}, {pp (1), pp (6)}, {pp (2), pp (5)}, {pp (3), pp (4)}. BSD_FA and BSD_FA0 cells are utilized for the addition. The results are denoted as pp'(0), pp'(1), pp'(2), pp'(3), respectively. It should be noted that this structure makes larger intermediate results during steps than the second method. In the next step, the same processes are done for the results of first step. That is {pp'(0) + pp'(3)} and {pp'(1) + pp'(2)} are performed simultaneously. The results are denoted as pp"(0) and pp"(1), respectively. In the last step, pp"(0) and pp"(1) are added together and the final sum is obtained. These two structures have equal delays which are less than the first structure because, in both structures, addition operation of partial products is performed in three steps while in the first structure it is done sequentially in eight steps.

Figure 6. Second and Third structure for adding partial products

Fig.7 shows the process of 4-digit BSD multiplication for 1-out-of-3 encoding numbers, X and Y. pp(0), pp(1), pp(2), pp(3) are partial products of XY according to (19). Second structure is utilized to accumulate of partial products. In the first step, two BSD additions are performed in parallel for two groups of partial products i.e. {pp(0), pp(1)}, {pp(2), pp(3)}. The results are called pp'(0) and pp'(1), respectively. Finally, pp'(0) and pp'(1) are added together and the final sum is produced. The final sum has 9-digit while in the conventional binary number system, multiplication of 4-bit inputs results in 8-bit output. If we ignore the last digit in the final sum, we may not obtain a correct result.
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Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 1, February 2014

Figure 7. Multiplication structure of 4-digit BSD numbers X and Y in 1-out-of-3 representation

Example 2: This example depicts BSD multiplication described in Fig.7. Let's assume X="001001001001"=(15)10 Y="001001001001"=(15)10

In the above example, if we ignore the last digit of final sum, the value of final sum will be -31 while, the result must be 225 because X and Y= (1 1 1 1) BSD= (15)10. Therefore, if we ignore the last digit in final sum in three structures, we may not achieve a valid result. In the second and third proposed structures, if we express final sum of multiplication with 16digit, we won't have valid results for many cases. Therefore, to achieve a correct result in these structures, final sum must have 18-digit.

4. SIMULATION AND RESULTS

As discussed earlier, 1-out-of-3 BSD xi which is encoded as (xi2xi1xi0) with the same weight. Thus, a p-digit BSD number X is represented by a vector with 3p-bit length. For example, (1 0 0 1) BSD = (001010010100). Using the binary representation, BSD multiplication operation was described in the last section of this paper for the first time. The proposal structures are considered in this section for simulation and synthesis. To evaluate the area, speed, and power of the
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Electrical and Electronics Engineering: An International Journal (ELELIJ) Vol 3, No 1, February 2014

proposed BSD multipliers with 1-out-of-3 encoding scheme, firstly, the structural VHDL descriptions of these structures are generated. Secondly, they were exhaustively verified. To this end, we implemented a test-bench which reads an input text file containing all input possibilities. The outputs were compared to the expected outputs. Afterwards, we synthesized the structures using Synopsys Design Vision tool and the TSMC 180 nm CMOS standard cell library with typical conditions (1.8 V, 25c). Three important parameters of arithmetic circuits i.e. area, speed, and power for these structures are reported in Table VI. Delay, area, and power results are given in ns, m2, and mw, respectively. This table indicates that the delay of the first structure is more than the second and third structures regarding the fact that this structure is done sequentially in eight steps while the additions are performed in parallel in the second and third structures. As it was expected, the second and third modules have same delay which is equal to 2.85 while the first one has the delay equal to 6.27 ns. Besides, the multiplication delay dose not depends on the length of the input operands. Area depends on the number of BSD_FA and BSD_FA0 cells which is utilized for addition operation of partial products. Since the number of cells used in the third structure is more than that of the two others structure, therefore area in this structure is larger than the two other structures. Besides, the second structure consumes the least amount of cells and therefore has the minimum delay among the structures. The maximum and minimum amounts of power are for the first and second structures, respectively. So it can be included that the second structure in terms of delay, area and power consumption is appropriate than the other two structures.
Table 4. synthesis results of three proposed multipliers for 8-digit inputs Delay 6.27 2.85 2.85 Area 29169.2 27861.9267 31035.3123 Power 8.1453 6.3748 6.5766 PDP 51.071031 18.16818 18.74331

First Structure Second Structure Third Structure

5. CONCLUSION
In this paper we proposed three different architectures of BSD multiplication operation using the 1-out-of-3 encoding scheme for the first time. We also removed the incorrect equation of BSD_FA cell using the 1-out-of-3 encoding presented in [16]. The synthesis result indicates that the first structure is a low-speed module which makes it improper for arithmetic units. The second and third structures were proposed in order to improve performance. Using these structures, we succeeded to decrease about 54.54% of the delay, 21% of the power comparing to the first structure. These improvements are achieved based on designing efficient tree structures for addition of partial products. The second structure consumes the least delay, area, power and PDP. The second structure has 54.54% less delay, 21.74% less power, 4.48% less area, and 64.43% less PDP than the first one, it also consumes 10.23% less area, 3% less power, and 3% less PDP than the third structure. Therefore, the second proposed structure for BSD multiplication operation with 1-out-of-3 encoding is appropriate for arithmetic units.

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