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135

TECHl'iOLOGICAL

UNIVERSITY

KAKINA))A

III Year B_Tech. Electronics and Computer Engineering DIGITALSIGNAL PROCESSING UNITI

n Sem,

INTRODUCTION: Introduction to Digital Signal Processing: Discrete time signals & sequences, linear shift invariant systems, stability, and causality. Linear constant coefficient difference equations. Frequency domain representation of discrete time signals and systems. UNlTlI DISCRETE FOURIER SERIES: Propertiesof discrete fourier series, DrS representation of periodic sequences. Discrete Fourier transforms: Properties of DFf. linear convolution of sequences using DFT, Computation of DFI'. Relation between Z-transform and DFS UNIT III

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UJ'.ITfIV REALIZATION OF DIGITAL FILTERS: Review of lAransfonns. Applications of Z - transforms, solution of difference equations of digital filters. Block diagram representation of linear constant-coefficient difference equations. Basic structures of IIR systems, Transposed forms. Basic structures of FIR systems, System function,
UNITV

FAST FOURIER TRANSFORMS: Fast Fourier transforms O:Fr) .'.Radix2 decimation in time and decimation in frequency FFf Algorithms, Inverse fFT, and F1<i for composite N

UR DIGITAL FILTERS: Analog filter approximations ._nutter worth and Chebyshev, Design of Illc Digital filters from analog filters, Design Examples: Analog-Digital transformations. lJ!'olT vt FIR DIGITAL FILTERS: Characteristics of I-m Digital Filters, frequency response. Design of HR Digital Filters using Window Techniques. Frequency Sampling technique, Comparison of fIR & FIR filters. CNITVII M"LLTtRATE DIGITAL SIGNAL PROCESSING: Decimation, interpolation.

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136 sampling rate conversion. Implementation

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sampling rate conversion

UNIT VIII
INTRODUCTION TO DSP PROCESSORS: Introduction to programmabk DSPs: Mulripl ier and 1\1ultiplier Accumulator (MAC)_ Modi fied B II Structures and Memory Access schemes in DSPs Multiple access memor mulriport memory. VLSI Architecture. Pipelining, Special addressing modeOn-Chip Peripherals. Architecture of TMS 320C5X- Introduction, IlLStructure. Central Arithmetic Logic Unit. Auxiliary Registrar. Index Regis!ra' Aux il i ary Rcgistger Compare Register, Block 1\10ve .'\ddres~ Re~'is12 Parallel Logic Unit Mcmorx mapped registers. program controller. S(\l flag.<; in the ,tatus registers. On- chip registers. On chip peripherals TEXT nOOKS; I. Digital S ignai Processing, Prine iples. Algorithms. and Appl icat ior' John G. Proakis. Dimitri, G, Manolakis. Pearson Education I PH,
2(Kl7.

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3. l)ig~ta! Signa! Proccssors Architecture. Programming Applicaiions., B,Venkatarannni, 0.1. Bhaskar, TAL\ Mcriraw IL
2{)02.

2,

Discrete Time Signal Processing -_A.V.Oppenheim and R.W. Schaffc PIn

REFERENCE BOOK"': I. 2,

Digital Signal Processing: Andreas Antoniou. ]~~\l'_'\ lVlcGra'N II!

2CKl6 Digital 5 ignal Processing: Ashuk Arnbardar . Satya Prasad , CeIL'~, Learning, Digital S igna] Processing: MIl Hayes, Schaum's Out! ines. TAT/\ :\:_ Oraw HilL 20m,

3.
,1. 5. 6,

USP Primer - C. Britton Rorabaugh, Tala I'vfcClra\v Hill, ~()OS,

Fundamentals of Digital Signal Processing using Matlab Schilling, Sandra L, Harris. Thomson, 2007, Digital :-lignal Procesxing PIll Ed,. 2006 Roher'

Alan V Oppenheim. Ronald W, Scha:,

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