Low-Power Switched-Capacitor Integrator for Delta-Sigma ADCs

Tao Wang and Gabor C. Temes

School of Electrical Engineering and Computer Science Oregon State University Corvallis, Oregon, USA wangta@eecs.oregonstate.edu
Abstract A new low-power switched-capacitor integrator is proposed for high-resolution ADCs. Compared to the conventional switched-capacitor integrator, it achieves much lower power dissipation for the same noise specifications. To verify the effectiveness of the new integrator, and to compare it with the conventional one, a third-order delta-sigma modulator was simulated. A detailed comparison between the conventional SC integrator and the proposed SC integrator is also presented.

I.

INTRODUCTION

Switched-capacitor (SC) ADCs are widely used in high-resolution applications for their insensitiveness to parasitics and relaxed accuracy requirements. However, the SC circuit introduces kT/C noise due to the thermal noise generated by the on-resistance of the sampling switches. The oversampling ratio (OSR) in high-resolution low-to-medium bandwidth ADCs may be large, and the quantization noise in such applications is easy to suppress by increasing the loop order, internal quantizer resolution and OSR.
CI=CS/k O1 Cs1=Cs Vin Vout O2 Vdac 2Vdac O2 O1 Cs1=CS/2 O1 CI=CS/2k O2 Vin Vout O1 Cs2=CS/2 O1 O2 O1 O2

However, the kT/C noise depends only on the OSR, sampling capacitor size and input topology. For the same kT/C noise specification and the same input topology, the power dissipation of the first integrator remains almost unchanged for different OSRs. This is because the sampling capacitor size can be halved for every doubling of the OSR. The power dissipation of the input integrator with halved load and doubled speed is roughly unchanged, neglecting the parasitics and the load capacitance. The power consumption of the quantizer and the digital decimation filter is proportional to the operating speed. Therefore, the overall dissipation can be reduced by using a low OSR, while at the same time ensuring enough quantization noise suppression. However, the OSR cannot be too low. One reason is quantization noise suppression concern mentioned above; another reason is that the chip area would be very big for large sampling capacitor size. Recently, Nilchi and Johns proposed a new SC integrator which has a lower kT/C noise for the same power dissipation (or lower power dissipation for the same kT/C noise) compared to conventional SC integrator [1]. It uses a voltage doubling input branch. Fig. 1 compares the Nilchi-Johns integrator with a conventional one. The new integrator has smaller load capacitor and higher feedback factor than the conventional one, and therefore for the same clock frequency and noise, the required OTA transconductance is much smaller (by a factor of 4) than in the conventional integrator. Unfortunately, due to the doubled voltages in the input branch, the maximum allowable input voltage is halved in the new circuit. Hence, it is best suited for applications at the front end of a system, where the signal is very small. In this paper, we propose a modified structure which has the same beneficial features as the Nilchi-Johns integrator, but without the restrictions on the maximum input signal. The paper is organized as follows: Section II introduces the new SC input integrator for ADCs. Section III analyzes the new integrator, and compares its properties with those of a conventional SC integrator. In Section IV, ADCs with the new SC integrator and the conventional one are simulated and compared. Section V summarizes the paper.

(a)

(b)
Fig. 1. (a) Conventional SC integrator. (b) Nilchi-Johns integrator. This research was supported in part by the NSF Center of Analog/Digital Integrated Circuits and by the National Semiconductor Corporation.

978-1-4244-7773-9/10/$26.00 2010 IEEE

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CI O2 Vout Vcm

O1 Vin Cs/Ns Vdac O1 Vcm O2

O1 O2

O1 O2 Cs/Ns Cs/Ns

Cs/Ns O1

O1

Fig. 3 shows an equivalent kT/C noise analysis model during sampling phase 1. The power of the sampling noise voltage during 1 is kT/(OSRCs) [2]. Here, k is the Boltzmann constant, and T is the absolute temperature in degrees Kelvin. During 2, all the Ns sampling capacitors are connected in series and the effective capacitance is (Cs/Ns)/Ns. The voltage difference across this equivalent capacitance is Ns(Vin-Vdac). Therefore, this sampling scheme amplifies the difference between Vin and Vdac by a factor Ns. The power of the thermal noise charge delivered into the integration capacitor CI using the switches closed during 2 is kT(NsNs)/Cs. This value is very large for large Ns values. However, as mentioned above, the sampling capacitors in series realize a signal gain of Ns from the input Vin-Vdac. Therefore, the input-referred voltage noise power is still kT/Cs. Fig. 4 shows the noise analysis model during integration phase. III. COMPARISON WITH THE CONVENTIONAL SC INTEGRATOR

Fig. 2. The general structure of the low-power SC integrator.

II.

LOW-POWER SC INTEGRATOR

Fig. 2 shows the general structure of the new SC integrator. 1 and 2 here are non-overlapping clock phases. During 1, all the Ns sampling capacitors are connected in parallel. The effective sampling capacitor is Cs during 1. The voltage difference Vin-Vdac is stored on the sampling capacitors. Here, Vin is the input signal and Vdac is the feedback DAC output of the ADC. The difference of Vin and Vdac becomes smaller for a higher resolution feedback DAC and a more slowly moving input, which means a higher resolution internal quantizer and a higher OSR. This is true for high-resolution low-to-medium bandwidth ADCs.
CI

For comparison purpose, Figs. 5 and 6 show the conventional SC integrator and the low-power SC integrator in integration phase. Here, k is the gain of the integrator. The feedback factors C and L for the two circuits are

C = L =

Cs / k 1 = Cs / k + Cs 1 + k

(1)

C s /(kN s ) Ns = 2 C s /(kN s ) + C s / N s N s + k

(2)

O1 Vin Cs Vdac O1
Vcm

O2 Vout Vcm O2

Neglecting the parasitics and the load from the next stage, the load capacitances of the integrators in the integration phase are given by

Fig. 3. Noise analysis model in the sampling phase. Fig. 5. Conventional SC integrator in the integration phase.

Fig. 4. Noise analysis model in the integration phase.

Fig. 6. Low-power SC integrator in the integration phase.

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Fig. 7. A modified third-order low-distortion modulator with a multi-bit internal quantizer.

C L ,C = C L, L =

C s2 / k C = s Cs / k + Cs 1 + k
2 s 3 s

DACs

N O2 O2

(3)
O1 Vin O1 C1/N O1 O2
Vcm

C /(kN ) C / Ns = s 2 C s /(kN s ) + C s / N s Ns + k

(4)
Vrefp Vrefn

O1 Di

C2/N

The power of the amplifiers is proportional to the required gm [1]. Hence, it is given by

PC = k 0 g m,C = PL = k 0 g m , L =

k 0 3dB C L,C

O1 Di

C
k 0 3dB C L, L

= k 0 3dB C s k Cs = 0 3dB N s2

(5)

(6) IV.

Fig. 8. SC feedback DAC implementation.

Here, k0 is the proportionality constant between the power required and the transconductance of the amplifier, while -3dB is the closed-loop 3-dB bandwidth. Therefore, for the same kT/C noise specification, the proposed low-power SC integrator saves a significant amount of power. The saving is the same as for the Nilchi-Johns integrator. Table I compares the performances of the conventional SC integrator and the low-power SC integrator.
TABLE I. COMPARISON BETWEEN THE CONVENTIONAL SC INTEGRATOR AND LOW-POWER SC INTEGRATOR

ADC USING LOW-POWER INTEGRATOR

To verify the effectiveness of the new scheme, a modified third-order low-distortion feed-forward modulator [3] with a 15-level internal quantizer was simulated. For simplicity, Ns in Fig. 2 was chosen to be 2. This structure was used to incorporate the low-power SC integrator. By removing the delay in the feed-forward signal path, the structure becomes the standard low-distortion feed-forward modulator (SLD) [4] and was used to incorporate the conventional SC integrator for simulation. For the modified structure, the adder operates during 2. The quantization is done during the non-overlapping time. The DAC output is already available before the next phase 1. For the low-distortion feed-forward structure [4], the adder performs the addition in 1. The quantization is also done the non-overlapping time. The DAC output is available before the next phase 2. Fig. 8 shows the implementation of the feedback DAC in Fig. 7. N=14 and C1=C2=0.5Cs were used here. Di and D i are the complementary digital thermometer-code outputs from the quantizer. At the beginning of the phase 1, some of the capacitor DAC unit elements are connected to Vrefp, and the rest to Vrefn, depending on the quantizer output.
_

Conventional SC integrator Gain Sampling capacitance Integration capacitance kT/C noise Feedback factor Capacitance load Power dissipation
k

Low-power SC integrator
k

Cs Cs/k 2kT/(OSRCs) (1+k)-1 Cs(1+k)-1

k0-3dBCs

Cs Cs/(kNs) 2kT/(OSRCs)
Ns(Ns+k)-1

(Cs/Ns)(Ns+k)-1
k0-3dBCsNs-2

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Fig. 9 shows the power spectrum densities (PSDs) of the modulator outputs Vout in Fig. 7 and SLD without kT/C noise. Fig. 10 shows the output PSDs of the two modulators with kT/C noise. The simulated SNR was 86 dB for both cases for the same input signal (-4.2dBFS). However, the power dissipation of the first integrator with the low-power realization is only one-fourth of the conventional one. The effective voltage swing across the sampling capacitors of the first stage integrator in Fig. 7 is shown in Fig. 11 (normalized to the reference voltage). Fig. 12 shows the allowable Ns value versus the number of comparators in the internal quantizer of the modulator. Ns can be made as high as 4 for a 31-level internal quantizer without the voltage swing of the sampling capacitors exceeding the reference voltage of the modulator. However, the nonideal effects introduced by the floating switches may limit Ns to lower values. A dc analysis of the low-power stage [5] reveals that the input bias voltage of the opamp, provided by the SC input branch, is Vcm + Ns(Vin,a Vdac,a), where the subscript a denotes the average value. Since the dc averages Vin,a and Vdac,a are kept equal by the loop, the input bias is forced to be Vcm . The equivalent resistance connected between the opamp common mode input and the bias voltage Vcm is N s2TCs1 , where T is the cycle of the non-overlapping clocks. I.
Fig. 10. The output PSDs of the third-order modulators (kT/C noise included).

Fig. 9. The output PSDs of the third-order modulators.

CONCLUSION

A low-power integrator was described which uses voltage multiplication as the Nilchi-Johns integrator [1] but does not limit the input signal swing. The performance of the new integrator was analyzed and compared with that of the conventional integrator. The usefulness of the proposed structure was verified by simulating third-order modulators with a 15-level internal quantizer using either the conventional input integrator or the proposed low-power one. ACKNOWLEDGMENT The authors are grateful to Prof. David Johns for informing them about ref. [1], and for useful discussions.

Fig. 11. Voltage swing across the sampling capacitor. [1]

REFERENCES
A. Nilchi, D.A. Johns, Charge-pump based switched-capacitor integrator for modulators, Electron. Lett., 2010, 46, (6), pp. 400 401. R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, IEEE Press/Wiley, 2005. H. Park, K. Nam, D.K. Su, K. Vleugels and B.A. Wooley, A 0.7-V 870-W Digital-Audio CMOS Sigma-Delta Modulator, IEEE J. SolidState Circuits, vol. 44, no. 4, pp.10781088, March 2009. J. Silva, U. Moon, J. Steengard, and G. Temes, Wideband low distortion delta-sigma ADC topology, Electron. Lett., 2001, 37, (12), pp. 737738. M. Keskin, N. Keskin and G. C. Temes, An efficient and accurate dc analysis technique for switched-capacitor circuits, Analog Integrated Circuits and Signal Processing, vol. 30, pp. 239-241, March 2002.

[2] [3]

[4]

[5] Fig. 12. The achievable Ns value versus the number of comparators in the internal quantizer of the modulator.

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