EEE527: Nyquist-Rate Analog-to-Digital Converters Professor: Dr. Douglas Garrity Project 2: Matlab model of an RSD-based 1.

5-bit per stage pipelined ADC

NAME : Paramaiahgari Srikanth R ASU ID # : 1206321047

1) Model of an N-bit, RSD-based, 1.5-bit per stage, pipelined ADC is implemented in MATLAB using following flowchart and the equations shown below:

Vo e = Vio *( Gvi/(1+1/A))z-1/2 Gvi= 1 +C2/C1; Gvr= C2/C1; =C1/(C1+C2); Vref= vrefp-vrefm= 1-(-1)=2; Vh= vref/4 Vl= -vref/4

+/-

Vr *( Gvr/(1+1/A));

2) ADC output is verified by Setting N=6, vrefp to 1V, vrefm to -1V, Av=140dB, vh = vref/4 and vl = -vref/4 and then converting an input voltage of 0.432V to the correct digital value in offset binary format as 100110 corresponding to 38th code word from the bottom.

Vres value at different stages is plotted and is shown below:

3) Ramp input signal is generated with 13 inputs per code and is plotted as shown:

Histogram output for this 10 bit ADC with C2/C1=0.98 is plotted as shown below:

DNL: For C2/C1= 0.98 Av=140 dB. Missing codes are 320, 382, 576, 640, 641.

INL: for C2/C1=0.98 Av=140 dB

4) Sinewave input(first few samples are shown) 1.999V*sin(2*pi* 1.777MHz*t) with 10 MHz sampling frequency and 2^14 Samples is as follows:

Powerspectrum from DC to Fs/2:

SNDR(dB)= Mangnitude of signal bin- Sum of Magnitudes of all bins except signal= 48.9 dB ENOB= (SNDR-1.76)/6.02 = 7.83.

5) Ramp input generated as 13 samples per code word is as follows:

DNL: Missing codes are 205, 383, 410, 614, 641, 819

INL:

6) Sinewave input(first few samples are shown) 1.999V*sin(2*pi* 1.777MHz*t) with 10 MHz sampling frequency and 2^14 Samples is as follows:

Powerspectrum from DC to Fs/2:

SNDR(dB)= Mangnitude of signal bin- Sum of Magnitudes of all bins except signal= 52.9 dB ENOB= (SNDR-1.76)/6.02 = 8.499. 7) N = 12. C2/C1 is varied from 0.80 to 1.0 with steps of 0.02 and sine wave input with sampling rate 10 MHz and 2^14 samples is applied and SNDR and ENOB are calculated for each capacitor ratio. C2/C1 0.8 0.82 0.84 0.86 0.88 0.90 0.92 0.94 0.96 0.98 1.00 SNDR 28.455 29.469 30.59 31.84 33.27 34.94 36.96 39.53 43.11 49.17 68.35 ENOB 4.43 4.60 4.78 4.99 5.23 5.51 5.84 6.27 6.87 7.87 11.06

8) C2/C1= 1 with DC gain varied from 40 dB to 120 dB in 10 dB steps: Av (dB) 40 50 60 70 80 90 100 110 120 SNDR 43.95 53.40 62.16 67.16 68.25 68.34 68.359 68.357 68.355 ENOB 7.009 8.578 10.034 10.864 11.044 11.060 11.063 11.0627 11.0623

ENOB vs Amplifier gain is plotted as shown below:

9) Capacitor matching of almost 1 for 80 dB Av is required for 11 bit ENOB as same as in part 7 for 140 dB Av.