Single and Pipeline Processors

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!oey Mercler
LlecLrlcal Lnglneerlng ueparLmenL
Lakehead unlverslLy
Aprll 19, 2012
LnCl-0331-W8 LlecLrlcal Lnglneerlng ueparLmenL Lakehead unlverslLy
Slngle Cycle and lpellne rocessor - Mercler | age 2
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I|gure 1: Compar|son of S|ng|e Cyc|e (1op) and |pe||ne (8ottom) rocessor ......... 6

I|gure 2: A-Iormat 8|t Ass|gnment ........................................................................ 8

I|gure 3: 8-Iormat 8|t Ass|gnment ........................................................................ 8

I|gure 4: L-Iormat 8|t Ass|gnment ......................................................................... 9

I|gure S: Comp|ete Instruct|on Set ........................................................................ 9

I|gure 6: rocessor 8ox D|agram ......................................................................... 10

I|gure 7: S|ng|e Cyc|e Data ath ........................................................................... 2S

I|gure 8: S-Stage |pe||ne Data ath .................................................................... 26

I|gure 9: |pe||ne S|mu|at|on ............................................................................... 27
4*+1'506+.'*
A mlcroprocessor ls an lnLegraLed clrculL whlch execuLes commands used ln compuLers and
oLher compuLaLlonal devlces. 1hls reporL covers Lhe deslgn and lmplemenLaLlon of a slngle
cycle and plpellne processor. 1he processor was deslgned uslng verllog code Lhrough xlllnx
13.4 sofLware as well as lan Ahead sofLware for floor plan deslgn. 1he processor has been
lmplemenLed on a SparLan3L-xC3S300L-lC320 board Lo ensure proper funcLlonallLy.
1he processor was deslgned wlLh uslng a 8lSC archlLecLure, mlmlcklng a MlS processor
(buL exLremely slmpllfled, due Lo Lhe exLenslvely reduced lnsLrucLlon seL). When speaklng
of slngle cycle lL ls lmplled LhaL one clock cycle ls used Lo execuLe each lnsLrucLlon. 1he
processor lncluded ln Lhls reporL conslsLs of flve maln sLages, lnsLrucLlon leLch (ll),
lnsLrucLlon uecode (lu), LxecuLlon (LxL), uaLa Memory (uM) and WrlLe 8ack (W8) - all of
whlch are uLlllzed ln one cycle for one lnsLrucLlon.
1he processor deslgn uses a 16-blL lnsLrucLlon memory as well as 3 lnLernal reglsLers. 1he
uaLa Memory holds 8-blL daLa and Lhe processor uses an 8-blL lnpuL/ouLpuL. 1he deslgn of
Lhe processor was done wlLh 13 lnsLrucLlons ln mlnd.
Also lncluded ln Lhls reporL ls Lhe deslgn of a plpellne processor. 1he plpellne processor
uses Lhe same flve sLages, however, lL has lnLermedlaLe reglsLers ln beLween Lhe sLages.

I|gure 1: Compar|son of S|ng|e Cyc|e (1op) and |pe||ne (8ottom) rocessor


1he basls of Lhe plpellne processor ls LhaL Lhe lnsLrucLlons wlll be execuLed ln a Landem
fashlon wlLh proper sLalls and forwardlng. We can see ln llgure 1 LhaL Lhe Lop lmage (slngle
cycle) Lakes longer Lhen Lhe boLLom lmage (plpellne) Lo run Lhe same lnsLrucLlon seL. Whlle
boLh slngle cycle and plpellne processors can execuLe Lhe same lnsLrucLlons, lL ls clear LhaL
Lhe plpellne processor can do so wlLh a hlgher degree of performance lf properly deslgned.
1hls reporL wlll lnclude lnformaLlon on Lhe deslgn of Lhe processor, Lhe daLa paLhs Laken by
Lhe dlfferenL lnsLrucLlons, Lhe conLrol scheme, Lhe bugs encounLered whlle deslgnlng, and
flnally, a brlef dlscusslon on Lhe posslble lmprovemenLs LhaL could poLenLlally be made Lo
opLlmlze boLh Lhe slngle cycle and plpellne verslons.

8&,./*
1he processors deslgned for Lhls pro[ecL are able Lo execuLe 13 lnsLrucLlons, and Lhe
processors Lhemselves are modeled slmllarly Lo Lhe MlS archlLecLure (8lSC archlLecLure).
1he processors are deslgned on verllog PuL, and are lmplemenLed on a xlllnx SparLan 3L
lleld rogrammable CaLe Array (lCA) board. 1he processors have 3 lnLernal reglsLers (all
of whlch wlll be dlscussed laLer ln Lhls reporL), and Lhe 13 lnsLrucLlons can be broken lnLo
Lhree dlsLlncL formaLs:
1he flrsL formaL conslsLs of Lhe arlLhmeLlc funcLlons handled by Lhe processor, Lhls formaL ls
called A-formaL. 1he machlne code (or blL sLream) ls handled ln Lhe manner lllusLraLed by
llgure 2.

I|gure 2: A-Iormat 8|t Ass|gnment
As can be seen ln llgure 2, Lhe operaLlon code Lakes Lhe hlgh-order nlbble of Lhe flrsL byLe,
whlle Lhe low-order nlbble speclfles whlch reglsLers are Lo be used. 1he second byLe ls noL
used for Lhese lnsLrucLlons. 1he A-formaL ls also responslble for seLLlng a Z-flag and an n-
llag for some of lLs lnsLrucLlons (denoLlng Zero-llag" and negaLlve-llag" respecLlvely) -
however Lhls wlll be covered ln Lhe ArlLhmeLlc Loglc unlL secLlon of Lhls reporL. lor Lhe
compleLe llsL of lnsLrucLlons for Lhe A-lormaL, consulL llgure 3.
1he second formaL conslsLs of Lhe branch funcLlons, Lhls formaL ls called Lhe 8-formaL and
Lhe blL sLream ls handled by Lhe processor ln Lhe manner deplcLed by llgure 3.

I|gure 3: 8-Iormat 8|t Ass|gnment
1he 8-formaL lnsLrucLlon seL has Lhe hlgh-order nlbble of Lhe flrsL byLe dedlcaLed Lo Lhe
operaLlon code, Lhe Lwo hlghesL blLs of Lhe low-order nlbble asslgned Lo Lhe speclal branch
(brx) fleld, and Lhe remalnlng blLs of Lhe flrsL byLe are lgnored. 1he second byLe ls used for
Lhe effecLlve address. 1he 8-formaL can handle Lhree dlfferenL Lypes of branches: normal

branch, branch-lf-n or Z-flag, and branch subrouLlne (wlLh reLurn). lor Lhe compleLe llsL of
lnsLrucLlons, along wlLh Lhelr general modes of operaLlon, consulL llgure 3.
1he Lhlrd and flnal formaL ls used for memory/lmmedlaLe operaLlons, and ls called Lhe L-
formaL. llgure 4 lllusLraLes Lhe blL asslgnmenL for Lhls formaL:

I|gure 4: L-Iormat 8|t Ass|gnment
1he L-formaL ls used whenever memory operaLlons are requlred. lL enables Lhe processor
Lo sLore or load lnformaLlon lnLo Lhe memory, or sLore an lmmedlaLe value lnslde of an
lnLernal reglsLer.
ln summary, Lhe Lhree dlfferenL formaLs allow Lhe processor Lo perform slmple arlLhmeLlc
funcLlons, branches, as well as load and sLore daLa from Lhe memory. Pere ls Lhe compleLe
llsL for Lhe lnsLrucLlon seL, along wlLh a brlef explanaLlon of each lnsLrucLlon:

I|gure S: Comp|ete Instruct|on Set
:1'6&,,'1 >C&6.(.6#+.'*,
As can be seen ln Lhe flrsL deslgn secLlon, Lhe processor reads and execuLes 16-blL
lnsLrucLlons. ln addlLlon, lL has separaLe lnsLrucLlon and daLa memorles, four 1-byLe
addressable reglsLers, a speclal llnk reglsLer (used for Lhe branch subrouLlne and reLurn
funcLlons - see llgure 3), and an 8-blL (1-byLe) lnpuL and ouLpuL porL. 1he processor verllog
module (along wlLh every oLher module) can be found ln Appendlx C.
1he processor ls comprlsed of varlous dlfferenL modules, all of whlch serve Lhelr own
unlque Lask. MosL of Lhe modules are asynchronous, ln order Lo allow for slngle cycle
operaLlon (and proper plpellne operaLlon). 1he only synchronous modules are Lhe ones
whlch are able Lo wrlLe/read daLa lnLo/from memory (be lL daLa memory or lnLernal
reglsLer memory), or Lhe one whlch synchronlzes Lhe operaLlon of Lhe processor wlLh Lhe
clock (program counLer)

)%'6L )'0*+&1 #*5 M#.* :1'6&,,'1
ln order Lo correcLly LesL Lhe lmplemenLaLlon, Lhe clock raLe musL be slowed down, Lhe
clock raLe on Lhe lCA ls much Loo hlgh Lo assure correcL operaLlon of Lhe processor,
Lherefore, Lwo separaLe modules were creaLed Lo accommodaLe Lhls mlnor lnconvenlence:
a clock counLer and a maln processor unlL (see llgure 6).

I|gure 6: rocessor 8ox D|agram
1he clock lnpuL from Lhe lCA ls rouLed Lo a 20-blL clock counLer, where Lhe MS8 (or 20
Lh

blL) ls rouLed Lo Lhe processor as lLs clock lnpuL. 1hls effecLlvely slows down Lhe clock
conslderably, wlLhouL alLerlng any hardware. 1he oLher lnpuLs (Lhe lnpuL porL and reseL)

are auLomaLlcally rouLed Lo Lhe processor, and Lhe ouLpuL porL comes dlrecLly ouL of Lhe
processor. Lrgo, for acLual lmplemenLaLlon, only Lhe 20-blL counLer need be removed and
Lhe processor would funcLlon as lnLended.

M0%+.C%&A&1
1he mulLlplexer modules are sLralghLforward ln Lhelr operaLlon: Lhey are asynchronous
modules LhaL choose an lnpuL from a selecLlon of lnpuLs and pass lL Lhrough Lo Lhe ouLpuL.

>;.(+ N./;+
1he shlfL rlghL module was creaLed Lo overcome an addresslng lssue LhaL sLemmed from
changlng Lhe processor from 8-blL Lo 16-blL. 1hls lssue wlll be dlscussed ln greaLer deLall ln
Lhe 8ugs and llxes secLlon of Lhls reporL (Lo summarlze, Lhe shlfL rlghL ls used Lo dlvlde Lhe
addresses by Lwo, Lhus proacLlvely flxlng Lhe addresslng lssue).

:1'/1#? )'0*+&1
1he program counLer ls used Lo Lell Lhe processor whlch address Lo read ln Lhe lnsLrucLlon
memory (8CM). lL ls a slmple synchronous module LhaL operaLes on Lhe negaLlve edge of
Lhe clock.

F55&1
1he adder slmply adds one Lo an 8-blL lnpuL, and forwards Lhe resulL Lo lLs ouLpuL. lL ls an
asynchronous module. lL ls used Lo lncremenL Lhe program counLer.

4*,+106+.'* M&?'1O
1he lnsLrucLlon memory (8ead-Cnly Memory) ls an asynchronous module (reason behlnd
Lhls ls dlscussed ln 8ugs and llxes secLlon of Lhls reporL) LhaL was creaLed wlLh Lhe xlllnx
Loglc l Core uynamlc Memory 8lock CeneraLor. lL ls 16-blLs wlde and 236-blLs deep.

N&/.,+&1 -.%&
1he reglsLer flle conLalns Lhe lnLernal reglsLers of Lhe processor (four general purpose
reglsLers, and one llnk reglsLer). lL ls boLh a synchronous and asynchronous module. lL has
Lwo dlfferenL verslons for Lhe slngle cycle and Lhe plpellne processors.
>.*/%& )O6%& K&1,.'*
1he slngle cycle verslon of Lhe reglsLer flle ls synchronous on Lhe negaLlve edge (Lo prevenL
Llmlng confllcLs wlLh Lhe daLa memory) for wrlLe operaLlons. lL deLecLs Lhe currenL op-code
and deLermlnes wheLher or noL Lo wrlLe Lhe daLa-ln value lnLo reglsLer 8a. lf Lhe op-code
deLecLs a branch subrouLlne lnsLrucLlon, Lhe daLa ls wrlLLen lnLo Lhe llnk reglsLer lnsLead
(Lhe daLa ln Lhls case ls Lhe address C + 1).
1he reglsLer flle ls asynchronous ln Lerms of conLlnuously asslgnlng Lhe values of 8a, 8b, and
Lhe llnk reglsLer. 1hls asynchronous funcLlon allows for slngle cycle operaLlon of Lhe
processor.
:.C&%.*& K&1,.'*
1he plpellne verslon of Lhe reglsLer flle ls much llke Lhe slngle cycle verslon, excepL LhaL ls
synchronous on Lhe poslLlve edge of Lhe clock (Lo prevenL Llmlng lssues wlLh Lhe
lnLermedlaLe reglsLers and Lhe wrlLe back). lL also has Lwo exLra lnpuLs, whlch deLecL Lhe
op-code and Lhe address of 8a aL Lhe wrlLe back sLage (Lo check wheLher or noL Lhe
lncomlng value of 8a should be updaLed, and lf so, replace Lhe correcL 8a). 1he
asynchronous porLlon ls Lhe same as Lhe slngle cycle verslon.

F1.+;?&+.6 P'/.6 Q*.+ RFPQS
1he ALu ls ln charge of performlng all of Lhe arlLhmeLlc funcLlons requlred by Lhe processor.
lL ls asynchronous and has Lhree lnLernal reglsLers used for sLorlng Lhe Z-flag, n-flag, and

ouLpuL value. unforLunaLely, Lhe ALu has comblnaLorlal loops wlLh lLs reglsLers (more on
Lhls ln Lhe osslble lmprovemenLs secLlon of Lhe reporL), buL lL does noL lmpede lLs
funcLlons. 1he ALu senses Lhe op-code and performs assoclaLed Lhe arlLhmeLlc funcLlon.

8#+# M&?'1O
1he daLa memory (8andom-Access Memory) ls a synchronous module LhaL operaLes on Lhe
poslLlve edge of Lhe clock. lL was generaLed wlLh Lhe xlllnx 8lock Memory CeneraLor, and ls
8-blLs wlde, 236-blLs deep. lL has a wrlLe-enable lnpuL for wrlLe operaLlons.

)'*+1'%%&1
1he conLroller's funcLlon ls Lhe processor ls Lo conLrol mosL of Lhe mulLlplexers. lL ls an
asynchronous module.
>.*/%& )O6%& K&1,.'*
ln Lhe slngle cycle verslon, Lhe conLroller senses Lhe currenL op-code, along wlLh Lhe brx
value and generaLes an ouLpuL LhaL conLrols Lhe mulLlplexers. lL also provldes Lhe wrlLe-
enable for Lhe daLa memory (more deLalls on Lhe conLroller wlll be provlded ln Lhe uaLa
aLhs and ConLrol Scheme secLlons of Lhls reporL).
:.C&%.*& K&1,.'*
1he plpellne verslon of Lhe conLroller ls very slmllar Lo LhaL of Lhe slngle cycle, excepL LhaL lL
musL also deLecL Lhe op-code of Lhe execuLe sLage, ln order Lo correcLly lmplemenL branch
Z or branch n lnsLrucLlons (reason behlnd Lhls wlll also be explalned ln Lhe uaLa aLhs and
ConLrol Scheme secLlons of Lhls reporL).

T#U#15 8&+&6+'1 R:.C&%.*& V*%OS
1he hazard deLecLor module ls an asynchronous module LhaL ls ln charge of deLecLlng daLa
hazards LhaL cannoL be ellmlnaLed wlLh daLa forwardlng, and lmplemenLlng Lhe requlred
amounLs of plpellne sLalls ln order Lo prevenL Lhese hazards. lL deLecLs Lhe op-codes of Lhe
Lhree flrsL sLages of Lhe plpellne, as well as Lhe posslble reglsLer dependencles, and sLalls
Lhe plpellne accordlngly (more on sLalls ln Lhe uaLa aLhs secLlon of Lhls reporL).

-'1W#15.*/ Q*.+ R:.C&%.*& V*%OS
Much llke Lhe hazard deLecLor module, Lhe forwardlng unlL ls an asynchronous module LhaL
ls ln charge of ellmlnaLlng daLa hazards ln Lhe plpellne by means of forwardlng daLa Lo Lhe
lnpuLs of Lhe ALu as requlred. lL deLecLs Lhe op-codes of Lhe Lhree lasL sLages of Lhe
plpellne, along wlLh reglsLer dependencles, and acLlvaLes forwardlng mulLlplexers
accordlngly.

4*+&1?&5.#+& N&/.,+&1, R:.C&%.*& V*%OS
1he lnLermedlaLe reglsLers, llke Lhe reglsLer flle, are boLh synchronous and asynchronous
modules, Lhey are synchronous on Lhe negaLlve edge of Lhe clock Lo wrlLe Lhe daLa Lo Lhelr
lnLernal reglsLers, and are asynchronous ln conLlnuously asslgnlng Lhe values of Lhelr
reglsLers Lo Lhelr ouLpuLs.
1he flrsL lnLermedlaLe reglsLer (ll_uL_reg - can be referenced ln Appendlx C) also has Lhe
[ob of lmplemenLlng a sLall command. lL deLecLs a sLall command from Lhe hazard deLecLor
and seLs Lhe op-code Lo zero (no-op) for Lhe currenL lnsLrucLlon lf sLall ls hlgh.

8#+# :#+;
1he daLa paLhs dlscussed are accordlng Lo Lhe paLh Laken by Lhe daLa Lhrough Lhe processor.
1he paLhs can be lnLulLlvely followed by consulLlng Appendlx A aL Lhe end of Lhe reporL.


FX-'1?#+
ln Lhe processor Lhe A-lormaL lnsLrucLlons are used Lo compleLe several operaLlons, ln
parLlcular arlLhmeLlc ones. 1he formaL conslsLs of Lwo byLes buL only uLlllzes one of Lhem.
1he byLe ls spllL lnLo Lhe operands as shown ln llgure 2.
lL can be seen LhaL Lhe op-code uses Lhe four hlgh blLs of Lhe byLe and Lhe ra and rb flelds
each use Lwo of Lhe four remalnlng blLs. 1he daLa paLh followed by Lhe A-lormaL lnsLrucLlon
Lhrough Lhe processor can be seen on llgure 6 ln Appendlx A.
1he rogram CounLer selecLs Lhe lnsLrucLlon value ln Lhe lnsLrucLlon memory where Lhe A-
lormaL lnsLrucLlon ls obLalned. 1he lnsLrucLlon wlll selecL Lhe correspondlng ra and rb
reglsLers from Lhe 8eglsLer llle. lrom here Lhe value LhaL ls held ln Lhe reglsLer ra proceeds
dlrecLly Lo Lhe ArlLhmeLlc Loglc unlL where Lhe rb reglsLer value ls forwarded Lhrough a
mulLlplexor flrsL Lhen Lo Lhe ALu. ln Lhe ALu any arlLhmeLlc operaLlon ls performed and Z/n
flags are produced. lrom here Lhe paLh conLlnues Lhrough Lhe WrlLe 8ack mulLlplexor and
Lhe C2 mulLlplexor and flnally wrlLes lnLo Lhe WrlLe uaLa of Lhe 8eglsLer llle.
1o elaboraLe more on Lhe producLlon of Lhe n and Z flags Lhelr funcLlons wlll be observed.
1hese flags Lell Lhe conLroller speclflc lnformaLlon abouL Lhe ouLcome of an operaLlon.
Looklng aL Lhe A-lormaL operaLlons ln llgure 3 (op-codes 1 Lhru 8), Lhe dlfferenL n and Z
values for each op-code can be seen.
Looklng aL Lhe Auu lnsLrucLlon, for example, lL can be seen LhaL Lhe value ln Lhe Z flag wlll
be a one lf Lhe ouLcome of Lhe addlLlon ls zero oLherwlse lL wlll be zero. 1he value of Lhe n
flag wlll be one lf Lhe ouLcome ls less Lhan zero oLherwlse Lhe value of Lhe n flag wlll be
zero. 1hls operaLes ln Lhe same fashlon for Lhe Su8 and nAnu lnsLrucLlons. lor Lhe SPL,
SP8, Cu1, ln, and MCv lnsLrucLlons no n and Z flags are produced.
ln Lhe plpellne, Lhe paLh ls Lhe same (aparL from Lhe lnLermedlaLe reglsLers), and all daLa
hazards are removed by means of daLa-forwardlng.

@X-'1?#+
1he 8-lormaL lnsLrucLlons are lnlLlallzed ln Lhe same manner as Lhe prevlously dlscussed A-
lormaL: Lhe rogram CounLer polnLs Lo an address ln Lhe lnsLrucLlon Memory and Lhe
correspondlng 16-blL lnsLrucLlon ls senL onLo Lhe remalnlng processor daLa-paLh. 1he 8-
lormaL (refer Lo llgure 3, op-codes 9 Lhru 12) has dlfferenL lnsLrucLlons wlLh slmllar paLhs,
as dlscussed below.
@1#*6;
1he branch has a sLralghLforward paLh: once Lhe branch op-code ls deLecLed by Lhe
conLroller, lL selecLs Lhe correcL lnpuL from Lhe program counLer mulLlplexor (C1 mux),
whlch Lhen rouLs Lhe effecLlve address Lo Lhe rogram CounLer.
1hls lnsLrucLlon ls execuLed exacLly Lhe same way ln Lhe plpellne, excepL LhaL lL musL go
Lhrough Lhe flrsL lnLermedlaLe reglsLer, and Lherefore musL sLall Lhe plpellne one cycle
(slnce lL ls resolved ln Lhe second sLage of Lhe plpellne by Lhe ConLroller).
@1#*6; Y #*5 @1#*6; Z
1he branch n and Z are a llLLle more complex Lhan Lhelr 8-lormaL counLerparLs. Cnce Lhe
conLroller deLecLs Lhe op-code for LhaL lnsLrucLlon, lL musL Lhen deLermlne wheLher lL ls a
branch n or Z lnsLrucLlon. Cnce LhaL ls deLermlned, Lhe ConLroller musL check wheLher Lhe
correspondlng flag ls hlgh, and seL Lhe C1 mux accordlngly (lf Lhe flag ls hlgh, Lhe branch ls
Laken, lf noL, Lhe C + 1 address ls rouLed Lo Lhe rogram CounLer).
lor Lhe plpellne, Lhese branch lnsLrucLlons are resolved ln Lhe ALu sLage (Lhlrd sLage of Lhe
plpellne), whlch requlres Lwo sLall cycles Lo avold conLrol/daLa hazards.
@1#*6; >0$1'0+.*&
1he branch subrouLlne paLh ls almosL Lhe same as Lhe branch for boLh Lhe slngle cycle and
plpellne verslon. lL dlffers only ln LhaL Lhe address of C + 1 musL be wrlLLen lnLo Lhe Llnk
8eglsLer, whlch ls conLalned ln Lhe 8eglsLer llle. lor Lhe plpellne, Lhls address musL go
Lhrough Lhe flrsL lnLermedlaLe reglsLer.
N&+01*
1he reLurn paLh ls very slmple - when Lhe conLroller deLecLs Lhe reLurn op-code, lL selecLs
Lhe approprlaLe lnpuL Lo Lhe C1 mux and Lhe reLurn address LhaL was sLored lnLo Lhe Llnk
8eglsLer ls rouLed Lo Lhe rogram CounLer. 1he plpellne sLalls one cycle for reLurn.

PX-'1?#+
Llke Lhe A and 8-lormaLs, Lhe L-lormaL ls lnlLlallzed by Lhe rogram CounLer polnLlng Lo an
address ln Lhe lnsLrucLlon memory, and Lhe correspondlng 16-blL ouLpuL ls Lhen rouLed Lo
Lhe resL of Lhe modules.
P'#5
1he load lnsLrucLlon, whlch follows Lhe crlLlcal paLh for Lhe processor, musL access memory
on Lhree occaslons (lnsLrucLlon memory, daLa memory, and reglsLer flle for sLorlng Lhe
loaded daLa lnLo ra). 1he effecLlve address ls rouLed dlrecLly from Lhe lnsLrucLlon Memory
Lo Lhe address lnpuL of Lhe uaLa Memory. 1here, Lhe correspondlng daLa aL LhaL parLlcular
address ln Lhe uaLa Memory ls loaded and senL Lo Lhe daLa-ln porL of Lhe 8eglsLer llle vla
Lhe wrlLe back mulLlplexor. 1he daLa ls Lhen wrlLLen lnLo reglsLer ra. 1he ConLroller
conLrols Lhe mulLlplexors.
1he load for Lhe plpellne has a slmllar paLh, buL lncorporaLes much more, whlch lncreases
lLs complexlLy. When a load op-code ls deLecLed ln Lhe second sLage of Lhe plpellne, Lhe
Pazard ueLecLor musL deLermlne wheLher Lhere ls a dependency ln Lhe nexL lnsLrucLlon. lf
Lhere ls, Lhe plpellne ls sLalled one cycle. 1he lnsLrucLlon Lhen proceeds Lhrough Lhe
plpellne unLll lL reaches Lhe uaLa Memory, and Lhen lL loads Lhe daLa ([usL llke above). Cnce
Lhe daLa geLs rouLed Lo Lhe 8eglsLer llle vla Lhe wrlLe back mux, Lhe correspondlng ra
address from Lhe load lnsLrucLlon ls also rouLed from Lhe lasL lnLermedlaLe reglsLer lnLo Lhe
wrlLe-back address lnpuL of Lhe 8eglsLer llle. 1he daLa ls Lhen wrlLLen lnLo Lhe correcL
reglsLer.
>+'1&
1he sLore lnsLrucLlon ls much llke Lhe load, wlLhouL Lhe wrlLe back. 1he maln dlfference ls
LhaL ra musL be read from Lhe 8eglsLer llle, and Lhen lL ls rouLed Lo Lhe daLa-ln lnpuL of Lhe
uaLa Memory. 1he effecLlve address follows Lhe same paLh as Lhe load lnsLrucLlon. 1o
allow a sLore operaLlon, Lhe ConLroller sends a wrlLe-enable slgnal Lo Lhe uaLa Memory
whenever lL senses Lhe sLore op-code.
1he sLore ln Lhe plpellne ls exacLly Lhe same as Lhe slngle cycle verslon, and all hazards are
ellmlnaLed wlLh daLa forwardlng.
P'#5 4??&5.#+&
1he load lmmedlaLe funcLlon ls Lhe only L-lormaL lnsLrucLlon LhaL does noL use Lhe uaLa
Memory. 1he lmmedlaLe porLlon of Lhe blL sLream goes lnLo Lhe flrsL lnpuL porL of Lhe ALu
vla Lhe C3 mux (Lhe ConLroller deLecLs Lhe load lmmedlaLe op-code and selecLs Lhe correcL
lnpuL Lo LhaL mux), and lnslde Lhe ALu Lhe lmmedlaLe value ls copled lnLo ra (much llke a
move lnsLrucLlon). 1he resulL ls Lhen rouLed from Lhe ALu, Lhrough Lhe wrlLe-back mux,
and back lnLo Lhe 8eglsLer llle vla Lhe C2 mux (Lhe ConLroller assures Lhe correcL lnpuLs Lo
Lhe muxes are selecLed).

)'*+1'% >6;&?&
1he conLrol schemes for Lhe processors are very slmllar. ln Lhls deslgn, Lhe ConLroller has
very llmlLed funcLlons, Lhose of whlch wlll be dlscussed shorLly.
>.*/%& )O6%&
ln Lhe slngle cycle lmplemenLaLlon, Lhe ConLroller's maln funcLlon ls Lo selecL Lhe proper
mulLlplexors. As menLloned ln Lhe deslgn secLlon, lL ls an asynchronous module LhaL uses
comblnaLorlal loglc (asslgn sLaLemenL) ln order Lo make lL more effecLlve and reduce Lhe
llkellhood of laLches. 1he ConLroller deLecLs Lhe op-code, Lhe brx porLlon of Lhe blL-sLream
(only used for branch n and Z lnsLrucLlons), and Lhe n and Z flags. uependlng on Lhe
comblnaLlon of Lhese lnpuLs, lL asslgns Lhe correcL lnpuLs Lo Lhe mulLlplexors (for Lhe exacL
operaLlon, please consulL Lhe ConLroller module verllog code ln Appendlx C). AddlLlonally, lL
Lells Lhe uaLa Memory wheLher lL should enable wrlLlng (by deLecLlng a sLore lnsLrucLlon
op-code).
Slnce Lhe ConLroller was deslgned ln a mlnlmallsL way, each lndlvldual module has Lo plck
up Lhe burden of conLrol lLself. ln Lhls deslgn, Lhe modules are responslble for Lhelr own
conLrol (Lhe only excepLlon ls Lhe uaLa Memory's wrlLe-enable, whlch ls conLrolled by Lhe
ConLroller). 1he Lype of conLrol lmplemenLed ln Lhls deslgn allows for easy operaLlon and
LroubleshooLlng, slnce every module ls ln charge of lLs own faLe, a problem can be easlly
deLecLed and flxed. A dlfferenL conLrol scheme ls dlscussed laLe ln Lhe osslble
lmprovemenLs secLlon of Lhls reporL.

:.C&%.*&
As menLloned earller, Lhe only dlfference beLween Lhe plpellne and slngle cycle conLroller ls
LhaL lL musL deLecL Lhe op-code of Lhe execuLe sLage also. 1hls ls due Lo Lhe branch Z and n
lnsLrucLlons. Slnce Lhe Z and n flags musL go Lhrough Lhe lnLermedlaLe reglsLer before
golng lnLo Lhe conLroller, Lhe branch n and Z lnsLrucLlons are only resolved ln Lhe execuLe
sLage of Lhe plpellne. 1herefore, lf Lhe conLroller deLecLs a branch n or Z aL Lhe execuLe
sLage lL musL declde wheLher or noL Lo branch dependlng on Lhe flags.
1he remalnder of Lhe conLrol scheme ls Lhe same as Lhe slngle cycle verslon. 1he only
addlLlons are Lhe lorwardlng unlL Lo ellmlnaLe daLa hazards, and Lhe Pazard ueLecLor, Lo
sLall Lhe plpellne when necessary.
lor an lllusLraLed example of Lhe plpellne (Lhe op-code aL Lhe dlfferenL sLages, sLalls,
eLceLera), a screen capLure of a slmulaLlon conducLed by xlllnx lSlm was lncluded ln
Appendlx 8.

@0/, #*5 -.A&,
>.*/%& )O6%&
Whlle deslgnlng Lhe processor several seLbacks were found ln Lhe process. ln parLlcular Lhe
lssues wlLh Lhe uaLa Memory noL worklng, Lhe Llmlng lssues wlLh Lhe processor memory,
Lhe branch lssues wlLh Lhe lnsLrucLlon Memory and Lhe lan Ahead pln asslgnmenL.
llrsL off, Lhe uaLa Memory was noL belng found by ModelSlm when runnlng Lhe
behavloural LesLs, an error occurred where Lhe memory flle seemed Lo be mlsslng, even
Lhough lL was creaLed properly. ln order Lo flx Lhls problem we flrsL aLLempLed Lo follow
some onllne advlce and complle Lhe wrapper flle". We were noL able Lo acLually do Lhls so
we declded Lo go anoLher rouLe and Lry Lo use xlllnx 13.4 whlch ln Lhe end solved Lhe
problem (by uslng lSlm). 1he older verslon of xlllnx slmply dld noL recognlse Lhe lcore
generaLed memory.
1he lssue wlLh Lhe processor memory Llmlng was LhaL Lhe daLa memory and lnsLrucLlon
memory were operaLlng on Lhe same clock cycle. 1hls caused a daLa hazard slLuaLlon,
where Lhe daLa belng accessed was noL Lhe currenL daLa. lL was acLually Lhe daLa from Lhe
prevlous clock cycle. ln order Lo flx Lhls Lhe lnsLrucLlon memory was Laken off Lhe clock
compleLely and Lhe program counLer and lnsLrucLlon memory were puL on opposlLe edges
of Lhe clock (negaLlve and poslLlve respecLlvely).
Cne of Lhe larger problems LhaL were found was LhaL Lhe lnsLrucLlons ln our LesL flles were
glven ln 8-blL wlde form, wlLh each lnsLrucLlon Laklng 2-byLes. 1hls caused serlous lssues
wlLh Lhe branch sLaLemenLs, ln parLlcular wlLh reLurnlng from a branch lnsLrucLlon. 1he
lnsLrucLlon memory conflguraLlon caused Lhe wrong lnsLrucLlon Lo be carrled ouL afLer Lhe
branch. ln order Lo overcome Lhls, Lhe 2-byLes were comblned LogeLher lnLo one 16-blL
word (Lhe .coe flles were alLered). 1o assure proper addresslng afLer Lhe modlflcaLlon of Lhe
LesL flle, Lhe effecLlve address was shlfLed rlghL by 1 (dlvlslon by 2), whlch ulLlmaLely flxed
Lhe problem.
When lmplemenLlng Lhe flnal deslgn onLo Lhe lCA lL musL flrsL be run Lhrough Lhe lan
Ahead program so LhaL Lhe l/C plnLs can be asslgned. lL was ln Lhls sLage LhaL Lhe flnal
seLback was found. 1he deslgn called for a processor capable of handllng an 8-blL lnpuL.
Slnce Lhe program only speclfled 4 of Lhe 8-blLs, Lhe oLher 4 had Lo be seL Lo 0. ln order Lo
do Lhls we flrsL Lrled Lo asslgn dummy" plns Lo Lhe lnpuLs ln lan Ahead. Powever Lhe plns
we chose on Lhe lCA were ln unknown sLaLes and because of Lhls Lhere were some lnpuLs
seL Lo 1 and oLhers Lo 0. 1hls caused Lhe program Lo noL operaLe correcLly. AL second glance
we reallsed LhaL Lhe pln asslgnmenL problem could be flxed by masklng Lhe 4 unused lnpuLs
ln Lhe verllog code. 1hls was done by concaLenaLlng Lhe 4 blLs wlLh zeros so LhaL Lhey were
seL Lo 0. 1hls flxed Lhe problem of Lhe 8-blL lnpuL.
Cnce all of Lhe bugs were flxed Lhe processor ran smooLhly.
:.C&%.*&
1here were less bugs ln Lhe lpellne verslon of Lhe processor because all of Lhe ma[or
problems were handled wlLh Lhe Slngle Cycle verslon. Powever, Lhe maln problems were
caused wlLh Llmlng lssues of Lhe wrlLe back, Lhe wrong address of wrlLe back, and sLalllng
lssues wlLh hazards.

1he Llmlng lssues were slmllar Lo LhaL of Lhe slngle cycle processor ln LhaL Lhey sLemmed
from Lhe reglsLer flle and lnLermedlaLe reglsLers falllng of Lhe same edge of Lhe clock. 1hls
synchronous hazard caused a daLa problem - Lhe wrlLe back value of ra was wrlLLen on Lhe
nexL clock cycle. 1o remedy Lhls problem, Lhe reglsLer flle ln Lhe plpellne verslon was seL Lo
poslLlve edge.
AnoLher lssue wlLh Lhe wrlLe back was Lhe reglsLer flle noL geLLlng Lhe correcL address for
Lhe wrlLe back reglsLer. Cnce Lhe new value of ra made lLs way back from Lhe lnLermedlaLe
reglsLer, lL would geL wrlLLen lnLo whaLever ra address was glven back Lhe currenL operand
(whlch wasn'L always Lhe rlghL one). 1hls was flxed by maklng a paLh for Lhe correcL ra
address Lo follow Lhe daLa all Lhe way Lhrough Lo Lhe wrlLe back sLage. AddlLlonally,
anoLher lnpuL had Lo be creaLed ln Lhe reglsLer flle Lo recognlze Lhls correcL ra address.
1he lasL, and probably mosL promlnenL bug, came from problems wlLh sLalllng. When a
sLall had Lo be lmplemenLed, someLlme Lhe processor would [usL keep sLalllng forever. 1hls
was due Lo lmproper asslgnlng of Lhe sLall - whlle sLalllng one cycle dld noL pose any
problems, Lhe 2 sLall cycles for 8ranch n and Z where Lhe culprlLs. 1o flx Lhls lssue, Lhe op-
code of 3 sLages were lncorporaLed lnLo Lhe Pazard ueLecLor module, and Lhls allowed Lhe
module Lo correcLly deLecL Lhose speclflc Lwo cycle sLall hazards.

:',,.$%& 4?C1'D&?&*+,
AlLhough boLh verslons of Lhe processor work flawlessly, Lhere are a few lmprovemenLs
LhaL could be made ln order Lo make Lhem boLh beLLer and more efflclenL. 1o alLer
someLhlng LhaL ls good ln order Lo make lL beLLer ls whaL makes a producL sLand ouL
amongsL Lhe resL. 1herefore, Lhe followlng Lwo secLlons are dedlcaLed Lo dlscusslng Lhe
posslble lmprovemenLs LhaL could be made Lo boLh verslons of Lhe processor, Lhe reasons
behlnd Lhese lmprovemenLs, and flnally, how Lhey could posslbly be lmplemenLed.
>.*/%& )O6%&
VC+.?.U&5 M'D&[P'#5 4??&5.#+&[4* :'1+ :#+;,
Whlle overlooklng Lhe currenL deslgn of Lhe processor, lL was noLlced LhaL Lhe MCvL, LCAu
lMMLulA1L, and ln-C81 daLa-paLhs could be opLlmlzed. CurrenLly (as descrlbed ln Lhe
daLa-paLhs secLlon), all of Lhese lnsLrucLlons are resolved ln Lhe ALu. 1hls paLh could be
efflclenLly shorLed by bypasslng Lhe ALu alLogeLher. lf Lhose lnsLrucLlons were senL dlrecLly
Lo Lhe daLa-ln porL of Lhe reglsLer flle, Lhey could be lmmedlaLely wrlLLen lnLo Lhelr
respecLlve reglsLers. 1o lmplemenL Lhls, anoLher mulLlplexor would have Lo be creaLed ln
cascade wlLh Lhe currenL one, and Lhe ConLroller could conLrol lL.
)'*+1'%%&1
As menLloned ln Lhe ConLrol Scheme secLlon, Lhe conLroller does noL have a blg role oLher
Lhan asslgnlng Lhe mulLlplexors. WlLh Lhe advenL of Lhe opLlmlzed lnsLrucLlons above, Lhe
conLroller could have a much greaLer funcLlon, whlch could lmprove Lhe overall efflclency of
Lhe program by lmprovlng Lhe comblnaLorlal paLhs wlLhln each module. lf each module
dldn'L have Lo deLecL Lhe op-code and everyLhlng else, Lhey could all be sped up, maklng
Lhe whole processor more efflclenL.
I1#5.6#+.*/ +;& )'?$.*#+'1.#% P''C,
1he comblnaLorlal loops ln Lhe ALu could be removed by addlng exLernal synchronous-
ln/asynchronous-ouL reglsLers for Lhe flags as well as Lhe ouLpuL. 1hese lnLermedlaLe
reglsLers" would work ln Lhe same manner as Lhe lnLermedlaLe reglsLers ln Lhe plpellne
(however, Lhe senslLlvlLy of Lhe always block would noL be Lrlggered by Lhe clock, buL by a
change ln flag for Lhe respecLlve flag, or change ln ouLpuL for Lhe ouLpuL).
:.C&%.*&
N&?&5.#+& # P'#5[>#D& 8#+# T#U#15
ln Lhe plpellne, whenever a load dependency ls deLecLed, Lhe plpellned ls sLalled. Lven lf
Lhls works flawlessly, lL could be parLlally opLlmlzed for a Load/Save dependency. Slnce Lhe
save ls performed ln Lhe uaLa Memory sLage, slmple daLa forward could ellmlnaLe Lhe need
for a sLall. 1hls could be lmplemenLed slmply by addlng a mulLlplexor Lo Lhe daLa-ln of Lhe
uaLa Memory module, and could be conLrolled by Lhe already lmplemenLed lorwardlng
unlL.

N&?'D.*/ +;& >+#%% ('1 @1#*6;\ @1#*6; >0$1'0+.*&\ #*5 N&+01*
1he reLurn address of a branch subrouLlne lnsLrucLlon ls sLored lnLo Lhe lnLermedlaLe
reglsLer ln Lhe nexL cycle. 1hls could be opLlmlzed by removlng Lhe llnk reglsLer ln Lhe
reglsLer flle, and lmplemenLlng lL ln Lhe flrsL lnLermedlaLe reglsLer. 1hls way, Lhe address of
Lhe llnk reglsLer would be lmmedlaLely sLored. 1hls would allow Lhe plpellne Lo avold a sLall
for Lhe reLurn - slnce Lhe address ls consLanLly belng fed back ln Lhe lnsLrucLlon memory
sLage, Lhe slmple addlLlon of a mulLlplexor ln cascade wlLh Lhe program counLer mulLlplexor
could allow Lhe proper address be selecLed ln lleu of C + 1 (Lhls mulLlplexor would have Lo
be conLrolled by Lhe Pazard ueLecLor, avoldlng Lhe need Lo go lnLo Lhe second sLage of Lhe
plpellne).
1he same ls Lrue for Lhe branch and branch subrouLlne lnsLrucLlons: lf Lhey could be
handled by Lhe Pazard ueLecLor lnsLead of Lhe ConLroller, Lhere would be no need for a
sLall for elLher of Lhem (slnce Lhey would be resolved ln Lhe flrsL sLage of Lhe plpellne), Lhus
dramaLlcally lmprovlng performance. lf Lhls was lmplemenLed, only load hazards (noL
lncludlng wlLh save dependency), along wlLh branch n and Z, would need Lo sLall Lhe
plpellne.
)'*6%0,.'*
1he lmplemenLaLlons of Lhe slngle cycle and plpellne processors were a success.
1he processors ran flawlessly on Lhe lCA board, wlLh no reporLable lssues. Lven lf Lhe
plpellne verslon was much more complex Lhan Lhe slngle cycle verslon, lLs lmplemenLaLlon
was falrly easy. 1hls was because mosL of Lhe ma[or lssues were recLlfled whlle Lhe slngle
cycle was deslgned.
As menLloned LhroughouL Lhls reporL, conLlnuous asslgn sLaLemenLs (comblnaLorlal
loglc) were used Lo deslgn Lhe bulk of Lhe modules. 1hls was Lo promoLe efflclenL
programmlng - whlle Lhe always block ls a greaL way Lo program, lL can lead Lo laLches and
oLher lssues whlch could cause problems. AddlLlonally, asslgn sLaLemenLs are all execuLed
aL Lhe same Llme, whlch favors parallellsm, anoLher key componenL Lo efflclency (Lhe
always block execuLes lLs sLaLemenLs sequenLlally).
1he proposed lmprovemenLs dlscussed ln Lhls reporL are only LheoreLlcal, and Lo
acLually lmplemenL Lhem would demand for an overhaul of Lhe verllog code. 1hls ls Lhe
maln reason why Lhey were noL lmplemenLed ln Lhe flrsL place. Cnce Lhe processor worked,
lL was declded LhaL lL should noL be excesslvely Lampered wlLh, only lmprovlng lL wlLh mlnor
changes. 1he ma[or changes were documenLed and lncluded ln Lhe lmprovemenL secLlon,
and lL musL be noLed LhaL Lhey would dramaLlcally lncrease laLency for Lhe plpellne.

!""#$%&' ! ) *+,+ -+,./
0&$12# 3452#

!"#$%& () *"+#,& -./,& 0121 3124

!"#$%"&$

!"#$%& () *+,-.#& /"0&1"2& 3.-. /.-4


!""#$%&' ) * +&,&$' -.&/ 0&"#,&$# 1'2/",#

!"#$%& () *"+&,"-& ."/$,01"2-
!""#$%&' ) * +#,&-./ ).%#
1he followlng pages conslsL of Lhe acLual verllog code. 1he modules LhaL have dlfferenL verslons for Lhe Slngle Cycle and
Lhe lpellne lmplemenLaLlons wlll be dlvlded lnLo Lhelr Lwo respecLlve verslons.
!%%#,
module adder1(ln, ouL),

lnpuL [7:0] ln,
ouLpuL [7:0] ouL,

asslgn ouL = ln + 1,

endmodule
!01 2!23
module alu_nand(a, b, ouL),

lnpuL [7:0] a, b,
ouLpuL [7:0] ouL,

asslgn ouL[0] = (a[0] == 1 && b[0] == 1) ? 0 : 1,
asslgn ouL[1] = (a[1] == 1 && b[1] == 1) ? 0 : 1,
asslgn ouL[2] = (a[2] == 1 && b[2] == 1) ? 0 : 1,
asslgn ouL[3] = (a[3] == 1 && b[3] == 1) ? 0 : 1,
asslgn ouL[4] = (a[4] == 1 && b[4] == 1) ? 0 : 1,
asslgn ouL[3] = (a[3] == 1 && b[3] == 1) ? 0 : 1,
asslgn ouL[6] = (a[6] == 1 && b[6] == 1) ? 0 : 1,
asslgn ouL[7] = (a[7] == 1 && b[7] == 1) ? 0 : 1,

endmodule

!01
module ALu(ln1, ln2, ln_porL, fxn, n_flag, z_flag, resulL, ouL_porL),

lnpuL [7:0] ln1, ln2, ln_porL, // ln1 = rb/lmm., ln2 = ra
lnpuL [3:0] fxn,
ouLpuL n_flag, z_flag,
ouLpuL [7:0] resulL, ouL_porL,

reg [7:0] ouL_sLore,
reg z_sLore, n_sLore,

wlre [7:0] nand_lnL,


alu_nand u0(
.a(ln1),
.b(ln2),
.ouL(nand_lnL)
),

asslgn resulL = (fxn == 1) ? ln1 + ln2 : // add
(fxn == 2) ? ln2 - ln1 : // sub
(fxn == 3) ? nand_lnL : // nand
(fxn == 4) ? ln2 << 1 : // shlfL lefL
(fxn == 3) ? ln2 >> 1 : // shlfL rlghL
(fxn == 7) ? [4'b0000,ln_porL[3:0]} : // ra = ln porL
(fxn == 8 || fxn == 13) ? ln1 : 0, // ra = rb or ra = lmm.

asslgn z_flag = (((fxn == 1 || fxn == 2 || fxn == 3) && resulL == 0) ||
(fxn == 4 && ln2[7] == 1) || (fxn == 3 && ln2[0] == 1)) ? 1 :
(((fxn == 1 || fxn == 2 || fxn == 3) && resulL != 0) ||
(fxn == 4 && ln2[7] != 1) || (fxn == 3 && ln2[0] != 1)) ? 0 : z_sLore,

asslgn n_flag = ((fxn == 1 || fxn == 2 || fxn == 3) && resulL[7] == 1) ? 1 :
((fxn == 1 || fxn == 2 || fxn == 3) && resulL[7] != 1) ? 0 : n_sLore,

asslgn ouL_porL = (fxn == 6) ? ln2 : ouL_sLore,

always [(ouL_porL)
begln
ouL_sLore = ouL_porL, // laLch ln Lhe ouL-porL unLll lL ls changed
end

always [(z_flag)
begln
z_sLore = z_flag, // laLch ln Lhe z-flag unLll lL ls changed
end

always [(n_flag)
begln
n_sLore = n_flag, // laLch ln Lhe n-flag unLll lL ls changed
end

endmodule

!"#$% !#'()*+
module clk_counLer(clk, ouL),

lnpuL clk,
ouLpuL[19:0] ouL,
reg [19:0] ouL,

always [(posedge clk)
begln
lf (ouL==20'b11111111111111111111)
ouL = 0,
else
ouL = ouL + 1,
end

endmodule

!"#$%"&&'%
)*#+&' !,-&' .'%/*"#
module conLroller(opcode, brx, z_flag, n_flag, mux1, dm_we, mux2, mux3, mux4),

lnpuL [3:0] opcode,
lnpuL [1:0] brx,
lnpuL z_flag, n_flag,
ouLpuL [1:0] mux1,
ouLpuL dm_we, mux2, mux3, mux4,

asslgn dm_we = (opcode == 14) ? 1 : 0,

asslgn mux1 = ((opcode == 9 || opcode == 11) ||
(opcode == 10 && ((brx == 0 && z_flag == 1) || (brx == 1 && n_flag == 1)))) ? 2 :
(opcode == 12) ? 1 : 0,

asslgn mux2 = (opcode == 11) ? 0 : 1,



endmodule

0*1'&*#' .'%/*"#
module conLroller(opcode, exehb, z_flag, n_flag, mux1, dm_we, mux2, mux3, mux4),

lnpuL [3:0] opcode,
lnpuL [7:0] exehb,
lnpuL z_flag, n_flag,
ouLpuL [1:0] mux1,
ouLpuL dm_we, mux2, mux3, mux4,

wlre [1:0] brx,
wlre [3:0] exe_opcode,


asslgn brx = exehb[3:2],
asslgn exe_opcode = exehb[7:4],

asslgn dm_we = (opcode == 14) ? 1 : 0,

asslgn mux1 = (opcode == 9 || opcode == 11) ? 2 :
(exe_opcode == 10 && ((brx == 0 && z_flag == 1) || (brx == 1 && n_flag == 1))) ? 3 :
(opcode == 12) ? 1 : 0,




endmodule

!"#$%&'$()" +,$'-./,')0, !"$,%1,0(2$, 3,4(#$,% 56(7,8(", 9"8:;
module ll_uL_reg (clk, sLalll, sLalll2, pc_1l, lnsLrl, lrl, sLallo, pc_1o, lnsLro, lro),

lnpuL clk,
lnpuL [1:0] sLalll, sLalll2,
lnpuL [7:0] pc_1l,
lnpuL [13:0] lnsLrl,
lnpuL [7:0] lrl,

ouLpuL [1:0] sLallo,
ouLpuL [7:0] pc_1o,
ouLpuL [13:0] lnsLro,
ouLpuL [7:0] lro,

reg [1:0] ln1,
reg [7:0] ln3, ln3,
reg [13:0] ln4,

always [(negedge clk) // wrlLe values ln
begln
lf (sLalll > 0 || sLalll2 > 0) // lf sLall ls deLecLed
begln
ln4 = [4'b0000, lnsLrl[11:0]}, // seL opcode Lo 0 - sLall (noop)
lf (sLalll2 == 1) ln1 = 0, // lf already sLalled once sLall, seL sLall Lo zero for nexL cycle

else ln1 = sLalll - 1, // decrease sLall by 1
end
else begln
ln1 = sLalll,
ln3 = pc_1l,
ln4 = lnsLrl,
ln3 = lrl,
end
end

asslgn sLallo = ln1,
asslgn pc_1o = ln3,
asslgn lnsLro = ln4,
asslgn lro = ln3,

endmodule

!"#$%"&'("#)*" ,-*"./"%01*" 2"304*". 5607"80-" 9-8:;
module uL_LxL_reg (clk, conLl, n_l, z_l, hbl, rbl, ral, addrl, conLo, n_o, z_o, hbo, rbo, rao, addro),

lnpuL clk,
lnpuL [3:0] conLl,
lnpuL n_l, z_l,
lnpuL [7:0] hbl, rbl, ral, addrl,

ouLpuL [3:0] conLo,
ouLpuL n_o, z_o,
ouLpuL [7:0] hbo, rbo, rao, addro,

reg [3:0] ln1,
reg ln2, ln3,
reg [7:0] ln4, ln3, ln6, ln7,

begln
ln1 = conLl,
ln2 = n_l,
ln3 = z_l,
ln4 = hbl,
ln3 = rbl,
ln6 = ral,
ln7 = addrl,
end

asslgn conLo = ln1,
asslgn n_o = ln2,
asslgn z_o = ln3,
asslgn hbo = ln4,
asslgn rbo = ln3,
asslgn rao = ln6,
asslgn addro = ln7,

endmodule


!"#$%&#'()&) +#,-./ 01&#.,#23)&# 4#536&#. 7839#:31# ;1:/<
module LxL_uM_reg (clk, conLl, hbl, resl, ral, addrl, conLo, hbo, reso, rao, addro),

lnpuL clk,
lnpuL [3:0] conLl,
lnpuL [7:0] hbl, resl, ral, addrl,

ouLpuL [3:0] conLo,
ouLpuL [7:0] hbo, reso, rao, addro,

reg [3:0] ln1,
reg [7:0] ln2, ln3, ln4, ln3,

begln
ln1 = conLl,
ln2 = hbl,
ln3 = resl,
ln4 = ral,
ln3 = addrl,
end

asslgn conLo = ln1,
asslgn hbo = ln2,
asslgn reso = ln3,
asslgn rao = ln4,
asslgn addro = ln3,

endmodule

()&) +#,-./'=.3&# >)$? 01&#.,#23)&# 4#536&#. 7839#:31# ;1:/<
module uM_W8_reg (clk, conLl, hbl, resl, dml, conLo, hbo, reso, dmo),

lnpuL clk,
lnpuL [3:0] conLl,
lnpuL [7:0] hbl, resl, dml,

ouLpuL [3:0] conLo,
ouLpuL [7:0] hbo, reso, dmo,

reg [3:0] ln1,
reg [7:0] ln2, ln3, ln4,

begln
ln1 = conLl,
ln2 = hbl,
ln3 = resl,
ln4 = dml,
end

asslgn conLo = ln1,
asslgn hbo = ln2,
asslgn reso = ln3,
asslgn dmo = ln4,

endmodule

!"#" %&'("')*+, -+*# ./*012*+1 3+245
module fwd_unlL(de_exe, exe_dm, dm_wb, ouL, ouLb),

lnpuL [7:0] de_exe, exe_dm, dm_wb, // 8-blL Plgh-8yLe from lM for dlfferenL sLages
ouLpuL [1:0] ouL, ouLb, // mux sel

wlre [3:0] opcode1, opcode2, opcode3, // opcodes from 3 dlfferenL sLages
wlre [1:0] ra1, ra2, ra3, rb1, // ra address from 3 dlfferenL sLages

asslgn opcode1 = de_exe[7:4],
asslgn opcode2 = exe_dm[7:4],
asslgn opcode3 = dm_wb[7:4],

asslgn ra1 = de_exe[3:2],
asslgn ra2 = exe_dm[3:2],
asslgn ra3 = dm_wb[3:2],

asslgn rb1 = de_exe[1:0],

asslgn ouL = (((opcode1 >= 1 && opcode1 <= 8) || (opcode1 >= 13 && opcode1 <= 13)) && // lf oper. 8eq. 8A
(((ra1 == ra2) && opcode3 != 13) && // no load ln W8 sLage and 8a.LxL = 8a.uM
((opcode2 >= 1 && opcode2 <= 3) || opcode2 == 7 || opcode2 == 8 || opcode2 == 13))) ? 1 :
// lwd from uM sLage
((((opcode1 >= 1 && opcode1 <= 8) || (opcode1 >= 13 && opcode1 <= 13)) && // lf op req 8A
((ra1 != ra2) || (opcode2 == 0 || opcode2 == 6 || (opcode2 >= 9 && opcode2 <= 14)))) &&
// lf uM sLage noL conLalnlng modlfled 8A
((ra1 == ra3) && ((opcode3 >= 1 && opcode3 <= 3) ||
opcode3 == 7 || opcode3 == 8 || opcode3 == 13 || opcode3 == 13))) ? 2 : 0,

asslgn ouLb = (((opcode1 >= 1 && opcode1 <= 3) || (opcode1 == 8)) && // lf operaLlon requlrlng 88
(((rb1 == ra2) && opcode3 != 13) && // no load ln W8 sLage and 8a.LxL = 8a.uM
((opcode2 >= 1 && opcode2 <= 3) || opcode2 == 7 || opcode2 == 8 || opcode2 == 13))) ? 1 :
// lwd from uM sLage
((((opcode1 >= 1 && opcode1 <= 3) || (opcode1 == 8)) && // lf op req 88
((rb1 != ra2) || (opcode2 == 0 || opcode2 == 6 || (opcode2 >= 9 && opcode2 <= 14)))) &&
// lf uM sLage noL conLalnlng modlfled 8A
((rb1 == ra3) && ((opcode3 >= 1 && opcode3 <= 3) ||

opcode3 == 7 || opcode3 == 8 || opcode3 == 13 || opcode3 == 13))) ? 2 : 0,

endmodule

!"#"$% '()(*)+$ ,-./(0.1( 21034
module haz_deLecL(lm_hb, lf_de, de_exe, sLall, mux),

lnpuL [7:0] lm_hb, lf_de, de_exe,
ouLpuL [1:0] sLall, // lf sLall = 1 (sLall one cycle)

ouLpuL mux,

wlre [3:0] opcode1, opcode2, opcode3,
wlre [1:0] ra1, ra2, rb1,

asslgn opcode1 = lm_hb[7:4],
asslgn opcode2 = lf_de[7:4],
asslgn opcode3 = de_exe[7:4],
asslgn ra1 = lm_hb[3:2],
asslgn ra2 = lf_de[3:2],
asslgn rb1 = lm_hb[1:0],

asslgn sLall = ((opcode2 == 9 || opcode2 == 10 || opcode2 == 11 || opcode2 == 12 ||
(opcode2 == 13 && (((opcode1 >= 1 && opcode1 <= 6) || (opcode1 == 8) || (opcode1 == 14)) &&
(ra1 == ra2 || rb1 == ra2)))) || // any branch or load
(opcode2 == 0 && opcode3 == 10)) ? 1 : 0, // sLall addlLlonal cycle for br.x

asslgn mux = (sLall > 0) ? 1 : 0, // lf sLall, selecL C + 0, noL C + 1

endmodule

560)./0(7($
*lor slmpllclLy, only Lhe 3 Lo 1 mux ls lncluded (Lhe 2-1 and 4-1 are almosL lndenLlcal)
module mux3_1(sel, ln1, ln2, ln3, ouL),

lnpuL [1:0] sel,
lnpuL [7:0] ln1, ln2, ln3,
ouLpuL [7:0] ouL,

asslgn ouL = (sel == 0) ? ln1 : (sel == 1) ? ln2: ln3,

endmodule

!"#$%&&#"
()*+,% -.$,% /%"&)#*
module processor(ln_porL, clk, rsL, ouL_porL),

lnpuL [7:0] ln_porL,
lnpuL clk, rsL,
ouLpuL [7:0] ouL_porL,

wlre [3:0] conL_ouL, // conLroller ouLpuLs (mux's and mem wrlLe)
wlre [7:0] pc_ln, pc_ouL, pc_2, pc_1, // program counLer connecLors
wlre [13:0] lm_ouL, // lnsLrucLlon mem ouLpuL
wlre [7:0] rf_wrdaLa, rf_lr, rf_ra, rf_rb, // 8eg llle connecLors
wlre [7:0] alu_ln1, alu_resulL, // ALu ln/ouLs
wlre z_flag, n_flag, // ALu ouLs
wlre [7:0] daLa_mem_ouL, wb_ouL, // uaLa mem ouL and WrlLe back mux ouL
wlre [7:0] brn_addr, // branch address

mux3_1 p0( // mux 1
.sel(conL_ouL[1:0]),
.ln1(pc_1),
.ln2(rf_lr),
.ln3(brn_addr),
.ouL(pc_ln)
),

prog_counLer p1(
.ln(pc_ln),
.clk(clk),
.rsL(rsL),
.ouL(pc_ouL)
),

adder1 p2(
.ln(pc_ouL),
.ouL(pc_1)
),

lm_noclk p3 (
.a(pc_ouL), // lnpuL [7 : 0] a
.spo(lm_ouL) // ouLpuL [13 : 0] spo
),

shlfL_rlghL2 p4( // dlvlde branch address by Lwo Lo compensaLe for 16-blL lnsLrucLlon Memory
.ln(lm_ouL[7:0]),
.ouL(brn_addr)
),

conLroller p3(
.opcode(lm_ouL[13:12]),

.brx(lm_ouL[11:10]),
.z_flag(z_flag),
.n_flag(n_flag),
.mux1(conL_ouL[1:0]),
.dm_we(conL_ouL[3]),
.mux2(conL_ouL[2]),
.mux3(conL_ouL[3]),
.mux4(conL_ouL[4])
),

mux2_1 p6( // mux 2
.sel(conL_ouL[2]),
.ln1(pc_1),
.ln2(wb_ouL),
.ouL(rf_wrdaLa)
),

reg_flle p7(
.opcode(lm_ouL[13:12]),
.clk(clk),
.rd_reg(lm_ouL[9:8]),
.wr_reg(lm_ouL[11:10]),
.daLa_ln(rf_wrdaLa),
.daLa_ouL1(rf_rb),
.daLa_ouL2(rf_ra),
.rllnk(rf_lr)
),

mux2_1 p8( // mux 3
.sel(conL_ouL[3]),
.ln1(rf_rb),
.ln2(lm_ouL[7:0]),
.ouL(alu_ln1)
),

ALu p9(
.ln1(alu_ln1),
.ln2(rf_ra),
.ln_porL(ln_porL),
.fxn(lm_ouL[13:12]),
.n_flag(n_flag),
.z_flag(z_flag),
.resulL(alu_resulL),
.ouL_porL(ouL_porL)
),

daLa_mem p10 (
.clka(clk), // lnpuL clka
.wea(conL_ouL[3]), // lnpuL [0 : 0] wea
.addra(lm_ouL[7:0]), // lnpuL [7 : 0] addra
.dlna(rf_ra), // lnpuL [7 : 0] dlna
.douLa(daLa_mem_ouL) // ouLpuL [7 : 0] douLa
),

mux2_1 p11( // mux 4
.sel(conL_ouL[4]),
.ln1(daLa_mem_ouL),
.ln2(alu_resulL),
.ouL(wb_ouL)
),

endmodule

!"#$%"&$ ($)*"+&
module processor(ln_porL, clk, rsL, ouL_porL),

lnpuL clk, rsL,

// lnsLrucLlon leLch SLage
wlre [7:0] pc_ln, pc_ouL, pc_2, hazmux_pc, lf_reg_lr, ea_shL, ea2_shL,
wlre [13:0] lm_ouL,
wlre [1:0] sLallw,
wlre hazmux,

// lnsLrucLlon uecode SLage
wlre [13:0] de_reg_lm_ouL,
wlre [7:0] de_reg_pc_2, rf_lr, rf_daLaln, rf_ra, rf_rb,
wlre de_reg_z, de_reg_n,
wlre [3:0] conL_ouL,
wlre [1:0] de_reg_sLall,
wlre [2:0] de_reg_conLouL,

// LxecuLlon SLage
wlre [7:0] exe_reg_lmhb, exe_reg_rb, exe_reg_ra, exe_reg_lmlb, mux3_ouL, alu_ln1, alu_ln2, alu_res,
wlre exe_reg_z, exe_reg_n,
wlre [3:0] exe_reg_conLouL,
wlre [1:0] fwdmux, fwdmuxb,

// uaLa Memory SLage
wlre [7:0] dm_reg_alures, dm_reg_ra, dm_reg_lmlb, dm_reg_lmhb, daLa_mem_ouL,
wlre [3:0] dm_reg_conLouL,

// WrlLe 8ack SLage
wlre [7:0] wb_reg_lmhb, wb_reg_daLamem, wb_reg_alures, wbmux_val,
wlre [3:0] wb_reg_conLouL,


mux4_1 ll0( // mux 1
.sel(conL_ouL[1:0]),
.ln1(hazmux_pc),
.ln2(lf_reg_lr),
.ln3(ea_shL),
.ln4(ea2_shL),
.ouL(pc_ln)
),

prog_counLer ll1(
.ln(pc_ln),
.clk(clk),
.rsL(rsL),
.ouL(pc_ouL)
),

adder1 ll2(
.ln(pc_ouL),
.ouL(pc_2)
),

mux2_1 ll3 ( // hazard mux
.sel(hazmux),
.ln1(pc_2),
.ln2(pc_ouL),
.ouL(hazmux_pc)
),

lm_noclk ll4 (
.a(pc_ouL), // lnpuL [7 : 0] a
.spo(lm_ouL) // ouLpuL [13 : 0] spo
),

haz_deLecL ll3 (
.lm_hb(lm_ouL[13:8]),
.lf_de(de_reg_lm_ouL[13:8]),
.de_exe(exe_reg_lmhb),
.sLall(sLallw),
.mux(hazmux)
),

shlfL_rlghL2 ll6 (
.ln(de_reg_lm_ouL[7:0]),
.ouL(ea_shL)
),

shlfL_rlghL2 ll7 (
.ln(exe_reg_lmlb),
.ouL(ea2_shL)
),

ll_uL_reg 8LC0 (
.clk(clk),
.sLalll(sLallw),
.sLalll2(de_reg_sLall),
.pc_1l(pc_2),
.lnsLrl(lm_ouL),
.lrl(rf_lr),
.sLallo(de_reg_sLall),
.pc_1o(de_reg_pc_2),
.lnsLro(de_reg_lm_ouL),
.lro(lf_reg_lr)
),

// lnsLrucLlon uecode

mux2_1 lu0 ( // mux 2
.sel(conL_ouL[2]),
.ln1(de_reg_pc_2),
.ln2(wbmux_val),
.ouL(rf_daLaln)
),

reg_flle lu1 (
.opcode(de_reg_lm_ouL[13:12]),
.wr_op(wb_reg_lmhb[7:4]),
.clk(clk),
.rd_reg(de_reg_lm_ouL[9:8]),
.wr_reg(de_reg_lm_ouL[11:10]),
.wb_reg(wb_reg_lmhb[3:2]),
.daLa_ln(rf_daLaln),
.daLa_ouL1(rf_rb),
.daLa_ouL2(rf_ra),
.rllnk(rf_lr)
),

conLroller lu3 (
.opcode(de_reg_lm_ouL[13:12]),
.exehb(exe_reg_lmhb),
.z_flag(de_reg_z),
.n_flag(de_reg_n),
.mux1(conL_ouL[1:0]),
.dm_we(conL_ouL[3]),
.mux2(conL_ouL[2]),
.mux3(conL_ouL[3]),
.mux4(conL_ouL[4])
),

uL_LxL_reg 8LC1 (

.clk(clk),
.conLl(conL_ouL),
.n_l(exe_reg_n),
.z_l(exe_reg_z),
.hbl(de_reg_lm_ouL[13:8]),
.rbl(rf_rb),
.ral(rf_ra),
.addrl(de_reg_lm_ouL[7:0]),
.conLo(exe_reg_conLouL),
.n_o(de_reg_n),
.z_o(de_reg_z),
.hbo(exe_reg_lmhb),
.rbo(exe_reg_rb),
.rao(exe_reg_ra),
.addro(exe_reg_lmlb)
),

// LxecuLe SLage

mux2_1 LxL0 ( // mux 3
.sel(exe_reg_conLouL[3]),
.ln1(exe_reg_rb),
.ln2(exe_reg_lmlb),
.ouL(mux3_ouL)
),

mux3_1 LxL1 ( // lorwardlng Mux
.sel(fwdmux),
.ln1(exe_reg_ra),
.ln2(dm_reg_alures),
.ln3(wbmux_val),
.ouL(alu_ln2)
),

ALu LxL2 (
.ln1(alu_ln1),
.ln2(alu_ln2),
.ln_porL(ln_porL),
.fxn(exe_reg_lmhb[7:4]),
.n_flag(exe_reg_n),
.z_flag(exe_reg_z),
.resulL(alu_res),
.ouL_porL(ouL_porL)
),

fwd_unlL LxL3 (
.de_exe(exe_reg_lmhb),
.exe_dm(dm_reg_lmhb),
.dm_wb(wb_reg_lmhb),
.ouL(fwdmux),
.ouLb(fwdmuxb)
),

mux3_1 LxL4 (
.sel(fwdmuxb),
.ln1(mux3_ouL),
.ln2(dm_reg_alures),
.ln3(wbmux_val),
.ouL(alu_ln1)
),

LxL_uM_reg 8LC2 (
.clk(clk),
.conLl(exe_reg_conLouL),
.hbl(exe_reg_lmhb),
.resl(alu_res),
.ral(alu_ln2),
.addrl(exe_reg_lmlb),
.conLo(dm_reg_conLouL),
.hbo(dm_reg_lmhb),
.reso(dm_reg_alures),
.rao(dm_reg_ra),
.addro(dm_reg_lmlb)
),

// uaLa Memory and WrlLe 8ack SLages

daLa_mem uM0 (
.clka(clk), // lnpuL clka
.wea(dm_reg_conLouL[3]), // lnpuL [0 : 0] wea
.addra(dm_reg_lmlb), // lnpuL [7 : 0] addra
.dlna(dm_reg_ra), // lnpuL [7 : 0] dlna
.douLa(daLa_mem_ouL) // ouLpuL [7 : 0] douLa
),

uM_W8_reg 8LC3 (
.clk(clk),
.conLl(dm_reg_conLouL),
.hbl(dm_reg_lmhb),
.resl(dm_reg_alures),
.dml(daLa_mem_ouL),
.conLo(wb_reg_conLouL),
.hbo(wb_reg_lmhb),
.reso(wb_reg_alures),
.dmo(wb_reg_daLamem)
),

mux2_1 W80 ( // mux 4
.sel(wb_reg_conLouL[4]),

.ln1(wb_reg_daLamem),
.ln2(wb_reg_alures),
.ouL(wbmux_val)
),

endmodule

!"#$"%& (#)*+,"
module prog_counLer(ln, clk, rsL, ouL),

lnpuL [7:0] ln,
lnpuL clk, rsL,
ouLpuL [7:0] ouL,

reg [7:0] ouL,

always [(negedge clk)
begln
// lf sLarLup or reseL, lnlLlallze/resLarL counLer Lo 0
lf (rsL == 1) ouL = 0,
else ouL = ln,
end

endmodule

-,$./+," 0.1,
2.*$1, (341, 5,"/.#*
module reg_flle(opcode, clk, rd_reg, wr_reg, daLa_ln, daLa_ouL1, daLa_ouL2, rllnk),

lnpuL [3:0] opcode,
lnpuL clk,
lnpuL [1:0] rd_reg, wr_reg,
lnpuL [7:0] daLa_ln,
ouLpuL [7:0] daLa_ouL1, daLa_ouL2, rllnk,

reg [7:0] rf_reg[0:4], // 0 = r0, ... , 4 = llnk reglsLer

wlre we,

asslgn we = (opcode == 0 || opcode == 6 || opcode == 9 || opcode == 10 || opcode == 11 || opcode == 12 || opcode ==
14) ? 0 : 1,

asslgn rllnk = rf_reg[4],
asslgn daLa_ouL1 = rf_reg[rd_reg],
asslgn daLa_ouL2 = rf_reg[wr_reg],
always [(negedge clk) // sLore daLa ln reglsLers
begln
lf (we) rf_reg[wr_reg] = daLa_ln,
lf (opcode == 1) rf_reg[4] = daLa_ln,
end

endmodule

!"#$%"&$ ($)*"+&
module reg_flle(opcode, wr_op, clk, rd_reg, wr_reg, wb_reg, daLa_ln, daLa_ouL1, daLa_ouL2, rllnk),

lnpuL [3:0] opcode, wr_op,
lnpuL clk,
lnpuL [1:0] rd_reg, wr_reg, wb_reg,
lnpuL [7:0] daLa_ln,
ouLpuL [7:0] daLa_ouL1, daLa_ouL2, rllnk,

reg [7:0] rf_reg[0:4], // 0 = r0, ... , 4 = llnk reglsLer

wlre we,

asslgn we = (wr_op == 0 || wr_op == 6 || wr_op == 9 || wr_op == 10 || wr_op == 11 || wr_op == 12 || wr_op == 14) ?
0 : 1,

asslgn rllnk = rf_reg[4],
asslgn daLa_ouL1 = rf_reg[rd_reg],
asslgn daLa_ouL2 = rf_reg[wr_reg],

always [(posedge clk) // sLore daLa ln reglsLers
begln
lf (we == 1) rf_reg[wb_reg] = daLa_ln,
lf (opcode == 11) rf_reg[4] = daLa_ln,
end

endmodule

,-"& !)+.$**+) ,+/0%$ 1+) 2!34 56"78 *%+6 .%+.9:
module sc_processor(ln_porL, clk, rsL, ouL_porL),

lnpuL clk, rsL,

wlre [19:0] clk_slow,

clk_counLer s0(
.clk(clk),
.ouL(clk_slow)

),

processor s1(
.ln_porL(ln_porL),
.clk(clk_slow[19]),
.rsL(rsL),
.ouL_porL(ouL_porL)
),

endmodule

!"#$% '#("%
module shlfL_rlghL2(ln, ouL),

lnpuL [7:0] ln,
ouLpuL [7:0] ouL,

asslgn ouL = ln >> 1, // shlfL rlghL 1 blL (dlvlde by Lwo)

endmodule


!"#$%&&#" (%&)*%+$,
module 18_processor,
// lnpuLs
reg [7:0] ln_porL,
reg clk,
reg rsL,

// CuLpuLs
wlre [7:0] ouL_porL,

// lnsLanLlaLe Lhe unlL under 1esL (uu1)
processor uuL (
.ln_porL(ln_porL),
.clk(clk),
.rsL(rsL),
.ouL_porL(ouL_porL)
),

lnlLlal begln
// lnlLlallze lnpuLs
ln_porL = 8'b00001111,
clk = 0,
rsL = 1,

// WalL 100 ns for global reseL Lo flnlsh
#100,
[(posedge clk)
[(posedge clk)
[(posedge clk)
[(posedge clk)
[(posedge clk)
rsL = 0,

// Add sLlmulus here
end

always clk = #100 ~clk,

endmodule

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