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S.No TITLE 1 A high-throughput low-latency arithmetic encoder design for D!V" $ & 1 2 3 5 7 9 1% 11 1$ 1& 11 12 13 15 17 19 $% 'ield-programma(le gate array implementation of low-density parity-chec) codes decoder and hardware test(ed" '*+A-,ased 'ast Detection -ith .educed Sensor /ount for a 'ault!olerant !hree-*hase con0erter" A .econfigura(le Application-specific Instruction-set *rocessor for 'ast 'ourier !ransform processing" A sur0ey of '*+A (ased Interference cancellation architectures for (iomedical signals" #fficient #lliptic /ur0e *oint Multiplication 4sing Digit-Serial ,inary 'ield Operations" Specific processor in '*+A for ,LA6# algorithm" !otal Design of an '*+A-,ased ,rain8/omputer Interface /ontrol ospital ,ed Nursing System" igh speed hardware ar(itration supporting priorities and (ounded ser0ice latency" No0el Architecture for #fficient '*+A Implementation of #lliptic /ur0e /ryptographic *rocessor O0er +':$;<=" A Multi-.esolution '*+A-,ased Architecture for .eal-!ime #dge and /orner Detection" VLSI Implementation of a Low-/ost igh->uality Image Scaling *rocessor eterogeneous Multi-/ore System? synchroni@ed (y a *etri *rocessor on '*+A" Design and implementation of high throughput (idirectional 'ano decoding" A No0el VLSI D ! Algorithm for a ighly Modular and *arallel Architecture" VLSI Architectures for the 1-!ap and 3-!ap $-D Dau(echies -a0elet 'ilters 4sing Alge(raic Integers" Design of So(el operator using 'ield *rogramma(le +ate Arrays" A real-time 0ideo denoising implementation on '*+A using contourlet transform" $%-,it .IS/ and DS* System Design in an '*+A" '*+A (ased design and implementation of modified Viter(i decoder for a -i-'i recei0er" YEAR I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1&

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$1 $$ $& $1 $2 $3 $5 $7 $9 +':A= LD*/ decoder design for '*+A implementation" *erformance e0aluation of ''! processor using con0entional and Vedic algorithm" Design and Implementation of a igh Speed MA* Decoder Architecture for !ur(o Decoding" /om(ining chec)pointing and scru((ing in '*+A-(ased real-time systems" Simulation and implementation of LD*/ code in '*+A" Impro0ed low-cost '*+A image processor architecture with eBternal line memory" An area efficient multipleBer (ased /O.DI/" Design and implementation of hardware architecture for denoising using '*+A" !ransducerless AcAuisition of the .otor *osition for *redicti0e !orAue /ontrolled *M Synchronous Machines ,ased on a DS*-'*+A Digital &% &1 &$ && &1 &2 &3 &5 &7 &9 1% 11 1$ 1& 11 12 System" Speed optimi@ation of a '*+A (ased modified 0iter(i decoder" A Superregenerati0e >*S6 .ecei0er" '*+A implementation for real-time /hroma-)ey effect using /oarse and 'ine 'ilter" Low cost permanent fault detection using ultra-reduced instruction set coprocessors" A no0el techniAue for run-time loading for MI*S soft-core processor" No0el high speed 0edic mathematics multiplier using compressors" Implementation of (inary to floating point con0erter using DL" Modified '*+A (ased design and implementation of reconfigura(le ''! architecture" .econfigura(le pipelined coprocessor for multi-mode communication transmission" An approach for redundancy in 'leB.ay networ)s using '*+A partial reconfiguration" A high speed (inary floating point multiplier using Dadda algorithm" A Design Approach of Low *ower VLSI for Downsampler 4sing Multirate !echniAue" VLSI Implementation of #nhanced #dge *reser0ing Impulse Noise .emo0al !echniAue" A factori@ation method for '*+A implementation of sample rate con0erter for a multi-standard radio communications" #m(edded System for ,iometric Online Signature Verification" !hroughputC.esource-#fficient .econfigura(le *rocessor for Multimedia I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1&

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13 15 17 19 2% 21 2$ 2& 21 22 23 25 27 29 3% 31 3$ 3& Applications" /omparison of num(er formats on '*+A-(ased O'DM modem architecture" Adapti0e Multiset Stochastic Decoding of Non-,inary LD*/ /odes" A $"% +(Cs !hroughput Decoder for >/-LD*/ /on0olutional /odes" A real time high definition architecture for the Varia(le-Length .eference 'rame Decoder" '*+A architecture for O'DM Software Defined .adio with an optimi@ed Direct Digital 'reAuency Synthesi@er" #fficient '*+A Implementation of Address +enerator for -iMAD Deinterlea0er" MA*roE A !iny *rocessor for .econfigura(le ,ase(and Modulation Mapping" '*+A implementation of pipelined /O.DI/ (ased Auadrature direct digital synthesi@er with impro0ed S'D." '*+A implementation of digital modulation techniAues" '*+A implementation of >AM modems using *. for reconfigura(le wireless radios" Dynamically reconfigura(le *-M controller for a single phase rectifier" A 4niAue !echniAue for .educing the #ffects of ot-carrier Induced Degradations in /MOS ,ista(le/ircuits for 'ault !olerant VLSI Design" DS-/DMA Implementation -ith Iterati0e Multiple Access Interference /ancellation" *ower-4p SeAuence /ontrol for M!/MOS Designs" /O.DI/ Designs for 'iBed Angle of .otation" Low power reconfigura(le '*+A (ased on S.AM" .esearch and implementation on multi-DDS technology in high performance digital up-con0ersion" ardware-software eBtensions to a softcore processor for '*+A-(ased adapti0e *ID control" I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1& I### $%1&