1

TSL inf3410
1
Opamp design
Two stage opamp
Generic amp topology
Gain and frequency response
Offset and slew rate limitations
Input stage
Compensation
Feedback
Classic opamp still suitable for CMOS technology (also bipolar)
TSL inf3410
2
Two stage OPAMP
Two gain stages (A
1
and A
2
)
Compensated second stage (Miller capacitance)
Output buffer for resistive loads
Not present for capacitive loads
Differential input stage Second gain stage Output buffer
2
TSL inf3410
3
CMOS OPAMP topology
PMOS diff input stage
Numbers realistic transistor widths
Length 1-2 times minimum
Output buffer dropp for capacitive loads
Bias circuit
Diff input stage
Common-source
1 stage 2 stage
TSL inf3410
4
First order model
) log( 20
2 1
A A
0
Gain
(dB)
Phase
(degrees)
Freq
(log)
Freq
(log)
0
90
180
1 p
e
1 p
e
ta
e
decade dB/ 20
c
m
ta
C
g
1
= e
Inadequate for advanced analysis
3
TSL inf3410
5
Opamp gain
Gain for diff pair 1. stage
Typical gain 50-100
Gain of common source 2. stage
Typical gain 50-100
Gain of source follower output buffer
Gain 1
Not included for capacitive loads
( )
4 2 1 1
||
ds ds m v
r r g A =
2
2 2
1
bias
ox n D ox n m
I
L
W
C I
L
W
C g = =
( )
7 6 7 2
||
ds ds m v
r r g A =
9 8 8 8
8
3
ds ds s m L
m
v
g g g g G
g
A
+ + + +
=
F SB
m
s
V
g
g
|

2 2
8
+
=
0
0
2
2
1
ds
DS eff
s
ds
A
ds
D
k
L V V
K
k
qN
r
I

=
+ u
=
~
TSL inf3410
6
Frequency response
Midband frequencies
Below unit-gain frequency
Above frequencies without compensation effects
( )
2 2
1 A C A C C
C C eq
~ + =
2
1 1 1
4 2 1 1 1 1
1 1
dominates freq midband at
1
|| ||
A sC
g
sC
g A
C
sC
r r g Z g A
C
m
eq
m
eq
eq
ds ds m out m
= =
|
|
.
|

\
|
= =
C
m
C
m
in
out
v
sC
g
A
A sC
g A A A
v
v
A
1
2
2
1 3 2 1
1
1
= ~ = =
1 5
1
m D
ta
C eff C
g I
C V C
e = =
Unit-gain frequency proportional to g
m
assuming A
3
=1
setting
( ) 1 =
ta V
j A e
and solve
4
TSL inf3410
7
Small signal opamp model
Assume R
C
=0 give transfer function
7 4 2 1 2 4 1
and ||
gs db db ds ds
C C C C r r R + + = =
2 6 7 2 7 6 2
and ||
L db db ds ds
C C C C r r R + + = =
( ) ( )
( )
C C
C m C C
m
C
m m
in
out
C C C C C C R R b
C R R g R C C R C C a
b s sa
g
sC
R R g g
v
v
2 1 2 1 2 1
2 1 7 1 1 2 1
2
7
2 1 7 1
1
1
+ + =
+ + + + =
+ +
|
|
.
|

\
|

=
TSL inf3410
8
Assume widely separated poles
Dominant pole
Non-dominant pole
( )
2 1
2
1 2 1
1 1 1
p p p p p
s s s s
s D
e e e e e
+ + ~
|
|
.
|

\
|
+
|
|
.
|

\
|
+ =
( ) | | ( )
( )
C m
m C
C m C
p
C R R g
R g C R
C C R R g C C R
2 1 7
2 7 1
1 2 2 7 1 1
1
1
1
1
1
1
~
+
~
+ + + +
= e
2 1
7
2 1 2 1
7
2
C C
g
C C C C C C
C g
m
C C
C m
p
+
~
+ +
= e
Increasing g
m7
increased pole distance
Pole splitting compensation
Cc may decrease
p1
5
TSL inf3410
9
Additional zero
Right half-planenegative phase shift with decreased PM
Stability issues
Hard to get rid of, but pole distance is increased with g
m7
Have to make R
C
>0
Zero-pole with some resistive element
May eliminate that zero-pole by setting
Alternatively try to cancel
p2
with
z
Overcompensation might even be wise:
b s sa
g
sC
R R g g
v
v
m
C
m m
in
out
2
7
2 1 7 1
1
1
+ +
|
|
.
|

\
|

=
C
m
Z
C
g
7
= e
( )
C m C
Z
R g C
=
7
1
1
e
7
1
m
C
g
R =
( )
|
|
.
|

\
| +
+ =

=
+
C m
C
C m C
m
C
C C
g
R
R g C C C
g
2 1
7 7 2 1
7
1
1
1
1
t Z
e e 2 . 1 =
1
1 1
2 . 1
1
gives ,
1
1
m
C C m t
C C
Z m C
g
R C g
C R
g R = ~ ~ >> e e
TSL inf3410
10
Slew rate
Fastest change on output
For large input signals
What node is lagging?
Output buffer gain of 1
Miller compensation eliminates common source gain
Gain primarily in input stage
Lagging due to capacitive load
Current limited by tail current, I
5
max
max max
1 1
I
C t
Q
C t
V
SR
out out
=
c
c
=
c
c
=
ta eff
m
ta
C C
V
g
I
C
I
C
I
SR e
e
= = = =
1
1
1 1 5
2 2
Increasing slew-rate in two stage OPAMPs can only be done by
Increasing unit-gain frequency increase
p2
keeping PM
Increasing effective voltage of diff pair
( ) L W C
I
V
ox n
D
eff

2
=
6
TSL inf3410
11
NMOS diff-pair or PMOS diff-pair?
PMOS
Higher saturation voltage (V
eff
)
Less flicker noise (1/f) noise
Lower mobility (transconductance)
NMOS
Lower saturation voltage (V
eff
)
Higher transconductance (mobility 2-3 times higher)
According to book:
PMOS diff pair due to improved slew-rate
Giving NMOS second stage
In low-voltage modern process:
Always folded cascode giving same type in input and drive
NMOS input with NMOS drive may be better than PMOS on both
TSL inf3410
12
Systematic errors
Systematic offset with V
in
=0
Output should be V
dd
/2
Splits tail current
Pull-up and pull-down current
should match
Adjusted by current gain
2
5
4
I
I =
6 7
I I =
( )
( )
( )
( )
5
6
4
7
2
L W
L W
L W
L W
=
7
TSL inf3410
13
Opamp compensation
Dominant-pole compensation
Forcing a feedback system to have 1. order response up to
loop unit-gain frequency
t
Stable system with
increased PM
Lead compensation
Adding zero,
z
,
just above
t
May improve PM
with 20
ta t
|e e ~
Compensation procedure
Exploring zero
Coarse approximation
Dominant pole
Determined by C
C
and
t
Proper C
c
used for dominant pole compensation
Lead compensation
Using R
C
to tune zero,
z
Adding a third pole, but at HF
May cancel zero:
Even better, locate zero at second pole:
Increasing R
C
even further slightly above second ole does it!
TSL inf3410
14
( )
1
1 2
( )
Z
L s A s
Z Z
~
+
1
0 1
m
t p
C
g
L
C
e e | = =
7
1
1
z
C C
m
C R
g
e

~
| |

|
\ .
7
1
give 0
C z
m
R
g
e > <
7
1
C
m
R
g
=
( )
7 1 2
2
1 2 1 2 7 7
1 1
1
1
m C
p C
C C C m C m C
g C C C
R
C C C C C C C g R g C
e
| | +
= = = +
|
+ +
\ .
8
Compensation
Compensation resistor
Replaced by transistor in triode region
TSL inf3410
15
1
C ds
n ox eff
R r
W
C V
L

= =
TSL inf3410
16
Opamp compensation procedure
1. Start with some setting unit-gain
frequency close to second pole
2. By simulation (SPICE, CADENCE) find frequency with -125 phase
shift (gain A)
Our aimed unit gain frequency
t
3. Choose new C
C
such that
t
is unit-gain freq of L(s)
C
C
=C
C
A giving 55 phase margin
A couple of simulation iterations may be necessary
4. Choose R
C
:
Giving phase margin of 85 (+30) leaving 5 for variations
5. Sometimes phase margins are not adequate, then increase C
C
6. Replace R
C
with a transistor
C t
C
C
R
e 2 . 1
1
=
Almost optimum lead compensation for any opamp
16
16
1
eff ox n
C
V
L
W
C
R
|
.
|

\
|
=

( )
'
1 7 C m m L
C g g C | =
9
TSL inf3410
17
Two stage opamp compensation
Dominant pole compensation
Setting the
p1
and
t
since
Q
16
operate in triode region
Resistive element
Resistive element ensures left
half-plane zero
Damping element
Lead compensation
0 0 t
A e e =
16
16
1
eff ox n
DS C
V
L
W
C
r R

= =
TSL inf3410
18
Opamp compensation example
Find best compensation network C
c
and R
c
for:
10
TSL inf3410
19
Find bias voltage:
Vbias1=2.3V give 84A tail current
Found by simple simulation run displaying tail current
TSL inf3410
20
Start with Cc=0.5pF and Rc=0
Find (180-125)=55 phase shift at t=50.1MHz with gain A=3.7
pF pF A C C
C C
9 . 1 7 . 3 5 . 0
' '
~ = =
0 phase in CADENCE
display is -180 actual
phase shift
11
TSL inf3410
21
New simulation with Cc=1.9pF give

t
=44.7MHz with A=1.32
New simulation with Cc=2.5pF give

t
=41MHz with A=1.2
New simulation with Cc=3.1pF give

t
=37.7MHz with A=1.00
Finding Rc
pF pF A C C
C C
5 . 2 32 . 1 3 . 1
' '
~ = =
pF pF A C C
C C
1 . 3 2 . 1 5 . 2
' '
~ = =
O ~

= =

7132
10 1 . 3 10 7 . 37 2 . 1
1
2 . 1
1
12 6
C t
C
C
R
e
TSL inf3410
22
Adding compensation resistor Rc
Give unit-gain freq of 209MHz
12
TSL inf3410
23
Phase margins?
Phase margins only 10 !!!
TSL inf3410
24
What to do?
Book: increase Cc
Try to decrease Rc
Give unit-gain freq of 133MHz with PM=84 with Rc=2050
13
TSL inf3410
25
Two-pole amplifier
Dominant poles of two-stage amps
1. stage
High gain
Dominant pole at output
Output
pole
1. stage
pole
Mirror
pole
TSL inf3410
26
Advanced mirrors and opamps
Advanced Current Mirrors
Wide-Swing Current Mirrors
Enhanced Output-Impedance Current Mirrors
Advanced OTAs
Folded-Cascode OTA
Current-Mirror OTA
Fully Differential OTAs
Folded-Cascode
Current-Mirror
Common-Mode Feedback Circuits
Current-Feedback Opamps
Simulation Example
14
TSL inf3410
27
Wide swing current mirror
Bias mirror transistors close to triode region
assuming
Giving
Minimum output voltage
Q
2
and Q
3
on the edge of triode region
L W L W
( )
2
1 + n
L W
2
n
L W
( ) L W C
I
V V V
ox n
D
eff eff eff

2
3 2
2
= = =
( )
eff eff
V n V 1
5
+ =
eff eff eff
nV V V = =
4 1
( )
eff tn eff G GS G DS DS
V V nV V V V V V = + = = =
5 1 5 3 2
( )
eff eff eff out
V n V V V 1
2 1
+ = + >
Ordinary cascode: V
out
>2V
eff
+V
tn
( )
tn eff G G G
V V n V V V + + = = = 1
4 1 5
in bias
I I ~
TSL inf3410
28
What n?
Often a small number
Typical effective voltage
Extend swing to 0.4V to 0.5V off rail
What bias current?
The input current varies.
Biasing current a little larger than max(I
in
)
Lower biasing might introduce slew rate problems
Might be tolerated for low frequency applications
Practical hints
Make Q
5
W/L smaller than nominal value to ensure active region
Reduce L of Q
2
and Q
3
close to minimum maximizing frequency
Let Q
1
and Q
4
be longer to reduce short channel effects
eff out
V V n 2 1 > =
| | V V V
eff
25 . 0 , 15 . 0 =
15
TSL inf3410
29
Enhanced output-impedance
Mirror with opamp gain boosting
Feedback to keep V
ds2
stable
Output impedance boosted by the
gain of the opamp +1
Gain boosting
No more stacking
( ) A r r g R
ds ds m out
+ ~ 1
1 2 1
One opamp for each mirror.
TSL inf3410
30
Simplified output enhancement
Opamp common source amp
Loop gain
Output impedance
Input network ensure matching
2
3 3 ds m
r g
2
3 2 1 3 1 ds ds ds m m
out
r r r g g
r ~
NOT WIDE-SWING: V
out
>2V
eff3
+V
tn
16
TSL inf3410
31
Wide swing, enhanced mirror
Diodes as level shifters
Q
3
and Q
7
biased with 4
times current density
Double power compared to
previous
Might require compensation
bias in
I I 7 ~
eff out
V V 2 >
Triple cascoding
TSL inf3410
32
Diff pair boosting
Differential signal
Regulated cascode
swing-limited
Regulated cascode diff pair
17
Current mirror symbol
Several mirror circuit solutions
Generic symbol
Arrow indicate input side
Direction of current flow
TSL inf3410
33
Modern op amps
MOSFETS loads are mostly capacitive
Drop output buffer
Enabling large swing, high gain single stage aamps
Only output node high impedance
Internal node low impedance
Reduced voltage swing
Compensation by output capacitive loading
Increased stability, but lower speed
Transconductance
Most important parameter
Operational Transconductance Amplifiers (OTA)
TSL inf3410
34
18
TSL inf3410
35
Folded cascode opamp
Operational Transconductance Amplifier OTA
Folding give same bias voltage on input and output
Typical
gain 700 to 3000
TSL inf3410
36
Compensation achieved using load capacitor
No internal compensation
As load increases, opamp slower but more
stable
Useful for driving capacitive loads only
Large output impedance
not useful for driving resistive loads
Reduced with feedback
Internal nodes low impedance
Single-gain stage but dc gain can still be quite
large (say 700 to 3000)
Shown design makes use of wide-swing
mirrors
Simplified bias circuit shown
Inclusion of Q
12
and Q
13
for improved slew-
rate
19
TSL inf3410
37
Small signal analysis
Ignoring HF poles and zeros diff-pair transconductance
With output enhanced impedance
Quite high
Mid-band frequencies: unit-gain frequency:
Unit-gain freq with feedback:
Amp bandwidth maximized
High input transconductance using nMOS and wide devices
By maximizing bias current though the differential pair
( )
( )
( )
L out
out m
L m
in
out
V
C sr
r g
s Z g
s V
s V
A
+
= = =
1
1
1
2
2
ds m
out
r g
r ~
1 m
V
L
g
A
sC
~
1 m
ta
L
g
C
e =
1 m
t
L
g
C
e | =
TSL inf3410
38
Design guidelines for maximum bandwidth
Maximizing g
m
of input pair
Use nMOS and wide devices
Choose current of input stage larger than output cascode
also maximizes dc gain
Might go as high as 4:1 ratio
Large input g
m
results in less thermal noise
Second poles due to nodes at sources of Q
5
and Q
6
Minimize areas of drains and sources at these nodes with good layout
techniques
Insufficient phase margins
Lead compensating load capacitor in parallel with load capacitance
Lead resistance R
C
may be chosen to place a zero at 1.7 times unit gain frequency
Increase current and devices widths of output stage
( )
L
L C m
L C out
m
V
sC
C sR g
sC R r
g
A
+
~
+
+
=
1
1
1 1
1 1
20
TSL inf3410
39
Slew rate
Q
12
and Q
13
turned off during normal operation
Improve slew-rate
Q
2
turned off due to large input voltage
Q
1
sinking tail current through Q
3
With Q
2
off. Q
4
current through Q
5
Charging load capacitance:
Drain of Q
1
pulled near negative power supply
Since I
bias2
> I
bias1
Q
1
in triode
Must recover going out of slew-rate
Adding significant slewing time
Add Q
12
(and Q
13
) to clamp node closer to positive
power supply
Q
12
(and Q
13
) also dynamically increase bias
currents during slew-rate limiting
They pull more current through Q
11
thereby
increasing bias current in Q
3
and Q
4
L
D
C
I
SR
4
=
TSL inf3410
40
Example: Folded-cascode
AMS 0.35m 3.3V process
1.5V supply
1mW power
Input stage output stage ratio 4:1
Q
11
= 1/30Q
3(4)
(Q
11
current ignored for power)
Maximum width 300m
Unit length 0.6m
V
eff
0.25V
Assume C
L
=10pF load
Assume
2
100 3
V
A
C C
ox p ox n

= ~
21
TSL inf3410
41
Major current
We want
Defining
Give
With maximum 1mW power consumption
Giving
Using
( )
6 1 4 3
2
D D D D tot
I I I I I + = + =
6 1
4
D D
I I =
6 5 D D B
I I I = =
( )
B D D tot
I I I I 10 2
6 1
= + =
A
V
mW
I
I I I
tot
D D B
33
10
3
1
10
6 5
= = = = =
A I I I
D D D
165 5
5 4 3
= = =
A I I I
D D D
132 4
5 2 1
= = =
2
2
eff oxi i
Di
V C
I
L
W

=
Q
1
300/0.6
Q
2
300/0.6
Q
3
270/0.6
Q
4
270/0.6
Q
5
54/0.6
Q
6
54/0.6
Q
7
18/0.6
Q
8
18/0.6
Q
9
18/0.6
Q
10
18/0.6
Q
11
9/0.6
Q
12
9/0.6
Q
13
3/0.6
TSL inf3410
42
Input stage transconductance
Unit gain frequency
Slew rate
Adding clamp transistor, increase current
Since and
Give
and
( ) ( )
V
mA
V
A
A L W C I g
ox n D m
6 . 3 6 . 0 300 100 132 2 2
2 1 1
= = =


MHz s rad
pF
V
mA
C
g
L
m
t
57 10 6 . 3
10
6 . 3
8 1
= = = =

e
s V s V
pF
A
C
I
SR
L
D

5 . 16 10 5 . 16
10
165
6 4
= = = =
A I I I
D D bias
264
12 3 2
= + =
11 3
30
D D
I I =
12 11
5 . 5
D D
I A I + =
A
A A
I
D


7 . 8
31
5 . 5 264
11
=
+
=
s V
pF
A
SR A I
D

1 . 26
10
261
261 7 . 8 30
4
= = = =
22
TSL inf3410
43
Cadence simulation
Entering schematics
TSL inf3410
44
DC operation points
Vbias1 for 5.5A current
Vbias1=662mV
Vbias2 for 264A current
Vbias2=626mV
VB1 for 33A
VB1=2.194V
23
TSL inf3410
45
Frequency response
TSL inf3410
46
Slew rate
With clamp
Giving approx. 3.6V/s
Without clamp
Giving approx. 2,8V/s
24
TSL inf3410
47
Current mirror opamp
Low impedance
nodes
Except output node
Extra gain in current
mirrors
TSL inf3410
48
Wide swing current mirror opamp
( )
( )
( )
L
m
L out
out m
L m
in
out
V
sC
Kg
C sr
r Kg
s Z Kg
s V
s V
A
1 1
1
1
~
+
= = =
2
1 14
b
I
K KI I = =
K factor is current gain from mirrors
Maximum K is around 5
25
TSL inf3410
49
Unit gain frequency
Transconductance and unit-gain frequency increase with K
Assuming limited by load capacitance, not other HF poles
Often K=5 is practical
Increased K
Larger capacitance at drain of Q
1
(Q
2
and Q
9
as well)
Moving down HF poles
Load capacitance may have to be increased to maintain
stability
Decreased bandwidth
For high bandwidth K might be lowered to 1
1 1 1
1
,1 ,1
2 2
, (3 )
3
m D D
ta total D ta
C C eff C eff
kg kI K I
I K I
C C V K C V
e e = = = + =
+
TSL inf3410
50
Power
Slew rate
Assuming large input swing
All bias current one way
Larger K improve slew rate
Often better slew rate than folded cascode
Larger bandwidth as well
Folded cascode has better noise performance
L
b
C
KI
SR =
( ) ( )
2
3 3
1
b
D total
I
K I K I + = + =
26
TSL inf3410
51
Example: current mirror opamp
Similar constraints as folded cascode opamp
Bias current
Gives 65A in all input stage transistors
Output stage transistors twice as much current
Using
Finding sizes
Q
1
300/0.6
Q
2
300/0.6
Q
3
60/0.6
Q
4
60/0.6
Q
5
60/0.6
Q
6
60/0.6
Q
7
60/0.6
Q
8
120/0.6
Q
9
60/0.6
Q
10
120/0.6
Q
11
20/0.6
Q
12
40/0.6
Q
13
20/0.6
Q
14
40/0.6
( ) ( )
A
mW
K
I
I
total
b
130
2 3
3
1
2
3
2
=
+
=
+
=
2
2
eff oxi i
Di
V C
I
L
W

=
TSL inf3410
52
Setting biasing
Tail current 130A
V
bias2
= 0.591V
Setting cascode voltages
Assuming
Finding
tn eff bias
V V n V + + = ) 1 (
V V
tn
7 . 0 = V V
tp
9 . 0 = V V
eff
25 . 0 =
V V
B
4 . 1
2
=
V V
B
2 . 1
1
=
27
TSL inf3410
53
Frequency response
( )
V
mA
L W C I g
ox n D m
5 . 2 2
1 1
= = MHz
C
Kg
L
m
t
79
1
= = e
TSL inf3410
54
Slew rate
Simulated:
Theory:
s
V
SR

1 . 27
08 . 0
17 . 2
= =
s
V
pF
A
C
KI
SR
L
b

26
10
65 2
=

= =
28
TSL inf3410
55
Linear settling time
Time constant for linear settling time
Classic 2-stage opamps
t
relatively independent of load
Not the case for folded-cascode and current-mirror opamps
High impedance output

ta
strongly related to load
Settling time dependent on both feedback factor and load
Analyzing open-loop behavior to find capacitive load
Example:
High-impedance opamps are fine internally on-chip
Load compensation is simple, but may limit performance
3dB t ta
e e |e

= ~
( ) | |
( ) | |
2 1
2
2 1
1
1 1
1
C C C
C
sC C C s
C C s
p p
p
+ +
=
+ +
+
= |
( )
2 1
1 2
C C C
C C C
C C C
p
p
load C L
+ +
+
+ + =
1 m
ta current mirror
L
Kg
C
e

=
1 m
ta folded cascode
L
g
C
e

=
Open loop output load
TSL inf3410
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Topology comparison
Gain
Output
Swing Speed
Power
dissipation Noise
Telescopic Medium Low Highest Low Low
Folded-Cascode Medium Medium High Medium Medium
Two-stage High Highest Low Medium Low
Gain-boosted High Medium Medium High Medium
29
Fully differential opamps
Single-ended similar to fully differential opamp
Double signal swing
Double area?
TSL inf3410
57
Single-ended diff amp
Small signal comparison
Basically the same small-signal performance
TSL inf3410
58
30
Diff amp advantage
Noise performance
Common mode systematic noise injected in both half-signals
Cancel when looking at difference
Cancel fluctuations in supply and biasing
Major issue in integrated systems
Random noise double!
Still SNR is OK with double signal swing
Only odd order distortion
Tend to be smaller
TSL inf3410
59
Common-mode feedback
CMFB circuits
Defining output common-mode (average) voltage
Keeping common-mode voltage half-way between rails
Will add additional power consumption
TSL inf3410
60
31
TSL inf3410
61
Differential current mirror opamp
pMOS version also feasible
nMOS for high-order pole bandwidth limitations and lower thermal
noise
pMOS for high DC-gain and unit-gain bandwidth and lower flicker
noise
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Common-mode feedback
Two approaches:
Continuous time
Switched capacitor (SC)
The purpose of the CMFB circuit is to keep the common-mode
(average) output voltage at a constant level
Halfway between the power-supply voltages
The speed of the CMFB circuit should be comparable to the unity-
gain frequency of the differential path
Avoiding noise on the power rails
32
TSL inf3410
63
Continuous time, double diff pair
Positive difference will increase V
cmfb
Negative difference will decrease V
cmfb
Negative feedback through lower current regulator
Improved common mode gain
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Common mode gain
Differential input
Common mode voltage
Real amplifiers are non-ideal:
A should be large while A
CM
should be small
Common mode rejection CMRR
Power supply rejection ration PSRR
Ratio between power ripple and the ripple visible on the output
+
= V V V
in
2
+
+
=
V V
V
CM
CM CM in out
v A Av V + =
CM
A
A
CMRR log 20 =
ripple
ripple out
V
V
PSRR

= log 20
33
Keypoints
Classical opamp: differential input stage + CS 2. stage + optional
unit-gain buffer
Overall gain equal to product of stage gain
Dominating pole is 2. stage input pole (CS) due to Miller effect
Second pole at output may be increase by 2. stage
transconductance
Slew rate giving maximum drive capability of output for large signals
and may only be improved by 1) increase 1. stage effective voltage
(g
m1
) or move second pole upwards
Compensation is done by pole splitting usually by exploring Miller
capacitance
Differential amps have less common mode noise, but require
additional common mode feedback circuit on output stage
Current mirror opamps are good and easy to use.
TSL inf3410
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