APRIL 1997

GeneraI Description Features

L1 11-71
LXT905 BIock Diagram
DATA SHEET
LXT905
Universal Ethernet Interface Adapter
Revision 2.0
Mode Select Logic
Controller
Compatibility /
Loopback /
Link Test
Manchester
Encoder
Squelch/
Link Detect
Manchester
Decoder
Watch-Dog
Timer
Loopback
Control
Pulse
Shaper
&
Filter
Collision/
Polarity
Detect/
Correct
CMOS
TX
Amp
Collision
Logic
RX
Slicer
XTAL
OSC
RC
RC
L
TCLK
CLK
CLKO
TEN
CD
LEDL
RCLK
RXD
COL
TXD
MD0
MD1
TPOP
TPON
TPP
TPN
LBK DSQE LEDC/FDE LEDT/PDN
LEDR
DO
The LXT905 Universal Ethernet InterIace Adapter is
designed Ior IEEE 802.3 physical layer applications. It
provides, in a single CMOS device, all the active circuitry
Ior interIacing most standard 802.3 controllers to 10BASE-
T media.
LXT905 Iunctions include Manchester encoding/decoding,
receiver squelch and transmit pulse shaping, jabber, link
integrity testing and reversed polarity detection/correction.
The LXT905 drives the 10BASE-T twisted-pair cable with
only a simple isolation transIormer. Integrated Iilters sim-
pliIy the design work required Ior FCC compliant EMI per-
Iormance.
The LXT905 is Iabricated with an advanced process and
requires only a single 5 or 3.3 volt power supply.
AppIications
Hub/Switched Dedicated LANs Ior 10BASE-T
Desktop 10BASE-T LAN adapter boards
Laptop and Portable applications
Transparent 3.3 V or 5 V operation
Integrated Iilters SimpliIies FCC compliance
Integrated Manchester encoder/decoder
10BASE-T compliant transceiver
Automatic polarity correction
Available in 28-pin PLCC and 32-pin LQFP packages
SQE enable/disable
Four LED drivers
Full duplex capability
Power-down mode with tristate
LXT905 UniversaI Ethernet Interface Adapter
11-72
L1
LXT905 TABLE OF CONTENTS
PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS...............................................11-73
FUNCTIONAL DESCRIPTION...................................................................................11-75
ntroduction ................................................................................................................. 11-75
Controller Compatibility Modes ................................................................................... 11-75
Transmit Function ....................................................................................................... 11-75
Jabber Control Function.............................................................................................. 11-76
SQE Function.............................................................................................................. 11-76
Receive Function ........................................................................................................ 11-77
Polarity Reverse Function........................................................................................... 11-77
Collision Detection Function........................................................................................ 11-77
Loopback Function..................................................................................................... 11-78
Link ntegrity Test Function ........................................................................................ 11-78
APPLICATION INFORMATION.................................................................................11-80
ntroduction ................................................................................................................. 11-80
Magnetic nformation................................................................................................... 11-80
Typical 10BASE-T Application .................................................................................... 11-81
Dual Network Support - 10BASE-T and Token Ring................................................... 11-82
Simple 10BASE-T Connection.................................................................................... 11-83
TEST SPECIFICATIONS............................................................................................11-84
Absolute Maximum Ratings ........................................................................................ 11-84
Recommended Operating Conditions......................................................................... 11-84
/O Electrical Characteristics....................................................................................... 11-84
TP Electrical Characteristics ....................................................................................... 11-85
Switching Characteristics............................................................................................ 11-86
RCLK/Start-of-Frame Timing ...................................................................................... 11-86
RCLK/End-of-Frame Timing........................................................................................ 11-86
Transmit Timing........................................................................................................... 11-87
Miscellaneous Timing.................................................................................................. 11-87
Mode 1 Timing Diagrams ............................................................................................ 11-88
Mode 2 Timing Diagrams ............................................................................................ 11-90
Mode 3 Timing Diagrams ............................................................................................ 11-92
Mode 4 Timing Diagrams ............................................................................................ 11-94
11-73
L1
LXT905 Pin Assignments and SignaI Descriptions
LXT905 PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS
Figure 1: LXT905 Pin Assignments
TabIe 1: LXT905 SignaI Descriptions
LQFP
Pin #
PLCC
Pin #
SymboI I/O Description
13
20
27
28
29
1
22

VCC1
VCC2
VCC3
VCC4
VCC5

3RZHU ,QSXWV WKUX Power supply inputs oI 5 volts or 3.3 volts.

30
31
2
3
CLKI
CLKO
I
O
&U\VWDO 2VFLOODWRU A 20 MHz crystal must be connected across these
pins, or a 20 MHz clock applied at CLKI with CLKO leIt open.
11
12
21
32
15
23
4

GND1
GND2
GND3
GND4

*URXQG
1 5 LBK I Loopback When High, forces internal loopback. Disables collision and
the transmission of both data and link pulses. Pulled Low internally.
2 6 TEN I Transmit Enable Enables data transmission and starts the watchdog
timer. Synchronous to TCLK. Pulled Low internally.
3 7 TCLK O Transmit Clock A 10 MHz clock output. This clock signal should be
directly connected to the transmit clock input of the controller.
4 8 TXD I Transmit Data Input signal containing NRZ data to be transmitted on the
network. TXD should be connected directly to the transmit data output of
the controller. Pulled Low internally.
5 9 COL O Collision Signal Output that drives the collision detect input of the con-
troller.
LBK
TEN
TCLK
TXD
COL
LEDC/FDE
LEDT/PDN
25
24
23
22
21
20
19
5
6
7
8
9
10
11
1
2
1
3
1
4
1
5
1
6
1
7
1
8
4321
2
8
2
7
2
6
MD0
TPON
GND2
VCC2
TPOP
DSQE
RBAS
G
N
D
3
C
L
K
O
C
L
K

V
C
C
1
T
P

N
T
P

P
M
D
1
L
E
D
R
L
E
D
L
C
D
G
N
D
1
R
C
L
K
R
X
DL

LXT905PC
PLCC
LBK
TEN
TCLK
TXD
COL
LEDC/FDE
LEDT/PDN
LEDR
1
2
3
4
5
6
7
8
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
L
E
D
L
C
D
G
N
D
1
G
N
D
2
V
C
C
1
R
C
L
K
R
X
D
L

9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
MD1
MD0
TPON
GND3
VCC2
TPOP
DSQE
RBAS
LXT905LC
LQFP
24
23
22
21
20
19
18
17
G
N
D
4
C
L
K
O
C
L
K

V
C
C
5
V
C
C
4
V
C
C
3
T
P

N
T
P

P
LXT905 UniversaI Ethernet Interface Adapter
11-74
L1
6 10 LEDC/
FDE
O
I
LED Collision RU Full Duplex Enable
LEDC is an open drain driver for the collision indicator pulls Low during
collision. LED on (i.e., Low output) time is extended by approximately
100 ms.
)'( enables Iull duplex mode (external loopback) iI tied Low externally.
Pulled high internally.
7 11 LEDT/
PDN
O
I
/(' 7UDQVPLW RU 3RZHU 'RZQ
/('7 is an open drain driver Ior the transmit indicator. LED 'on (LH,
Low output) time is extended by approximately 100 ms. Output is pulled
Low during transmit.
II externally tied Low, the LXT905 goes to power down state (3'1). In
Power-down Mode, all logic inputs and outputs are tristated.
8 12 LEDR O LED Receive Open drain driver for the receive indicator LED. LED
on (i.e., Low output) time is extended by approximately 100 ms. Output
is pulled Low during receive. Pulled High internally.
9 13 LEDL O LED Link Open drain driver for link integrity indicator. Output is pulled
Low during link test pass. Pulled High internally.
10 14 CD O Carrier Detect An output for notifying the controller that activity exists
on the network.
14 16 RCLK O Receive Clock A recovered 10 MHz clock which is synchronous to the
received data and connected to the controller receive clock input.
15 17 RXD O Receive Data Output signal connected directly to the receive data input
of the controller.
16 18 LI I Link Enable Controls link integrity test; enabled when LI is High, dis-
abled when LI is Low.
17 19 RBIAS I Bias Circuitry A 7.5 k 1% resistor to ground at this pin controls operat-
ing circuit bias.
18 20 DSQE I SQE Disable When DSQE is High, the SQE function is disabled.
When DSQE is Low, the SQE function is enabled. SQE should be dis-
abled for normal operation in Hub/Switch/Repeater applications. Pulled
Low internally.
19
22
21
24
TPOP
TPON
O
O
Twisted Pair Outputs Differential outputs to the twisted-pair cable. The
outputs are pre-equalized.
23
24
25
26
MDO
MDI
I
I
Mode Select 0 DQG Mode select pins determine controller compatibility
mode in accordance with Table 2. Pulled Low internally.
25
26
27
28
TPIP
TPIN
I
I
Twisted-Pair ,QSXWV A differential input pair from the twisted-pair cable.
Receive filter is integrated on-chip. No external filters are required.
TabIe 1: LXT905 SignaI Descriptions continued
LQFP
Pin #
PLCC
Pin #
SymboI I/O Description
LXT905 FunctionaI Description
11-75
L1
LXT905 FUNCTIONALDESCRIPTION
Introduction
The LXT905 Universal Ethernet InterIace Transceiver per-
Iorms the physical layer signaling (PLS) and Media
Attachment Unit (MAU) Iunctions as deIined by the IEEE
802.3 speciIication. It Iunctions as an integrated PLS/
MAU Ior use with 10BASE-T twisted-pair networks.
The LXT905 interIaces a back end controller to a twisted-
pair (TP) cable. The controller interIace includes transmit
and receive clock and NRZ data channels, as well as mode
control logic and signaling. The twisted-pair interIace
comprises two circuits: Twisted-Pair Input (TPI) and
Twisted-Pair Output (TPO). In addition to the two basic
interIaces, the LXT905 contains an internal crystal oscilla-
tor and Iour LED drivers Ior visual status reporting.
Functions are deIined Irom the back end controller side oI
the interIace. The LXT905 Transmit Iunction reIers to data
transmitted by the back end to the twisted-pair network.
The LXT905 Receive Iunction reIers to data received by
the back end Irom the twisted-pair network. The LXT905
perIorms all required Iunctions deIined by the IEEE 802.3
10BASE-T MAU speciIication such as collision detection,
link integrity testing, signal quality error messaging, jabber
control and loopback.
Controller Compatibility
Modes
The LXT905 is compatible with most industry standard
controllers including devices produced by Advanced Micro
Devices (AMD), Intel, Fujitsu, National Semiconductor,
Seeq, Motorola and Texas Instruments. Four diIIerent con-
trol signal timing and polarity schemes (Modes 1 through
4) are required to achieve this compatibility. Mode select
pins MD0 and MD1 determine controller compatibility
modes as listed in Table 2. ReIer to the Test SpeciIications
section Ior timing diagrams and parameters.
Transmit Function
The LXT905 receives NRZ data Irom the controller at the
TXD input as shown in the block diagram, and passes it
through a Manchester encoder. The encoded data is then
transIerred to the twisted-pair network (the TPO circuit).
The advanced integrated pulse shaping and Iiltering net-
work produces the output signal on TPON and TPOP,
shown in Figure . The TPO output is pre-distorted and pre-
Iiltered to meet the 10BASE-T jitter template. An internal
continuous resistor-capacitor Iilter is used to remove any
high-Irequency clocking noise Irom the pulse shaping cir-
cuitry. Integrated Iilters simpliIy the design work required
Ior FCC compliant EMI perIormance. During idle periods,
the LXT905 transmits link integrity test pulses on the TPO
circuit (iI LI is enabled and LBK is disabled).
Figure 2: LXT905 TPO Output Waveform
TabIe 2: ControIIer CompatibiIity Mode Options
ControIIer Mode
MD1 MD0
Mode 1 - For Advanced Micro Devices AM7990 or compatible controllers Low Low
Mode 2 - For Intel 82596 or compatible controllers
1
High Low
Mode 3 - For Fujitsu MB86950, MB86960 or compatible controllers (Seeq 8005)
2
Low High
Mode 4 - For National Semiconductor 8390 or compatible controllers (TI TMS380C26) High High
2. ReIer to Level One Application Note 51 when designing with Intel controllers.
3. SEEQ controllers require inverters on CLKI, LBK, RCLK and COL.
LXT905 UniversaI Ethernet Interface Adapter
11-76
L1
Jabber Control Function
Figure 3 is a state diagram oI the LXT905 jabber control
Iunction. The LXT905 on-chip watchdog timer prevents
the DTE Irom locking into a continuous transmit mode.
When a transmission exceeds the time limit, the watchdog
timer disables the transmit and loopback Iunctions and acti-
vates the COL pin. Once the LXT905 is in the jabber state,
the TXD circuit must remain idle Ior a period oI 0.25 to
0.75 seconds beIore it will exit the jabber state.
Figure 3: Jabber ControI Function
SQE Function
The LXT905 supports the signal quality error (SQE) Iunc-
tion as shown in Figure 4. AIter every successIul transmis-
sion on the 10BASE-T network, the LXT905 transmits the
SQE signal Ior 10 bit times (BT) 5BT on the COL pin oI
the device.
The SQE can be disabled Ior repeater/switch applications.
When DSQE is set High, the SQE Iunction is disabled.
When DSQE is Low, the SQE Iunction is enabled.
Figure 4: SQE Function
No Output
Nonjabber Output
Start_XMT_MAX_Timer
Power On
DO=Active
Jab
XMT=Disable
LPBK=Disable
C=SQE
Unjab Wait
Start_Unjab_Timer
XMT=Disable
LPBK=Disable
C=SQE
DO=Active
XMT_Max_Timer_Done
DO=dle
DO=dle
Unjab_ Timer_Done DO=Active
Unjab_Timer_Not_Done
XMT=Disable
SQE_Test_Timer_Done
DSQE=1
DO=Active
Output IdIe
Output Detected
Power On
SQE Wait Test
Start_SQE_Test__Wait_Timer
SQE Test
Start_SQE_Test_Timer
C=SQE
SQE_Test__Wait_Timer_Done
XMT=Enable
DO=dle
DSQE=0
11-77
L1
LXT905 FunctionaI Description
Receive Function
The LXT905 receive Iunction acquires timing and data
Irom the twisted-pair network (the TPI circuit). Valid
received signals are passed through the on-chip Iilters and
Manchester decoder then output as decoded NRZ data and
receive timing on the RXD and RCLK pins, respectively.
An internal RC Iilter and an intelligent squelch Iunction
discriminate noise Irom link test pulses and valid data
streams. The receive Iunction is activated only by valid
data streams above the squelch level with proper timing.
II the diIIerential signal at the TPI circuit inputs Ialls below
85 oI the threshold level (unsquelched) Ior 8 bit times
(typical), the LXT905 receive Iunction enters the idle state.
The LXT905 automatically corrects reversed polarity on
the TPI circuit.
Polarity Reverse Function
The LXT905 polarity reverse Iunction uses both link pulses
and end-oI-Irame data to determine polarity oI the received
signal. II Link Integrity testing is disabled, polarity detec-
tion is based only on received data. A reversed polarity
condition is detected when eight consecutive opposite
receive link pulses are detected without receipt oI a link
pulse oI the expected polarity. Reversed polarity is also
detected iI Iour consecutive Irames are received with a
reversed start-oI-idle. Whenever a correct polarity Irame
or a correct link pulse is received, these two counters are
reset to zero. II the LXT905 enters the link Iail state and
no valid data or link pulses are received within 96 to 128
ms, the polarity is reset to the deIault non-Ilipped condi-
tion. Polarity correction is always enabled.
Collision Detection Function
A collision is deIined as the simultaneous presence oI valid
signals on both the TPI circuit and the TPO circuit. The
LXT905 reports collisions to the back-end via the COL pin.
II the TPI circuit becomes active while there is activity on
the TPOcircuit, the TPI data is passed to the back-end over
the RXD circuit, disabling normal loopback. Figure 5 is a
state diagram oI the LXT905 collision detection Iunction.
Figure 5: CoIIision Detection Function
IdIe
Power On A
CoIIision
TPO=TXD
RXD=TP
COL=ACTVE
Output
TPO=TXD
RXD=TXD
Input
RXD=TP
TEN=Active
TP=dle
XMT=Enable
TEN=Active
TP=Active
XMT=Enable
A A
TEN=Active
TP=Active
XMT=Enable
TEN=Active
TP=dle
TEN=dle +
XMT=Disable
TEN=dle
TP=dle
TP=Active
LXT905 UniversaI Ethernet Interface Adapter
11-78
L1
Loopback Function
The LXT905 provides the normal loopback Iunction spec-
iIied by the 10BASE-T standard Ior the twisted-pair port,
as well as a Iorced loopback Iunction. The loopback Iunc-
tion operates in conjunction with the transmit Iunction.
Data transmitted by the back-end is internally looped back
within the LXT905 Irom the TXD pin through the
Manchester encoder/decoder to the RXD pin and returned
to the back-end. This 'normal loopback Iunction is dis-
abled when a data collision occurs, clearing the RXD cir-
cuit Ior the TPI data. Normal loopback is also disabled
during link Iail, jabber, and Iull duplex states. Loopback is
always enabled during the Iorced loopback state.
The LXT905 provides an additional loopback Iunction.
External loopback mode, useIul Ior system-level testing, is
controlled by the LEDC/FDE pin. With both LEDC/FDE
and LBK Low, the LXT905 device:
disables internal loopback circuits
disables SQE
disables Collision Detection
enables Full Duplex Mode
This allows external loopback testing.
Link Integrity Test Function
Figure 6 is a state diagram oI the LXT905 Link Integrity
test Iunction. The link integrity test is used to determine
the status oI the receive side twisted-pair cable. Link integ-
rity testing is enabled when pin 18 (LI) is tied High. When
enabled, the receiver recognizes link integrity pulses which
are transmitted in the absence oI receive traIIic. II no serial
data stream or link integrity pulses are detected within
50~150 ms, the chip enters a link Iail state and disables the
transmit and normal loopback Iunctions. The LXT905
ignores any link integrity pulse with interval less than 2~7
ms. The LXT905 will remain in the Link Fail State until it
detects either a serial data packet or two or more link integ-
rity pulses.
11-79
L1
LXT905 FunctionaI Description
Figure 6: Link Integrity Test Function
IdIe Test
Start_Link_Loss_Timer
Start_Link_Test_Min_Timer
Power On
Link Test FaiI Reset
Link_Count=0
XMT=Disable
RCVR=Disable
LPBK=Disable
Link_Loss_Timer_Done
TP=dle
Link_Test_Rcvd=False
TP=Active +
(Link_Test_Rcvd=True
Link_Test_Min_Timer_Done)
Link Test FaiI Wait
XMT=Disable
RCVR=Disable
LPBK=Disable
Link_Count=Link_Count + 1
Link Test FaiI
Start_Link_Test_Min_Timer
Start_Link_Test_Max_Timer
XMT=Disable
RCVR=Disable
LPBK=Disable
Link_Test_Rcvd=False
TP=dle
TP=Active
TP=Active
Link_Test_Rcvd=dle
TP=dle
Link Test FaiI Extended
XMT=Disable
RCVR=Disable
LPBK=Disable
TP=Active +
Link_Count=LC_Max
Link_Test_Min_Timer_Done
Link_Test_Rcvd=True
(TP=dle Link_Test_Max_Timer_Done) +
(Link_Test_Min_Timer_Not_Done
Link_Test_Rcvd=True)
TP=dle
DO=dle
LXT905 UniversaI Ethernet Interface Adapter
11-80
L1
LXT905 APPLICATION INFORMATION
Introduction
Figures 7 through 9 show typical LXT905 applications.
These diagrams group similar pins; they do not portray the
actual chip pinout. The controller interIace pins; Transmit
Data (TXD), Transmit Clock (TCLK) Transmit Enable
(TEN), Receive Data (RXD), Receive Clock (RCLK),
Collision Signal (COL) and Carrier Detect (CD) pins are at
the upper leIt.
Power and ground pins are at the bottom oI each diagram.
VCC1 and VCC2 use a single power supply with
decoupling capacitors installed between the power and
ground busses. VCC may be powered by a 5V or 3.3V
supply.
Twisted-Pair Interface
The Twisted-Pair interIace (TPOP/N and TPIP/N) is at the
upper right. The I/O pairs have impedance matching
resistors Ior 100 UTP but no external Iilters are required.
RBIAS Pin
The RBIAS pin sets the levels Ior the LXT905 output
drivers. The LXT905 requires a 7.5k, 1 resistor directly
connected between the RBIAS pin and ground. This
resistor should be located as close to the device as possible.
Keep the traces as short as possible and isolated Irom all
other high speed signals.
CrystaI Information
Based on limited evaluation, Table 3 lists some oI the
suitable crystals. Designers should test and validate all
crystals beIore committing to a speciIic component.
Magnetic Information
The LXT905 requires a 1:1 turns ratio Ior the receive
transIormer and a 1:2 turns ratio Ior the transmit
transIormer. Table 4 lists transIormers suitable Ior the
applications described in this data sheet. Designers are
advised to test and validate all magnetics beIore
committing to a speciIic component.
TabIe 3: SuitabIe CrystaIs
Manufacturer Part Number
MTRON MP-1
MP-2
TabIe 4: SuitabIe Magnetics
Manufacturer Part Number
Surface Mount Thru-hoIe
Valor ST4160
ST4202
ST4167
HALO TG74-1406N1 TG74-1406Q
TG75-1406N TG74-1406K
Fil-Mag 23Z441SM 23Z441
LXT905 AppIication Information
11-81
L1
Typical 10BASE-T Application
Figure 7 is a typical LXT905 application. The DTE is
connected to a 10BASE-T network through the twisted-
pair RJ45 connector. With MD0 tied high and MD1
grounded, the LXT905 logic and Iraming are set to Mode 2
(compatible with Intel 82596 controllers*). Connect 20
MHz system clock input at CLKI. (Leave CLKO open.)
The LI pin externally controls the link test Iunction.
*ReIer to Level One Application Note 51 when designing
with Intel controllers.
Figure 7: Intel Controller Application (Mode 2)
CLKO
CLK
TXD
TEN
TCLK
RCLK
RXD
CD
COL
MD0
MD1
DSQE
L
LBK
LEDL
LEDC/FDE
LEDT/PDN
VCC1
VCC2
100 pF
50 1%
Not Connected
Power
Down
Full
Duplex
+5V
10K
10K
10K
Line Status
GND1
GND2
RBAS
Programming
Options
Link Test Enable
Loopback Enable
82596
Back-End/
ControIIer
Interface
20 MHz System Clock
CLK
TXD
RTS
TXC
RXC
RXD
CRS
CDT
L
X
T
9
0
5
50 1%
11.8 1%
11.8 1%
0.1 F
100 pF
RJ45
TPN
TPP
TPON
TPOP
6
5
4
3
2
1
1
3
16
14
11
9
6
8
1:2
1:1
T
o
1
0
B
a
s
e
-
T
T
w
i
s
t
e
d
P
a
i
r
N
e
t
w
o
r
k
7.5 k 1%
1
1
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
0.1 F
11-82
L1
LXT905 UniversaI Ethernet Interface Adapter
Dual Network Support -
10BASE-T and Token Ring
Figure 8 shows the LXT905 with a Texas Instruments
380C26 CommProcessor. The 380C26 is compatible with
Mode 4 (MD0 and MD1 both high). When used with the
380C26, both the LXT905 and a TMS38054 Token Ring
transceiver can be tied to a single RJ45 allowing dual
network support Irom a single connector.
Figure 8: LXT905/380C26 Interface for Dual 10BASE-T & Token Ring Support (Mode 4)
TXD
TEN
TCLK
RCLK
RXD
CD
COL
LBK
MD0
MD1
L
LEDR
LEDC/FDE
LEDT/PDN
LEDL
VCC1
VCC2
100 pF
50 1%
+5V
Line Status
GND2 GND3
RBAS
To T TMS38054
Token Ring
Transceiver
L
X
T
9
0
5
50 1%
11.8 1%
11.8 1%
0.1 F
100 pF
RJ45
TPN
TPP
TPON
TPOP
6
5
4
3
2
1
1
3
16
14
11
9
6
8
1:2
1:1
T
o
1
0
B
a
s
e
-
T
T
w
i
s
t
e
d
P
a
i
r
N
e
t
w
o
r
k
7.5 k 1%
20 pF
20 MHz
CLK CLKO
1 20 pF
TXD
TXE
TXC
RXC
RXD
CRS
COL
LBK
3
8
0
C
2
6
0.1 F
GND1
300
300 300 300
Green Red
Red Red
From T TMS38054
Token Ring
Transceiver
Additional magnetics and switching logic (not shown) are required to implement the dual network solution.
2
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
2
1
LXT905 AppIication Information
11-83
L1
Simple 10BASE-T Connection
Figure 9 shows a simple 10BASE-T application using an
LXT905 transceiver and a Motorola MC68EN360. The
MC68EN360 is compatible with Mode 1 (MD0 and MD1
both low).
Figure 9: LXT905/MC68EN360 Interface for Full Duplex 10BASE-T (Mode 1)
RCLK
TCLK
TXD
RXD
TEN
CD
COL
LBK
DSQE
LEDC/FDE
MD0
MD1
LEDL
VCC1
VCC2
L
100 pF
1
+5V
GND2 GND3
RBAS
L
X
T
9
0
5
100
11.8 1%
11.8 1%
Not Connected
100 pF
RJ45
TPN
TPP
TPON
TPOP
6
5
4
3
2
1
1
3
16
14
11
9
6
8
1:2
1:1
T
o
1
0
B
a
s
e
-
T
T
w
i
s
t
e
d
P
a
i
r
N
e
t
w
o
r
k
7.5 k 1%
LEDC/FDE requires an open-collector driver.
CLK
CLKO
CLK1-4
CLK1-4
TXD
RXD
RTS
CD
CTS
S
C
C
1
0.1 F
GND1
300
Green
MC68EN360
20 MHz
System
Clock
300
Parallel
/O
+5V
+5V
1
LXT905 UniversaI Ethernet Interface Adapter
11-84
L1
LXT905 TEST SPECIFICATIONS
NOTE
The minimum and maximum values in Tables 5 through 13 and Figures 10 through 25 represent the perIormance
speciIications oI the LXT905 and are guaranteed by test, except where noted by design.
TabIe 5: AbsoIute Maximum VaIues
Parameter SymboI Min Max Units
Supply voltage VCC -0.3 6 V
Ambient operating temperature TOP 0 70 C
Storage temperature TST -65 150 C
CAUTION
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Exposure to maximum rating conditions Ior extended periods may aIIect device reliability.
TabIe 6: Recommended Operating Conditions
Parameter SymboI Min Typ Max Units Test Conditions
Recommended supply voltage
1
VCC 3.135 5.0 5.25 V
Recommended operating temperature TOP 0 70 C
1. Voltage is with respect to ground unless speciIied otherwise.
TabIe 7: I/O EIectricaI Characteristics (Over Recommended Range)
Parameter Sym Min Typ
1
Max Units Test Conditions
Input low voltage
2
VIL 0.8 V
Input high voltage
2
VIH 2.0 V
Output low voltage VOL 0.4 V IOL 1.6 mA
VOL 10 VCC
IOL 10

A
Output low voltage
(Open drain LED driver)
VOLL 0.7 VCC IOLL 10 mA
Output high voltage VOH 2.4 V
IOH 40

A
VOH 90 VCC IOH 10 A
1. Typical values are at 25 C and are Ior design aid only; not guaranteed and not subject to production testing.
2. Limited Iunctional tests are perIormed at these input levels. The majority oI Iunctional tests are perIormed at levels oI 0V and 3V. This applies
to all inputs except TPIP and TPIN.
11-85
L1
LXT905 Test Specifications
Output rise time
TCLK & RCLK
CMOS 3 15 ns CLOAD 20 pF
TTL 2 15 ns
Output Iall time
TCLK & RCLK
CMOS 3 15 ns CLOAD 20 pF
TTL 2 15 ns
CLKI rise time (externally driven) 10 ns
CLKI duty cycle (externally driven) 50/50 40/60
Supply current Normal
Mode
ICC 40 80 mA Idle Mode
ICC 70 100 mA Transmitting on TP
Power Down Mode ICC 0.01 1
A
TabIe 8: TP EIectricaI Characteristics (Over Recommended Range)
Parameter SymboI Min Typ
1
Max Units Test Conditions
Transmit output impedance ZOUT 5
Transmit timing jitter addition
2
6.4 10 ns 0 line length Ior internal MAU
Transmit timing jitter added by
the MAU and PLS sections
2, 3
3.5 5.5 ns AIter line model speciIied by
IEEE 802.3 Ior 10BASE-T inter-
nal MAU
Receive input impedance ZIN 24 k Between TPIP/TPIN
DiIIerential squelch threshold VDS 300 420 585 mV 5 MHz square wave input
1. Typical values are at 25 C and are Ior design aid only; not guaranteed and not subject to production testing.
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 speciIies maximum jitter additions at 0.5 ns Irom the encoder, and 3.5 ns Irom the MAU.
TabIe 9: Switching Characteristics (Over Recommended Range)
Parameter SymboI Minimum TypicaI
1
Maximum Units
Jabber Timing Maximum transmit time 20 150 ms
Unjab time 250 750 ms
Link Integrity
Timing
Time link loss receive 50 150 ms
Link min receive 2 7 ms
Link max receive 50 150 ms
Link transmit period 8 10 24 ms
1. Typical values are at 25 C and are Ior design aid only; not guaranteed and not subject to production testing.
TabIe 7: I/O EIectricaI Characteristics (Over Recommended Range) continued
Parameter Sym Min Typ
1
Max Units Test Conditions
1. Typical values are at 25 C and are Ior design aid only; not guaranteed and not subject to production testing.
2. Limited Iunctional tests are perIormed at these input levels. The majority oI Iunctional tests are perIormed at levels oI 0V and 3V. This applies
to all inputs except TPIP and TPIN.
LXT905 UniversaI Ethernet Interface Adapter
11-86
L1
TabIe 10: RCLK/Start-of-Frame Timing (Over Recommended Range)
Parameter SymboI Min Typ
1
Max Units
Decoder acquisition time tDATA 1300 1500 ns
CD turn-on delay tCD 400 550 ns
Receive data setup Irom RCLK Mode 1 tRDS 60 70 ns
Modes 2, 3 and 4 tRDS 30 45 ns
Receive data hold Irom RCLK Mode 1 tRDH 10 20 ns
Modes 2, 3 and 4 tRDH 30 45 ns
RCLK shut oII delay Irom CD assert (Mode 3) tsws 100 ns
1. Typical values are at 25 C and are Ior design aid only; not guaranteed and not subject to production testing.
TabIe 11: RCLK/End-of-Frame Timing (Over Recommended Range)
Parameter Type Sym Mode 1 Mode 2 Mode 3 Mode 4 Units
RCLK aIter CD oII Min tRC 5 1 5 bit times
Rcv data through-put delay Max tRD 400 375 375 375 ns
CD turn-oII delay
2
Max tCDOFF 500 475 475 475 ns
Receive block out aIter TEN oII
3
Typical
1
tIFG 5 50 bit times
RCLK switching delay aIter CD oII Typical
1
tswe 120 (80) ns
1. Typical Iigures are at 25 C and are Ior design aid only; not guaranteed and not subject to production testing.
2. CD TurnoII delay measured Irom middle oI last bit: timing speciIication is unaIIected by the value oI the last bit.
3. Blocking oI Carrier Detect is disabled during Iull duplex operation.
11-87
L1
LXT905 Test Specifications
TabIe 12: Transmit Timing (Over Recommended Range)
Parameter SymboI Minimum TypicaI
1
Maximum Units
TEN setup Irom TCLK tEHCH 22 ns
TXD setup Irom TCLK tDSCH 22 ns
TEN hold aIter TCLK tCHEL 5 ns
TXD hold aIter TCLK tCHDU 5 ns
Transmit start-up delay tSTUD 350 450 ns
Transmit through-put delay tTPD 338 350 ns
1. Typical values are at 25 C and are Ior design aid only; not guaranteed and not subject to production testing.
TabIe 13: Miscellaneous Timing (Over Recommended Range)
Parameter SymboI Minimum TypicaI
1
Maximum Units
COL (SQE) Delay aIter TEN oII
2
tSQED 0.65 1.6
s
COL (SQE) Pulse Duration
2
tSQEP 500 1500 ns
Power Down recovery time tPDR 25 ms
1. Typical values are at 25 C and are Ior design aid only; not guaranteed and not subject to production testing.
2. When SQE is enabled (DSQE is Low).
LXT905 UniversaI Ethernet Interface Adapter
11-88
L1
Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low) Figures 10 through 13
Figure 10: Mode 1 RCLK/Start-of-Frame Timing
Figure 11: Mode 1 RCLK/End-of-Frame Timing
NOTE: 1. RXD changes 25 ns after the rising edge of RCLK.
1 1 0 1 0 1 0 1 0 1 1
1 0 1 0 1 0 1 1 1 0 1 0 1
W&'
W'$7$
TPP/TPN
or DP/DN
CD
RCLK
RXD
W5'6
W5'+
0 1 0 0 0 1 0 1 0
NOTE: 1. RXD changes 25 ns after the rising edge of RCLK.
1 0 1 0 1 0 1 0 0
1 0 1 0 1 0 1 0 0
WRD
WCDOFF
TPP/TPN
or DP/DN
CD
RCLK
RXD
WRC
11-89
L1
LXT905 Test Specifications
Figure 12: Mode 1 Transmit Timing
Figure 13: Mode 1 COL Output Timing
tCHEL tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tTPD
tDSCH
tSTUD
WSQEP
WSQED
7(1
&2/
LXT905 UniversaI Ethernet Interface Adapter
11-90
L1
Timing Diagrams for Mode 2 (MD1=Low, MD0=High) Figures 14 through 17
Figure 14: Mode 2 RCLK/Start-of-Frame Timing
Figure 15: Mode 2 RCLK/End-of-Frame Timing
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
1 0 1 0 1 0 1 1 1 0 1 0 1
WCD
WRDS
WRDH
CD
RCLK
RXD
WDATA
TPP/TPN
or DP/DN
1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
1 0 1 0 1 0 1 0 0
tRD
TPP/TPN
or DP/DN
CD
RCLK
RXD
1 0 1 0 1 0 1 0 0
tCDOFF
11-91
L1
LXT905 Test Specifications
Figure 16: Mode 2 Transmit Timing
Figure 17: Mode 2 COL Output Timing
tCHEL tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tDSCH
tTPD tSTUD
NOTE:
1. CD output is disabled for a maximum of 55 bit times after TEN turns off.
WSQED
7(1
&2/
WFG
WSQEP
LXT905 UniversaI Ethernet Interface Adapter
11-92
L1
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low) Figures 18 through 21
Figure 18: Mode 3 RCLK/Start-of-Frame Timing
Figure 19: Mode 3 RCLK/End-of-Frame Timing
Note:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
1 0 1 0 1 0 1 1 1 0 1 0 1
WRDS
WRDH
WDATA
CD
RCLK
RXD
TPP/TPN
1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1
WCD
WSWS Recovered from nput Data Stream
Generated from TCLK
Note:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
tRD
tCDOFF
CD
RCLK
RXD
tSWE
Recovered Clock
Generated from TCLK
1 0 1 0 1 0 1 0 0
1 0 1 0 1 0 1 0 0
TPP/TPN
11-93
L1
LXT905 Test Specifications
Figure 20: Mode 3 Transmit Timing
Figure 21: Mode 3 COL Output Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tSTUD
tDSCH
tTPD
WSQED
7(1
&2/
WSQEP
LXT905 UniversaI Ethernet Interface Adapter
11-94
L1
Timing Diagrams for Mode 4 (MD1 = High, MD0 = High) Figures 22 through 25
Figure 22: Mode 4 RCLK/Start-of-Frame Timing
Figure 23: Mode 4 RCLK/End-of-Frame Timing
Note:
1. RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge.
1 0 1 0 1 0 1 1 1 0 1 0 1
WCD
WDATA
CD
RCLK
RXD
TPP/TPN
or DP/DN
WRDS
WRDH
1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1
Note:
1. RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge.
1 0 1 0 1 0 1 0 0
1 0 1 0 1 0 1 0 0
WRD
TPP/TPN
or DP/DN
CD
RCLK
RXD
WCDOFF
11-95
L1
LXT905 Test Specifications
Figure 24: Mode 4 Transmit Timing
Figure 25: Mode 4 COL Output Timing
tCHEL tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tDSCH
tSTUD
tTPD
WSQEP
WSQED
7(1
&2/
LXT905 UniversaI Ethernet Interface Adapter
11-96
L1
NOTES
LXT905