Mini Project

Power Theft Identification System In Distribution

Lines Using Differential Power Measurement
Submitted by
S.sathishlal (10D11A0236)
Ainash !umar sin"h (10D11A02#1)
$nder Su%erision o&'
Y.BHARATH REDDY
De%artment o& (lectronic and (lectrical (n"ineerin"
)** (+,-+((*-+, ./00,(
(A&&iliated to 1a2aharlal +ehru )echnolo"ical $niersity)
3yderabad4 #02301
5ear' 2013
1
Power Theft Identification System In
Distribution Lines Using Differential
Power Measurement
Mini Project re%ort submitted in %artial &ul&illment o& the re6uirement &or
the
A2ard o& the De"ree o& 7.)ech
7y
S.sathishlal (10D11A0236)
Ainash !umar sin"h (10D11A02#1)
De%artment o& (lectronic and (lectrical (n"ineerin"
)** (+,-+((*-+, ./00,(
(A&&iliated to 1a2aharlal +ehru )echnolo"ical $niersity)
3yderabad4 #02301
5ear' 2013
2
Certificate
)his is to certi&y that the %roject re%ort entitled Power Theft
Identification System In Distribution ines !sin" Differentia# Power $easurement
bein" submitted by Mr.S.sathishlal8 Mr.Ainash !umar sin"h in %artial
&ul&illment &or the a2ard o& the De"ree o& 7achelor o& )echnolo"y in ((( to
the 1a2aharlal +ehru )echnolo"ical $niersity is a record o& bona&ied 2or!
carried out by him under my "uidance and su%erision.
)he results embodied in this %roject re%ort hae not been submitted to any
other $niersity or -nstitute &or the a2ard o& any De"ree or Di%loma.
(3ead o& the De%artment) ,uide +ame 5.bharath reddy
Desi"nation 3/D
3
Certificate
)his is to certi&y that the %roject re%ort entitled Power Theft
Identification System In Distribution ines !sin" Differentia# Power $easurement
bein" submitted by Mr.S.sathishlal8 Mr.Ainash !umar sin"h in %artial
&ul&illment &or the a2ard o& the De"ree o& 7achelor o& )echnolo"y in ((( to
the 1a2aharlal +ehru )echnolo"ical $niersity is a record o& bona&ied 2or!
carried out by him under my "uidance and su%erision.
)he results embodied in this %roject re%ort hae not been submitted to any
other $niersity or -nstitute &or the a2ard o& any De"ree or Di%loma.
(3ead o& the /r"ani9ation) ,uide +ame Mr. M. 3anumanth *ao
Desi"nation
:
AC%&'(ED)E$E&T
;e are %leased to ac!no2led"e Pro& .Dr. (!ambaram +aidu &or "iin" the
%ermission &or course o& this %roject 2or!.
;e are %leased to ac!no2led"e 5.73A*A)3 *(DD5 &or their inaluable
"uidance durin" the course o& this %roject 2or!.
;e e<tend our sincere than!s to Mr. M. 3anumanth *ao 2ho continuously hel%ed
us throu"hout the %roject and 2ithout his "uidance this %roject 2ould hae been
an u%hill tas!.
;e are also "rate&ul to other members o& the 5AM-+- S/=)().3 team 2ho co4
o%erated 2ith us.
;e 2ould also li!e to than! >?-S-/+ -D( &or 2ritin" the ery use&ul so&t2are.
0ast but not least the su%erisor o& =P,A 0ab also co4o%erated 2ith us nicely &or
the smooth deelo%ment o& this %roject.
1uly 2013


S.sathishlal (10D11A0236)
Ainash !umar sin"h (10D11A02#1)
#
I&DE*
CHAPTER +. ABSTRACT,,,,,,,,,,,,,,,,,,-.+/
CHAPTER0. I&TR'D!CTI'& T' E$BEDED SYSTE$S,,,..+0.+1
2.1 -+)*/D$.)-/+
2.2 APP0-.A)-/+S /= (M7(DD(D S5S)(MS
CHAPTER 2. I&TR'D!CTI'& T' $ICR'C&TR'ER,,,,+-.1/
3.1 A)@A.#1
3.2 =(A)$*(S
3.3 )-M(*S
3.: S(*-A0 ./MM$+-.A)-/+
3.# -+)(**$P)S
CHAPTER 3. P'(ER S!PPY,,,,,,,,,,,,,,,,..10.4/
CHAPTER 5. SPECI6IED TECH&'')Y,,,,,,,,,,,..40.-4
#.1 )*-A.
#.2 .$**(+) )*A+S=/*M(*
CHAPTER 1. S'6T(ARE DE7E'P$E&T,,,,,,,,,,-8.+/0
CHAPTER 4. C'&C!SI'&,,,,,,,,,,,,,,,,,+/2.+/5
B.1 ./+.0$S-/+
B.2 *(=(*(+.(

6
CHAPTER +
ABSTRACT
B
Power Theft Identification System In Distribution
Lines Using Differential Power Measurement
Science and technolo"y 2ith all its miraculous adancements has &ascinated
human li&e to a "reat e<tent that ima"inin" a 2orld 2ithout these innoations is hardly
%ossible. ;hile technolo"y is on the raisin" slo%e8 2e should also note the increasin"
immoral actiities. ;ith a technical ie28 CPo2er )he&tD is a non4i"norable crime that is
hi"hly %realent8 and at the same time it directly a&&ects the economy o& a nation.
)his %roject is desi"ned to &ind out such %o2er the&t in the normal distribution
lines. (en thou"h there are certain %ractical %roblems in im%lementin" this !ind o&
systems in &uture there is a sco%e &or deelo%ment o& these ty%es o& systems. )his %roject
is usin" the %rinci%le o& the di&&erential %rotection scheme &or the identi&ication o& the
%o2er the&t. )he di&&erential %rotection scheme consists o& t2o .)s (current
trans&ormers) connected at both the terminals o& the load. -& there is no &ault in the load
then the secondary currents o& both the .)s 2ill be same. $sin" the same %rinci%le one
.) is connected at the startin" end o& the distributor and the remainin" other .) is
connected to the di&&erent loads 2hich are le"al. -& there is no %o2er the&t in the line then
the ector sum o& all the ctEs 2hich are connected to the load 2ill be e6ual to the current
in the main ct. i& there is a di&&erence then 2e can ma!e out that it should either be the
%o2er the&t or a &ault in the line.
)his consists o& the &ollo2in" com%onents'
1) #? dc "eneration unit' )his unit 2ill "ie # dc &rom the 230 ac8 2hich is used as the
internal su%%ly olta"e in the circuit.
2) Measurin" circuit' )his section is built 2ith o% am%s this 2ill "et the data &rom the
entire .) and ma!e the ector sum o& the entire .). All the mathematical o%eration is
%er&ormed in this section by usin" /P Am%s.
@
S'6T(ARE T''S9
%EI -D( &or deelo%in" micro controller code
'RCAD &or desi"nin" schematics
PR''AD or 6ASH $A)IC &or dum%in" the he< &ile into controller
HARD(ARE T''S9
AT-8C5+ Micro controller.
$'C2/0+ &or driin" )*-A.s.
BT+21 &or controllin" A. loads.
.urrent trans&ormers
AD.
*e"ulated :5; Po2er su%%ly.
AD7A&TA)ES9
*eal4time %o2er monitorin".
Sensin" the %o2er the&t at the e<act location.
)ransmittin" the in&ormation oer 2ireless.
*educes man%o2er
3i"hly secured and easy to install
APPICATI'&S9
Po2er monitorin" at homes8 a%artments
-ndustrial %o2er monitorin"
A
10
MICROCONTROLER
MICROCONTROLER
230 V
AC
SUPPLY
230 V
AC
SUPPLY
POWER SUPPLY
SECTlON
5 V DC
SUPPLY
CRYSTAL
LC
D
LC
D
ADC
ADC
CT l
CT l
CT 2
CT 2
LOAD
l
LOAD
l
THEFT
LOAD
THEFT
LOAD
CHAPTER 2
INTRODUCTION TO EMBEDDED SYSTEM
11
2. INTRODUCTION TO EMBEDDED SYSTEM
An embedded system is a special-purpose computer system designed to
perform one or a few dedicated functions, sometimes with real-time computing
constraints. lt is usually embedded as part of a complete device including
hardware and mechanical parts. ln contrast, a general-purpose computer, such
as a personal computer, can do many different tasks depending on
programming. Embedded systems have become very important today as they
control many of the common devices we use.
Since the embedded system is dedicated to specific tasks, design
engineers can optimize it, reducing the size and cost of the product, or increasing
the reliability and performance. Some embedded systems are mass-produced,
benefiting from economies of scale.
Physically, embedded systems range from portable devices such as digital
watches and MP3 players, to large stationary installations like traffic lights,
factory controllers, or the systems controlling nuclear power plants. Complexity
varies from low, with a single microcontroller chip, to very high with multiple units,
peripherals and networks mounted inside a large chassis or enclosure.
ln general, "embedded system" is not an exactly defined term, as many
systems have some element of programmability. For example, Handheld
computers share some elements with embedded systems such as the
operating systems and microprocessors which power them but are not truly
embedded systems, because they allow different applications to be loaded and
peripherals to be connected.
An embedded system is some combination of computer hardware and
software, either fixed in capability or programmable, that is specifically designed
for a particular kind of application device. lndustrial machines, automobiles,
medical equipment, cameras, household appliances, airplanes, vending
12
machines, and toys (as well as the more obvious cellular phone and PDA) are
among the myriad possible hosts of an embedded system. Embedded systems
that are programmable are provided with a programming interface, and
embedded systems programming is a specialized occupation.
Certain operating systems or language platforms are tailored for the
embedded market, such as Embedded Java and Windows XP Embedded.
However, some low-end consumer products use very inexpensive
microprocessors and limited storage, with the application and operating system
both part of a single program. The program is written permanently into the
system's memory in this case, rather than being loaded into RAM (random
access memory), as programs on a personal computer are.
2.1 APPLICATIONS OF EMBEDDED SYSTEM
We are living in the Embedded World. You are surrounded with many
embedded products and your daily life largely depends on the proper functioning
of these gadgets. Television, Radio, CD player of your living room, Washing
Machine or Microwave Oven in your kitchen, Card readers, Access Controllers,
Palm devices of your work space enable you to do many of your tasks very
effectively. Apart from all these, many controllers embedded in your car take care
of car operations between the bumpers and most of the times you tend to ignore
all these controllers.
ln recent days, you are showered with variety of information about these
embedded controllers in many places. All kinds of magazines and journals
regularly dish out details about latest technologies, new devices; fast applications
which make you believe that your basic survival is controlled by these embedded
products. Now you can agree to the fact that these embedded products have
successfully invaded into our world. You must be wondering about these
embedded controllers or systems. What is this Embedded System?
13
The computer you use to compose your mails, or create a document or
analyze the database is known as the standard desktop computer. These
desktop computers are manufactured to serve many purposes and applications.
You need to install the relevant software to get the required processing
facility. So, these desktop computers can do many things. ln contrast, embedded
controllers carryout a specific work for which they are designed. Most of the time,
engineers design these embedded controllers with a specific goal in mind. So
these controllers cannot be used in any other place.
Theoretically, an embedded controller is a combination of a piece of
microprocessor based hardware and the suitable software to undertake a specific
task.
These days designers have many choices in
microprocessors/microcontrollers. Especially, in 8 bit and 32 bit, the available
variety really may overwhelm even an experienced designer. Selecting a right
microprocessor may turn out as a most difficult first step and it is getting
complicated as new devices continue to pop-up very often.
ln the 8 bit segment, the most popular and used architecture is lntel's 803l.
Market acceptance of this particular family has driven many semiconductor
manufacturers to develop something new based on this particular architecture.
Even after 25 years of existence, semiconductor manufacturers still come out
with some kind of device using this 803l core.
Military a! a"r#$%a&" $#'t(ar" a%%li&ati#$
From in-orbit embedded systems to jumbo jets to vital battlefield networks,
designers of mission-critical aerospace and defense systems requiring real-time
performance, scalability, and high-availability facilities consistently turn to the
LynxOS RTOS and the LynxOS-l78 RTOS for software certification to DO-
l78B.
1:
Rich in system resources and networking services, LynxOS provides an off-
the-shelf software platform with hard real-time response backed by powerful
distributed computing (CORBA), high reliability, software certification, and long-
term support options.The LynxOS-l78 RTOS for software certification, based on
the RTCA DO-l78B standard, assists developers in gaining certification for their
mission- and safety-critical systems. Real-time systems programmers get a boost
with LynuxWorks' DO-l78B RTOS training courses.LynxOS-l78 is the first DO-
l78B and EUROCAE/ED-l2B certifiable, POSlX-compatible RTOS solution.
Communications a<<#ications
"Five-nines" availability, CompactPCl hot swap support, and hard real-time
responseLynxOS delivers on these key requirements and more for today's
carrier-class systems. Scalable kernel configurations, distributed computing
capabilities, integrated communications stacks, and fault-management facilities
make LynxOS the ideal choice for companies looking for a single operating
system for all embedded telecommunications applicationsfrom complex central
controllers to simple line/trunk cards.
LynuxWorks Jumpstarts for Communications package enables OEMs to
rapidly develop mission-critical communications equipment, with pre-integrated,
state-of-the-art, data networking and porting software componentsincluding
source code for easy customization.
The Lynx Certifiable Stack (LCS) is a secure TCP/lP protocol stack designed
especially for applications where standards certification is required.
El"&tr#i&$ a%%li&ati#$ a! &#$)*"r !"+i&"$
As the number of powerful embedded processors in consumer devices
continues to rise, the Blue Cat Linux operating system provides a highly
reliable and royalty-free option for systems designers.
1#
And as the wireless appliance revolution rolls on, web-enabled navigation
systems, radios, personal communication devices, phones and PDAs all benefit
from the cost-effective dependability, proven stability and full product life-cycle
support opportunities associated with Blue Cat embedded Linux. Blue Cat has
teamed up with industry leaders to make it easier to build Linux mobile phones
with Java integration.
For makers of low-cost consumer electronic devices who wish to integrate the
LynxOS real-time operating system into their products, we offer special MSRP-
based pricing to reduce royalty fees to a negligible portion of the device's MSRP.
I!)$trial a)t#*ati# a! %r#&"$$ &#tr#l $#'t(ar"
Designers of industrial and process control systems know from experience
that LynuxWorks operating systems provide the security and reliability that their
industrial applications require.From lSO 900l certification to fault-tolerance,
POSlX conformance, secure partitioning and high availability, we've got it all.
Take advantage of our 20 years of experience.
16
CHAPTER 2
I&TR'D!CTI'& T' $ICR'C'&TR'ERS
1B
$ICR' C'&TR'ER -8C5+
Introduction
A Micro controller consists o& a %o2er&ul .P$ ti"htly cou%led 2ith memory8
arious -F/ inter&aces such as serial %ort8 %arallel %ort timer or counter8 interru%t
controller8 data ac6uisition inter&aces4Analo" to Di"ital conerter8 Di"ital to Analo"
conerter8 inte"rated on to a sin"le silicon chi%.
-& a system is deelo%ed 2ith a micro%rocessor8 the desi"ner has to "o &or e<ternal
memory such as *AM8 */M8 (P*/M and %eri%herals. 7ut controller is %roided all
these &acilities on a sin"le chi%. Deelo%ment o& a Micro controller reduces P.7 si9e and
cost o& desi"n.
/ne o& the major di&&erences bet2een a Micro%rocessor and a Micro controller is that a
controller o&ten deals 2ith bits not bytes as in the real 2orld a%%lication.
-ntel has introduced a &amily o& Micro controllers called the M.S4#1.
The $a=or 6eatures9
.om%atible 2ith M.S4#1 %roducts
:! 7ytes o& in4system *e%ro"rammable &lash memory
=ully static o%eration' 03G to 2:M3G
)hree leel %ro"rammable cloc!
12@ H @ Ibit timerFcounters
Si< interru%t sources
Pro"rammable serial channel
0o2 %o2er idle %o2er4do2n modes
1@
,-y AT ./C01
The system requirements and control specifications clearly rule out the
use of l6, 32 or 64 bit micro controllers or microprocessors. Systems using these
may be earlier to implement due to large number of internal features. They are
also faster and more reliable but, 8-bit micro controller satisfactorily serves the
above application. Using an inexpensive 8-bit Microcontroller will doom the 32-bit
product failure in any competitive market place.
.omin" to the 6uestion o& 2hy to use A)@A.#1 o& all the @4bit microcontroller
aailable in the mar!et the main ans2er 2ould be because it has : Jb on chi% &lash
memory 2hich is just su&&icient &or our a%%lication. )he on4chi% =lash */M allo2s the
%ro"ram memory to be re%ro"rammed in system or by conentional non4olatile memory
Pro"rammer. Moreoer A)M(0 is the leader in &lash technolo"y in todayEs mar!et %lace
and hence usin" A) @A.#1 is the o%timal solution.
AT./C01 MICROCONTROLLER ARCHITECTURE
The 89C5l architecture consists of these specific features:
Eight bit CPU with registers A (the accumulator) and B
Sixteen-bit program counter (PC) and data pointer (DPTR)
Eight- bit stack pointer (PSW)
Eight-bit stack pointer (Sp)
lnternal ROM or EPROM (875l) of 0(803l) to 4K (89C5l)
lnternal RAM of l28 bytes:
l. Four register banks, each containing eight registers
2. Sixteen bytes, which maybe addressed at the bit level
3. Eighty bytes of general- purpose data memory
1A
Thirty two input/output pins arranged as four 8-bit ports:p0-p3
Two l6-bit timer/counters: T0 and Tl
Full duplex serial data receiver/transmitter: SBUF
Control registers: TCON, TMOD, SCON, PCON, lP, and lE
Two external and three internal interrupts sources.
Oscillator and clock circuits.

Fig 7 : Functional block diagram of micro controller

T-" ./C01 #$&illat#r a! &l#&12
)he heart o& the @A.#1 circuitry that "enerates the cloc! %ulses by 2hich all the
internal all internal o%erations are synchroni9ed. Pins K)A01 And K)A02 is %roided
&or connectin" a resonant net2or! to &orm an oscillator. )y%ically a 6uart9 crystal and
ca%acitors are em%loyed. )he crystal &re6uency is the basic internal cloc! &re6uency o&
20
the microcontroller. )he manu&acturers ma!e @A.#1 desi"ns that run at s%eci&ic
minimum and ma<imum &re6uencies ty%ically 1 to 16 M39
4 /scillator and timin" circuit
21
Ty%"$ #' *"*#ry2
The 89C5l have three general types of memory. They are on-chip
memory, external Code memory and external Ram. On-Chip memory refers to
physically existing memory on the micro controller itself. External code memory
is the code memory that resides off chip. This is often in the form of an external
EPROM. External RAM is the Ram that resides off chip. This often is in the form
of standard static RAM or flash RAM.
a3 C#!" *"*#ry
Code memory is the memory that holds the actual 89C5l programs that is
to be run. This memory is limited to 64K. Code memory may be found on-chip or
off-chip. lt is possible to have 4K of code memory on-chip and 60K off chip
memory simultaneously. lf only off-chip memory is available then there can be
64K of off chip ROM. This is controlled by pin provided as EA
43 It"ral RAM
The 89C5l have a bank of l28 of internal RAM. The internal RAM is
found on-chip. So it is the fastest Ram available. And also it is most flexible in
terms of reading and writing. lnternal Ram is volatile, so when 89C5l is reset,
this memory is cleared. l28 bytes of internal memory are subdivided. The first 32
bytes are divided into 4 register banks. Each bank contains 8 registers. lnternal
RAM also contains l28 bits, which are addressed from 20h to 2Fh. These bits
are bit addressed i.e. each individual bit of a byte can be addressed by the user.
They are numbered 00h to 7Fh. The user may make use of these variables with
commands such as SETB and CLR.
22
&3 FLASH MEMORY2
Flash memory (sometimes called "flash RAM") is a type of constantly-
powered non volatile that can be erased and reprogrammed in units of memory
called blocks. lt is a variation of electrically erasable programmable read-only
memory (EEPROM) which, unlike flash memory, is erased and rewritten at the
byte level, which is slower than flash memory updating. Flash memory is often
used to hold control code such as the basic input/output system (BlOS) in a
personal computer. When BlOS needs to be changed (rewritten), the flash
memory can be written to in block (rather than byte) sizes, making it easy to
update. On the other hand, flash memory is not useful as random access
memory (RAM) because RAM needs to be addressable at the byte (not the
block) level.
Flash memory gets its name because the microchip is organized so that a
section of memory cells are erased in a single action or "flash." The erasure is
caused by Fowler-Nordheim tunneling in which electrons pierce through a thin
dielectric material to remove an electronic charge from a floating gate associated
with each memory cell. lntel offers a form of flash memory that holds two bits
(rather than one) in each memory cell, thus doubling the capacity of memory
without a corresponding increase in price.
Flash memory is used in digital cellular phones, digital cameras, LAN
switches, PC Cards for notebook computers, digital set-up boxes, embedded
controllers, and other devices.
23
M"*#ry Ty%" F"at)r"$
FLASH Low-cost, high-density, high-speed
architecture; low power; high
reliability
ROM
Read-Only Memory
Mature, high-density, reliable, low
cost; time-consuming mask
required, suitable for high production
with stable code
SRAM
Static Random-Access Memory
Highest speed, high-power, low-
density memory; limited density
drives up cost
EPROM
Electrically Programmable Read-
Only Memory
High-density memory; must be
exposed to ultraviolet light for
erasure
EEPROM#rE
2
PROM
Electrically Erasable
Programmable Read-Only
Memory
Electrically byte-erasable;
lower reliability, higher cost,
lowest density
DRAM
Dynamic Random Access
Memory
High-density, low-cost, high-
speed, high-power
T"&-i&al O+"r+i"( #' Fla$- M"*#ry
Flash memory is a nonvolatile memory using NOR technology, which
allows the user to electrically program and erase information. lntel Flash
memory uses memory cells similar to an EPROM, but with a much thinner,
2:
precisely grown oxide between the floating gate and the source . Flash
programming occurs when electrons are placed on the floating gate. The charge
is stored on the floating gate, with the oxide layer allowing the cell to be
electrically erased through the source. lntel Flash memory is an extremely
reliable nonvolatile memory architecture.
=i" @' Pin dia"ram o& A)@A.#1
Pi D"$&ri%ti#2
VCC2 Supply voltage.
2#
5ND2 Ground.
P#rt 02
Port 0 is an @4bit o%en4drain bi4directional -F/ %ort. As an out%ut %ort8 each %in
can sin! ei"ht ))0 in%uts. ;hen oneEs are 2ritten to %ort 0 %ins8 the %ins can be used as
hi"h im%edance in%uts. Port 0 may also be con&i"ured to be the multi%le<ed lo2 order
addressFdata bus durin" accesses to e<ternal %ro"ram and data memory. -n this mode P0
has internal %ull4u%s. Port 0 also receies the code bytes durin" =lash %ro"rammin"8 and
out%uts the code bytes durin" %ro"ram eri&ication. (<ternal %ull4u%s are re6uired durin"
%ro"ram eri&ication.
P#rt 12
Port 1 is an @4bit bi4directional -F/ %ort 2ith internal %ull4u%s. )he Port 1 out%ut
bu&&ers can sin!Fsource &our ))0 in%uts. ;hen 1s are 2ritten to Port 1 %ins they are
%ulled hi"h by the internal %ull4u%s and can be used as in%uts. As in%uts8 Port 1 %ins that
are e<ternally bein" %ulled lo2 2ill source current (--0) because o& the internal %ull4u%s.
Port 1 also receies the lo24order address bytes durin" =lash %ro"rammin" and
eri&ication.
P#rt 22
Port 2 is an @4bit bi4directional -F/ %ort 2ith internal %ull4u%s. )he Port 2 out%ut
bu&&ers can sin!Fsource &our ))0 in%uts. ;hen 1s are 2ritten to Port 2 %ins they are
%ulled hi"h by the internal %ull4u%s and can be used as in%uts. As in%uts8 Port 2 %ins that
are e<ternally bein" %ulled lo2 2ill source current (--0) because o& the internal %ull4u%s.
Port 2 emits the hi"h4order address byte durin" &etches &rom e<ternal %ro"ram memory
and durin" accesses to e<ternal data memories that use 164bit addresses (M/?K
LDP)*). -n this a%%lication8 it uses stron" internal %ull4u%s 2hen emittin" 1s. Durin"
accesses to e<ternal data memories that use @4bit addresses (M/?K L *-)8 Port 2 emits
the contents o& the P2 S%ecial =unction *e"ister. Port 2 also receies the hi"h4order
address bits and some control si"nals durin" =lash %ro"rammin" and eri&ication.
26
P#rt 32
Port 3 is an 8-bit bi-directional l/O port with internal pull-ups. The Port 3
output buffers can sink/source four TTL inputs. When ls are written to Port 3 pins
they are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source current (llL) because
of the pull-ups.
Port 3 also serves the functions of various special features of the AT89C5l as
listed below:
Port 3 also receives some control signals for Flash programming and verification
Tab 6.2.l Port pins and their alternate functions
RST2
Reset input. A high on this pin for two machine cycles while the oscillator
is running resets the device.
ALE6PRO52
2B
Address 0atch (nable out%ut %ulse &or latchin" the lo2 byte o& the address durin"
accesses to e<ternal memory. )his %in is also the %ro"ram %ulse in%ut (P*/,) durin"
=lash %ro"rammin". -n normal o%eration A0( is emitted at a constant rate o& 1F6the
oscillator &re6uency8 and may be used &or e<ternal timin" or cloc!in" %ur%oses. +ote8
ho2eer8 that one A0( %ulse is s!i%%ed durin" each access to e<ternal Data Memory.
lf desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH.
With the bit set, ALE is active only during a MOVX or MOVC instruction.
Otherwise, the pin is pulled high. Setting the ALE-disable bit has no effect if the
microcontroller is in external execution mode.
PSEN2
Pro"ram Store (nable is the read strobe to e<ternal %ro"ram memory. ;hen the
A)@A.#1 is e<ecutin" code &rom e<ternal %ro"ram memory8 PS(+ is actiated t2ice
each machine cycle8 e<ce%t that t2o PS(+ actiations are s!i%%ed durin" each access to
e<ternal data memory.
EA6VPP2
External Access Enable EA must be strapped to GND in order to enable
the device to fetch code from external program memory locations starting at
0000H up to FFFFH.
Note, however, that if lock bit l is programmed, EA will be internally
latched on reset.
EA should be strapped to VCC for internal program executions. This pin also
receives the l2-volt programming enable voltage (VPP) during Flash
programming, for parts that require l2-volt VPP.
7TAL12
2@
-n%ut to the inertin" oscillator am%li&ier and in%ut to the internal cloc! o%eratin"
circuit.
7TAL22
lt is the Output from the inverting oscillator amplifier.
O$&illat#r C-ara&t"ri$ti&$2
K)A01 and K)A02 are the in%ut and out%ut8 res%ectiely8 o& an inertin"
am%li&ier 2hich can be con&i"ured &or use as an on4chi% oscillator8 as sho2n in =i"s A.
(ither a 6uart9 crystal or ceramic resonator may be used. )o drie the deice &rom an
e<ternal cloc! source8 K)A02 should be le&t unconnected 2hile K)A01 is drien as
sho2n in =i"ure 10.)here are no re6uirements on the duty cycle o& the e<ternal cloc!
si"nal8 since the in%ut to the internal cloc!in" circuitry is throu"h a diide4by4t2o &li%4
&lo%8 but minimum and ma<imum olta"e hi"h and lo2 time s%eci&ications must be
obsered.
Fig 9 Oscillator Connections
2A
Fig l0 External Clock Drive Configuration

&otes'
2 Under steady state (non-transient) conditions, lOL must be
externally
limited as follows:
Maximum lOL per port pin : l0 mA
Maximum lOL per 8-bit port : Port 0 : 26 mA
Ports l, 2, 3: l5 mA
Maximum total lOL for all output pins: 7l mA
lf lOL exceeds the test condition, VOL may exceed the related
specification. Pins are not guaranteed to sink current greater than the
listed test conditions.
2. Minimum VCC for Power-down is 2V.
RE5ISTERS2
ln the CPU, registers are used to store information temporarily. That
information could be a byte of data to be processed, or an address pointing to the
30
data to be fetched. The vast majority of 805l registers are 8bit registers. ln the
805l there is only one data type: 8bits. The 8bits of a register are shown in the
diagram from the MSB (most significant bit) D7 to the LSB (least significant bit)
D0. With an 8-bit data type, any data larger than 8bits must be broken into 8-bit
chunks before it is processed. Since there are a large number of registers in the
805l, we will concentrate on some of the widely used general-purpose registers
and cover special registers in future chapters.
D
7
D
6
D
5
D
4
D
3
D
2
D
l
D
0
The most widely used registers of the 805l are A (accumulator), B, R0,
Rl, R2, R3, R4, R5, R6, R7, DPTR (data pointer), and PC (program counter). All
of the above registers are 8-bits, except DPTR and the program counter. The
accumulator, register A, is used for all arithmetic and logic instructions.
S6Rs >S<ecia# 6unction Re"isters?
Amon" the re"isters *04*B is %art o& the 12@ bytes o& *AM memory. ;hat about
re"isters A8 78 PS;8 and DP)*M Do they also hae addressesM )he ans2er is yes. -n the
@0#18 re"isters A8 78 PS; and DP)* are %art o& the "rou% o& re"isters commonly
re&erred to as S=* (s%ecial &unction re"isters). )here are many s%ecial &unction re"isters
and they are 2idely used. )he S=* can be accessed by the names (2hich is much easier)
or by their addresses. =or e<am%le8 re"ister A has address (0h8 and re"ister 7 has been
i"nited the address =038 as sho2n in table.
)he &ollo2in" t2o %oints should noted about the S=* addresses.
1. )he S%ecial &unction re"isters hae addresses bet2een @03 and ==3. )hese
addresses are aboe @038 since the addresses 00 to B=3 are addresses o& *AM
memory inside the @0#1.
31
2. +ot all the address s%ace o& @03 to ==3 is used by the S=*. )he unused
locations @03 to ==3 are resered and must not be used by the @0#1
%ro"rammer.
*e"ardin" direct addressin" mode8 notice the &ollo2in" t2o %oints' (a) the
address alue is limited to one byte8 004==38 2hich means this addressin" mode is
limited to accessin" *AM locations and re"isters located inside the @0#1. (b) -& you
e<amine the l
st
&ile &or an assembly lan"ua"e %ro"ram8 you 2ill see that the S=* re"isters
names are re%laced 2ith their addresses as listed in table.
Sy*4
#l
Na*" A!!r"
$$
ACC Accumulator 0E0H
B B register 0F0H
PSW Program status word 0D0H
SP Stack pointer 8lH
DPTR Data pointer 2 bytes
DPL Low byte 82H
DPH High byte 83H
P0 Port0 80H
Pl Portl 90H
P2 Port2 0A0H
P3 Port3 0B0H
lP lnterrupt priority control 0B8H
lE lnterrupt enable control 0A8H
TMOD Timer/counter mode control 89H
TCON Timer/counter control 88H
T2CO
N
Timer/counter 2 control 0C8H
T2MO Timer/counter mode2 control 0C9H
32
D
TH0 Timer/counter 0high byte 8CH
TL0 Timer/counter 0 low byte 8AH
THl Timer/counter l high byte 8DH
TLl Timer/counter l low byte 8BH
TH2 Timer/counter 2 high byte 0CDH
TL2 Timer/counter 2 low byte 0CCH
RCAP
2H
T/C 2 capture register high
byte
0CBH
RCAP
2L
T/C 2 capture register low
byte
0CAH
SCON Serial control 98H
SBUF Serial data buffer 99H
PCON Power control 87H
Ta4l"2 .001 S%"&ial ')&ti# r"8i$t"r A!!r"$$
A R"8i$t"r 9A&&)*)lat#r3

Fig ll: Accumulator register
)his is a "eneral4%ur%ose re"ister 2hich seres &or storin" intermediate results durin"
o%eratin". A number (an o%erand) should be added to the accumulator %rior to e<ecute an
33
instruction u%on it. /nce an arithmetical o%eration is %re&ormed by the A0$8 the result is
%laced into the accumulator. -& a data should be trans&erred &rom one re"ister to another8
it must "o throu"h accumulator. =or such uniersal %ur%ose8 this is the most commonly
used re"ister that none microcontroller can be ima"ined 2ithout (more than a hal& @0#1
microcontrollerEs instructions used use the accumulator in some 2ay).
B R"8i$t"r
7 re"ister is used durin" multi%ly and diide o%erations 2hich can be %er&ormed only
u%on numbers stored in the A and 7 re"isters. All other instructions in the %ro"ram can
use this re"ister as a s%are accumulator (A).
Fig l2: B register
During programming, each of registers is called by name so that their
exact address is not so important for the user. During compiling into machine
code (series of hexadecimal numbers recognized as instructions by the
microcontroller), PC will automatically, instead of registers' name, write
necessary addresses into the microcontroller.
R R"8i$t"r$ 9R0:R;3
3:
Fig l3:RAM
)his is a common name &or the total @ "eneral %ur%ose re"isters (*08 *18 and
*2 ...*B). (en they are not true S=*s8 they desere to be discussed here because o& their
%ur%ose. )he ban! is actie 2hen the * re"isters it includes are in use. Similar to the
accumulator8 they are used &or tem%orary storin" ariables and intermediate results.
;hich o& the ban!s 2ill be actie de%ends on t2o bits included in the PS; *e"ister.
)hese re"isters are stored in &our ban!s in the sco%e o& *AM.
)he &ollo2in" e<am%le best illustrates the use&ul %ur%ose o& these re"isters.
Su%%ose that mathematical o%erations on numbers %reiously stored in the * re"isters
should be %er&ormed' (*1N*2) I (*3N*:). /biously8 a re"ister &or tem%orary storin"
results o& addition is needed. (erythin" is 6uite sim%le and the %ro"ram is as &ollo2s'
$'7 A@ R2A Means' moe number &rom *3 into accumulator
ADD A@ R3A Means' add number &rom *: to accumulator (result remains in accumulator)
$'7 R5@ AA Means' tem%orarily moes the result &rom accumulator into *#
$'7 A@ R+A Means' moe number &rom *1 into accumulator
ADD A@ R0A Means' add number &rom *2 to accumulator
S!BB A@ R5A Means' subtract number &rom *# (there are *3N*:)
3#
.001 R"8i$t"r Ba1$ a! Sta&1
RAM *"*#ry $%a&" all#&ati# i t-" .001
There are l28 bytes of RAM in the 805l. The l28 bytes of RAM inside
the 805l are assigned addresses 00 to7FH. These l28 bytes are divided into
three different groups as follows:
l. A total of 32 bytes from locations 00 to lFH hex are set aside for
register banks and the stack.
2. A total of l6 bytes from locations 20 to 2FH hex are set aside for bit-
addressable read/write memory.
3. A total of 80 bytes from locations 30H to 7FH are used for read and
write storage, or what is normally called Scratch pad. These 80
locations of RAM are widely used for the purpose of storing data and
parameters nu 805l programmers.
R"8i$t"r 4a1$ i t-" .001
A total of 32bytes of RAM are set aside for the register banks and stack.
These 32 bytes are divided into 4 banks of registers in which each bank has
registers, R0-R7. RAM locations 0 to 7 are set aside for bank 0 of R0-R7 where
R0 is RAM location 0, Rl is RAM location l, and R2 is location 2, and so on, until
memory location7, which belongs to R7 of bank0. The second bank of registers
R0-R7 starts at RAM location 08 and goes to location 0FH. The third bank of R0-
R7 starts at memory location l0H and goes to location l7H. Finally, RAM
locations l8H to lFH are set aside for the fourth bank of R0-R7. Fig shows how
the 32 bytes are allocated into 4 banks.
As we can see from fig l, the bank l uses the same RAM space as the
stack. This is a major problem in programming the 805l. We must either not
use register bankl, or allocate another area of RAM for the stack.
36
D"'a)lt r"8i$t"r 4a1
lf RAM locations 00-lF are set aside for the four register banks, which
register bank of R0-R7 do we have access to when the 805l is powered up? The
answer is register bank 0; that is , RAM locations 0, l,2,3,4,5,6, and 7 are
accessed with the names R0, Rl, R2, R3, R4, R5, R6, and R7 when
programming the 805l. lt is much easier to refer to these RAM locations with
names such as R0, Rl and so on, than by their memory locations as shown in fig
2.The register banks are switched by using the D3 & D4 bits of register PSW.
FlGl4 : RAM Allocation in the 805l
3B
3@
Fig l5: 805l Register Banks and their RAM Addresses
PS, R"8i$t"r 9Pr#8ra* Stat)$ ,#r!3
Fig l6: PSW register
)his is one o& the most im%ortant S=*s. )he Pro"ram Status ;ord (PS;)
contains seeral status bits that re&lect the current state o& the .P$. )his re"ister contains'
.arry bit8 Au<iliary .arry8 t2o re"ister ban! select bits8 /er&lo2 &la"8 %arity bit8 and
user4de&inable status &la". )he A0$ automatically chan"es some o& re"isterEs bits8 2hich
is usually used in re"ulation o& the %ro"ram %er&ormin".
P B Parity bit -& a number in accumulator is een then this bit 2ill be automatically set
(1)8 other2ise it 2ill be cleared (0). -t is mainly used durin" data transmission and
receiin" ia serial communication.
. Bit +. )his bit is intended &or the &uture ersions o& the microcontrollers8 so it is not
su%%osed to be here.
'7 ';erf#ow occurs 2hen the result o& arithmetical o%eration is "reater than 2##
(decimal)8 so that it can not be stored in one re"ister. -n that case8 this bit 2ill be set (1).
-& there is no oer&lo28 this bit 2ill be cleared (0).
RS/@ RS+ B Re"ister banC se#ects bits. )hese t2o bits are used to select one o& the &our
re"ister ban!s in *AM. 7y 2ritin" 9eroes and ones to these bits8 a "rou% o& re"isters *04
*B is stored in one o& &our ban!s in *AM.
3A
RS1 RS2 S%a&" i RAM
0 0 Bank0 00h-07h
0 l Bankl 08h-0Fh
l 0 Bank2 l0h-l7h
l l Bank3 l8h-lFh
6/ B 6#a" /. )his is a "eneral4%ur%ose bit aailable to the user.
AC B AuDi#iary Carry 6#a" is used &or 7.D o%erations only.
CY B Carry 6#a" is the (ninth) au<iliary bit used &or all arithmetical o%erations and shi&t
instructions.
DPTR R"8i$t"r 9Data P#it"r3
)hese re"isters are not true ones because they do not %hysically e<ist. )hey
consist o& t2o se%arate re"isters' DP3 (Data Pointer 3i"h) and (Data Pointer 0o2). )heir
16 bits are used &or e<ternal memory addressin". )hey may be handled as a 164bit
re"ister or as t2o inde%endent @4bit re"isters. 7esides8 the DP)* *e"ister is usually used
&or storin" data and intermediate results 2hich hae nothin" to do 2ith memory
locations.
:0
Fig l7: DPTR register
SP R"8i$t"r 9Sta&1 P#it"r3

Fig l8: SP register
)he stac! is a section o& *AM used by the .P$ to store in&ormation
tem%orarily. )his in&ormation could be data or an address. )he .P$ needs this stora"e
area since there are only a limited number o& re"isters.
How stacCs are accessed in the -/5+
-& the stac! is a section o& *AM8 there must be re"isters inside the .P$ to %oint
to it. )he re"ister used to access the stac! is called the SP (Stac! %oint) *e"ister. )he
stac! %ointer in the @0#1 is only @ bits 2ideO 2hich means that it can ta!e alues o& 00 to
==3. ;hen the @0#1 is %o2ered u%8 the SP re"ister contains alue 0B. )his means that
*AM location 0@ is the &irst location used &or the stac! by the @0#1. )he storin" o& a
.P$ re"ister in the stac! is called a P$S38 and %ullin" the contents o&& the stac! bac!
into a .P$ re"ister is called a P/P. -n other 2ords8 a re"ister is %ushed onto the stac! to
sae it and %o%%ed o&& the stac! to retriee it. )he job o& the SP is ery critical 2hen
%ush and %o% actions are %er&ormed.
Pushin" onto the stacC
-n the @0#1 the stac! %ointer (SP) %oints to the last used location o& the stac!. As
2e %ush data onto the stac!8 the stac! %ointer is incremented by one. +otice that this
:1
di&&erent &rom many micro%rocessors8 notably <@6 %rocessors in 2hich the SP is
decremented 2hen data is %ushed onto the stac!. As each P$S3 is e<ecuted8 the
contents o& the re"ister are saed on the stac! and SP is incremented by 1. +otice that &or
eery byte o& data saed on the stac! and then SP is incremented only once. +otice also
that to %ush the re"isters onto the stac! 2e must use their *AM addresses. =or e<am%le8
the instruction CP$S3D %ushes re"ister *1 onto the stac!.
Po<<in" from the stacC
Po%%in" the contents o& the stac! bac! into a "ien re"ister is the o%%osite %rocess
o& %ushin". ;ith eery %o%8 the to% byte o& the stac! is co%ied to the re"ister s%eci&ied by
the instruction and the stac! %ointer is decremented once.
The u<<er #imit of the stacC
As8 mentioned earlier8 locations 0@ to 1=3 in the @0#1 *AM can be used &or the
stac!. )his is because locations 2042=3 o& *AM are resered &or bit4addressable
memory and must not be used by the stac!. -& in a %ro"ram 2e need more than 2: bytes
(0@ to 1=3P2:bytes) o& stac!8 2e can chan"e the SP to %oint to *AM locations 304B=3.
)his is done 2ith the instruction CM/? SP8 QKKD.
P0< P1< P2< P3 = I%)t6O)t%)t R"8i$t"r$

Fig l9: PORT0 l/O register
-n case that e<ternal memory and serial communication system are not in use
then8 : %orts 2ith in total o& 32 in%ut4out%ut lines are aailable to the user &or connection
to %eri%heral enironment. (ach bit inside these %orts corres%onds to the a%%ro%riate %in
on the microcontroller. )his means that lo"ic state 2ritten to these %orts a%%ears as a
:2
olta"e on the %in (0 or # ?). +aturally8 2hile readin"8 the o%%osite occurs I olta"e on
some in%ut %ins is re&lected in the a%%ro%riate %ort bit.
)he state o& a %ort bit8 besides bein" re&lected in the %in8 determines at the same
time 2hether it 2ill be con&i"ured as in%ut or out%ut. -& a bit is cleared (0)8 the %in 2ill be
con&i"ured as out%ut. -n the same manner8 i& a bit is set to 1 the %in 2ill be con&i"ured as
in%ut. A&ter reset8 as 2ell as 2hen turnin" the microcontroller /+8 all bits on these %orts
are set to one >+?. )his means that the a%%ro%riate %ins 2ill be con&i"ured as in<uts.
Pro"ram counter'
)he im%ortant re"ister in the @0#1 is the P. (Pro"ram counter). )he %ro"ram
counter %oints to the address o& the ne<t instruction to be e<ecuted. As the .P$ &etches
the /P./D( &rom the %ro"ram */M8 the %ro"ram counter is incremented to %oint to the
ne<t instruction. )he %ro"ram counter in the @0#1 is 16bits 2ide. )his means that the
@0#1 can access %ro"ram addresses 0000 to ====38 a total o& 6:! bytes o& code.
3o2eer8 not all members o& the @0#1 hae the entire 6:J bytes o& on4chi% */M
installed8 as 2e 2ill see soon.
Ty<es of instructions
De%endin" on o%eration they %er&orm8 all instructions are diided in seeral "rou%s'
Arithmetic lnstructions
Branch lnstructions
Data Transfer lnstructions
Logical lnstructions
Logical lnstructions with bits
)he &irst %art o& each instruction8 called M+(M/+-. re&ers to the o%eration an
instruction %er&orms (co%yin"8 addition8 lo"ical o%eration etc.). Mnemonics commonly
are shortened &orm o& name o& o%eration bein" e<ecuted. =or e<am%le'
:3
INC R1; lncrement Rl (increment register Rl)
LJMP LAB5 ;Long Jump LAB5 (long jump to address specified as LAB5)
JNZ LOOP ;Jump if Not Zero LOOP (if the number in the accumulator is not 0,
jump to address specified as LOOP)
Another %art o& instruction8 called /P(*A+D is se%arated &rom mnemonic at
least by one em%ty s%ace and de&ines data bein" %rocessed by instructions. Some
instructions hae no o%erandO some hae one8 t2o or three. -& there is more than one
o%erand in instruction8 they are se%arated by comma. =or e<am%le'
RET (return from sub-routine)
JZ TEMP (if the number in the accumulator is not 0, jump to address specified
as TEMP)
ADD A,R3 (add R3 and accumulator)
CJNE A,#20,LOOP (compare accumulator with 20. lf they are not equal, jump to
address specified as LOOP)
Arit-*"ti& i$tr)&ti#$
)hese instructions %er&orm seeral basic o%erations (addition8 subtraction8
diision8 multi%lication etc.) A&ter e<ecution8 the result is stored in the &irst o%erand. =or
e<am%le'
ADD A, R1 The result of addition (A+Rl) will be stored in the accumulator.
Arit-*"ti&al I$tr)&ti#$
M"*#i& D"$&ri%ti#
Byt"
N)*4"r
O$&illat#r
P"ri#!
::
ADD A,Rn Add R Register to accumulator l l
ADD A,Rx
Add directly addressed Rx Register to
accumulator
2 2
ADD A,@Ri
Add indirectly addressed Register to
accumulator
l l
ADD A,#X Add number X to accumulator 2 2
ADDC A,Rn
Add R Register with Carry bit to
accumulator
l l
Bra&- I$tr)&ti#$
)here are t2o !inds o& these instructions'
!nconditiona# =um< instructions9
A&ter their e<ecution a jum% to a ne2 location &rom 2here the %ro"ram
continues e<ecution is e<ecuted.
Conditiona# =um< instructions9
-& some condition is met I a jum% is e<ecuted. /ther2ise8 the %ro"ram normally
%roceeds 2ith the ne<t instruction.
Bra&- I$tr)&ti#
M"*#i& D"$&ri%ti#
Byt"
N)*4"r
O$&illat#r
P"ri#!
ACALL adrll
Call subroutine located at address within 2 K
byte Program Memory space
2 3
LCALL adrl6 Call subroutine located at any address within 3 4
:#
64 K byte Program Memory space
RET Return from subroutine l 4
RETl Return from interrupt routine l 4
AJMP adrll
Jump to address located within 2 K byte
Program Memory space
2 3
LJMP adrl6
Jump to any address located within 64 K byte
Program Memory space
3 4
Data Tra$'"r I$tr)&ti#$
)hese instructions moe the content o& one re"ister to another one. )he re"ister 2hich
content is moed remains unchan"ed. -& they hae the su&&i< CKD (M/?K)8 the data is e<chan"ed
2ith e<ternal memory.
Data Tra$'"r I$tr)&ti#
M"*#i& D"$&ri%ti#
Byt"
N)*4"r
Cy&l"
N)*4"r
MOV A,Rn Move R register to accumulator l l
MOV A,Rx
Move directly addressed Rx register to
accumulator
2 2
MOV A,@Ri
Move indirectly addressed register to
accumulator
l l
MOV A,#X Move number X to accumulator 2 2
L#8i&al I$tr)&ti#$
These instructions perform logical operations between corresponding bits of two
registers. After execution, the result is stored in the first operand.
:6
L#8i&al I$tr)&ti#$
M"*#i& D"$&ri%ti#
Byt"
N)*4"r
Cy&l"
N)*4"r
ANL A,Rn Logical AND between accumulator and R register l l
ANL A,Rx
Logical AND between accumulator and directly
addressed register Rx
2 2
ANL A,@Ri
Logical AND between accumulator and indirectly
addressed register
l l
ANL A,#X Logical AND between accumulator and number X 2 2
L#8i&al O%"rati#$ # Bit$
Similar to lo"ical instructions8 these instructions %er&orm lo"ical o%erations. )he
di&&erence is that these o%erations are %er&ormed on sin"le bits.
L#8i&al #%"rati#$ # 4it$
M"*#i& D"$&ri%ti#
Byt"
N)*4"r
Cy&l"
N)*4"r
CLR C Clear Carry bit l l
CLR bit Clear directly addressed bit 2 2
SETB C Set Carry bit l l
SETB bit Set directly addressed bit 2 2
CPL C Complement Carry bit l l
CPL bit Complement directly addressed bit 2 2
:B
TI$ERS
On-chip timing/counting facility has proved the capabilities of the
microcontroller for implementing the real time application. These includes pulse
counting, frequency measurement, pulse width measurement, baud rate
generation, etc,. Having sufficient number of timer/counters may be a need in a
certain design application. The 805l has two timers/counters. They can be used
either as timers to generate a time delay or as counters to count events
happening outside the microcontroller. Let discuss how these timers are used to
generate time delays and we will also discuss how they are been used as event
counters.
PRO5RAMMIN5 .001 TIMERS
The 805l has timers: Timer 0 and Timerl.they can be used either as timers
or as event counters. Let us first discuss about the timers' registers and how to
program the timers to generate time delays.
BASIC RI5ISTERS OF THE TIMER
Both Timer 0 and Timer l are l6 bits wide. Since the 805l has an 8-bit
architecture, each l6-bit timer is accessed as two separate registers of low byte
and high byte.
TIMER 0 RE5ISTERS
The l6-bit register of Timer 0 is accessed as low byte and high byte. The low
byte register is called TL0(Timer 0 low byte)and the high byte register is referred to as
TH0(Timer 0 high byte).These register can be accessed like any other register, such as
A,B,R0,Rl,R2,etc.for example, the instruction "MOV TL0, #4F"moves the value 4FH
into TL0,the low byte of Timer 0.These registers can also be read like any other register.
:@
Fig 20:Timer 0(TH0 and TL0 ) registers
TIMER 1 RE5ISTERS
Timer l is also l6-bit register is split into two bytes, referred to as TLl
(Timer l low byte) and THl (Timer l high byte).these registers are accessible n
the same way as the register of Timer 0.
TMOD 9ti*"r *#!"3 RE5ISTER
Both timers TlMER 0 and TlMER l use the same register, called TMOD,
to set the various timer operation modes. TMOD is an 8-bit register in which the
lower 4 bits are set aside for Timer 0 and the upper 4 bits for Timer l.in each
case; the lower 2 bits are used to set the timer mode and the upper 2 bits to
specify the operation.
MODES2
M1< M02
:A
M0 and Ml are used to select the timer mode. There are three modes:
0, l, 2.Mode 0 is a l3-bit timer, mode l is a l6-bit timer, and mode 2 is an 8-bit
timer. We will concentrate on modes l and 2 since they are the ones used most
widely. We will soon describe the characteristics of these modes, after describing
the reset of the TMOD register.
5ATE2 Gate control when set. The timer/counter is
enabled only
While the lNTx pin is high and the TRx control
pin is.
Set. When cleared, the timer is enabled.
C6T Timer or counter selected cleared for timer
operation
(lnput from internal system clock).set for
counter
Operation (input TX input pin).
M 1 Mode bit l
M0 Mode bit 0
M1 M0 MODE O%"rati8 M#!"
0 0 0 l3-bit timer mode
8-bit timer/counter THx
with TLx as 5 Bit pre-
scaler.
0 1 1 l6-bit timer mode
#0
l6-bit timer/counters THx
with TLx are Cascaded;
there is no prescaler
1 0 2 8-bit auto reload
8-bit auto reload
timer/counter;THx Holds a
value that is to be reloaded
into TLx each time it
overflows.
1 1 3 Split timer mode.

C6T 9&l#&16ti*"r3
This bit in the TMOD register is used to decide whether the timer is
used as a delay generator or an event counter. lf C/T=0, it is used as a timer for
time delay generation. The clock source for the time delay is the crystal
frequency of the 805l.this section is concerned with this choice. The timer's use
as an event counter is discussed in the next section.
S"rial C#**)i&ati#2
Computers can transfer data in two ways: parallel and serial. ln parallel
data transfers, often 8 or more lines (wire conductors) are used to transfer data
to a device that is only a few feet away. Examples of parallel data transfer are
printers and hard disks; each uses cables with many wire strips. Although in
such cases a lot of data can be transferred in a short amount of time by using
many wires in parallel, the distance cannot be great. To transfer to a device
located many meters away, the serial method is used. ln serial communication,
#1
the data is sent one bit at a time, in contrast to parallel communication, in which
the data is sent a byte or more at a time. Serial communication of the 805l is the
topic of this chapter. The 805l has serial communication capability built into it,
there by making possible fast data transfer using only a few wires.
lf data is to be transferred on the telephone line, it must be converted
from 0s and ls to audio tones, which are sinusoidal-shaped signals. A peripheral
device called a modem, which stands for "modulator/demodulator", performs this
conversion.
Serial data communication uses two methods, asynchronous and
synchronous. The synchronous method transfers a block of data at a time, while
the asynchronous method transfers a single byte at a time.
ln data transmission if the data can be transmitted and received, it is a
duplex transmission. This is in contrast to simplex transmissions such as with
printers, in which the computer only sends data. Duplex transmissions can be
half or full duplex, depending on whether or not the data transfer can be
simultaneous. lf data is transmitted one way at a time, it is referred to as half
duplex. lf the data can go both ways at the same time, it is full duplex. Of
course, full duplex requires two wire conductors for the data lines, one for
transmission and one for reception, in order to transfer and receive data
simultaneously.
A$y&-r##)$ $"rial &#**)i&ati# a! !ata 'ra*i8
The data coming in at the receiving end of the data line in a serial data
transfer is all 0s and ls; it is difficult to make sense of the data unless the sender
and receiver agree on a set of rules, a protocol, on how the data is packed, how
many bits constitute a character, and when the data begins and ends.
Start a! $t#% 4it$
#2
Asynchronous serial data communication is widely used for character-
oriented transmissions, while block-oriented data transfers use the synchronous
method. ln the asynchronous method, each character is placed between start
and stop bits. This is called framing. ln the data framing for asynchronous
communications, the data, such as ASCll characters, are packed between a start
bit and a stop bit. The start bit is always one bit, but the stop bit can be one or
two bits. The start bit is always a 0 (low) and the stop bit (s) is l (high).
Data tra$'"r rat"
The rate of data transfer in serial data communication is stated in bps
(bits per second). Another widely used terminology for bps is baud rate.
However, the baud and bps rates are not necessarily equal. This is due to the
fact that baud rate is the modem terminology and is defined as the number of
signal changes per second. ln modems a single change of signal, sometimes
transfers several bits of data. As far as the conductor wire is concerned, the
baud rate and bps are the same, and for this reason we use the bps and baud
interchangeably.
The data transfer rate of given computer system depends on
communication ports incorporated into that system. For example, the early
lBMPC/XT could transfer data at the rate of l00 to 9600 bps. ln recent years,
however, Pentium based PCS transfer data at rates as high as 56K bps. lt must
be noted that in asynchronous serial data communication, the baud rate is
generally limited to l00,000bps.
RS232 Sta!ar!$
To allow compatibility among data communication equipment made by
various manufacturers, an interfacing standard called RS232 was set by the
Electronics lndustries Association (ElA) in l960. ln l963 it was modified and
called RS232A. RS232B AND RS232C were issued in l965 and l969,
respectively. Today, RS232 is the most widely used serial l/O interfacing
standard. This standard is used in PCs and numerous types of equipment.
#3
However, since the standard was set long before the advert of the TTL logic
family, its input and output voltage levels are not TTL compatible. ln RS232, a l
is represented by -3 to -25V, while a 0 bit is +3 to +25V, making -3 to +3
undefined. For this reason, to connect any RS232 to a microcontroller system
we must use voltage converters such as MAX232 to convert the TTL logic levels
to the RS232 voltage levels, and vice versa. MAX232 lC chips are commonly
referred to as line drivers.
RS232 %i$
*S232 cable is commonly re&erred to as the D742# connector. -n labelin"8 D74
2#P re&ers to the %lu" connector (male) and D742#S is &or the soc!et connector (&emale).
Since not all the %ins are used in P. cables8 -7M introduced the D74A ?ersion o& the
serial -F/ standard8 2hich uses A %ins only8 as sho2n in table.
1 2 3 : #
6 B @ A

(Out of computer and exposed end of cable)
Fig 2l: DB-9 pin connector
Pin Functions:
Pin Descri%tion
1 Data carrier detect (D.D)
2 *eceied data (*KD)
3 )ransmitted data ()KD)
: Data terminal ready(D)*)
# Si"nal "round (,+D)
6 Data set ready (DS*)
B *e6uest to send (*)S)
@ .lear to send (.)S)
A *in" indicator (*-)
#:
+ote' DCD@ DSR@ RTS and CTS are actie lo2 %ins.
)he method used by *S4232 &or communication allo2s &or a sim%le connection o& three
lines' )<8 *<8 and ,round. )he three essential si"nals &or 242ay *S4232
.ommunications are these'
T*D' carries data &rom D)( to the D.(.
R*D' carries data &rom D.( to the D)(
S)' si"nal "round
.001 &#"&ti# t# RS232
The RS232 standard is not TTL compatible; therefore, it requires a line
driver such as the MAX232 chip to convert RS232 voltage levels to TTL levels,
and vice versa. The interfacing of 805l with RS232 connectors via the MAX232
chip is the main topic.
The 805l has two pins that are used specifically for transferring and
receiving data serially. These two pins are called TXD and RXD and a part of the
port 3 group (P3.0 and P3.l). Pin ll of the 805l is assigned to TXD and pin l0 is
designated as RXD. These pins are TTL compatible; therefore, they require a
line driver to make them RS232 compatible. One such line driver is the MAX232
chip.
MAX232 converts from RS232 voltage levels to TTL voltage levels, and
vice versa. One advantage of the MAX232 chip is that it uses a +5V power
source which, is the same as the source voltage for the 805l. ln the other
words, with a single +5V power supply we can power both the 805l and
MAX232, with no need for the power supplies that are common in many older
systems. The MAX232 has two sets of line drivers for transferring and receiving
data. The line drivers used for TXD are called Tl and T2, while the line drivers
##
for RXD are designated as Rl and R2. ln many applications only one of each is
used.






(mbedded
.ontroller
*KD
)KD
)KD
*KD
2
3
#
,+D
MAK 232
FlG 22 :CONNECTlNG C to PC using MAX 232
I&TERR!PTS
A sin"le microcontroller can sere seeral deices. )here are t2o 2ays to do
that' -+)(**$P)S or P/00-+,.
POLLIN52
-n %ollin" the microcontroller continuously monitors the status o& a "ien
deiceO 2hen the status condition is met8 it %er&orms the serice .A&ter that8 it moes on
to monitor the ne<t deice until each one is sericed. Althou"h %ollin" can monitor the
status o& seeral deices and sere each o& them as certain condition are met.
#6
INTERRUPTS2
-n the interru%ts method8 2heneer any deice needs its serice8 the deice
noti&ies the microcontroller by sendin" it an interru%ts si"nal. $%on receiin" an interru%t
si"nal8 the microcontroller interru%ts 2hateer it is doin" and seres the deice. )he
%ro"ram associated 2ith the interru%ts is called the interru%t serice routine (-S*).or
interru%t handler.
INTERRUPTS V$ POLLIN52
)he adanta"e o& interru%ts is that the microcontroller can sere many
deices (not all the same time8 o& course)O each deice can "et the attention o& the
microcontroller based n the %riority assi"ned to it. )he %ollin" method cannot assi"n
%riority since it chec!s all deices in round4robin &ashion. More im%ortantly8 in the
interru%t method the microcontroller can also i"nore (mas!) a deice re6uest &or serice.
)his is a"ain not %ossible 2ith the %ollin" method. )he most im%ortant reason that the
interru%t method is %re&erable is that the %ollin" method 2astes much o& the
microcontrollerEs time by %ollin" deices that do not need serice. So8 in order to aoid
tyin" do2n the microcontroller8 interru%ts are used.
INTERRUPT SERVICE ROUTINE
For every interrupt, there must be an interrupt service routine (lSR), or
interrupt handler. When an interrupt is invoked, the microcontroller runs the
interrupts service routine. For every interrupt, there is a fixed location in memory
that holds the address of its lSR. The group of memory location set aside to hold
the addresses of lSR and is called the lnterrupt Vector Table. Shown below:
It"rr)%t V"&t#r Ta4l" '#r t-" .0012
#B
S.N#. INTERRUPT ROM LOCATION 9HE73 PIN FLA5
CLEARIN5
l. Reset 0000 9 Auto
2. External hardware
lnterrupt 0
0003 P3.2 (l2) Auto
3. Timers 0 interrupt
(TF0)
000B Auto
4. External hardware
lnterrupt l(lNTl)
00l3 P3.3 (l3) Auto
5. Timers l interrupt
(TFl)
00lB Auto
6. Serial COM (Rl
and Tl)
0023 Programmer
clears it
Si> It"rr)%t$ i t-" .0012
ln reality, only five interrupts are available to the user in the 805l, but
many manufacturers' data sheets state that there are six interrupts since they
include reset .the six interrupts in the 805l are allocated as above.
l. Reset. When the reset pin is activated, the 805l jumps to address location
0000.this is the power-up reset.
2. Two interrupts are set aside for the timers: one for Timer 0 and one for
Timer l.Memory location 000BH and 00lBH in the interrupt vector table
belong to Timer 0 and Timer l, respectively.
3. Two interrupts are set aside for hardware external harder interrupts. Pin
number l2(P3.2) and l3(P3.3) in port 3 are for the external hardware
interrupts lNT0 and lNTl,respectively.These external interrupts are also
#@
referred to as EXl and EX2.Memory location 0003H and 00l3H in the
interrupt vector table are assigned to lNT0 and lNTl, respectively.
4. Serial communication has a single interrupt that belongs to both receive
and transmit. The interrupt vector table location 0023H belongs to this
interrupt.
Notice that a limited number of bytes are set aside for each interrupt. For
example, a total of 8 bytes from location 0003 to 000A is set aside for lNT0,
external hardware interrupt 0.similarly,a total of 8 bytes from location 00BH to
00l2H is reserved for TF0, Timer 0 interrupt. lf the service routine for a given
interrupt is short enough to fit in the memory space allocated to it, it is placed in
the vector table; otherwise, and an LJMP instruction is placed in the vector table
to point to the address of the lSR. ln that rest of the bytes allocated to that
interrupt are unused.
From the above table also notice that only three bytes of ROM space
are assigned to the reset pin. They are ROM address location 0,l and2.address
location 3 belongs to external hardware interrupt 0.for this reason, in our program
we put the LJMP as the first instruction and redirect the processor away from
the interrupt vector table, as shown below
St"%$ i ">"&)ti8 a it"rr)%t
Upon activation of an interrupt, the microcontroller goes through the following
steps.
l. lt finishes the instruction it is executing and saves the address of the next
instruction (PC) on the stack.
2. lt also saves the current status of all the interrupts internally (i.e., not on
the stack).
3. lt jumps to a fixed location in memory called the interrupt vector table that
holds the address of the interrupts service routine.
#A
4. The microcontroller gets the address of the lSR from the interrupt vector
table and jumps to it. lt starts to execute the interrupt service subroutine
until it reaches the last instruction of the subroutine, which is RETl (return
from interrupt).
5. Upon executing the RETl instruction, the microcontroller returns to the
place where it was interrupted. First, it gets the program counter (PC)
address from the stack by popping the top two bytes of the stack into the
PC. Then it starts to execute from that address.
Notice from step 5 the critical role of the stack. For this reason, we must be
careful in manipulating the stack contents in the lSR. Specifically, in the lSR, just
as in any CALL subroutine, the number of pushes and pops must be equal.
Ea4li8 a! !i$a4li8 a it"rr)%t2
Upon reset, all interrupt are disabled (masked), meaning that none will
be responded to by the microcontroller if they are activated. The interrupt must
be enabled by software in order for the microcontroller to respond to them. There
is a register called lE (interrupt enable) that is responsible for enabling
(unmasking) and disabling (masking) the interrupts.
Notice that lE is a bit-addressable register.
St"%$ i "a4li8 a it"rr)%t2
To enable an interrupt, we take the following steps:
l. Bit D7 of the lE register (EA) must be set to high to allow the reset to take effect.
lf EA=l, interrupts are enabled and will be responded to if their corresponding bit in lE
are high. lf EA=0, no interrupt will be responded to, even if the associated bit in the lE
register is high.
It"rr)%t Ea4l" R"8i$t"r
D7 D6 D5 D4 D3 D2 Dl D0

60
EA -- ET2 ES ETl EXl ET0 EX0

EA lE.7 disables all interrupts. lf EA=0, no interrupts is acknowledged.
lf EA=l, each interrupt source is individually enabled disabled
By setting or clearing its enable bit.
-- lE.6 Not implemented, reserved for future use.
ET2 lE.5 Enables or disables Timer 2 overflow or capture interrupt (8052
Only)
ES lE.4 Enables or disables the serial port interrupts.
ETl lE.3 Enables or disables Timers l overflow interrupt
EXl lE.2 Enables or disables external interrupt l.
ET0 lE.l Enables or disables Timer 0 overflow interrupt.
EX0 lE.0 Enables or disables external interrupt.
CHAPTER 3
61
P'(ER S!PPY
P'(ER S!PPY
All di"ital circuits re6uire re"ulated %o2er su%%ly. -n this article 2e are "oin" to learn
ho2 to "et a re"ulated %ositie su%%ly &rom the mains su%%ly.

=i"ure 1 sho2s the basic bloc! dia"ram o& a &i<ed re"ulated %o2er su%%ly. 0et us "o
throu"h each bloc!.
TRA&S6'R$ER
62
A trans&ormer consists o& t2o coils also called as C;-+D-+,SD namely P*-MA*5 R
S(./+DA*5.
)hey are lin!ed to"ether throu"h inductiely cou%led electrical conductors also called as
./*(. A chan"in" current in the %rimary causes a chan"e in the Ma"netic =ield in the
core R this in turn induces an alternatin" olta"e in the secondary coil. -& load is a%%lied
to the secondary then an alternatin" current 2ill &lo2 throu"h the load. -& 2e consider an
ideal condition then all the ener"y &rom the %rimary circuit 2ill be trans&erred to the
secondary circuit throu"h the ma"netic &ield.
So

)he secondary olta"e o& the trans&ormer de%ends on the number o& turns in the Primary as 2ell as in
the secondary.
63
Rectifier
A recti&ier is a deice that conerts an A. si"nal into D. si"nal. =or recti&ication %ur%ose
2e use a diode8 a diode is a deice that allo2s current to %ass only in one direction i.e.
2hen the anode o& the diode is %ositie 2ith res%ect to the cathode also called as &or2ard
biased condition R bloc!s current in the reersed biased condition.

*ecti&ier can be classi&ied as &ollo2s'
13 Hal' ,a+" r"&ti'i"r.
)his is the sim%lest ty%e o& recti&ier as you can see in the dia"ram a hal& 2ae recti&ier
consists o& only one diode. ;hen an A. si"nal is a%%lied to it durin" the %ositie hal&
cycle the diode is &or2ard biased R current &lo2s throu"h it. 7ut durin" the ne"atie hal&
cycle diode is reerse biased R no current &lo2s throu"h it. Since only one hal& o& the
in%ut reaches the out%ut8 it is ery ine&&icient to be used in %o2er su%%lies.
6:
23 F)ll (a+" r"&ti'i"r.
3al& 2ae recti&ier is 6uite sim%le but it is ery ine&&icient8 &or "reater e&&iciency 2e
2ould li!e to use both the hal& cycles o& the A. si"nal. )his can be achieed by usin" a
center ta%%ed trans&ormer i.e. 2e 2ould hae to double the si9e o& secondary 2indin" R
%roide connection to the center. So durin" the %ositie hal& cycle diode D1 conducts R
D2 is in reerse biased condition. Durin" the ne"atie hal& cycle diode D2 conducts R D1
is reerse biased. )hus 2e "et both the hal& cycles across the load.
/ne o& the disadanta"es o& =ull ;ae *ecti&ier desi"n is the necessity o& usin" a center
ta%%ed trans&ormer8 thus increasin" the si9e R cost o& the circuit. )his can be aoided by
usin" the =ull ;ae 7rid"e *ecti&ier.
33 Brid"e Rectifier.
6#
As the name su""ests it conerts the &ull 2ae i.e. both the %ositie R the ne"atie hal&
cycle into D. thus it is much more e&&icient than 3al& ;ae *ecti&ier R that too 2ithout
usin" a center ta%%ed trans&ormer thus much more cost e&&ectie than =ull ;ae
*ecti&ier.
=ull 7rid"e ;ae *ecti&ier consists o& &our diodes namely D18 D28 D3 and D:. Durin"
the %ositie hal& cycle diodes D1 R D: conduct 2hereas in the ne"atie hal& cycle diodes
D2 R D3 conduct thus the diodes !ee% s2itchin" the trans&ormer connections so 2e "et
%ositie hal& cycles in the out%ut.

66
-& 2e use a center ta%%ed trans&ormer &or a brid"e recti&ier 2e can "et both %ositie R
ne"atie hal& cycles 2hich can thus be used &or "eneratin" &i<ed %ositie R &i<ed
ne"atie olta"es.
6ITER CAPACIT'R
(en thou"h hal& 2ae R &ull 2ae recti&ier "ie D. out%ut8 none o& them %roides a
constant out%ut olta"e. =or this 2e re6uire to smoothen the 2ae&orm receied &rom the
recti&ier. )his can be done by usin" a ca%acitor at the out%ut o& the recti&ier this ca%acitor
is also called as C=-0)(* .APA.-)/*D or CSM//)3-+, .APA.-)/*D or
C*(S(*?/-* .APA.-)/*D. (en a&ter usin" this ca%acitor a small amount o& ri%%le
2ill remain.
;e %lace the =ilter .a%acitor at the out%ut o& the recti&ier the ca%acitor 2ill char"e to the %ea! olta"e
durin" each hal& cycle then 2ill dischar"e its stored ener"y slo2ly throu"h the load 2hile the recti&ied
olta"e dro%s to 9ero8 thus tryin" to !ee% the olta"e as constant as %ossible.
6B
-& 2e "o on increasin" the alue o& the &ilter ca%acitor then the *i%%le 2ill decrease. 7ut then the
costin" 2ill increase. )he alue o& the =ilter ca%acitor de%ends on the current consumed by the circuit8
the &re6uency o& the 2ae&orm R the acce%ted ri%%le.
;here8
?rP acce%ted ri%%le olta"e. (Should not be more than 10S o& the olta"e)
-P current consumed by the circuit in Am%eres.
=P &re6uency o& the 2ae&orm. A hal& 2ae recti&ier has only one %ea! in one cycle so =P2# 39
;hereas a &ull 2ae recti&ier has )2o %ea!s in one cycle so =P100 39.
6@
7'TA)E RE)!AT'R
A ?olta"e re"ulator is a deice 2hich conerts aryin" in%ut olta"e into a constant
re"ulated out%ut olta"e. ?olta"e re"ulator can be o& t2o ty%es
1) 0inear ?olta"e *e"ulator Also called as *esistie ?olta"e re"ulator because they
dissi%ate the e<cessie olta"e resistiely as heat.
2) S2itchin" *e"ulators.
)hey re"ulate the out%ut olta"e by s2itchin" the .urrent /+F/== ery ra%idly.
Since their out%ut is either /+ or /== it dissi%ates ery lo2 %o2er thus achiein" hi"her
e&&iciency as com%ared to linear olta"e re"ulators. 7ut they are more com%le< R
"enerate hi"h noise due to their s2itchin" action. =or lo2 leel o& out%ut %o2er
s2itchin" re"ulators tend to be costly but &or hi"her out%ut 2atta"e they are much
chea%er than linear re"ulators.
)he most commonly aailable 0inear Positie ?olta"e *e"ulators are the B@KK series
2here the KK indicates the out%ut olta"e. And BAKK series is &or +e"atie ?olta"e
*e"ulators.
A&ter &ilterin" the recti&ier out%ut the si"nal is "ien to a olta"e re"ulator. )he
ma<imum in%ut olta"e that can be a%%lied at the in%ut is 3#?.+ormally there is a 243
?olts dro% across the re"ulator so the in%ut olta"e should be at least 243 ?olts hi"her
than the out%ut olta"e. -& the in%ut olta"e "ets belo2 the ?min o& the re"ulator due to
the ri%%le olta"e or due to any other reason the olta"e re"ulator 2ill not be able to
%roduce the correct re"ulated olta"e.
6A
2 Circuit dia"ram9
6i" 0.2. Circuit Dia"ram of <ower su<<#y
IC 4-/59
B@0# is an inte"rated three4terminal %ositie &i<ed linear olta"e re"ulator. -t su%%orts an
in%ut olta"e o& 10 olts to 3# olts and out%ut olta"e o& # olts. -t has a current ratin"
o& 1 am% althou"h lo2er current models are aailable. -ts out%ut olta"e is &i<ed at #.0?.
)he B@0# also has a built4in current limiter as a sa&ety &eature. B@0# is manu&actured by
many com%anies8 includin" +ational Semiconductors and =airchild Semiconductors.
)he B@0# 2ill automatically reduce out%ut current i& it "ets too hot.)he last t2o di"its
re%resent the olta"eO &or instance8 the B@12 is a 124olt re"ulator. )he B@<< series o&
re"ulators is desi"ned to 2or! in com%lement 2ith the BA<< series o& ne"atie olta"e
re"ulators in systems that %roide both %ositie and ne"atie re"ulated olta"es8 since the
B@<< series canTt re"ulate ne"atie olta"es in such a system.
)he B@0# R B@ is one o& the most common and 2ell4!no2n o& the B@<< series re"ulators8
as itTs small com%onent count and medium4%o2er re"ulated #? ma!e it use&ul &or
%o2erin" ))0 deices.
B0
Tab#e 0.+. S<ecifications of IC4-/5
B1
SPECI6ICATI'&S IC 4-/5
?
out
#?
?
ein
4 ?
out
Di&&erence #? 4 20?
/%eration Ambient )em% 0 4 12#U.
/ut%ut -
ma<
1A
.3AP)(* #
SP(.-=-(D )(.3+/0/,5
B2
TRIAC
)he )*-A. is a three terminal semiconductor deice &or controllin" current. -t "ains its
name &rom the term TRIode &or Alternatin" Current.
-t is e&&ectiely a deelo%ment o& the S.* or thyristor8 but unli!e the thyristor 2hich is
only able to conduct in one direction8 the )*-A. is a bidirectional deice.
TRIAC / thyristor comparison
)he )*-A. is an ideal deice to use &or A. s2itchin" a%%lications because it can control
the current &lo2 oer both hales o& an alternatin" cycle. A thyristor is only able to
control them oer one hal& o& a cycle. Durin" the remainin" hal& no conduction occurs
and accordin"ly only hal& the 2ae&orm can be utilised.
Ty%i&al 6 i!"ali$"! TRIAC ? t-yri$t#r $(it&-i8 (a+"'#r*$
)he &act that the )*-A. can be used to control current s2itchin" on both hales o& an
alternatin" 2ae&orm allo2s much better %o2er utilisation. 3o2eer the )*-A. is not
al2ays as conenient &or some hi"h %o2er a%%lications 2here its s2itchin" is more
di&&icult.
B3
TRIAC symbol
)he circuit symbol reco"nises the 2ay in 2hich the )*-A. o%erates. Seen &rom the
outside it may be ie2ed as t2o bac! to bac! thyristors and this is 2hat the circuit
symbol indicates.
TRIAC $y*4#l '#r &ir&)it !ia8ra*$
/n the )*-A. symbol there are three terminals. )hese are the ,ate and t2o other
terminals are o&ten re&erred to as an VAnodeV or VMain )erminalV. As the )*-A. has t2o
o& these they are labelled either Anode 1 and Anode 2 or Main )erminal8 M)1 and M)2.
TRIAC basics
)he )*-A. is a com%onent that is e&&ectiely based on the thyristor. -t %roides A.
s2itchin" &or electrical systems. 0i!e the thyristor8 the )*-A.s are used in many
electrical s2itchin" a%%lications. )hey &ind %articular use &or circuits in li"ht dimmers8
etc.8 2here they enable both hales o& the A. cycle to be used. )his ma!es them more
e&&icient in terms o& the usa"e o& the %o2er aailable. ;hile it is %ossible to use t2o
thyristors bac! to bac!8 this is not al2ays cost e&&ectie &or lo2 cost and relatiely lo2
%o2er a%%lications.
-t is %ossible to ie2 the o%eration o& a )*-A. in terms o& t2o thyristors %laced bac! to
bac!.
B:
TRIAC "@)i+al"t a$ t(# t-yri$t#r$
/ne o& the dra2bac!s o& the )*-A. is that it does not s2itch symmetrically. -t 2ill o&ten
hae an o&&set8 s2itchin" at di&&erent "ate olta"es &or each hal& o& the cycle. )his creates
additional harmonics 2hich is not "ood &or (M. %er&ormance and also %roides an
imbalance in the system
-n order to im%roe the s2itchin" o& the current 2ae&orm and ensure it is more
symmetrical is to use a deice e<ternal to the )*-A. to time the tri""erin" %ulse. A
D-A. %laced in series 2ith the "ate is the normal method o& achiein" this.
DIAC a! TRIAC &#"&t"! t#8"t-"r
Advantages and disadvantages
;hen re6uirin" to s2itch both hales o& an A. 2ae&orm there are t2o o%tions that are
normally considered. /ne is to use a )*-A.8 and the other is to use t2o thyristors
connected bac! to bac! 4 one thyristor is used to s2itch one hal& o& the cycle and the
second connected in the reerse direction o%erates on the other hal& cycle.
As there are t2o o%tions the adanta"es and disadanta"es o& usin" a )*-A. must be
2ei"hed u%.
B#
A!+ata8"$ Di$a!+ata8"$
Can switch both
halves of an AC
waveform
Single component
can be used for full
AC switching
A TRlAC does not fire
symmetrically on both sides of
the waveform
Switching gives rise to high level
of harmonics due to non-
symmetrical switching
More susceptible to EMl
problems as a result of the non-
symmetrical switching
Care must be taken to ensure the
TRlAC turns off fully when used
with inductive loads
Des%ite 2hat may seem li!e a number o& disadanta"es8 it is still the best o%tion &or many
circumstances. 3o2eer 2hen usin" a )*-A.8 it is necessary to be a2are o& its
limitations so that these can be satis&actorily addressed and oercome should they a&&ect
the o%eration o& the oerall circuit in any si"ni&icant 2ay.
Applications
)*-A.s are used in a number o& a%%lications. 3o2eer they tend not to be used in hi"h
%o2er s2itchin" a%%lications 4 one o& the reasons &or this is the non4symmetrical
s2itchin" characteristics. =or hi"h %o2er a%%lications this creates a number o&
di&&iculties8 es%ecially 2ith electroma"netic inter&erence.
3o2eer )*-A.s are still used &or many electrical s2itchin" a%%lications'
Domestic light dimmers
Electric fan speed controls
Small motor controls
Control of small AC powered domestic appliances
)he )*-A. is easy to use and %roides cost adanta"es oer the use o& t2o thyristors &or
many lo2 %o2er a%%lications. ;here hi"her %o2ers are needed8 t2o thyristors %laced in
Vanti4%arallelV are almost al2ays used.
)he )*-A. is an electronic com%onent that is 2idely used in many circuit a%%lications8
ran"in" &rom li"ht dimmers throu"h to arious &orms o& A. control. -t is "enerally only
B6
used &or lo2er %o2er a%%lications8 thyristors "enerally bein" used &or the hi"h %o2er
s2itchin" circuits
)he )*-A. structure is ery di&&erent to that o& the ordinary thyristor.
3ain" the ability to s2itch si"nals on both hales o& a cycle re6uires the )*-A.
structure to be considerably more com%licated than other similar deices.
+eertheless the )*-A. &abrication is 2ell established and )*-A.s are 2idely and
chea%ly aailable.
TRIAC structure
)he structure o& a )*-A. may be considered to be a D-A. 2ith an additional "ate
contact %roided to enable control o& the deice.
0i!e other %o2er deices8 the )*-A. is normally made o& silicon. $sin" a silicon
&abrication %rocess &urther enables the deices to be %roduced ery chea%ly. )he mar!et
2ould not tolerate the deices i& they 2ere made usin" more e<%ensie technolo"ies.
As can be seen8 the )*-A. structure consists o& a number o& di&&erent areas 4 ty%ically
&our n4ty%e areas as sho2n and t2o %4ty%e areas.
T-" $tr)&t)r" #' a TRIAC
)he "ate contact is made to the %4base re"ion8 althou"h there is an additional n4ty%e
di&&usion layer %laced under much o& the "ate.
BB
Additionally connections &or both anodes or main terminals8 i.e. M)1 and M)2 cross %
and n re"ions as sho2n. .
)*-A. theory can be ta!en at seeral leels8 and this can be used to sho2 the )*-A.
o%eration8 and ho2 it can be used in electronics circuits.
)he )*-A. o%eration can be ie2ed on a number o& leels8 sho2in" ho2 the )*A-.
o%eration in arious circuits can be desi"ned to oercome some o& the issues.
TRIAC operation
-t can be ima"ined &rom the circuit symbol that the )*-A. consists o& t2o thyristors bac!
to bac! but 2ith a common "ate terminal8 and the cathode o& one thyristor connected to
the anode o& the other8 and ice ersa. )his con&i"uration is more correctly termed
anti%arallel
/n a basic leel8 the o%eration o& the )*-A. can be loo!ed on in the &ormat o& the
anti%arallel thyristors8 althou"h the actual o%eration at the semiconductor leel is rather
com%licated.
;hen the olta"e on the M)1 is %ositie 2ith re"ard to M)2 and a %ositie "ate olta"e
is a%%lied8 one o& the S.*s conducts. ;hen the olta"e is reersed and a ne"atie
olta"e is a%%lied to the "ate8 the other S.* conducts. )his is %roided that there is
su&&icient olta"e across the deice to enable a minimum holdin" current to &lo2.
E@)i+al"t &ir&)it #' a TRIAC
-n terms o& the structure o& the deice8 and its more detailed o%eration8 the main terminals
M)1 and M)2 are both connected to % and n re"ions 2ithin the deice. )he current %ath
de%ends u%on the %olarity o& the olta"e across the main terminals.
As there is considerable sco%e &or con&usion8 the deice %olarity is normally described
2ith re&erence to M)1.
B@
-n terms o& its o%eration8 the /+ characteristics &or a )*-A. in any direction are similar
to that o& a thyristor. 3o2eer as a result o& the %hysical structure o& the )*-A.8 the
latchin" current8 holdin" current8 and "ate tri""er current ary accordin" to the di&&erent
hales o& the cycle and 2hich VthyristorV 2ithin the )*-A. is bein" used.
TRIAC switching issues
)*-A.s do not &ire symmetrically as a result o& sli"ht di&&erences bet2een the t2o hales
o& the deice. )his results in harmonics bein" "enerated and the less symmetrical the
)*-A. &ires8 the "reater the leel o& harmonics %roduced. -t is "enerally undesirable to
hae hi"h leels o& harmonics in a %o2er system and as a result )*-A.s are not &aoured
&or hi"h %o2er systems. -nstead t2o thyristors may be used as it is easier to control their
&irin".
DIAC a! TRIAC &#"&t"! t#8"t-"r
)o hel% in oercomin" this %roblem8 a deice !no2n as a D-A. (D-ode A. s2itch) is
o&ten %laced in series 2ith the "ate. )his deice hel%s ma!e the s2itchin" more een &or
both hales o& the cycle. )his results &rom the &act that the D-A. s2itchin" characteristic
is &ar more een than that o& the )*-A.. Since the D-A. %reents any "ate current
&lo2in" until the tri""er olta"e has reached a certain olta"e in either direction8 this
ma!es the &irin" %oint o& the )*-A. more een in both directions.
Current Transformer Basics
)he Current Transformer ( C.T. )8 is a ty%e o& Vinstrument trans&ormerV that is
desi"ned to %roduce an alternatin" current in its secondary 2indin" 2hich is %ro%ortional
to the current bein" measured in its %rimary. Current transformers reduce hi"h olta"e
currents to a much lo2er alue and %roide a conenient 2ay o& sa&ely monitorin" the
actual electrical current &lo2in" in an A. transmission line usin" a standard ammeter.
)he %rinci%al o& o%eration o& a current trans&ormer is no di&&erent &rom that o& an ordinary
trans&ormer.
BA
Typical Current Transformer
$nli!e the olta"e or %o2er trans&ormer loo!ed at %reiously8 the current trans&ormer
consists o& only one or ery &e2 turns as its %rimary 2indin". )his %rimary 2indin" can
be o& either a sin"le &lat turn8 a coil o& heay duty 2ire 2ra%%ed around the core or just a
conductor or bus bar %laced throu"h a central hole as sho2n.
Due to this ty%e o& arran"ement8 the current trans&ormer is o&ten re&erred too as a Vseries
trans&ormerV as the %rimary 2indin"8 2hich neer has more than a ery &e2 turns8 is in
series 2ith the current carryin" conductor.
)he secondary 2indin" may hae a lar"e number o& coil turns 2ound on a laminated core
o& lo24loss ma"netic material 2hich has a lar"e cross4sectional area so that the ma"netic
&lu< density is lo2 usin" much smaller cross4sectional area 2ire8 de%endin" u%on ho2
much the current must be ste%%ed do2n. )his secondary 2indin" is usually rated at a
standard 1 Am%ere or # Am%eres.
)here are three basic ty%es o& current trans&ormers' V2oundV8 VtoroidalV and VbarV.
Wound current transformers The transformers primary winding is
physically connected in series with the conductor that carries the
measured current flowing in the circuit. The magnitude of the secondary
current is dependent on the turns ratio of the transformer.
Toroidal current transformers These do not contain a primary winding.
lnstead, the line that carries the current flowing in the network is threaded
through a window or hole in the toroidal transformer. Some current
transformers have a "split core" which allows it to be opened, installed,
and closed, without disconnecting the circuit to which they are attached.
Bar-type current transformers This type of current transformer uses the
actual cable or bus-bar of the main circuit as the primary winding, which is
equivalent to a single turn. They are fully insulated from the high operating
voltage of the system and are usually bolted to the current carrying device.
@0
Current transformers can reduce or Vste%4do2nV current leels &rom thousands o&
am%eres do2n to a standard out%ut o& a !no2n ratio to either # Am%s or 1 Am% &or
normal o%eration. )hus8 small and accurate instruments and control deices can be used
2ith .)Ts because they are insulated a2ay &rom any hi"h4olta"e %o2er lines. )here are
a ariety o& meterin" a%%lications and uses &or current trans&ormers such as 2ith
2attmeterTs8 %o2er &actor meters8 2att4hour meters8 %rotectie relays8 or as tri% coils in
ma"netic circuit brea!ers8 or M.7Ts.
Current Transformer
,enerally current trans&ormers and ammeters are used to"ether as a matched %air in
2hich the desi"n o& the current trans&ormer is such as to %roide a ma<imum secondary
current corres%ondin" to a &ull4scale de&lection on the ammeter. -n most current
trans&ormers an a%%ro<imate inerse turns ratio e<ists bet2een the t2o currents in the
%rimary and secondary 2indin"s. )his is 2hy calibration o& the .) is "enerally &or a
s%eci&ic ty%e o& ammeter.
=or most current trans&ormers the %rimary and secondary currents are e<%ressed as a ratio
such as 100F#. )his means that 2hen 100 Am%s is &lo2in" in the %rimary 2indin" it 2ill
result in # Am%s &lo2in" in the secondary 2indin". 7y increasin" the number o&
secondary 2indin"s8 +28 the secondary current can be made much smaller than the
current in the %rimary circuit bein" measured. -n other 2ords8 as +2 increases8 -2 "oes
do2n by a %ro%ortional amount.
;e !no2 &rom our tutorial on double 2ound trans&ormers that its turns ratio is e6ual to'
@1
&rom 2hich 2e "et'
As the %rimary usually consists o& one or t2o turns 2hilst the secondary can hae seeral
hundred turns8 the ratio bet2een the %rimary and secondary can be 6uite lar"e. =or
e<am%le8 assume that the current ratin" o& the %rimary 2indin" is 100A. )he secondary
2indin" has the standard ratin" o& #A. )hen the ratio bet2een the %rimary and the
secondary currents is 100A4to4#A8 or 20'1. -n other 2ords8 the %rimary current is 20
times "reater than the secondary current.
-t should be noted ho2eer8 that a current trans&ormer rated as 100F# is not the same as
one rated as 20F1 or subdiisions o& 100F#. )his is because the ratio o& 100F# e<%resses
the Vin%utFout%ut current ratin"V and not the actual ratio o& the %rimary to the secondary
currents. Also note that the number o& turns and the current in the %rimary and secondary
2indin"s are related by an inerse %ro%ortion.
7ut relatiely lar"e chan"es in a current trans&ormers turns ratio can be achieed by
modi&yin" the %rimary turns throu"h the .)Ts 2indo2 2here one %rimary turn is e6ual to
one %ass and more than one %ass throu"h the 2indo2 results in the electrical ratio ben"
modi&ied.
So &or e<am%le8 a current trans&ormer 2ith a relationshi% o& say8 300F#A can be conerted
to another o& 1#0F#A or een 100F#A by %assin" the main %rimary conductor throu"h its
interior 2indo2 t2o or three times as sho2n. )his allo2s a hi"her alue current
trans&ormer to %roide the ma<imum out%ut current &or the ammeter 2hen used on
smaller %rimary current lines.
Current Transformer Primary Turns Ratio
Eample !o"
A bar4ty%e current trans&ormer 2hich has 1 turn on its %rimary and 160 turns on its
secondary is to be used 2ith a standard ran"e o& ammeters that hae an internal resistance
@2
o& 0.2WTs. )he ammeter is re6uired to "ie a &ull scale de&lection 2hen the %rimary
current is @00 Am%s. .alculate the ma<imum secondary current and secondary olta"e
across the ammeter.
Secondary .urrent'
?olta"e across Ammeter'
;e can see aboe that since the secondary o& the current trans&ormer is connected across
the ammeter8 2hich has a ery small resistance8 the olta"e dro% across the secondary
2indin" is only 1.0 olts at &ull %rimary current. -& the ammeter is remoed8 the
secondary 2indin" becomes o%en4circuited and the trans&ormer acts as a ste%4u%
trans&ormer resultin" in a ery hi"h olta"e e6ual to the ratio o&' ?%(+sF+%) bein"
deelo%ed across the secondary 2indin".
So &or e<am%le8 assume our current trans&ormer &rom aboe is connected to a :@0 olt
three4%hase %o2er line. )here&ore'
)his is 2hy a current trans&ormer should neer be o%en4circuited or o%erated 2ith no4
load attached 2hen the main %rimary current is &lo2in". -& the ammeter is to be remoed8
a short4circuit should be %laced across the secondary terminals &irst. )his is because 2hen
the secondary is o%en4circuited the iron core o& the trans&ormer o%erates at a hi"h de"ree
o& saturation8 2hich %roduces an abnormally lar"e secondary olta"e8 and in our sim%le
e<am%le aboe8 this 2as calculated at B6.@!?X. )his hi"h secondary olta"e could
dama"e the insulation or cause electric shoc! i& the .)Ts terminals are accidentally
touched.
@3
#andheld Current Transformers
)here are many s%eciali9ed ty%es o& current trans&ormers no2 aailable. A %o%ular and
%ortable ty%e 2hich can be used to measure circuit loadin" are called Vclam% metersV as
sho2n. .lam% meters o%en and close around a current carryin" conductor and measure its
current by determinin" the ma"netic &ield around it8 %roidin" a 6uic! measurement
readin" usually on a di"ital dis%lay 2ithout disconnectin" or o%enin" the circuit.
As 2ell as the handheld clam% ty%e .)8 s%lit core current trans&ormers are aailable
2hich has one end remoable so that the load conductor or bus bar does not hae to be
disconnected to install it. )hese are aailable &or measurin" currents &rom 100 u% to #000
am%s8 2ith s6uare 2indo2 si9es &rom 1V to oer 12V (2#4to4300mm).
)hen to summarise8 the Current Transformer@ >CT? is a ty%e o& instrument trans&ormer
used to conert a %rimary current into a secondary current throu"h a ma"netic medium.
-ts secondary 2indin" then %roides a much reduced current 2hich can be used &or
detectin" oercurrent8 undercurrent8 %ea! current8 or aera"e current conditions.
A current trans&ormers %rimary coil is al2ays connected in series 2ith the main
conductor "iin" rise to it also bein" re&erred to as a series trans&ormer. )he nominal
secondary current is rated at 1A or #A &or ease o& measurement. .onstruction can be one
sin"le %rimary turn as in )oroidal8 Donut8 or 7ar ty%es8 or a &e2 2ound %rimary turns8
usually &or lo2 current ratios.
.urrent trans&ormers are intended to be used as %ro%ortional current deices. )here&ore a
current trans&ormers secondary 2indin" should neer be o%erated into an o%en circuit8
just as a olta"e trans&ormer should neer be o%erated into a short circuit. ?ery hi"h
olta"es 2ill result &rom o%en circuitin" the secondary circuit o& an ener"i9ed .) so their
terminals must be short4circuited i& the ammeter is to be remoed or 2hen a .) is not in
use be&ore %o2erin" u% the system.
@:
CD $'D!E
To display interactive messages we are using LCD Module. We examine
an intelligent LCD display of two lines,l6 characters per line that is interfaced to
the controllers. The protocol (handshaking) for the display is as shown. Whereas
D0 to D7th bit is the Data lines, RS, RW and EN pins are the control pins and
remaining pins are +5V, -5V and GND to provide supply. Where RS is the
Register Select, RW is the Read Write and EN is the Enable pin.
The display contains two internal byte-wide registers, one for commands
(RS=0) and the second for characters to be displayed (RS=l). lt also contains a
user-programmed RAM area (the character RAM) that can be programmed to
generate any desired character that can be formed using a dot matrix. To
distinguish between these two data areas, the hex command byte 80 will be used
to signify that the display RAM address 00h will be chosen.Portl is used to
furnish the command or data type, and ports 3.2 to3.4 furnish register select and
read/write levels.
The display takes varying amounts of time to accomplish the functions as listed.
LCD bit 7 is monitored for logic high (busy) to ensure the display is overwritten.
Liquid Crystal Display also called as LCD is very helpful in providing user
interface as well as for debugging purpose. The most common type of LCD
controller is HlTACHl 44780 which provides a simple interface between the
controller & an LCD. These LCD's are very simple to interface with the controller
as well as are cost effective.
@#
2xl6 Line Alphanumeric LCD Display
The most commonly used ALPHANUMERIC displays are 1x16 (Single Line & l6
characters), 2x16 (Double Line & l6 character per line) & 4x20 (four lines &
Twenty characters per line).
The LCD requires 3 control lines (RS, R/W & EN) & 8 (or 4) data lines. The
number on data lines depends on the mode of operation. lf operated in 8-bit
mode then 8 data lines + 3 control lines i.e. total ll lines are required. And if
operated in 4-bit mode then 4 data lines + 3 control lines i.e. 7 lines are required.
How do we decide which mode to use? lt's simple if you have sufficient data lines
you can go for 8 bit mode & if there is a time constrain i.e. display should be
faster then we have to use 8-bit mode because basically 4-bit mode takes twice as
more time as compared to 8-bit mode.
Pin Symbol Function
1 Vss Ground
2 Vdd Supply Voltage
3 Vo Contrast Setting
4 RS Register Select
5 R/ Read/rite Select
! "n C#ip "nable Signal
$%14 &'(%&'$ &ata )ines
15 */Vee
Gnd +or t#e
bac,lig#t
1! - Vcc +or bac,lig#t
When R is low (0), the data is to be treated as a command. When RS is high
(l), the data being sent is considered as text data which should be displayed on
the screen.
@6
When R!" is low (0), the information on the data bus is being written to the LCD.
When RW is high (l), the program is effectively reading from the LCD. Most of
the times there is no need to read from the LCD so this line can directly be
connected to Gnd thus saving one controller line.
The ENA#LE pin is used to latch the data present on the data pins. A HlGH -
LOW signal is required to latch the data. The LCD interprets and executes our
command at the instant the EN line is brought low. lf you never bring EN low,
your instruction will never be executed.
COMMANDS USED IN LCD
@B
@@
CHAPTER . 1
S'6T(ARE DE7E'P$E&T
S'6T(ARE
@A
E7ision2
>?ision3 is an -D( (-nte"rated Deelo%ment (nironment) that hel%s you 2rite8 com%ile8
and debu" embedded %ro"rams. -t enca%sulates the &ollo2in" com%onents'
A %roject mana"er.
A ma!e &acility.
)ool con&i"uration.
(ditor.
A %o2er&ul debu""er.
)o hel% you "et started8 seeral e<am%le %ro"rams (located in the FC5+FEDam<#es8
FC05+FEDam<#es8 FC+11FEDam<#es8 and FAR$F...FEDam<#es) are %roided.
HE' is a sim%le %ro"ram that %rints the strin" V3ello ;orldV usin" the Serial
-nter&ace.
Bui#din" an A<<#ication in E7ision0
)o build (com%ile8 assemble8 and lin!) an a%%lication in >?ision28 you must'
1. Select Project 4 (&or e<am%le8 +11FE*A$PESFHE'FHE'.!70).
2. Select Project 4 *ebuild all tar"et &iles or 7uild tar"et.
>?ision2 com%iles8 assembles8 and lin!s the &iles in your %roject.
Creatin" Your 'wn A<<#ication in E7ision0
To create a new <ro=ect in E7ision0@ you must'
1. Select Project 4 +e2 Project.
2. Select a directory and enter the name o& the %roject &ile.
3. Select Project 4 Select Deice and select an @0#18 2#18 or .16<FS)10 deice &rom
the Deice DatabaseY.
:. .reate source &iles to add to the %roject.
#. Select Project 4 )ar"ets8 ,rou%s8 =iles8 AddF=iles8 select Source ,rou%18 and add
the source &iles to the %roject.
A0
6. Select Project 4 /%tions and set the tool o%tions. +ote 2hen you select the tar"et
deice &rom the Deice DatabaseY all s%ecial o%tions are set automatically. 5ou
ty%ically only need to con&i"ure the memory ma% o& your tar"et hard2are. De&ault
memory model settin"s are o%timal &or most a%%lications.
B. Select Project 4 *ebuild all tar"et &iles or 7uild tar"et.
Debu""in" an A<<#ication in E7ision0
)o debu" an a%%lication created usin" >?ision28 you must'
1. Select Debu" 4 StartFSto% Debu" Session.
2. $se the Ste% toolbar buttons to sin"le4ste% throu"h your %ro"ram. 5ou may enter
)@ main in the /ut%ut ;indo2 to e<ecute to the main . &unction.
3. /%en the Serial ;indo2 usin" the Seria# G+ button on the toolbar.
Debu" your %ro"ram usin" standard o%tions li!e Ste%8 ,o8 7rea!8 and so on.
Startin" E7ision0 and creatin" a Pro=ect
>?ision2 is a standard ;indo2s a%%lication and started by clic!in" on the %ro"ram icon.
)o create a ne2 %roject &ile select &rom the >?ision2 menu
Pro=ect I +e2 ProjectZ. )his o%ens a standard ;indo2s dialo" that as!s you &or the
ne2 %roject &ile name.
;e su""est that you use a se%arate &older &or each %roject. 5ou can sim%ly use the icon
.reate +e2 =older in this dialo" to "et a ne2 em%ty &older. )hen select this &older and
enter the &ile name &or the ne2 %roject8 i.e. Project1.
>?ision2 creates a ne2 %roject &ile 2ith the name P*/1(.)1.$?2 2hich contains a
de&ault tar"et and &ile "rou% name. 5ou can see these names in the Project
(indow B 6i#es.
+o2 use &rom the menu Project I Select Deice &or )ar"et and select a .P$ &or your
%roject. )he Select Deice dialo" bo< sho2s the >?ision2 deice database. 1ust select the
microcontroller you use. ;e are usin" &or our e<am%les the Phili%s @0.#1*DN .P$.
A1
)his selection sets necessary tool o%tions &or the @0.#1*DN deice and sim%li&ies in this
2ay the tool .on&i"uration.
Bui#din" Pro=ects and Creatin" a HE* 6i#es
)y%ical8 the tool settin"s under /%tions I )ar"et are all you need to start a ne2
a%%lication. 5ou may translate all source &iles and line the a%%lication 2ith a clic! on the
7uild )ar"et toolbar icon. ;hen you build an a%%lication 2ith synta< errors8 >?ision2
2ill dis%lay errors and 2arnin" messa"es in the /ut%ut
;indo2 I 7uild %a"e. A double clic! on a messa"e line o%ens the source &ile on the
correct location in a >?ision2 editor 2indo2.
/nce you hae success&ully "enerated your a%%lication you can start debu""in".
A&ter you hae tested your a%%lication8 it is re6uired to create an -ntel 3(K &ile to
do2nload the so&t2are into an (P*/M %ro"rammer or simulator. >?ision2 creates 3(K
&iles 2ith each build %rocess 2hen .reate 3(K &iles under /%tions &or )ar"et I /ut%ut is
enabled. 5ou may start your P*/M %ro"rammin" utility a&ter the ma!e %rocess 2hen
you s%eci&y the %ro"ram under the o%tion *un $ser Pro"ram Q1.
CP! Simu#ation
>?ision2 simulates u% to 16 Mbytes o& memory &rom 2hich areas can be ma%%ed &or
read8 2rite8 or code e<ecution access. )he >?ision2 simulator tra%s and re%orts ille"al
memory accesses bein" done.
-n addition to memory ma%%in"8 the simulator also %roides su%%ort &or the inte"rated
%eri%herals o& the arious @0#1 deriaties. )he on4chi% %eri%herals o& the .P$ you hae
selected are con&i"ured &rom the Deice
A2
Database se#ection
5ou hae made 2hen you create your %roject tar"et. *e&er to %a"e #@ &or more
-n&ormation about selectin" a deice. 5ou may select and dis%lay the on4chi% %eri%heral
com%onents usin" the Debu" menu. 5ou can also chan"e the as%ects o& each %eri%heral
usin" the controls in the dialo" bo<es.
Start Debu""in"
5ou start the debu" mode o& >?ision2 2ith the Debu" I StartFSto% Debu" Session
command. De%endin" on the /%tions &or )ar"et I Debu" .on&i"uration8 >?ision2 2ill
load the a%%lication %ro"ram and run the startu% code >?ision2 saes the editor screen
layout and restores the screen layout o& the last debu" session. -& the %ro"ram e<ecution
sto%s8 >?ision2 o%ens an editor 2indo2 2ith the source te<t or sho2s .P$ instructions
in the disassembly 2indo2. )he ne<t e<ecutable statement is mar!ed 2ith a yello2
arro2. Durin" debu""in"8 most editor &eatures are still aailable.
=or e<am%le8 you can use the &ind command or correct %ro"ram errors. Pro"ram
source te<t o& your a%%lication is sho2n in the same 2indo2s. )he >?ision2 debu" mode
di&&ers &rom the edit mode in the &ollo2in" as%ects'
[ )he CDebu" Menu and Debu" .ommandsD described on %a"e 2@ are Aailable. )he
additional debu" 2indo2s are discussed in the &ollo2in".
[ the %roject structure or tool %arameters cannot be modi&ied. All build .ommands are
disabled.
Disassemb#y (indow
)he Disassembly 2indo2 sho2s your tar"et %ro"ram as mi<ed source and
assembly %ro"ram or just assembly code. A trace history o& %reiously e<ecuted
instructions may be dis%layed 2ith Debu" I ?ie2 )race *ecords. )o enable the trace
history8 set Debu" I (nableFDisable )race *ecordin".
A3
-& you select the Disassembly ;indo2 as the actie 2indo2 all %ro"ram ste%
commands 2or! on .P$ instruction leel rather than %ro"ram source lines. 5ou can
select a te<t line and set or modi&y code brea!%oints usin" toolbar buttons or the conte<t
menu commands.
5ou may use the dialo" Debu" I -nline AssemblyZ to modi&y the .P$
instructions. )hat allo2s you to correct mista!es or to ma!e tem%orary chan"es to the
tar"et %ro"ram you are debu""in".
S'!RCE C'DE
+. .lic! on the Jeil u?ision -con on Des!to%
0. )he &ollo2in" &i" 2ill a%%ear.
=i" 32' %roject
2. .lic! on the Project menu &rom the title bar
3. )hen .lic! on +e2 Project
A:
=i" 33' ne2 %roject
5. Sae the Project by ty%in" suitable %roject name 2ith no e<tension in u r
o2n &older sited in either .'\ or D'\
A#

1. )hen .lic! on sa;e button aboe.
4. Select the com%onent &or u r %roject. i.e. AtmelZZ
-. .lic! on the N Symbol beside o& Atmel
=i" 3: ' select tar"et deice
8. Select A)@A.#1 as sho2n belo2
A6
=i" 3#' select deice &oer tar"et
+/. )hen .lic! on C/JD
++. )he =ollo2in" &i" 2ill a%%ear
=i" 36' .o%y @0#1 startu% code
+0. )hen .lic! either 5(S or +/ZZZmostly C+/D
+2. +o2 your %roject is ready to $S(
AB
+3. +o2 double clic! on the )ar"et18 you 2ould "et another o%tion CSource
"rou% 1D as sho2n in ne<t %a"e.
=i" 3B' Source "rou% 1
+5. .lic! on the &ile o%tion &rom menu bar and select Cne2D
=i" 3@ ne2 &ile
A@
+1. )he ne<t screen 2ill be as sho2n in ne<t %a"e8 and just ma<imi9e it by double
clic!in" on its blue boarder.
=i" 3A' /%ened ne2 &ile
+4. +o2 start 2ritin" %ro"ram in either in C.D or CASMD
+-. =or a %ro"ram 2ritten in Assembly8 then sae it 2ith e<tension C. asmD and &or
C.D based %ro"ram sae it 2ith e<tension C ..D
AA
=i" :0' =ile Sae
+8. +o2 ri"ht clic! on Source "rou% 1 and clic! on CAdd fi#es to )rou<
SourceD
=i" :1' Add &iles to the source "rou%
0/. +o2 you 2ill "et another 2indo28 on 2hich by de&ault C.D &iles 2ill
a%%ear.
100
=i" :2' Addin" &iles to the source "rou%
0+. +o2 select as %er your &ile e<tension "ien 2hile sain" the &ile
00. .lic! only one time on o%tion CADDD
02. +o2 Press &unction !ey =B to com%ile. Any error 2ill a%%ear i& so ha%%en.
=i" :3 .om%ilation
03. -& the &ile contains no error8 then %ress .ontrolN=# simultaneously.
05. )he ne2 2indo2 is as &ollo2s
=i" ::' buildin"
101
01. )hen .lic! C/JD
04. +o2 .lic! on the Peri%herals &rom menu bar8 and chec! your re6uired
%ort as sho2n in &i" belo2
=i" :# ' Selectin" the Ports to be isuali9ed
0-. Dra" the %ort a side and clic! in the %ro"ram &ile.
=i" :6' start debu""in"
08. +o2 !ee% Pressin" &unction !ey C=11D slo2ly and obsere.
102
2/. 5ou are runnin" your %ro"ram success&ully.
CHAPTER 4
CONCLUSION
103
The project "PO,ER THEFT IDENTIFICATION SYSTEM IN
DISTRIBUTION LINES USIN5 DIFFERENTIAL PO,ER
MEASUREMENT A has been successfully designed and tested. lntegrating
features of all the hardware components used have developed it. Presence of
every module has been reasoned out and placed carefully thus contributing to
the best working of the unit.
Secondly, using highly advanced lC's and with the help of growing technology
the project has been successfully implemented
REFERENCES
805l-MlCROCONTROLLER AND EMBEDDED SYSTEMS.
-Mohd. Mazidi.
)he @0#1 Micro controller Architecture8 Pro"rammin" R A%%lications
.%enneth H.Aya#a
=undamentals /& Micro %rocessors and Micro com%uters
.B.Ram
Micro %rocessor Architecture8 Pro"rammin" R A%%lications
.Ramesh S. )aonCar
(lectronic .om%onents
4D.7. Prasad
10:
10#