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University Of Santo Tomas Espaa, Manila Faculty of Engineering Electronics Engineering Department

CPU NAME (optional)


Central Processing Unit (CPU) Design

Submitted by:

Surname, First Name MI. Surname, First Name MI. Surname, First Name MI. Surname, First Name MI. Surname, First Name MI. Surname, First Name MI. (Centered and alphabetically arranged) 4 ECE _

*Insert name of your Professor here* Professor

February 22, 2014

(Centered, font size: 14) TABLE OF CONTENTS


I. Introduction A. Background of the Study B. Design Overview C. Scope and Delimitation

(font size: 11 for Arial, 12 for TNR)


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II.

Architecture A. Block Diagram B. Bus Unit C. I/O Ports D. Program Counter E. General Purpose Registers K. L. M. N. O. Accumulator and TMP Register Status/Flag Register Arithmetic and Logic Unit Instruction Register Controller/Sequencer

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*The contents of this Chapter II (Architecture) will vary depending on your design. Just make sure you include the descriptions of every register/unit/part of your design.* III. Controller/Sequencer A. State Counter B. State Decoder C. Control Logic D. Control Signals Instruction Set Architecture A. Instruction Set Format / Opcode Mapping B. Instruction Summary C. Instruction Description Simulation Results A. Sample Code B. Execution Trace (Tabulated)
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IV.

V.

VI.

Design Calculations A. Noise Margin B. Power Dissipation C. Fan Out D. Propagation Delay E. Clock Frequency Recommendations

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VII.

References List of Instructions Appendix A: Hardware Summary Appendix B: Specification Sheets

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I.

INTRODUCTION
the body

CHAPTER HEADER: Centered, Bold, font size: 14)

A. Background of the Study Sub-header: Left-justified, bold, one font size larger than
CPU designing involves the first task of knowing its usage. An ideal CPU for a particular task should be powerful enough to handle a job. For example a simple 4-bit processor is sufficient enough to control room-air-conditioning unit and on and on a different side, a complicated quad-core microprocessor is ideal for a personal computer. The interchange of their usage has significant disadvantages for both applications. And according to Carpinelli The key is to match the capabilities of the CPU to the tasks it will perform. According to Malvino, the CPU or central processing unit are circuits which are designed to act as the brain of a computer. The CPU could perform basic arithmetic operations such as addition and subtraction, logic operations such as AND and OR and control operations. Thus, it could process data. By definition, a microprocessor is a CPU which is constructed on a single silicon chip. A CPU is an electronic circuit which can interpret and execute instructions and control input and output. According to Carpinelli, to design a CPU, we first develop its instruction set architecture, including its instruction set and its internal registers. We then create a finite state machine model of the micro-operations needed to fetch, decode and execute every instruction in its instruction set. Then we develop an RTL specification for this state machine. This paper aims to present a CPU design in partial fulfillment of the requirements of the course COMP421. BODY: observe proper indention, justified, font size:11 if Arial, 12 if TNR, 1.5 spacing, no space between paragraphs

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B. Design Overview
The SAP143 microprocessor is an 8-bit microprocessor. It makes use of a 16-bit word bus which serves as a 16-bit address bus and 8-bit data bus. It also has an addressable memory of 64KB and 82 instructions. The architecture of the SAP143 microprocessor is based on a combined SAP 2 / Carpinelli design. It is composed of two I/O ports, memory address register, memory data register, a program counter, a stack pointer, status register, an arithmetic and logic unit, its accumulator, index register, two general purpose registers( B and C), HL register, instruction register and a control unit. The ALU is capable of performing arithmetic and logic operations. It can perform the following arithmetic operations, ., and the following logic operations OR, AND, XOR and NOT.

C. Scope and Delimitation

SAP143 is an 8-bit microprocessor which uses a 16-bit word bus, 16-bit address bus and 8-bit data bus. It has two bidirectional input/ output ports and it has dual data format which can perform arithmetic and logic operations for both BCD and signed integers. The Arithmetic Logic Unit can perform . as arithmetic operations and logical operations such as AND, OR, XOR and NOT. The register set consists of the accumulator, status/ flag register (sign, zero, carry and overflow flags. The control unit design consists of the . Low-endian scheme is used in this microprocessor. This design uses only TTL logic family. No RAM block is designed for this microprocessor. In addition, no power supply, clock and clear circuit designs are presented here.

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II.

ARCHITECTURE

A. Block Diagram
A generalized block diagram of KISAP microprocessor is shown in Figure 1.

Figure 1. SAP143 Microprocessor Block Diagram

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B. Bus Unit
SAP143 has a 16-bit address bus and an 8-bit data bus. Access to the bus is controlled via three-state buffers; those not connected to the bus are two-state. Additional bus is included whose function is to

C. I/O Unit Ports 1 and 3 are implemented using 8-bit controlled buffer registers. Ports 2 and 4 use controlled shift-right registers. A control logic controls loading/sending data through ports 2 and 4 via a high ACK signal.

D. Program Counter
The program counter is a 16-bit controlled ripple counter. At the start of a program run, a CLR signal resets the count value to 0000h. A high CP signal increments the counter up to FFFFh.

N. Instruction Register
The SAP143 uses an 8-bit operation code (op-code). After fetching the instruction from the RAM, the op-code is loaded into the instruction register (IR). The IR is an 8-bit controlled buffer register, the inputs of which are latched to the lower byte of the word bus. The output of the IR drives the controller-sequencer until a new instruction is fetched and loaded.

O. Controller / Sequencer
5SAP2s controller/sequencer (CON) is asynchronous (unclocked). The CON is combinational circuit, driven by a state controller, provided by a 18-state ring counter. The CON provides a variable machine cycle, which resets the ring counter after every instruction. More detailed descriptions on the controller/sequencer can be read in the next chapter.

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III.

CONTROLLER / SEQUENCER

The Control Unit of SAP143 is designed using hardwired control. Under this design, the states (Give a short background about the control unit design)

A. State Counter
SAP143 includes 187 instructions, which consumes 241 T-states. Thus, the state counter.

B. State Decoder
The output of the T-State counter is connected to the T-State decoder. Since there are 241 states, the state decoder uses two 4x16 decoders which are connected in a coincident decoding scheme to form outputs, which creates the 8x256 decoder leaving 15 decoder outputs unused. The states are activated depending on the counters input.

C. Control Logic
The outputs of the decoder will serve as the inputs to a control logic which is responsible in sending control signals to registers, ALU, .

D. Control Signals Summary


Control Signals are used to direct the registers, dictate the operations and operands. Table 1 shows that summary of the control signals used in SAP143 design.

TABLE 1. Control Signal Definition CONTROL SIGNAL ACCBUS ACCDEC ACCINC ACCLD DEFINITION output accumulator to bus decrement the accumulator increment the accumulator enable loading to accumulator

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ADD ALULD AND BBUS BLD CBUS CLD HBUS HLD HXALD IRLD IXDEC MARLD MEMBUS NOT OR PCBUS PCINC SPDEC SUB XOR

add the data in the designated register to the accumulator enable loading to ALU AND the accumulator contents with the designated register output register B to bus enable loading to register B output register C to bus enable loading to register C output H to bus enable loading to H load H to ALU enable loading to instruction register decrement index register enable loading to memory address register output MDR to bus invert the accumulator contents OR the accumulator contents with the designated register

output program counter to bus increment program counters decrement SP subtract the data in the designated register to the accumulator XOR the accumulator contents with the designated register

(Arrange the Control Signals alphabetically)

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IV.

INSTRUCTION SET ARCHITECTURE

A. Instruction Format / Op-code Mapping

Describe here how you came up with your instruction codes/opcodes. Also, present in tabular form all the instructions together with their opcodes in binary and hex form. Ex:
SAP143 has 180 instructions which are represented by an 8-bit instruction code. The instructions are divided according to their functions, namely, memory-referenced, arithmetic, logical, . The last 2 bits, B7 and B6, of the op-code determines which functional group the instruction belongs to. Then, the next bits represent

B7

B6

B5

B4

B3

B2

B1

B0

Instruction Group/Function

Operand

Table _. Op-code Mapping for B7 and B6 B7 0 0 1 1 B6 0 1 0 1 Instruction Group Arithmetic / Logical Memory-Referenced Branching Machine Control

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For Arithmetic and Logical Operations: B5 Function B4 0 0 0 Arithmetic 1 1 0 0 1 Logical 1 1 0 1 OR XOR 0 1 0 1 SUB SBB NOT AND B3 0 1 Function ADD ADC B2 B1

B. Instruction Summary
The SAP143 have 180 instructions which can be divided functionally into the following groups: Memory-reference Arithmetic Register Jump / Branching Logical Machine Control Other Instructions

The following summary shows the instructions belonging to each group and the number of operands required for each. The source operand is src, the destination operand is dst.

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MEMORY-REFERENCE INSTRUCTIONS Instruction LDA LDB LDC LDSP LDIX LDAX LDBX LDCX STA STB STC STAX STBX STCX Opcode 70H 71H 72H 68H 69H 80H 81H 82H 90H 91H 92H A0H A1H A2H T-States 12 12 12 10 10 14 14 14 12 12 12 14 14 14 Flags Needed Affected None None None None None None None None None None None None None None None None None None None None None None None None None None None None Addressing Mode Direct Direct Direct Implied Implied Index Index Index Direct Direct Direct Index Index Index Byte 3 3 3 1 1 3 3 3 3 3 3 3 3 3

JUMP INSTRUCTIONS Instruction JP JZ JNZ JM JNM JC JNC JO JNO CALL RET Opcode C0H C1H C2H C3H C4H C5H C6H C7H C8H E0H F0H T-States 10 10 10/5 10/5 10/5 10/5 10/5 10/5 10/5 16 10 Flags Needed None Zero Zero Sign Sign Carry Carry Overflow Overflow None None Affected None None None None None None None None None None None Addressing Mode Direct Direct Direct Direct Direct Direct Direct Direct Direct Direct Implied Byte 3 3 3 3 3 3 3 3 3 3 1

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C. Instruction Description

This section describes each instruction by means of presenting its op code, addressing mode, T states, flags needed & affected and its microinstructions per T state. Table _. Description of .

MEMORY REFERENCE INSTRUCTIONS


LDA Op Code Addressing Mode T States Flags Needed Flags Affected FETCH1: FETCH2: FETCH3: LDA1: LDA2: LDA3: LDSP Op Code Addressing Mode T States Flags Needed Flags Affected FETCH1: FETCH2: FETCH3: LDSP1: LDSP2: LDSP3: LDSP4: LDSP5: LOAD ACCUMULATOR 70H DIRECT 6 NONE NONE Microinstructions per T State: MAR PC MARLD, PCBUS MDR M, PC PC + 1 MEMOT, PCINC IR MDR IRLD, MEMBUS MAR SP MARLD, SPBUS MDR M, SP SP + 1 MEMOT, SPINC ACC MDR ACCLD, MEMBUS, CLR LOAD STACK POINTER 68H IMPLIED 10 NONE NONE Microinstructions per T State: MAR PC MDR M, PC PC + 1 IR MDR MAR PC MDR M, PC PC + 1 L MDR MAR PC MDR M, PC PC + 1

MARLD, PCBUS MEMOT, PCINC IRLD, MEMBUS MARLD, PCBUS MEMOT, PCINC LLD, MEMBUS MARLD, PCBUS MEMOT, PCINC 13 | P a g e

LDSP6: H MDR LDSP7: SP HL STAX Op Code Addressing Mode T States Flags Needed Flags Affected

HLD, MEMBUS SPLD, HLBUS, CLR

STORE ACCUMULATOR WITH INDEX ADDRESS TO MEMORY A0H INDEX 14 NONE NONE Microinstructions per T State: MAR PC MARLD, PCBUS MDR M, PC PC + 1 MEMOT, PCINC IR MDR IRLD, MEMBUS MAR PC MARLD, PCBUS MDR M, PC PC + 1 MEMOT, PCINC L MDR LLD, MEMBUS MAR PC MARLD, PCBUS MDR M, PC PC + 1 MEMOT, PCINC H MDR HLD, MEMBUS L L + IX(0-7) LBUS, LXALD, ADD H H + IX(8-15) HBUS, HXALD, ADD MAR HL MARLD, HLBUS MDR ACC MEMLD, ACCBUS M MDR MEMIN, CLR

FETCH1: FETCH2: FETCH3: STAX1: STAX1: STAX2: STAX3: STAX4: STAX5: STAX6: STAX7: STAX8: STAX9: STAX10:

JUMP AND CALL INSTRUCTIONS


JP Op Code Addressing Mode T States Flags Needed Flags Affected JUMP C0H DIRECT 10 NONE NONE Microinstructions per T State: FETCH1: MAR PC MARLD, PCBUS FETCH2: MDR M, PC PC + 1 MEMOT, PCINC FETCH3: IR MDR IRLD, MEMBUS 14 | P a g e

JP1: JP2: JP3: JP4: JP5: JP6: JP7: JZ Op Code Addressing Mode T States Flags Needed Flags Affected 1 Branch FETCH1: FETCH2: FETCH3: JZY1: JZY2: JZY3: JZY4: JZY5: JZY6: JZY7: JZN1: JZN2: JZN3: JZN4:

MAR PC MDR M, PC PC + 1 L MDR MAR PC MDR M, PC PC + 1 H MDR PC HL JUMP IF ZERO C1H DIRECT 10 ZERO NONE Microinstructions per T State: MAR PC MDR M, PC PC + 1 IR < MDR MAR PC MDR M, PC PC + 1 L MDR MAR PC MDR M, PC PC + 1 H MDR PC HL MAR <-- PC MDR <-- M, PC <-- PC + 1 IR <-- MDR PC <-- PC + 1 CALL SUBROUTINE E0H DIRECT 16 NONE NONE Microinstructions per T State:

MARLD, PCBUS MEMOT, PCINC LLD, MEMBUS MARLD, PCBUS MEMOT, PCINC HLD, MEMBUS PCLD, HLBUS, CLR

MARLD, PCBUS MEMOT, PCINC IRLD, MEMBUS MARLD, PCBUS MEMOT, PCINC LLD, MEMBUS MARLD, PCBUS MEMOT, PCINC HLD, MEMBUS PCLD, HLBUS

0 Branch

MARLD, PCBUS MEMOT, PCINC IRLD, MEMBUS PCINC, PCINC, CLR

CALL Op Code Addressing Mode T States Flags Needed Flags Affected FETCH1: FETCH2:

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FETCH3:

RET Op Code Addressing Mode T States Flags Needed Flags Affected FETCH1: . FETCH2: FETCH3:

RETURN F0H IMPLIED 16 NONE NONE Microinstructions per T State:

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V.
A. Sample Code

SIMULATION RESULTS

To verify that the CPU design is working, let us consider the segment of code shown below. Table 9 shows the execution trace of these codes. Suppose 10 bytes of data are stored in memory from address 2000H to 2009H. Show a program that will copy these 10 bytes at address 5000H to 5009H. LXI H, 1FFFh MVI C, 0Ah Loop: INX H MOV B,M MOV A,H ADI 30h MOV H,A MOV M,B SUI 30h MOV H,A DCR C JNZ Loop HLT Before computer run: PSW: 0082h BC: 0102h DE: 0304h 3000: 11h 3001: 12h 3002: 13h 3003: 14h 3004: 15h 3005: 16h 3006: 17h 3007: 18h 3008: 19h 3009: 1Ah ;Initialize index register ;load decimal 10 to C register ;increment index register ;store byte to B register ;load data of H to accumulator ;add offset ;load offset value to index register ;write byte in new location ;subtract offset ;restore H ;decrement counter ;check if zero, if not jump back ;stop

HL: SP: PC: 5000: 5001: 5002: 5003: 5004: 5005: 5006: 5007: 5008: 5009:

0506h FFEEh 1000h 2Ah 2Fh 6Bh 7Ah CDh EFh 8Ah BBh DCh 00h

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B. Execution Trace
Table 9. Execution Trace of the Sample Code (see previous page) ADDRESS 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A 100B 100C 100D 100E 100F 1010 1011 1012 1013 ADDRESS 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A 100B 100C DATA F6h (LXI H) FFh 1Fh EAh (MVI C) 0Ah 32h (INX H) 8Fh (MOV B,M) 85h (MOV A,H) 60h (ADI) 30h A8h (MOV H, A) B9h (MOV M, B) 62h (SUI) 30h A8h (MOV H, A) 2Ah (DCR C) CFh (JNZ) 05h 10h FFh (HLT) DATA F6h (LXI H) FFh 1Fh EAh (MVI C) 0Ah 32h (INX H) 8Fh (MOV B,M) 85h (MOV A,H) 60h (ADI) 30h A8h (MOV H, A) B9h (MOV M, B) 62h (SUI) C=0Ah H=1Fh L=FFh C=0Ah H=20h L=00h B=11h A=20h A=50h SR=06h H=50h 5000:11h A=20h SR=02h H=20h C=09h SR=06h TRUE H=20h L=01h B=12h A=20h A=50h SR=06h H=50h 5001:12h A=20h SR=02h H=20h C=08h SR=02h TRUE H=20h L=02h B=13h A=20h A=50h SR=06h H=50h 5002:13h A=20h SR=02h H=20h C=07h SR=02h TRUE H=20h L=03h B=14h A=20h A=50h SR=06h H=50h 5003:14h A=20h SR=02h H=20h C=06h SR=06h TRUE H=20h L=04h B=15h A=20h A=50h SR=06h H=50h 5004:15h A=20h SR=02h H=20h C=05h SR=06h TRUE C=09h C=08h C=07h C=06h

C=05h

C=04h

C=03h

C=02h

C=01h

H=20h L=05h B=16h A=20h A=50h SR=06h H=50h 5005:16h A=20h

H=20h L=06h B=17h A=20h A=50h SR=06h H=50h 5006:17h A=20h

H=20h L=07h B=18h A=20h A=50h SR=06h H=50h 5007:18h A=20h

H=20h L=08h B=19h A=20h A=50h SR=06h H=50h 5008:19h A=20h

H=20h L=09h B=1Ah A=20h A=50h SR=06h H=50h 500A:1Ah A=20h 18 | P a g e

100D 100E 100F 1010 1011 1012 1013

30h A8h (MOV H, A) 2Ah (DCR C) CFh (JNZ) 05h 10h FFh (HLT)

SR=02h H=20h C=04h SR=02h TRUE

SR=02h H=20h C=03h SR=06h TRUE

SR=02h H=20h C=02h SR=02h TRUE

SR=02h H=20h C=01h SR=02h TRUE

SR=02h H=20h C=00h SR=86h FALSE

INSTRUCTION LXI H, 1FFFh 5

STATES T1 T2 T3 T4 T5

ACTIVE CONTROL SIGNALS FP, CP, CE, Li EP, LM CP, CE, LHL EP, LM CP, CE, LHH FP, CP, CE, Li EP, LM CP, CE, LC FP, CP, CE, Li MU FP, CP, CE, Li LM, EM LB, CE FP, CP, CE, Li LA, EMH FP, CP, CE, Li EP, LM CE, LT, Cp EU, LA, LF FP, CP, CE, Li LHH, EA FP, CP, CE, Li EM, LM WE, CE, EB FP, CP, CE, Li 19 | P a g e

MVI C, 0Ah

T1 T2 T3

INX H

T1 T2

MOV B,M

T1 T2 T3

MOV A,H

T1 T2

ADI 30h

T1 T2 T3 T4

MOV H,A

T1 T2

MOV M,B

T1 T2 T3

SUI 30h

T1

T2 T3 T4 MOV H,A 2 3 T1 T2 DCR C T1 T2 JNZ Loop 6/3 T3 If TRUE T1 T2 T3 T4 T5 T6 If FALSE T1 T2 T3 HLT 2 T1 T2

EP, LM CE, LT, CP EU, LA, LF, S FP, CP, CE, Li LHH, EA FP, CP, CE, Li LT, EC LC, EU, LF, S, EID FP, CP, CE, Li EP, LM' CE', LXH', CP EP, LM' CE', LPH EXL, LPL FP, CP, CE, Li CP CP FP, CP, CE, Li

**For other reference on simulation results documentation, please see slides 24 to 28 of our lecture on Microprocessor Design (Lecture 6 PPT).

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VI.

DESIGN CALCULATIONS

Data and pertinent computations with respect to the design are shown below such as power dissipation, noise margin, fan out, propagation delay and clock frequency.

A. Noise Margin
(Write a short description here) Noise margin, also called Noise Immunity, is the maximum noise voltage added or subtracted to the input of a digital circuit that does not cause an undesirable change in the circuit output. It is calculated from the level voltage level available in the output gate and the voltage level required at the input gate. Table 15 shows the logic level specifications of a TTL family to be used for the computations of noise margin. (table of logic level specification to be used) Table 15. Logic Level Specifications: VOL, VIL, VOH, VIH

The general formula for Noise Margin is: (Then, general formula) ( or ( ) )

(Then show your computations here. You can opt to use tables to clearly present the specific gates and their corresponding noise margins.) .

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B. Power Dissipation
(short description) (logic level specification) (general formula) (computations)

E. Clock Frequency Calculation


. .

1 x (J-K flip-flop) = 1 x 26 ns 3 x (4 input NOR) = 3 x 18.5 ns 1 x (3 input NOR) = 1 x 6.25 ns 2 x (4 input NAND) = 2 x 5.65 ns 2 x (2 input NAND) = 2 x 15 ns 1 x (3 input NAND) = 1 x 18.5 ns 2 x (2 input OR) = 2 x 22 ns 1 x (INVERTER) = 1 x 15 ns ------------------------------------------------------------------------------------------Total delay = 206.55 ns Clock Frequency = 1 / (206.55n x 2) = 2.421 MHz

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VII.

RECOMMENDATIONS

Since the design is an 8 data bit microprocessor, the group recommends maximizing the number of instructions possible. is It is capable of supporting up to 256 instructions so

additional sets may be introduced such as interrupt request. Another point for improvement

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REFERENCES
[1] [2] Malvino, . (Font size: 11 for Arial, 12 for TNR) .

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INDEX (3 or 4-column list of all instructions; include the page number where the description of the instruction can be found in the documentation/ Chapter IV Section C)

A Font size: 22
ADC B ADD B ADD C 37 30 31

Font size: 11

B
BCD 25

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APPENDIX A
Hardware Summary

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APPENDIX B
Specification Sheets

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