Smart Trip Logic for Smart Grids to Block Distance

Relay Maloperation - Implementation and Validation

Venkatesh C, Student Member, IEEE
Department of Electrical Engineering
Indian Institute of Technology Madras
Chennai - 600036
Email: ee10d036@ee.iitm.ac.in
K Shanti Swarup, Senior Member, IEEE
Department of Electrical Engineering
Indian Institute of Technology Madras
Chennai - 600036
Email:ksswarup@iitm.ac.in
Vishnu Prasath S
Email:vishnuprasaths@yahoo.com
AbstractZone 1 reach setting of a distance relay depend upon
many factors, such as, dc offset in current signals, loading effect,
fault resistance in the presence of in-feed from remote end and
also capacitive voltage transformer (CVT) transients. All these
factors are taken care of except for CVT transients, which is
dealt either by reducing zone 1 reach or by providing a xed time
delay in todays intelligent electronic devices (IED). This paper
proposes a new and simple logic to prevent numerical distance
relay mal-operation by zone 1 element due to CVT transients
without sacricing zone 1 reach. This is achieved by providing
adaptive time delay by actually monitoring the CVT transients
in time domain. The proposed logic is validated in real time by
incorporating the proposed logic along with positive sequence
polarized distance relay model in eld programmable gate array
(FPGA).
I. INTRODUCTION
Today, power grids are undergoing some major changes in
the quest to transform themselves into smarter power grids. In-
order to meet these needs, IEDs are equipped with different
functionalities to make trip decision in a intelligent fashion
to prevent mal-operation which may lead to cascaded tripping
and nally blackout. IED mal-operation may be due to differ-
ent reasons like hidden failures, overreaching, under-reaching,
power swings, load encroachment and due to the presence
of series capacitors. Distance relay may also mal-operate due
to fault resistance in the presence of remote end in-feed [1],
[2]. In addition to this, zone 1 element may overreach due to
CVT transients [3], [4], [5] especially during high source to
line reach impedance ratio (SIR) [6], [7]. This is due to the
presence of energy storage elements (inductor and capacitor
in active type CVT or saturable inductor and resistor in case
of passive type CVT) in ferro-resonance suppression circuit
(FSC) which fails to replicate the primary system information
in secondary instantaneously.
It is six decades before, this problem i.e. distance relay mal-
operation due to CVT transients is suspected [8]. The problem
got aggravated when electromechanical relays are replaced
with digital relays with high speed tripping features i.e. es-
pecially when half-cycle algorithms are used for fundamental
frequency voltage and current phasor estimation. Even-though
the problem seems to be very old, it is still important in todays
scenario, as it is one of the main governing factors to decide
the zone 1 reach setting apart from other overreaching factors.
Different solutions are proposed by relay manufacturers to
handle the overreaching by providing nite impulse response
lters [9] in current path to overcome overreaching due to
dc offset in current waveform, adaptive tilting angle [10] to
prevent overreaching due to fault resistance in the presence of
remote end in-feed. The emphasis will be still more, especially
when the voltage signal to IED is fed from active type CVT
which is prone to CVT transients due the presence of energy
storage elements in FSC.
The paper is organized as follows, Section II discusses the
literature review, followed by Section III with the proposed
logic. Section IV discusses the test system modeling and
simulation results. Hardware implementation and validation
results are shown in Section V and section VI with conclusion.
II. LITERATURE REVIEW
IED receives the system primary information via instrument
transformers i.e. CVT and current transformer (CT). Fault
information delivered by CVT and CT are corrupted by
unwanted information like dc offset [1]. These CVT and CT
signals cause distance elements to overreach i.e. mal-operate,
since distance relay estimates positive sequence impedance
by extracting the fundamental frequency current and voltage
phasors. Different techniques like mimic ltering [9], double
differentiator [7] are available to lter out the unwanted
low frequency information. Even-though the above mentioned
nite impulse response lters can effectively remove expo-
nentially decaying dc offset in current or voltage signals, it
fails, when unwanted information is quite close to the desired
information i.e. fundamental frequency which is the case with
CVT transients.
Relay manufacturers handle this issue by providing either
special lters or counters to overcome this overreach problem
due to CVT transient. Current solution available in different
IED to handle this issue is listed in Table. I.
As it can be seen from Table. I that the current solution
is either to pull back the reach setting or to provide a xed
time delay. Moreover the existing techniques rely on frequency
domain information to detect CVT transients. This paper
proposes a new and simple logic to handle this problem
without sacricing zone 1 reach by directly monitoring the
transients in time domain itself. The proposed smart trip (ST)
IEEE ISGT Asia 2013 1569807391
1
TABLE I: Techniques used in IEDs to handle issue due to
CVT transient
Manufacturer Technique
Relay A xed time delay if high SIR is detected
Relay B adaptive algorithm to reduce zone 1 reach
Relay C
use of double zone 1 where, inner zone 1 reach
is dynamic without delay whereas outer zone 1
has xed reach (100%) with time delay
Relay D
patented technique to block trip signal
based on frequency domain information
for a xed time delay (assuming CVT transients
dies out within this time delay) if high SIR is detected
Relay E
special lters are introduced in voltage path
if high SIR is detected in addition to adaptive counter
logic, blocks the trip signal if it detects that the CVT signal is
not t (SNF) to be used for trip decision. The added feature
is that, the blocking time is adaptive as it depends on the
extracted unwanted signal information.
III. SMART TRIP LOGIC
This section discusses the functioning of proposed smart
trip (ST) logic which is shown in Fig. 1. The proposed logic
decides whether to forward the trip command to the circuit
breaker or not. The main advantage of this proposed logic
is, the decision is based on the information available in time
domain. In order to perform this task, one cycle moving
Ph. Element
RYZ1
Y BZ1
BRZ1
G. Element
RZ1
YZ1
BZ1
Trip SC
T
Vr(t) Filter Vlth Vrf (t) Vuth
Vrf
Vy(t) Filter Vlth Vyf (t) Vuth
Vyf
Vb(t) Filter Vlth Vbf (t) Vuth
Vbf
Signal Not Fit
SNF
Smart Trip
ST
Block Trip
SIR>5
Proposed
BT
Latching Relay
Fig. 1: Proposed smart trip logic
where,
R
Z1
, Y
Z1
, B
Z1
Ground elements
RY
Z1
, Y B
Z1
, BR
Z1
Phase elements
SC Security counter
V
rf
, V
yf
, V
bf
Filter output
V
r
(t), V
y
(t), V
b
(t) Voltage samples
SNF Signal not t
BT Block trip
T Trip
ST Smart trip
V
lt
Lower threshold
V
ut
Upper threshold
average lter (MAF), as shown in equation (1) is used to
extract the unwanted information from the voltage samples
which are obtained after prepossessing using anti-aliasing lter
(AAF).
y[n] =
1
N
N1

k=0
x[n k] (1)
where,
N number of samples per power cycle
n sample number
x input voltage sample
y lter output
The extracted time domain information is compared with
both lower (V
lth
) and upper (V
uth
) bounds to assert SNF, since
the output of MAF (V
rf
, V
yf
, V
bf
) will be almost zero during
normal operating condition or when CVT transients dies out
completely. Ideally the lter output should be zero when CVT
transients dies out completely, but it will not be zero due
to errors quantization errors and due to the presence of arc
resistance. A threshold setting of 1V is used to monitor CVT
transients and no user setting is required. SNF gets asserted if
any phase voltage violates the threshold condition indicating
that the signal is not t for trip decision, thereby blocking
the trip signal asserted by zone 1 ground (R
Z1
, Y
Z1
, B
Z1
) or
phase (RY
Z1
, Y B
Z1
, BR
Z1
) elements if estimated SIR [11]
is above 5.
IV. TEST SYSTEM MODELING AND SIMULATION
In order to test the performance of ST logic, system shown
in Fig. 2 is implemented in Alternative Transient Program
(ATP). The 200km transmission line (Z
L
) [12] shown in
Protected by Zone 1 instantaneous Protected by Zone 2 with time delay typically (200ms)
CT CVT Zone 2
Zone 1
Source A Source B

Bus A Bus B
Zone 1
Zone 2 CT CVT
Z a Z L
CB CB
Z b
IEDA
IEDB
Fig. 2: Single line diagram of 400kV test system
where,
Z
a
, Z
b
Source impedance
Z
L
line impedance
CB Circuit breaker
IED Intelligent Electronic Device
Fig. 2 is modeled as frequency dependent line model [13]
with CVT model [14], [15], CT model [16], primary arc
model along with elongation effect [17] and bus bar model.
2
Source impedance (Z
a
, Z
b
) is modeled as distributed param-
eter model. Distance relay (IED
A
) is modeled as positive
sequence polarized mho characteristic [2] as shown in Fig. 3.
AAF
Sampling
unit, sampling
frequency
600Hz
Double dier-
entiatior lter
Smart
Trip Logic
Full cycle
discrete
Fourier
transform
AAF
Sampling
unit, sampling
frequency
600Hz
Double dier-
entiatior lter
Full cycle
discrete
Fourier
transform
positive
sequence
polarized
mho char-
acteristic
with security
count 2 for
trip decision
vr,y,b CVT
ir,y,b from CT
T ST
Fig. 3: Model of numerical distance relay with ST logic
In-order to satisfy Nyquist sampling theorem [18], the
extracted fault information is ltered by anti-aliasing low pass
lter before sampling, which is done at a rate of 600Hz. The
signals are then preprocessed before it is fed to the discrete
Fourier transform, which transforms the time domain informa-
tion to frequency domain information in the form of phasors.
The extracted information i.e fundamental frequency voltage
and current phasors are then fed to the positive sequence
polarized mho characteristic distance relay and nally the
available information i.e. the current, voltage and polarizing
phasors is fed to the ground and phase elements for trip
decision.
In-order to verify the performance of ST logic, reach setting
of zone 1 elements for both ground and phase elements are
kept at 50% of line reach i.e. 100km of line length and single
line to ground fault is applied at time instant T
f
at Bus B.
Since the fault is outside zone 1 reach setting i.e. 100%, it
is expected that zone 1 element i.e. either ground element or
phase element should not assert trip signal for faults outside
its protected zone.
Fig. 4 shows the fault information available to the numerical
distance relay, lter outputs and trip signals for SIR = 30
and
s
= 30, where
s
is the loading angle of sending end
generator i.e. at Bus A. In high SIR condition, the relay
overreaches and asserts the trip signal (T) due to the presence
of CVT transients immediately after fault as shown in Fig. 4.
Fig. 4 also indicates that, due to CVT transients the estimated
impedance trajectory moves into zone 1 characteristic thereby
asserting the trip signal (T) and then moves out after CVT
transients dies out thereby de-asserting the trip signal(T). How-
ever the ST logic which supervises the trip signal blocks this
signal as SNF is asserted, thereby preventing maloperation.
The presence of proposed ST logic will not provide hindrance
to trip for in-zone faults as ST logic forwards the trip signal
once the CVT transients die out.
100
50
0
50
100
C
V
T
s
e
c
o
n
d
a
r
y
v
o
l
t
a
g
e
(
V
)
vr vy vb
0.15
0
0.15
Voltage and current signals after
low pass ltering and sampling
C
T
s
e
c
o
n
d
a
r
y
c
u
r
r
e
n
t
(
A
)
ir iy ib
0
10
20
v
o
l
t
a
g
e
(
V
)
Vlth Vuth Vrf Vyf Vbf
20
30
40
S
I
R
SIRactual SIRestimated
0
1
T
r
i
p
T
0 0.1 0.2 0.3 0.4 0.5
1
0
Tf
time (s)
T
r
i
p
ST
Fig. 4: Voltage, current and logic signals for a single line to
ground fault at Bus B
V. HARDWARE IMPLEMENTATION
In order to validate the simulation results in real time the
proposed logic is realized in hardware using FPGA. FPGA
contains predened resources i.e. logic blocks which can be
recongured as desired by the user for any given application.
The interconnects between different logic blocks is achieved
using programmable interconnect and the external world com-
munication is achieved via input output blocks. The main
advantage in FPGA when compared to digital signal processor
is the ability to construct parallel structures for processing
and it can be recongured even after eld implementation.
Xilinx spartan 3A DSP 3SD1800A-FG676 [19] FPGA is
used to implement, test and validate the proposed logic by
synthesizing and implementing in FPGA using Xilinx ISE-
webpack.
Sending end voltage and current information is fed to the
FPGA where positive sequence polarized mho characteristic
distance relay along with the proposed logic is implemented
using hardware description language (HDL) verilog. Table. II
shows the list of modules and their function which are created
3
using HDL verilog.
TABLE II: Distance relay modules
Module Name Function
Discrete Fourier transform to estimate phasors
Sequence transformation to estimate sequence parameters
Polarizing quantity to estimate polarizing phasor
Ground element to estimate positive sequence impedance
Phase element to estimate positive sequence impedance
Proposed ST logic to prevent mal-operation
These modules processes the information in a parallel
fashion rather than pipelining each processes which is the
usual case in digital signal processors. In addition to this all the
elements i.e. three ground elements and three phase elements
estimate positive sequence impedance simultaneously.
Fig. 5 shows the register transfer level view of the distance
relay incorporating the proposed logic which is obtained after
synthesizing the verilog code.
gnd
XST_GND
G
inv
XLX_27
O
inv
XLX_29
O
and2
XLX_34
0
1 O
nand3
XLX_35
0
1
2
O
inv
XLX_36
O
and2
XLX_37
0
1 O
and2
XLX_39
0
1 O
and2
XLX_41
0
1 O
th
XLX_18
thresh(15:0)
oscilloscope
XLX_40
oe1
dir1
security_count
XLX_33
clk
rst
valid
trip_in
prst_s
curr_s
init_block
XLX_38
clk
reset
safe
dcm_top
XLX_24
CLKN_N
RST_N
LOCKED_OUT
CLKN_BUFG_OUT
CLK0_OUT
datamodule_MUSER_Relay
XLX_1
clk
dm_rst
ib(15:0)
ir(15:0)
iy(15:0)
romadd(8:0)
vb(15:0)
vr(15:0)
vy(15:0)
faul t
sc_val
valid_out_rom
symetrical_components_MUSER_Relay
XLX_15
b_i(15:0)
b_r(15:0)
r_i(15:0)
r_r(15:0)
y_i(15:0)
y_r(15:0)
Vb_i(15:0)
Vb_r(15:0)
Vr_i(15:0)
Vr_r(15:0)
Vy_i(15:0)
Vy_r(15:0)
sym_clk
sym_enabl e
sym_rst
a1_i(15:0)
a1_r(15:0)
a2_i(15:0)
a2_r(15:0)
o_i(15:0)
o_r(15:0)
Vo_i(15:0)
Vo_r(15:0)
V1_imag(15:0)
V1_real(15:0)
pol_enable
Polarizing_Quantity_MUSER_Relay
XLX_16
a1_imag(15:0)
a1_real(15:0)
a2_imag(15:0)
a2_real(15:0)
pol_V1_imag(15:0)
pol_V1_real(15:0)
pol_clk
pol_enabl e
pol _rst
Bph_conj_imag(15:0)
Bph_conj_real(15:0)
BRph_conj_real(15:0)
BR_ph_conj_imag(15:0)
Rph_conj_imag(15:0)
Rph_conj_real(15:0)
RYph_conj _imag(15:0)
RYph_conj _real(15:0)
YBph_conj_imag(15:0)
YBph_conj_real(15:0)
Yph_conj_imag(15:0)
Yph_conj_real(15:0)
dist_enable
distance_estimation_MUSER_Relay
XLX_20
dist_o_i(15:0)
dist_o_r(15:0)
dist_pol_i(15:0)
dist_pol_r(15:0)
dist_Vph_imag(15:0)
dist_Vph_real(15:0)
_ph_imag(15:0)
_ph_real(15:0)
threshold(15:0)
dist_est_clk
dist_est_enab
dist_est_rst
sc_val
comp_out
distance_estimation_MUSER_Relay
XLX_19
dist_o_i(15:0)
dist_o_r(15:0)
dist_pol_i(15:0)
dist_pol_r(15:0)
dist_Vph_imag(15:0)
dist_Vph_real(15:0)
_ph_imag(15:0)
_ph_real(15:0)
threshold(15:0)
dist_est_clk
dist_est_enab
dist_est_rst
sc_val
comp_out
distance_estimation_MUSER_Relay
XLX_17
dist_o_i(15:0)
dist_o_r(15:0)
dist_pol_i(15:0)
dist_pol_r(15:0)
dist_Vph_imag(15:0)
dist_Vph_real(15:0)
_ph_imag(15:0)
_ph_real(15:0)
threshold(15:0)
dist_est_clk
dist_est_enab
dist_est_rst
sc_val
comp_out
dist_ph_est_MUSER_Relay
XLX_23
ph1_curr_imag(15:0)
ph1_curr_real(15:0)
ph1_imag(15:0)
ph1_real(15:0)
ph2_curr_imag(15:0)
ph2_curr_real(15:0)
ph2_imag(15:0)
ph2_real(15:0)
pol_imag(15:0)
pol_real(15:0)
threshold(15:0)
dist_ph_est_ce
dist_ph_est_clk
dist_ph_est_rst
sc_val
comp_out
dist_ph_est_MUSER_Relay
XLX_22
ph1_curr_imag(15:0)
ph1_curr_real(15:0)
ph1_imag(15:0)
ph1_real(15:0)
ph2_curr_imag(15:0)
ph2_curr_real(15:0)
ph2_imag(15:0)
ph2_real(15:0)
pol_imag(15:0)
pol_real(15:0)
threshold(15:0)
dist_ph_est_ce
dist_ph_est_clk
dist_ph_est_rst
sc_val
comp_out
dist_ph_est_MUSER_Relay
XLX_21
ph1_curr_imag(15:0)
ph1_curr_real(15:0)
ph1_imag(15:0)
ph1_real(15:0)
ph2_curr_imag(15:0)
ph2_curr_real(15:0)
ph2_imag(15:0)
ph2_real(15:0)
pol_imag(15:0)
pol_real(15:0)
threshold(15:0)
dist_ph_est_ce
dist_ph_est_clk
dist_ph_est_rst
sc_val
comp_out
display_MUSER_Relay
XLX_28
m_all (5:0)
diplay_clk
displ ay_rst
lcd_data(7:0)
led(5:0)
lcd_cs
lcd_rs
T
smart_trip_MUSER_Relay
XLX_32
sampl e_scan(15:0)
acc_rst
acc_start
smart_clk
smart_rst
td
smart_trip_MUSER_Relay
XLX_31
sampl e_scan(15:0)
acc_rst
acc_start
smart_clk
smart_rst
td
smart_trip_MUSER_Relay
XLX_30
sampl e_scan(15:0)
acc_rst
acc_start
smart_clk
smart_rst
td
sdft_MUSER_Relay_1
XLX_2
sample_in(15:0)
clk
reset
valid_out_rom
imag_part(15:0)
real _part(15:0)
samples_scan(15:0)
acc_rst
acc_start
symm_enable
sdft_MUSER_Relay_2
XLX_10
sample_in(15:0)
clk
reset
valid_out_rom
imag_part(15:0)
real _part(15:0)
samples_scan(15:0)
acc_rst
acc_start
symm_enable
sdft_MUSER_Relay_3
XLX_11
sample_in(15:0)
clk
reset
valid_out_rom
imag_part(15:0)
real _part(15:0)
samples_scan(15:0)
acc_rst
acc_start
symm_enable
sdft_MUSER_Relay_4
XLX_12
sample_in(15:0)
clk
reset
valid_out_rom
imag_part(15:0)
real _part(15:0)
samples_scan(15:0)
acc_rst
acc_start
symm_enable
sdft_MUSER_Relay_5
XLX_13
sample_in(15:0)
clk
reset
valid_out_rom
imag_part(15:0)
real _part(15:0)
samples_scan(15:0)
acc_rst
acc_start
symm_enable
sdft_MUSER_Relay_6
XLX_14
sample_in(15:0)
clk
reset
valid_out_rom
imag_part(15:0)
real _part(15:0)
samples_scan(15:0)
acc_rst
acc_start
symm_enable
ibuf
rst_n_BUF
O
obuf
lcd_cs_OBUF
O
obuf
fault_OBUF
O
obuf
T_sc_OBUF
O
obuf
oe1_OBUF
O
obuf
lcd_rs_OBUF
O
obuf
ST_OBUF
O
obuf
dir1_OBUF
O
obuf
SNF_safe_OBUF
O
obuf
lcd_data_7_OBUF
O
obuf
lcd_data_6_OBUF
O
obuf
lcd_data_5_OBUF
O
obuf
lcd_data_4_OBUF
O
obuf
lcd_data_3_OBUF
O
obuf
lcd_data_2_OBUF
O
obuf
lcd_data_1_OBUF
O
obuf
lcd_data_0_OBUF
O
obuf
led_5_OBUF
O
obuf
led_4_OBUF
O
obuf
led_3_OBUF
O
obuf
led_2_OBUF
O
obuf
led_1_OBUF
O
obuf
led_0_OBUF
O
buf
XLX_1_valid_out_rom_1
O
buf
XLX_1_valid_out_rom_2
O
buf
XLX_16_dist_enable_1
O
buf
XLX_16_dist_enable_2
O
buf
XLX_16_dist_enable_3
O
buf
XLX_16_dist_enable_4
O
buf
XLX_16_dist_enable_5
O
buf
XLX_16_dist_enable_6
O
buf
XLX_27_1
O
buf
XLX_27_2
O
buf
XLX_27_3
O
buf
XLX_27_4
O
buf
XLX_27_5
O
buf
XLX_27_6
O
buf
XLX_27_7
O
buf
XLX_27_8
O
buf
XLX_27_9
O
buf
XLX_27_10
O
buf
XLX_27_11
O
buf
XLX_27_12
O
buf
XLX_27_13
O
Relay:1
Relay
clk_24M
rst_n lcd_data(7:0)
led(5:0)
dir1
faul t
lcd_cs
lcd_rs
oe1
SNF_safe
ST
T_sc
Fig. 5: Register transfer level view of numerical distance relay
along with the proposed logic
This shows the complexity in hardware level since entire
algorithm has to be handled in bit level. The synthesized
code is rst validated using Xilinx simulation tool before
implementation at each module level. During implementation
stage again each level is tested and validated using ChipScope
Pro which helps to tap the signals inside FPGA.
Fig. 6a and Fig. 6b shows the nal placed and routed view
in FPGA and the device utilization details are shown in Table.
III. FPGA placed view in Fig. 6a gives the indication of the
logic blocks utilized to implement the entire relay and Fig. 6b
shows the nal interconnection between logic blocks obtained
using programmable interconnects.
(a) placed view (b) routed view
Fig. 6: FPGA placed and routed view
TABLE III: Device utilization summary
Logic utilization Used Available Utilization
Number of slice ip ops 14263 33280 42%
Number of 4 input LUT 11910 33280 35%
Number of occupied slices 9586 16640 57%
Number of DSP48As 83 84 98%
The implementation of proposed logic is also simple, as
MAF lter can be visualized as constant coefcient nite
impulse response lter. Table IV shows the hardware con-
sumption details for implementing the proposed logic in Xilinx
FPGA. This shows that the proposed logic can be easily
incorporated in existing relays without any major hardware
modication.
TABLE IV: Device utilization summary
Logic utilization Utilization
Relay Relay+ ST logic
Number of slice ip ops 39% 42%
Number of 4 input 32% 35%
Number of occupied slices 53% 57%
Number of DSP48As 98% 98%
Fig. 7 shows the graphical view of area occupied for the
proposed logic (blue patches) which will be augmenting the
existing numerical distance relay algorithm (black patches).
Fig. 8 shows the actual hardware setup with test results
validated using Xilinx FPGA. Three signal information are
4
Fig. 8: Experimental setup showing the test results
Fig. 7: FPGA placed view highlighting the slices consumed
for the proposed logic
tapped from FPGA for oscilloscope display via input output
ports. In oscilloscope display, channel 1 shows the time at
which fault is applied i.e. 0.2 second for a total simulation
time of 0.5 seconds. Channel 2 shows the relay mal-operation
which occurs 30ms after fault inception and channel 3 shows
the SNF signal which monitors the CVT transients in real time
thereby blocking distance relay mal-operation. Oscilloscope
information in Fig. 8 also indicates that SNF gets asserted after
fault immediately after transient detection which is not the case
in existing techniques as it consumes one power cycle time
i.e. 20ms for 50Hz to transform the information to frequency
domain. Fig. 8 also shows that the blocking time is adaptive
as it entirely depends upon the CVT transient information
available in time domain.
VI. CONCLUSION
This paper proposes a new and simple logic to adaptively
block numerical distance relay mal-operation during high SIR
condition without reducing zone 1 reach or by giving xed
time delay. With the use of existing techniques the reach would
be reduced to a safe level which is estimated to be 5% for the
considered CVT and SIR, but the proposed logic prevents mal-
operation even at 50% reach setting with adaptive time delay.
The proposed logic is also validated in real time using Xilinx
FPGA.
APPENDIX
Estimated values of transmission line parameters,
TABLE V: Line Data
line parameters Resistance (pu) Reactance (pu)
positive sequence 1.4610
3
3.7010
2
negative sequence 1.4610
3
3.7010
2
zero sequence 3.39 10
2
1.1510
1
5
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