Revision no.: PPT/2K403/02 Revision no.

: PPT/2K403/02
Peripheral Chips of 8088
(Self Study)
Revision no.: PPT/2K403/02
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8284 Clock Generator
Three different functions perform by 8284
Generating system clock for the 8088
Generating ready signal for the 8088
Generating reset signal for the 8088.
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Clock Logic
Output signals: CLOCK, OSC and PCLK.
The clock is the system clock for the microprocessor, co-
processor and bus-controller.
It is a free running clock of 33% duty cycle.
The frequency of this signal is 1/3 the frequency of crystal at
pin X1, X2 or external input signal at EFI.
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Ready Logic
Generates READY signal for the microprocessor.
To introduce a wait state in the 8088 bus cycle, the READY
input is made low by 8284 otherwise READY is maintained at a
high level.
Two pairs of input signals which can make READY low:
Pair 1 : RDY1 and AEN1
Pair 2 : RDY2 and AEN2
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Ready Logic (contd.)
In PCs, the RDY2 and AEN2 are not used.
The RDY1 signal is used for generating cycle stealing wait
states for performing the DMA bus cycle.
The AEN1 pin is used for generating wait states in the CPU bus
cycle for synchronizing the CPU with slower memory or I/O
ports.
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Reset Logic
Generates the RESET signal for the 8088.
When the RES input pin is made low, the RESET logic
generates high active RESET signal.
Power good signal is generated by SMPS.
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Reset Logic (contd.)
In PCs, the RES input is connected to any of the following two
signals:
Power good signal from SMPS.
Power on reset from an R-C low pass filter circuit.
The manual reset from the front reset switch is also connected to
RES input.
Resetting the PC is done under any of the following
conditions:
During power-on ie. power-up reset.
By pressing the reset push button or switch ie. manual reset.
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Reset Logic (contd.)
By pressing Ctrl+Alt+Delete on the keyboard ie. soft reset.
The hardware resets (i.e. Manual reset and Power up reset)
effectively applies a reset clearing all flags, IP, DS, SS and ES
registers and setting up all ones in CS register.
The soft reset is purely a software sequence as a result of
which the POST gets control.
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8288 Bus Controller
8288 functions
Generates the ALE signal to control the address latch.
Generates the DT/R and the DEN signals to control the data bus
transceiver.
Generating the Read/Write Control signals on behalf of the 8088.
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8255 (Programmable Peripheral Interface)
Widely used as multipurpose programming I/O device for
interfacing several types of peripheral to a computer.
Important general purpose I/O device that can be used with
almost any microprocessor.
24 I/O pins that can be grouped primarily in two 8-bit parallel
ports A and B, with the remaining eight bits as port C.
The eight bits of port C can be used as individual bits or be
grouped in two 4 bits ports C upper (CU) and C Lower (CL).
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8255 PPI (contd.)
Modes of operation that can be
selected by software
Mode 0 - Basic Input/Output
Mode 1 - Strobe Input/Output
Mode 2 - BI-directional bus
Uses of the 8255
Printer interface for directly
interfacing a parallel interface
printer with handshake protocol.
Keyboard and display interface.
Digital to analog/analog to
digital interface.
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8253 Programmable Timer
Three multipurpose
programmable timers.
Each timer has a 16 bit
down counter, which
can be programmed to
operate in any of the six
different modes.
Each counter can be
programmed
independent of other
counters.
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8259 Programmable Interrupt controller
The micro processor provide service to I/O devices in one of
the two ways.
Polling routine
Interrupts.
Polling Routine
Microprocessor checks & tests to see if any device needs to be
serviced.
The order of testing and the priority given to different I/O devices
can be changed by changing the polling routine.
The I/O polling routine is only useful with the I/O devices which do
not demand immediate service or have very infrequent demands
for service.
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Interrupts and Interrupt process
Interrupts
Interrupt input tells the microprocessor that an external device
needs attention.
It is very much similar to a subroutine.
Interrupt process
An Interrupt signal is received by the microprocessor.
The microprocessor completes its current instruction. No
instruction is cut-off in the middle its execution.
The address of the next instruction with a value is stored on the
stack.
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Interrupt process (contd.)
The program counter is stored called the interrupt vector.
The microprocessor executes the interrupt routine which starts at
this vector address.
When the interrupt routine is finished a return instruction loads
the PC from the stack.
Program execution continues with the instruction which follows
the instruction which it was executing when the interrupt
occurred.
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8259 functions
Accepts the requests from the peripheral devices.
Determines which of the requests is of highest priority.
Ascertains whether the in-coming request has a higher
priority value than the level currently being serviced.
Issues an interrupt to a CPU based on this determination.
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8237 Programmable DMA Controller
DMA is used for quick transfer of large amount of data.
DMA reduces the workload of processor.
When the processor requires the periodic rest regarding
certain tasks, the DMA takes hand over from the processor by
taking its data bus &control signal and perform that task with
the same consistency and speed as of processor.
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Features of DMA
Four independent DMA channels.
Direct memory to memory transfer possible.
Independent Auto initialization of all channels.
Supports the software DMA requests.
It can be cascaded.
It has the necessary logic for supporting peripheral
subsystems, such as Floppy disks and Hard disks.
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