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vD-olq
Roll No

M.Tech ( VLSI-Design) First Semester Examination2009-20 1 0 Solid State Electronic Devices

Time : 3

hrs marks'

Max' Maiks: 100

i

Note : Attempt any five questions. All question carry equal

"

with Rl.u)Explain Bridgman technique of crystal growth with neat diagram .Also compare this method prochralski technique.

I--oifrererriiut" & Analyzethe performance. (\

.yjwtrutdoyouunderstandbyVaporphaseEpitaxyandMolecularbeamEpitaxy.
i

fc))A v7.2A0onthex_axis.Findthecorrespondinginterceptsontheyandzaxis.

crystal whose primitives aie 1.2A0, 1.8A0 ,and.2.0A0 a plane( 231) cuts an intercepts;at that can be filled by hard sphere in the sc,

,q/ fina the maximum fractions of unit cells volumq

'

bcc and diamond lattice.

Q2. a) What do you understand by Liquid phase Epitaxy and Molecular beam Epitaxy. Differentiate & Analyze the performance. b) Write a short note on of hole i) Erregtrve Effective mass ()1 u Semiconductor Dsllltuulluuutur Ex[rrr]srL: Extrinsic & 6a ii) Intrinsic lu lrunnslc iii) Tunneling effect in quantum mechanics A Si crystai is to be grown_ by the Czochralski method and it is desired that the ingot contains c) a) What concentration of phosphorous atoms should the melt contain to give this impugitii concentration in the crystal during the initial growth, for P in Si ku: 6.60 b) If the initial load of Si in the crucible is 8 Kg , how many grams of phosphorous should be added .The atomic weight of phosphorous is 31.
I ,

e3*ffixplain -

the process of lon-Implantation with suitable ciiagranr. Also define the Gaussian fotmulae fo, implanted ciosage and projected range. bwhat are the diffeient .upu.1turr."s formed in p-n junction formation .Derive the formulae for diffusion and transition 6))Boron is alloyed into an n-typ" Si sarnple (lrld:101e cm-31 ,forming an abruptjunction of circular

capacitance

\7"ros

section with a diameter of 0.02 in .Assume that the accepter concentration in the alloyed y',r1n20 rm-3 -o^i^- ic r rq rJ \.Ia: lvBru YYlr lvElvrr Calculate V0, xno, xpo and Ee for this junction at equilibrium (300K) .
I

(+.

u) Write short note on

1)

Varactor Diode
:

2\/ Tunnel Diode b)bxplain how a p-n junction diode can be used as photodiode for illumination purpose' Also
explain the energy band diagrams giving equation of current. and analyze Zenw and Avalanche breakdo$'n. c) L//xplain

Q*{" a) What

b)

are the different steps of BJT fabrication.Explain in details with suitable diaer;ms. For a Si one sided abrupt junction with Na:lQle cm-3 and No 1016 cm'3 ,Calcutatle tire width of depletion layer and maximum field at zera bias( T:300K )

Q6.a) what do you understand by Ebers- moll model in context to BJT. model with suitable diagram. b) Compare and contrast the construction and
diagrams.
j

for this

W.
*

elB*plain the different steps used in the fabrication of MOS IC. Give the . flecessary detail with suitable diagrams. 7S) Wt at is CCD. Explain the improvements in basic structul.e of CCD.

g) Explain population inversion phenomenon in semiconductor

spectra for p-n junction lasers.

lasers"

.p) Explain p-n-p-n diode with Two -Transistor topology. c) Write short note on TRAPATT diode.

(Following paper ID and *o,,

Roll No.:
(Advance Electronics 31! _Communication) _. Speciatizarion in VLSI D;;;rrt..rv4ar\ First Semester Examinrti*, z'riif _fz

Sub: Solid State Electronic Devices

Time:3 hours
9TE: All questions are compulsory

Max marks:100

Ql. Attemptanytwo,

a) A Si crystal is to be grown by the czochralski method, and it is

( rcx2)

what concentration of phosphorus atoms should the melt contain to give this impurity concentration in the crystal during the initial growth? Forp in Si, Ko:0.35. II' ifthe initial road of Si in the crucibre is 5

I.

desired that the ingot contain I 0'uphosphorus atoms/cm,.

of

phosphorus is 31.

kg, how many grams phosphorus should be added? The atomic weight of

b) Derive an expression for energy difference between orbits nl

c)
tqz.

andnZ using the BOHR model. Describe euantum Mechanics

and Tunneling.

Attemptanytwo:

with a scaring factor h for direct and indirect electron transitions in semiconductors. b) Derive an expression rerating the intrinsic

a) Draw (E, K) diagram plots of electron energy vs. Momentum,

(10 x 2)

revel E, to the center of the bandgapEr/2. carculate the dispracement of E, from E/2 for si at 300k, assuming the effective mass values for electrons and holes are l " l m, and 0.56 mo, respectively.

vD014
I

c) Draw

an schematics of band diagram, density of states, Fermi-

Dirac distribution, and the carrier concentrations for intrinsic, ntype, and p-type semiconductors at thermal equilibrium"

Q3. Attemptanytwo: (10 x 2) a) Derive diffusion equations for electrons and holes for solving transient problems of diffu sion with recombination. b) Briefly explain all the steps folrowed in rhe fabrication of p-n junctions. e) Describe Schottky Barriers and Rectifying Contacts.

Q4. Attemptany trvo:

(10 x 2)

a) Find the maximum width of the depletion region for an ideal MOS capacitor on p-fype Si with Na : 10'u cm-,. Draw characteristic profile of capacitance voltage relation for an nchannelMOs capacitor. b) Describe I. TheCoupled-DiodeModel' II" Charge ControlAnalysis c) compare the basic semiconductor lasers and hetero-junction
lasers"

Q5.

Attemptanytwo:
chip.

a) Explain how basic circuit elements can be implemented on the

l}x})

b) Draw and explain c-v characteristics of DRAM Mos eapacitor in stored "0" and stored" l " states" c) Briefly Explain I. TheIMPAITDiode trI. The GUNN Diode

III" PackagingforlCs.

VDO14

vDl0l
(Following Paper ID and Roll No. to RolI No.:
b-e

filled in yourAnswer Book)

\l\

llolslqlc,

M.Tech.

Examination,20ll-12
Sub: Advanced Computer

Architecture Max marks:100

Time:3

hours

NOTE: All questions arecompulsory All questions carry equal marks.

(10x2:20) Ql. Attemptanytwoofthefollowing a) i) What are the different approaches to solve the mismatch problem
between software and hardware parallelism?

ii) Draw a dependence graph to show all the dependences for the below
givenprogram:

Sl: 52: 53: 54: 55:

LoadRl,M(100) /Rl+-Memory(100)/
Move R2,

Rl

/IU+- (R1)/

IncRl AddR2,R1

iM<-(Rl)+

1/

/112<-(R2)+(Rl)/ StoreM(100),Rl /Memory(100)<-(R1)/

b) i) What do you mean by k-issue processor? Define the term MIPS rate. Differentiate among UMA, NUMA and COMA computers? ii) Explain node duplication scheduling to eliminate the
communication delays between processors with an example. c) Explain Flynn's classification of computer architecture in detail.

Q2"

Attemptanytwoofthefottowing.
a) Differentiate between characteristics

(10x2:20)
CISC

of typical RISC and

architectures.

How micro programme controlled and hardwired

controlled unit works to enhance the performance ofprocessors. b) Differentiate between omega and baseline networks? Also design a two stage 64x64 butterfly switch network built with sixteen 8x8 crossbar switches and eight way shuffle inter-stage connection. c) What are the characteristics ofvector and symbolic processor? Explain.

VDlO1

Q3. Attempt any two of the following. (10 x 2=20) a) Consider the tlve stage pipelined processor specified by follcwing reservation table.

I
SI
s2 s3
S4
x

,
x

6
x

x
x x

S5

For above ,list the set of forbid<len latencies and collision vector and draw the state diagram showing; all possible initial sequences(cycles) without causing collision in a pipeline. a) i) Differentiate among direct mapping, associative mapping and kway set associative mapping with reference to cache addressing. ii) Explain in short the static arithmetic pipelines.
b)

instructions. Assume that hit takes r clock cycre and miss penalty is I 00 clock cycles. A road and store (data) hit takes I extra clock cycle on unified cache. carcurate the average memory access time for sprit. memory and unifiedmemoryanrl compare them.

which has the rower miss rate: a 16 KB instruction cache with r6KB data cache or a32KB unified cache? The miss per 1000 instructions r6 KB instruction cache is 3.g2, data cache is 40.9 and for 32 KB unified cache is 43-3 are given. Assuin: -z6ok of rnstr-;ctions are de.ta transfer

Q4.

a) what is Multiprocessor cache crherence? Discuss the directory based cache coherence protocols in sht.,rt.

goxz:Zo)

b) Discuss MSI, MESI and MOESI cache coherence protocors in short with their state transition diagrarn. c) Explain in short about the symmetric shared memory architectures and distributed memory shared memory architectures.

Q5. Writeshortnotes onanyfour.

a. ALPHA 21364

(5x4:20)

b. Domain partitioning c. Enterprise RAS feafures set. d. Memory mirroring / migration e. Fault tolerant system

vD101

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is 1X10.., tttottts l]el C11I ttltLt

(ii;]i r*a dopa.r in the p", s..on.l. What is the calculated junction depth? r't''ith ueat diagrams' ft) dxpiain X-ra.y litirograpiry

lin

,--ffiat g*p la in the bas ic transport proces s e s atlcl *=-6l^ ,rr.l.^.""n fLtm tire 1;lot o1' 1/Cr versus V. What

le actio n kinetics'

sffaiglrt iurpiy about ti'; ti"l"'g profile sirape? witia neat diagrams' (c)Explain the IIC onttirtl'l'sma excitation

does thil

vD-102

-t-

{'[urtt Overl

OttO-Fo. an \-channel i''..*--."C,.,.*:7X10-8F

,./t**1

'*-\

MOS transistor. rvitlr pt,,:(i00cm2/Volt seconcl" per cur2, W:20pru. L:2 iun alrcl V1q:1.0V. Exaurint: the chain cugeqt ancl the terurinal.rroltages, o -. 1b)Desffie G*Gtutionship betrveen tG niask channel length and electrir-:al channel length. Are they iclentical? If not, how rvoulcl 1,oLr expl"ess electtical chanuel lengtir ii: terms o{'nrasli channel lepgth irr ternlr of orrrer pzu'arucrters?

Q5QilConsicler tlre Ci\4OS invc:rtel circuit i,r,itli the [bllorving pararnerer.:

V11p:3.3V. V;.11.11:0.6V. V.;s.p:-0.7V. k,,:200liA/Vl, l<.,.,:Bt)ptA/Vl. Calculate the noise ntargins of the circnit. lbJExplain the C-'omp lerlen taLy-pass-transistor lo gic ( C'pL). , .{c)Dr:srgn CUOS D latcli. Q6(a)Calculate Vrrr., Vorr,

[rpCo*: 201s,AlY', Vpp 5V. (blCorrsi,{e-r, thq r.irnr.ir. i" +l:: ' quu {,:,':.:^*^*'-;^'-:-"ii'r,r irguu.Ui slti_)wll Delow.

Vn, V111, n'M; uncl NN411 tbr a tr,vo input NOR gate fabricated r.vith CMOS technology. Given, 1W/L;,,=4. (WL),,=1, V1.p:0.7V, V1.p: - 0.7V. LrnCn*: 40 pAiV3"

logic ftlnetion f. (ii) Design a circnit to implement the sarne ftinction using NOR gates and AND-OR-Invert gate. Draw the transistor level

(U Uetefmine tlfe

schematic also.

*L
B

the ROM and RAM cells clesign. lQ7(ffixptain -fli)Explain the CMOS SRAM cell rvor&ing rvith neat sketch. Also give cEll clesign strategy.

t'i

i QBWrite '

\*-(i)

short notes on tire follorving:

(iil

(iii)
ItTt-t {t?

Optical lithography Reactive plasn'ra etching CX4OS Schmitt trigger Large signal model of I\4OS.

Primted Pages : 4 (Roll No. to be filled in \,our Answer Book)

Roll No.

vD-2.02

\ \

M. Tech.
(Second Semester) (Regular) Examinatio n,

20ll-lz

Low Power VLSI Design

Time:

HoursJ

[Total Marks : l0A

Note

: All questions are compulsory. All questions carry equal marks.

Attempt anytwo ofthe following
:

l0x2:24
?

(a) (i) (ii)

What are the basic sources ofpower dissipation in CMOS invefier

expression for short circuit power dissipation.

Derive an

A 16-bit bus is used to derive the load of l0 pF/bit. Each bit has 40% switching probability at each clock cycle. The supply voltage is 3.3V and its clock rate is
I

I0MHz. Calculate dynamic power dissipation during bus operation.

(b)

(i)

What are the three keyprinciples for lowpowerdesign

Explainbriefly.

(ii)

There

is a process with 0r:30pA/V', gn:45pNy2, V,,:1Vtpl:0.7V and

dissipation ol3Z.x32 ROM which has 1:32

Voo=SY. Calculate static power

pseudo-NMoS row decoder and PMoS pull ups on 32-bit line. The w/L ratio
,1

ofPMOS is 1 and it can source ft(Ysr*Yt)zlzcurrent. Assume at a time one row

decoder is on and 50%

ofbit line
(1)

are on at any

time
P.

T. O.

(c)

(i)

from pou'er dissipation Define hierarchy of limits upon scaling that arises
consideration. Explain circuit limit in detail'

(i

i)

what is the impact of device and technology on low power electronics

How

dosupplyvoltageandthresholdvoltageaffecttheperformanceofanyCMOS
device ?

2.

AttemPtanYtwoofthefollowing:

L0x2-20

(a)

(i) (ii)

power fordiscrete transistor? How does SPICE circuitsimulation estimate the

Explain briefly the development of

architecture Ievel'

powe )r models used

at switch

and

(b) (i)

Density' Switching Write down the definition of Static Probability, Transition

frequency.Characterizetherandomsignalshownbelowandcalculatethe
frequencY'

Time

lnr)

(iil

How can power be estimated What do You understand bY signal entropy ?

usingit?
to calculate static probability of Boolean Use the Shanuon Decomposition technique

(c)

function Z:A.(B+C). Given signal A, P(B):0.6 and P(C):0-8.

(2)

and

C are uncorrelated and P(A):0'4'

3.

Attempt any two ofthe following

0x2:20

(a) (i) (ii)

How the transistor sizing is opiimir"ri to reduce the dynamic and leakage
pou,er at circuit-level design 'l

What do you un<lerstand by equivalent pin ordering ? How is it helpful for

reducing the circuit power consumption ?

(b) (i)

What do you understand by local restructuring of gates ? What are the basic
steps of local transformation to the network ?

(i,
(c) (i)

HJTffi ;:'I:-:I:;T::"":,il:T* ;::il.il:ffi,X ::

same chip ?

Apply transistor network restructuring approach on Boolean function

Y:A(B+Q. How many architectures are possible for above function ? If
transition probability of A:0.7,8:0.5 and C:0.3, then find which architecture

will

consume less power.

(ii) 4"

Explain how bus invert logic results in less power consumption.

Attempt anytwo ofthe following:

'

l0x2:20

(a) (i) (ii)

What do you understand by power and performance management ? Explain with the help ofexample.

What are the two popular techniques used for microprocessor design at
architecture level to save the dynamic power ?

(b)

Consider the recursive compltation case using expressi6nyn:bo,rn*o/n-r, Draw the

flow graph (CDFG) for the loop Unroll the loop once and explain how power can be
saved by unrolling the loop.

(c)

Explain the low power scheme for SRAM 6-transistorcell.

(3)

5.

Attempt any tr.r,o ofthe following

lAxZ

(a)

The following are given:

phase A equal path clock tree T with buffers ihserted using balanced buffer method,

Determine the size of buffer (PMBS) in

to minimize total power P subject to the

to any condition maxQt)<tr, and max(d,.- d.r)<tb, where d;an d d, arcphase delays from
sink Points

(b) . (c)

Explain Delay balancing method in parallel multiplier to save pou'er by avoiding

glitches.

'

..

Explainthgpowersavingtechniquesforbuses:

(4)

200

M.Tech.(VLSI)
Tirne: 3 HosysJ Note: Aftcmpt all questions:

E 1!sz3e oo&
0

vD_202

(sEM.rI)EXAMINATION 2009_1 LOW POWER VLSI DESIGN

{Total tutarks; t 00

l.

Attempt.arry TWO questions from the following: a?' are the sources-of power ciissipurto,i,n / fo' power cMos circuits? Derive ,n. "what computation in cMoS circuits. A o+ "orutillf:'o' off-chip bus is operating at j v and 66 'it'IHz clock rate is driving u .upu.itun'e 1i1 of IOpF/bit.Each bit is estimated ro have a clock cvcte. carcurate rr," po*", Jissipation in the bus. y'.tossl;firTr::HY.$l: design? Give an overview of ernerging trends in lowei power design uoo.ou"onlrlower c' Discuss the positive and.negative impact of reducing gate oxide thickness, device vortage scaring and..ou.ine iortug" swing on power dissipation in :r,;t'$'jfir,ir:rd

i'"*n

o=ro, / ". suitabte o,fdata il;;;;"";erization in porver anarysis? *ltn ,ui,,ry::::jf l,_T,lTi*. exampre, exprain how dara , coneration can efrectiv;iil:H#lt"ilill*"rr,

2' Attempt any FouR questions from the foilowing:

/b' y'

approach) over simuration based moders estimation can be done using entropy? Jro* ry:.r Write a short note on _ Ir{onte Carlo simulation.

what are the advantages of estimating power dissipation using simuration techrriques such as SPICE? what is'the main disadvantage of gate lever porver anarysis? What are the merits and demerits.f transiticn ri*:rs!? n:,rde! ;.r_rr-._r-i!:_.i

;ffi;ilffi;#

;:i ;?i; ;i;i;;u"or,

and P(c) are the input static probabilities ., olcerrain 1ogic circuit. trind the output static probabirity ofy: rb * c by using Sftannon,s dccornposition theoreni.

lf

P(a)'P(b)

write the three steps of algorithm

density fbr combinational circuits.

rrsed in gute l"uer power anal,r,sis using transition

(:i Atternpt any !'oUR questirns lrom the fo[owing:

a'

(5x4:20) what are glitches? trhat impact cro they rrave on power consunrption? wrriti are techniqrres adopted to minimizc effect orr,igt capacitance nodes in lorv porver vLSI design?

rb: How logic encoding can help in power manageme,t? Ilrustrate rvith suitai-.re cxanrpre. c'lDiscuss thc significance of bt,s invert

d'

encoding in power manage,".ent. Discuss the translormarions irtvolved in irnplemeniing gu," rcorga,izatio. .uld iocal restructuring f,or power notc on anv ONE-

e. Write short
l+

marage*:,t in ror.r power vr-SI ltesignl,

(i) Significance of IrS\I encoding in t.pVD

,/1iil

f.ur,pLr\\,er riigirar ccll librar,,,

*t V

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FOtill

(5-\{:20i
dcsign at
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vD 242
(Following Paper ID and Ro.ll No. to be filled in yourAnswer Book) Roll No.:
i)

li

'l

M.Tech. Second Semester Examination (20 l0- I I )

LOW POWERVLST DESIGN

Time: 03

'Note:

Hours
Question I is compulsory. Attempt 5 questions in all.

Total Marks: 100

'-

6IThe chip size of a CPU is 15mm * 25mm with clock frequency of 300MHz operating at 3.3V. The length of the clock routing is
estimated to be twice the circumfereuce of the chip. What is the power dissipation of the clock signal if the clock signal is routed on a metal layer with width

of 1.2um and the parasitic capacitance of the metal

p
Q

(4) Iayeris lffium2. po\l'er in the Gate ievei components Grve a brief description of tirree (4) logic simulaiion

Compute the transition density and static probability tbr y : ab + c given that P(a) :0.2, P(b) :0.3, P(c):0.4, D(a) : l, D(b) :2, D(c)
-J.

(4)

How Double Edge Triggered Plip Flop reduces power dissipation?

Explain. (4)

Compare the power dissipation in a Uniprocessor system to that in Parallel processing systems and pipelined

systems.

(4)

Question 2 threshold -a)'What are the impacts of varying gate oxide thickness, voltage and voltage swing otr th,: p61v"t dissipation in CMOS

;circuits. \ Di..rs consumption.

vD
202

( 10)

the role of circuit capacitances in the power dissipation. How

the high capacitance nodes are dealt to reduce power

(10)

Question3

Q,xplain Dual Bit Type signal model. Derive the expression of power
dissipation for the Datapath module

characterization.

(10)
the

QHow

ther 'Stopping criteria

of the simulation' is estimated by

(10)

Monte Carlo power simulation. Question 4

/O"nr" thc terms'static Probability' and'Trans:ti on Density'. Discuss -\ the propatlation of Static Probability and Transition Derrsity in the
Iogic circuit.

(10)

b) How does the entropy of the system affbcts ihe power dissipation of
the system. Derive the po.ver expression to support the explanation.

Que,rtron

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5

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\ t What are the various logir" encoding schemes. I-rcscribe the power managcrnent plocess in Sti:te Machine E,ncoding. ( l0)
Question6

a) Discuss the partial activation of Multidivided Datalines and

Multidivided Wr:rdlines in the low powr DRAM circuits. How does
it help in power conselaticrn?
( 10)

b) Explain the working of Arlay Multiplier and state its shortcomings. How"Wallace Tree Multiplier' leads to low power desigrs. ( 1 0)
Question
7

a) What is the significance af Tolerable skew? l)erive the value of tolerable skew in order i; overcome Double-clocking and Zeroclocking condition.
Vector Quantization proce:rs.

(10)
( 10)

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VDO34

(Foltowing Paper ID and Rolt No. to bc filled in your Ansu'er copy)

Rollno:
NI. TECH

3rd Semester Examinations 2011-12 SUB: Nano TechnologY

"Ilime: J Hours

Total il{arks: i00

parts from Note: Attempt any two parts from section I-IV and four tionV.
Section-I

of rl,.{Vhat do you mean by quanhrm confinement? calculate density (10) -6ates for 3D, 2D and lb iYstem. .Considerametalnanoparticleofsizel0nmxl0nmxl0nm.

-dt
"

Fermi energy is 10 eV. Calculate (a) Density of electrons n? (10) "fotal numbJiof electrons N on the particle? &) ^ + +l.o of gap 1I/!:e facio;s band tile which affeci J. YV ildl Gi! ^-.. lrr! lqlrvrJ

semiconductor?

(10)

Section-II

( l0) -Importanc" of l"sotrrtlon in opiical lithography? . VlExotain deep ultra-violetiithography and also explain the factors

v,aefini

technique in 1. What is chemical beam epitaxy (cBE). Discuss this matching lattice why explain Atso detaitwith its merits and demerits. (10) duririg epitaxial growth is the explain and lithography with rti general processing steps

important?

*r..ringtheDiJVresist?
1.

(10)

Section-III

Derive

frou" .-/ :thickness

ilr"i"o u.a

relation for hrnleling rate iu metal tunnel junctions' ( l0) that transmission probability depends exponentially on

(10) $eposition of carbonNanotubes with their applications?

(lo) l.zWhatareCarbonNano.tubes?Writedowntwomethodsof
I

apd height

or ine banier in

rectangular potential

vD034

iiection-IV Effect Quantum Dot (FEQD) and Strain Induced Quantum Dots
Field 1. What do you mean by quantum dot? Differentiate between
(10)

{*"d

Y.t"".* $

vzwit6 anv two atomic scate characterization techniques which are io, suriace characterization in nano-structures? ( 10) down applicatio*s of nano-technology in electronics,
l4Vrite
an<i

(SIQDsI

me,iicinet

(10)

liection-V
Explain briefly the immersion lithography? 2. Write a short note on PA(i. 3. What is scattering or beam proximity effect? 4. Write a short note on SCALPEL. 5. Define dePhasing? \lfi,lrite a short note on SET.

(s) (s) (s) (s) (s) (s)

VDO34