Lecture Notes

Gate Turn-off Thyristors (GTOS)

OUTLINE

GTO construction and I-V characteristics. Physical operation of GTOs. Switching behavior of GTOS

Copyright by John Wiley & Sons 2003

GTOs - 1

GTO (Gate Turn-off Thyristor) Construction

Unique features of the GTO. Highly interdigitated gatecathode structure (faster switching) Etched cathode islands (simplify electrical contacts) Anode shorts (speed up turn-off) GTO has no reverse blocking capability because of anode shorts Otherwise i-v characteristic the same as for standard SCR
anode

copper cathode contact plate

gate metallization cathode metallization

N+ P P+ N+ NP+ anode shorts

N+

N+

P+ J3 J1 J2

anode

GTO circuit symbol

gate cathode

Copyright by John Wiley & Sons 2003

GTOs - 2

GTO Turn-off Gain

I A Q Q 2 1

Large turn-off gain requires a2 1, a1 << 1

I' G

Make a1 small by 1. Wide n1 region (base of Q1) - also needed for large blocking voltage 2. Short lifetime in n1 region to remove excess carriers rapidly so Q1 can turn off Short lifetime causes higher on-state losses Anode shorts helps resolve lifetime delimma 1. Reduce lifetime only moderately to keep on-state losses reasonable 2. N+ anode regions provide a sink for excess holes - reduces turn-off time Make a2 unity by making p2 layer relatively thin and doping in n2 region heavily (same basic steps used in making beta large in BJTs). Use highly interdigitated gate-cathode geometry to minimize cathode current crowding and di/dt limitations.
GTOs - 3

Turn off GTO by pulling one or both of the BJTs out of saturation and into active region. Force Q2 active by using negative base current IG to IC2 make IB2 < b2 IB2 = a1 IA - I'G a1 IA - I'G < ; IC2 = (1 - a1 ) IA = (1 - a1) (1 - a2) IA a2

(1 - a1) IA b2

IA a2 I'G < ; boff = = turn-off gain boff (1 - a1 - a2)

Copyright by John Wiley & Sons 2003

Maximum Controllable Anode Current

K G N+ G

shrinking plasma

P N

Large negative gate current creates lateral voltage drops which must be kept smaller than breakdown voltage of J3. If J3 breaks down, it will happen at gate-cathode periphery and all gate current will flow there and not sweep out any excess carriers as required to turn-off GTO. Thus keep gate current less than IG,max and so anode current restricted IG,max by IA < boff

K N+

P N

Copyright by John Wiley & Sons 2003

GTOs - 4

GTO Step-down Converter

GTO used in medium-to-high power applications where electrical stresses are large and where other solid state devices used with GTOs are slow e.g. freewheeling diode D F.

D +

I f

GTO almost always used with turn-on and turn-off snubbers. 1. Turn-on snubber to limit overcurrent from D F reverse recovery. 2. Turn-off snubber to limit rate-of-rise of voltage to avoid retriggering the GTO into the on-state.

V d

R D

C
Hence should describe transient behavior of GTO in circuit with snubbers.

Copyright by John Wiley & Sons 2003

GTOs - 5

GTO Turn-on Waveforms

iG td i A

IG I

GTO turn on essentially the same as for a standard thyristor

t "backporch" Large I GM and large rate-of-rise insure all GT cathode islands turn on together and have current
good current sharing.

tw

Backporch current I GT needed to insure all cathode islands stay in conduction during entire on-time interval. Anode current overshoot caused by freewheeling diode reverse recovery current.

v A t v GK t
Copyright by John Wiley & Sons 2003

Anode-cathode voltage drops precipitiously because of turn-on snubber

GTOs - 6

GTO Turn-off Waveforms

i G IG T t approximate waveform for analysis purposes ttail t t ts tg q v A K t approximate waveform for analysis purposes V t fi V d dv dv < dt dt max

ts interval Time required to remove sufficient stored charge to bring BJTs into active region and break latch condition tfi interval 1. Anode current falls rapidly as load current commutates to turn-off snubber capacitor 2. Rapid rise in anode-cathode voltage due to stray inductance in turn-off snubber circuit tw2 interval 1. Junction J3 goes into avalanche breakdown because of inductance in trigger circuit. Permits negative gate current to continuing flowing and sweeping out charge from p2 layer. 2. Reduction in gate current with time means rate of anode current commutation to snubber capacitor slows. Start of anode current tail. ttail interval 1. Junction J3 blocking, so anode current = negative gate current. Long tailing time required to remove remaining stored charge. 2. Anode-cathode voltage growth governed by turn-off snubber. 3. Most power dissipation occurs during tailing time.
GTOs - 7

Io i A

G K

tw 2

GG -

Copyright by John Wiley & Sons 2003

Lecture Notes

Insulated Gate Bipolar Transistors (IGBTs)

Outline Construction and I-V characteristics Physical operation Switching characteristics Limitations and safe operating area PSPICE simulation models

Copyright by John Wiley & Sons 2003

IGBTs - 1

Multi-cell Structure of IGBT

IGBT = insulated gate bipolar transistor.
emitter conductor field oxide contact to source diffusion

gate oxide gate width

+ P

NN+ + P

+ P

buffer layer (not essential) collector metallization

gate conductor
Copyright by John Wiley & Sons 2003 IGBTs - 2

Cross-section of IGBT Cell

gate emitter SiO 2 J 3 J 2 N + P N + N P+ collector Buffer layer (not essential) N +

Ls

J - Unique feature of IGBT 1 Parasitic thyristor

Cell structure similar to power MOSFET (VDMOS) cell. P-region at collector end unique feature of IGBT compared to MOSFET. Punch-through (PT) IGBT - N+ buffer layer present. Non-punch-through (NPT) IGBT - N+ buffer layer absent.
Copyright by John Wiley & Sons 2003 IGBTs - 3

Cross-section of Trench-Gate IGBT Unit Cell

Emitter boddy-source short Oxide N+ P Parasitic SCR ID Gate conductor NP+ Collector
Emitter boddy-source short Oxide N+ P Parasitic SCR ID P+ Gate conductor NN+ ID N+ Channel P length

N+ Channel P length ID

Non-punch-thru IGBT

Punch-thru IGBT

Collector

Copyright by John Wiley & Sons 2003

IGBTs - 4

IGBT I-V Characteristics and Circuit Symbols

i C
increasing V GE v GE4

No Buffer Layer VRM BV CES With Buffer Layer V 0 RM V

v GE3 v

GE2

V GE(th)

GE

v GE1

Transfer curve
v CE BV CES
collector

RM

Output characteristics
drain

gate
gate

N-channel IGBT circuit symbols

source

emitter
Copyright by John Wiley & Sons 2003 IGBTs - 5

Blocking (Off) State Operation of IGBT

gate emitter SiO 2 J 3 J 2 N + P N+ N P+ collector Parasitic thyristor Buffer layer (not essential) N +

Ls

J - Unique feature of IGBT 1

Blocking state operation - VGE < VGE(th) Junction J2 is blocking junction - n+ drift region holds depletion layer of blocking junction. Without N+ buffer layer, IGBT has large reverse blocking capability - so-called symmetric IGBT
Copyright by John Wiley & Sons 2003

With N+ buffer layer, junction J1 has small breakdownvoltage and thus IGBT has little reverse blocking capability anti-symmetric IGBT Buffer layer speeds up device turn-off

IGBTs - 6

IGBT On-state Operation

gate emitter N + N +

P
lateral (spreading) resistance

N-

N + + + +

+ + collector + + + +

MOSFET section designed to carry most of the IGBT collector current

emitter N + N P NN + +

gate

On-state VCE(on) = VJ1 + Vdrift + ICRchannel

Hole injection into drift region from J1 minimizes Vdrift.

P+ collector

Copyright by John Wiley & Sons 2003

IGBTs - 7

Approximate Equivalent Circuits for IGBTs

drift region r esist ance

V V drift

J1

Conduction path resulting in thyristor turn-on (IGBT latchup) if current in this path is too large

collector

gate

channel

gate

Approximate equivalent circuit for IGBT valid for normal operating conditions.

Principal (desired) path of collector current

Body region spreading r esist ance

emitter

VCE(on) = VJ1 + Vdrift + IC Rchannel

Copyright by John Wiley & Sons 2003

IGBT equivalent circuit showing transistors comprising the parasitic thyristor.

IGBTs - 8

Static Latchup of IGBTs

lateral (spreading) resistance

J N

gate 3 + emitter N P +

J2 J1

NN + + + + +

P+

collector Conduction paths causing lateral voltage drops and turn-on of parasitic thyristor if current in this path is too large

Lateral voltage drops, if too large, will forward bias junction J3. Parasitic npn BJT will be turned on, thus completing turn-on of parasitic thyristor. Large power dissipation in latchup will destroy IGBT unless terminated quickly. External circuit must terminate latchup - no gate control in latchup.
Copyright by John Wiley & Sons 2003 IGBTs - 9

Dynamic Latchup Mechanism in IGBTs

J 3 + J2 P
lateral (spreading) resistance expansion of depletion region

emitter N +

gate

N N + +

J1

collector

MOSFET section turns off rapidly and depletion layer of junction J2 expands rapidly into N- layer, the base region of the pnp BJT. Expansion of depletion layer reduces base width of pnp BJT and its a increases. More injected holes survive traversal of drift region and become collected at junction J2. Increased pnp BJT collector current increases lateral voltage drop in p-base of npn BJT and latchup soon occurs. Manufacturers usually specify maximum allowable drain current on basis of dynamic latchup.
Copyright by John Wiley & Sons 2003 IGBTs - 10

Internal Capacitances Vs Spec Sheet Capacitances

C gc G C ge C C ce

bridge +V b

C gc

Bridge balanced (Vb=0) Cbridge = C gc = C res

C ies E

C oes E

C ies = C g e + C gc

C oes = C gc + C ce
Copyright by John Wiley & Sons 2003

IGBTs - 11

IGBT Turn-on Waveforms

V GG+ t

Turn-on waveforms for IGBT embedded in a stepdown converter. Very similar to turn-on waveforms of MOSFETs. Contributions to tvf2. Increase in Cge of MOSFET section at low collector-emitter voltages. Slower turn-on of pnp BJT section.

GE

(t)

d(on) Io

i (t) C t t ri V V v CE (t) t fv1 t t fv2

IGBTs - 12

C E(on)

DD

Copyright by John Wiley & Sons 2003

IGBT Turn-off Waveforms

V v GE (t) GE(th ) V GGt

Turn-off waveforms for IGBT embedded in a stepdown converter. Current tailing (tfi2) due to stored charge trapped in drift region (base of pnp BJT) by rapid turn-off of MOSFET section. Shorten tailing interval by either reducing carrier lifetime or by putting N+ buffer layer adjacent to injecting P+ layer at drain. Buffer layer acts as a sink for excess holes otherwise trapped in drift region becasue lifetime in buffer layer can be made small without effecting on-state losses buffer layer thin compared to drift region.
IGBTs - 13

t t d(off) i (t) C t

fi2

MOSFET current BJT current

rv

t fi1

V v (t)

DD t

CE

Copyright by John Wiley & Sons 2003

IGBT Safe Operating Area

i

C -5

Maximum collector-emitter voltages set by breakdown voltage of pnp transistor 2500 v devices available.
sec sec

10 10

-4

FBSOA

DC v i C dv CE re-applied dt 1000 V/ ms 2000 V/ ms RBSOA 3000 V/ m s v CE CE

Maximum collector current set by latchup considerations - 100 A devices can conduct 1000 A for 10 sec and still turn-off via gate control.

Maximum junction temp. = 150 C.

Manufacturer specifies a maximum rate of increase of re-applied collector-emitter voltage in order to avoid latchup.
IGBTs - 14

Copyright by John Wiley & Sons 2003

Development of PSpice IGBT Model

Cm source N + N + Coxs gate Coxd Cgdj

P Ccer Drain-body or base-collector depletion layer N N + Cdsj Rb Cebj +

P+ drain

Cebd

Nonlinear capacitors Cdsj and Ccer due to

Reference - "An Experimentally Verified Nonlinear capacitor Cebj + Cebd due to P+N+ junction IGBT Model Implemented in the MOSFET and PNP BJT are intrinsic (no parasitics) devices SABER Circuit Simulator", Allen R. Nonlinear resistor Rb due to conductivity modulation of N- drain drift region of Hefner, Jr. and Daniel MOSFET portion. M. Diebolt, IEEE Trans. on Power Electronics, Nonlinear capacitor Cgdj due to depletion region of drain-body junction (N P junction). Vol. 9, No. 5, pp. 532542, (Sept., 1994) Circuit model assumes that latchup does not occur and parasitic thyristor does not turn.
Copyright by John Wiley & Sons 2003

N-P

junction depletion layer.

IGBTs - 15

Parameter Estimation for PSpice IGBT Model

Built-in IGBT model requires nine parameter values. Parameters described in Help files of Parts utility program.

Parts utility program guides users through parameter estimation process. IGBT specification sheets provided by manufacturer provide sufficient informaiton for general purpose simulations. Detailed accurate simulations, for example device dissipation studies, may require the user to carefully characterize the selected IGBTs.
Drain Cebj + Cebd Rb Cdsj Cm + Coxs Source
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Cgdj Coxd Gate

Ccer

Built-in model does not model ultrafast IGBTs with buffer layers (punch-through IGBTs) or reverse free-wheeling diodes

PSpice IGBT - Simulation Vs Experiment

0V 1 nF 5V 10 V 15 V 20 V 25 V

Data from IXGH40N60 spec sheet Simulated C GC versus V CE for IXGH40N60 V =0V GE

0.75 nF

0.5 nF

0.25 nF

100 V

200 V

300 V

400 V

500 V

Collector - emitter Voltage

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