INTRODUCTION

SPPECH OPERATED bank locker system

In todays world of technology every one think about comfort like controlling bank locker voice etc this system is Automatic recognition of speech by a machine has been a goal of research for more than four decades and has inspired technological wonders such as the ASIMO (a humanoid) AI!O (an android) robots by "O#$A%

&ith life getting increasingly more demanding' many of us find our plans can change at a moments notice and have a need to be able to change settings in our home whether it is the heating system' telephone system' security system or the ability to choose not to start the washing machine or cooker at a previously chosen start time% Speech (ecognition Machine give you these options and many more including the ability to see and speak to someone at your home front door whilst you are elsewhere%Our aim is to integrate speech recognition into the various consumer electronic devices%!ut an important )uestion is' *&hat do we mean by speech recognition by Machine+,-oice or speech recognition is the ability of a machine or program to receive and interpret dictation' or to understand and carry out spoken commands% .articularly speech recognition machine is a system where the user speaks a command and the machine' upon correctly recogni/ing the command acts appropriately% 0hus the user e1ercises control over the machine using simple voice commands%

PROPOSED SYSTEM
O2( .(O3450 $4A6S &I0" bank locker 5O#0(O66I#7 S8S04M control system For several years, demonstration 'bank locker of the future' have shown control of bank locker devices by voice. There are some obvious benefits. Voice allows hands-free control. This is vital for people who find keyboards difficult or impossible to use, such system provide high security since we need to tarin the system with the users voice only 'Spoken dialogue technology' takes voice control one step further, allowing a system to interact in a step-by-step fashion with a user, asking uestions and responding to the

replies. This makes advanced functionality of multiple, comple!, networked devices much more accessible, not "ust to the technically-minded with the patience to wade through manuals. #t also allows people to phone up their home and access devices remotely, for e!ample to turn on the heating or air conditioning before returning. Voice control and spoken dialogue is starting to become commonplace in cars, not "ust in top-of-range models. So what is the potential in the home, what are the component technologies, and what is needed for it to become e ually commonplace$ The technology 'Speech recognition' is the process of taking a speech signal and converting it into words. The technology has improved steadily, if not spectacularly, over the last few decades, but it is still not possible to accurately convert anyone's voice talking about any sub"ect. The recogniser therefore needs to be trained to one or more specific speakers, i.e. 'speaker-dependent, large vocabulary' recognition, or restricted in the number of words it can recognise, i.e. 'speaker independent, small vocabulary'.

A general model for speech recognition is as shown%

'ser S#eech

Word Recognition Model Dynamic %no&ledge Re#resentation

High Le el Processing

!oice O"t#"t

'ser S#eech

Synta$ Semantics Pragmatics Task Descri#tion

9igure :;:7eneral !lock diagram of speech recognition system%

0he model begins with a user creating a speech signal (speaking) to accomplish a given task% 0he spoken output is first recogni/ed' in that the speech signal is decoded into a series of words that are meaningful according to synta1' semantics and pragmatics according to the conte1t of what it has previously recogni/ed% 0he feedback from high level processing reduces the comple1ity of the recognition model by limiting the search for valid input speech from the user%

0he recognition system responds to the user in the form of voice output or e)uivalently in form of re)uested action being performed' with user being prompted for more input% One of the most difficult aspects of building up speech recognition machine is its interdisciplinary nature% 5onsider the discipline that have been applied to speech recognition% 1. Signal processing< the process of e1tracting relevant information from the speech in an efficient' robust manner ;speech analysis and enhancement% 2. .hysics (acoustics)< the science of understanding the relationship between the physical speech signal and the physiological mechanisms (the human vocal tract mechanism) that produced the speech and with which the speech is perceived % 3. Information 0heory: statistical modeling of speech signals% =% 6inguistics< the relationships between sounds (phonology)' words in a language (synta1)' meaning of spoken words (semantics) and sense derived from meaning % >% .hysiology: understanding of the higher;order mechanisms within the human central nervous system that account for speech production and perception in human beings ;Artificial neural network% ?% 5omputer science: the study of efficient algorithms for implementing' in software or hardware' the various methods used in practical speech recognition systems @% .sychology: the science of understanding the factors that enables a technology to be used by human beings in practical tasks% "owever' in spite of the glamour of designing an intelligent machine that can recogni/e the spoken word and comprehend its meaning' we are far away from achieving the desired goal of a machine that can understand spoken discourse on any subAect by all speakers in all environments%

Chapter 2: LITERATURE SURVEY 2.1 Speech Productio

9igure B%: portrays a medium saggital section of the speech system in which we view the anatomy midway through the upper torso as we look on from the right side C:D% 0he gross components of the system are the lungs' trachea (windpipe)' laryn1 (organ of speech production)' pharyngeal cavity (throat)' oral or buccal cavity (mouth)' and nasal cavity (nose)% In technical discussions' the pharyngeal and oral cavities are usually grouped into one unit

referred to as the vocal tract' and the nasal cavity is often called the nasal tract% Accordingly' the vocal tract begins at the output of the laryn1 (vocal cords' or glottis) and terminates at the input to the lips% 0he nasal tract begins at the velum and ends at the nostrils%

PROBLEM STATEMENT:
banking a##lications like controlling the locker &ith high sec"rity this system &ill be ery m"ch #ro en technology to control the bank locker by a single n"mber locker o#ening In todays world of technology every one think about comfort like controlling bank locker voice etc this system is Automatic recognition of speech by a machine has been a goal of research for more than four decades and has inspired technological wonders

METHODOLOGY:

'sing s#eech control circ"it and microcontroller is the method to ado#t

and to reach the goal o( accessing the locker

!LOC" DIA#RA$ 5onsists of :% B% E% =% >% ?% microphone voice processor microcontroller driver circuit lcd display system power supply

Micro phone is the one type of transducer which converts voice signal to electrical signal% 0hese electrical signals are very small mill voltage signal' so it is given to amplifier circuit% 0he amplifier circuit is constructed with operational amplifier which acts as power amplifier which is inbuilt in the voice recognition ic itself % 0hen the amplifier signal is given to signal conditioning unit which also constructed with operational amplifier% In this circuit operational amplifier act as comparator and

generate the s)uare pulse given to microcontroller% "ere the microcontroller may be Atmel or .I5 both are flash type reprogrammable microcontroller% In microcontroller we have already programmed so it receives the pulse signal from signal conditioning unit and activates the relay driver circuits% $river circuits consists of 0ransistor' it Aust act as switch to turn O#' turn O99 the relays% (elay outputs are directly connected to ant appliances or system or even motors which are attached in the robot%

Locker S+STEM

S&itches

,ROM !O)CE RECO-*)T)O* )C

M)CRO CO*TROLLER

)*D)CATORS

Oscillator Oscillator

POWER S'PPL+

#e era% de&criptio : "$BFF: is a monolithic user dependence speech recognition I5 designed for toy application% "$BFF: consist of microphone amplifier' AG$ converter' speech processor' and IGO controller% After pre;recording' "$BFF: can recogni/e up to @ different &ord sentences each with :%> sec long'% &ith highly IGO .rogrammability% "$BFF: can be adapted in a wide range application for toy products%

DR)!ER

. SE-EME*T D)SPLA+

Mike Mike

!O)CE RECO-*)T)O* )C

DR)!ER

. SE-EME*T D)SPLA+

RAM I troductio to $icro'Co tro%%er ()C*1 POWER S'PPL+

has gained great popularity since its introduction% Its standard form includes several standard on;chip peripherals' including timers' counters' and 2A(0Hs' plus =kbytes of on;chip program memory and :B@ bytes (note< bytes' not Ibytes) of data memory' making single;chip implementations possible% Its hundreds of derivatives' manufactured by several different companies (like .hilips) include even more on;chip peripherals' such as analog;digital converters' pulse;width modulators' IB5 bus interfaces' etc% 5osting only a few dollars per I5' the @F>: is estimated to be used in a large percentage (maybe :GB+) all embedded system products% 0he @F>: memory architecture includes :B@ bytes of data memory that are accessible directly by its instructions% A EB;byte segment of this :B@ byte memory block is bit addressable by a subset of the @F>: instructions' namely the bit;instructions% 41ternal memory of up to ?= Ibytes is accessable by a special Jmov1J instruction% 2p to = Ibytes of program instructions can be stored in the internal memory of the @F>:' or the @F>: can be configured to use up to ?= Ibytes of e1ternal program memory 0he maAority of the @F>:Hs instructions are e1ecuted within :B clock cycles% &e developed a -"$6 synthesi/able model of the @F>: and a 5KK based @F>: instruction;set simulator' both found below' on which weHve based some research directions% One of those directions is a tuning environment' also found below' to assist a designer who wants to modify the @F>: architecture to be more power efficient for a particular program 8ou see' a particular @F>: will probably e1ecute the same program over and over for its lifetime' so it would be nice to orient the @F>: towards that program% &eHve also developed some new architectural features that can be used to lower the power of an @F>:' which will appear on this page in the future% One of the defining characteristics of embedded systems is that they run one application for their entire e1ecution time% 0his characteristic creates a great potential for optimi/ations% 9or e1ample' a general purpose processor might have a datapath consisting of a register file' A62' and a shifter% 9or an instruction such as a move' this

datapath is e1pensive in terms of power because it must pass through the A62 and shifter before being written back into the register file% If this move operation was very common to a particular application' an optimi/ation could be made by modifying the register file to move data from one location to another% 0he information on this page describes an environment that simplifies the process of tuning a microprocessor% 0hree main tools are provided in order to analy/e the power consumption of an @F>: microprocessor% 0he first of these tools is an architectural view which generates a hierarchical display of power consumption throughout the components of the processor% 0he output is formatted so that it is readable by 1du' a graphical program for displaying tree structures% 0he second tool calculates the average power per instruction for the entire instruction set (several Aump instructions have not yet been implemented in this tool)% 0he third tool is an instruction set simulator which outputs a program memory view that displays the instruction' power' and fre)uency for every address% It also provides a data memory view that calculates accesses for each location in ram%

+eature&:

5ompatible with M5S;>: .roducts% =I !ytes of In;System (eprogrammable 9lash Memory% ; 4ndurance< :FFF &riteG4rase 5ycles 9ully Static Operation< F "/ to B= M"/ 0hree;level .rogram Memory 6ock% :B@ 1 @;bit Internal (AM% EB .rogrammable IGO 6ines% 0wo :?;bit 0imersG5ounters% Si1 Interrupt Sources% .rogrammable Serial 5hannel% 6ow;power Idle and .ower;down Modes%

De&criptio :

0he digital output of A$5 is given to the microcontroller (@L5>:)% 0he clock input is also given to the microcontroller for the synchroni/ation% 0he A0@L5>: is low;powerM high performance @;bit microcomputer with =I bytes of flash programmable and erasable read only memory (.4(OM)% 0he device is manufactured using Atmels high density non volatile memory technology and is compatible with the industry standard M5S;>: instruction set and pin out% 0he on;flash allows the program memory to be reprogrammed in system or by a conventional non; volatile memory programmer% !y combining a versatile @;bit 5.2 with flash on a monolithic chip' the Atmel A0@L5>: is a powerful microcomputer which provides a highly fle1ible and cost effective solution to many embedded control application%

Pi De&criptio :

VCC Supply voltage%

#ND 7round%

Port ,:

.ort F is an @;bit open;drain bi;directional IGO port% As an output port each pin can sink @ 006 inputs% &hen :s are written to port F pins' the pins can be used as high impedance inputs%

.ort F may also be configured to be the multiple1ed low;order addressGdata bus during accesses to e1ternal program and data memory% In this mode .F has internal pull;ups% .ort F also receives the code bytes during 9lash .rogramming' and outputs the code bytes during program verification% 41ternal pull;ups are re)uired during program verification%

Port 1:

.ort : is an @;bit bi;directional IGO port with internal pull;ups% 0he port : output buffers can sinkGsource = 006 inputs% &hen :s are written to .ort : pins they are pulled high by the internal pull;ups and can be used as inputs% As inputs' .ort : pins that are e1ternally being pulled by low will source current (II6) because of the internal pull;ups% .ort : also receives the low;order address bytes during 9lash .rogramming and verification%

Port 2:

.ort B is an @;bit bi;directional IGO port with internal pull;ups% 0he .ort B output buffers can sinkGsource = 006 inputs% &hen :s are written to .ort B pins they are pulled high by the internal pull;ups and can be used as inputs% As inputs' .ort B pins that are e1ternally being pulled low will source current (II6) because of the internal pull;ups%

.ort B emits the high;order address byte during fetches from e1ternal program memory and during accesses to e1ternal data memory that use :?;bit address (MO-N O $.0()% In this application' it uses strong internal pull;ups when emitting :s% $uring accesses to e1ternal data memory that use @;bit addresses (MO-N O (:)% .ort B emits the contents of the .B Special 9unction (egister(S9()% .ort B also receives the high;order address bits and some control signals during 9lash .rogramming and verification%

Port -:

.ort E is an @;bit bi;directional IGO port with internal pull;ups% 0he .ort E output buffers can sinkGsource = 006 inputs% &hen :s are

written to .ort E pins they are pulled high by the internal pull;ups and can be used as inputs% As inputs' port E pins that are e1ternally being pulled low will source current (I I6) because of the pull;ups% .ort E also serves the functions of the various features of the A0@L5>: as listed below<

Port Pi .E%F

A%ter ate +u ctio & (N$ (serial input port)

.E%:

0N$ (serial output port) PPPP

.E%B

I#0F (e1ternal interrupt F) PPPP

.E%E .E%= .E%>

I#0: (e1ternal interrupt :) 0F (timer F e1ternal input) 0: (timer : e1ternal input) PPP

.E%?

&( (e1ternal data memory write strobe) PPP

.E%Q

($ (e1ternal data memory read strobe)

RST:

(eset input% A high on this pin for two machine cycles while the oscillator is running resets the device%

ALE.PRO#:

Address 6atch 4nable output pulse for latching the low byte of the address during accesses to e1ternal memory% 0his pin is also the program pulse input (.(O7) during 9lash .rogramming% In normal operation A64 is emitted at a constant rate of :G? the oscillator fre)uency' and may be used for e1ternal timing or clocking purposes% #ote' however' that one A64 pulse is skipped during each access to e1ternal $ata Memory%

If desired' A64 operation can be disabled by setting bit F of S9( location @4"% &ith the bit set' A64 is active only during a MO-N or MO-5 instruction% Otherwise' the pin is weakly pulled high% Setting the A64;disable bit has no effect if the microcontroller is in e1ternal e1ecution mode%

///// PSEN:

.rogram Store 4nable is the read strobe to e1ternal program memory% &hen the A0@L5>: is e1ecuting code from e1ternal program memory' .S4# is activated twice each machine cycle e1cept that two .S4# activation are skipped during each access to e1ternal data memory%

// EA.VPP: PP 41ternal Access 4nable% 4A must be strapped to 7#$ in order to enable the device to fetch code from e1ternal program memory locations starting at FFFF" up to 9999"% #ote however' that if lock bit;: is programmed' 4A will be internally latched on reset% 4A should be strapped to -55 for internal program e1ecutions% 0his pin also receives the :B- programming enable voltage (-..) during flash programming for parts that re)uire :B-olt -..%

0TAL1:

Input to the inverting oscillator amplifier and input to the internal clock operating circuit%

0TAL2:

Output from the inverting oscillator amplifier%

Id%e $ode:

In idle mode' the 5.2 puts itself to sleep while all the non;chip peripheral remain active% the mode is invoked by software% 0he content of the on;chip (AM and all the S9( remain unchanged during this mode% 0he idle mode can be terminated by any enabled interrupt or by a hardware reset% It should be noted that when idle s terminated by a hardware reset the device normally resumes program e1ecutions' from where it left off' up to two machine cycles before the internal reset algorithm takes control% On;chip hardware inhibits access to internal (AM in this event' but access to the port pins is not inhibited% 0o eliminate the possibility of an une1pected write to a port pin when idle is terminated by reset the instruction following the one that invokes idle should not be one that writes to a port pin or to an e1ternal memory%

Po1er'do1 $ode:

In the power;down mod' the oscillator is stopped' and the instruction that invokes power; down is the last instruction e1ecuted% 0he on;chip (AM and S9( retain their values until the power;down mode is terminated% 0he only e1it from power;down is the hardware reset% (eset redefines the S9(s but does not change the on;chip (AM% 0he reset should not be activated before -55 is restored to its

normal operating level and must be held active long enough to allow the oscillator to restart and stabili/e%

Pro2ra3 $e3or4 Loc5 !it&:

On the chip are three lock bits which can be left unprogrammed (2) or can be programmed (.) to obtain the additional features listed in the table below% &hen lock bit : is programmed' the logic level at the 4A pin is sampled and latched during reset% If the device is powered up without a reset' the latch initiali/es to a random value' and holds the value until reset is activated% It is necessary that the latched value of 4A be in agreement with the current logic level at that pin in order for the device for the device to function properly%

Speech Reco2 itio Tech i6ue&

!roadly speaking there are three approaches to speech recognition namely CED

Acoustic .honetic approach% .attern (ecognition approach% Artificial Intelligence%

RAM/ 0102 is a memory &hich &ill store the S#eech Reco )n Ram Location

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PA#E NO : 78

TITLE

AUT9OR

9undamentals of Micro R processors and Micro R computers

SS

! % (am

Micro R processor Architecture .rogramming Applications

SS

( % 7aonkar

.rinted 5ircuit !oard $esign

0echnology

SS

& % !ossart

Micro R processor $ata "and !ook !.! .ublications

SS

;;;;;;

Micro R processor :

SS

!orole

C:D (abiner' *9undamentals of speech recognition,' >F;>E' chp B in 0he Speech Signal' .earson 4dition' BFF>%

CBD 3%6 9langan',Speech Analysis' Synthesis and .erception' Bnd ed% Springer;-erlag' #8' :LQB%

CED (abiner' *9undamentals of speech recognition,' Q@;@:' 5hp B in 0he speech signal' .earson 4dition' BFF>%