LABORATORY 3 : SIMULATION OF AN OPERATIONAL AMPLIFIER

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Laboratory 3 : Simulation of an operational amplier

During this laboratory you will verify that a two-stage operational amplier is correctly designed. The amplier is used in the non-inverting conguration shown in g.8. Capacitors C1 and C2 implement a capacitive feedback, typical of SCcircuits; R1 is used in closed-loop simulations to provide a DC-feedback for the amplier. The following data are of interest when simulating the amplier:

the bias point

the loop gain, T f b a s the phase margin, m

the unity-gain frequency of the loop gain, 0 6 the closed-loop transfer function, V V A s out in the slew rate, SR
The bias point is studied with the help of DC-analysis. fb A s , 0 and m are measured in an open-loop linearized frequency (AC) simulation, with the positive input signal connected to a DC voltage 7 and an AC-voltage source connected to the negative input. Since in AC simulations only the linearized models of the components at a certain bias point are used, non-linear phenomena like distortion, clipping, and slewing can not be captured with AC simulation. The value of AC magnitude in the AC source denition only works as a scaling factor. SR is best measured with a closed-loop transient simulation. A step of 0.5V is applied at the input (pay attention to the DC-level and the vpulse source voltages), and a transient analysis is performed.

Homework
Read through the manual for this laboratory, including the design example, and read relevant sections of the text book or other sources. Work on the schematic as
this manual fb is used instead of f as used in the book (e.g. section 8.1). a(s) is the open-loop amplier gain, A(s) is the closed-loop gain. 6 See e.g. g. 9.9 in the textbook 7 If the amplier is supplied with 0V and 1.2V, a signal ground at around 0.6V would be suitable. However, this DC voltage also sets the common node voltage at the drain of Q5 ; Thus, it is more suitable to choose VDC = 0.5 V so Q5 operates in saturation.
5 In

LABORATORY 3 : SIMULATION OF AN OPERATIONAL AMPLIFIER

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much as possible before the lab; This will save you time. Answer the questions below: Twostage Operational Amplier 1. Give the equation for the gain A(s) in a non-inverting feedback amplier with capacitive feedback (see g.8), and show that A s = 2 for C1 C2 . 2. Draw a schematic of the twostage amplier, as in g. 10. Follow the design example and calculate all bias currents and device sizes. Make sure the following specications are met: Vout Vin A s 2 (in-band) 2 18 106 rad/s 3dB CL SR 25 V s m > 60 For the capacitors in the loop and the load, the following specication can be used: CL 2pF, C1 C2 2pF. Choose Q16 so that the zero introduced by CC is at innity, and choose CC to be 1pF, 2pF, or 3pF. The supply voltage VDD 1 2V . 3. What is the order of magnitude of the input offset voltage, and how does it impact open-loop simulations and measurements? 4. How can the loop gain be measured? Indicate this in g. 9.

Laboratory Exercises
Twostage Operational Amplier 1. Create a cell with the necessary views for the twostage amplier you designed in the homework exercise (g. 10). Pick the compensation capacitor,

R1 C2 C1

Vout Vin CL

Figure 8: Non-inverting amplier.

LABORATORY 3 : SIMULATION OF AN OPERATIONAL AMPLIFIER

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Figure 9: Open loop conguration. MIMCAPS_MML130E, from the library umc130nmrfE. For the transistors use P_12_MML130E and N_12_MML130E. For the capacitors C 1 , C2 and CL capacitors from the library analogLib can be used. 2. Prepare for open-loop simulations by building a suitable test bench (g. 9). Start with a DC-analysis to study the bias points and measure the DC-offset voltage of the input of the amplier. Connect a DC voltage source, vdc from AnalogLib, between the inputs and dene the DC voltage as variable Voffset. Sweep this voltage in a small range until the output reaches 0.5V (see footnote 7): Set up for DC analysis (DC) (Analyses > Choose ...). Choose Task: sweep, press Select variable and choose Voffset. Dont forget to select Enabled. Set up relevant Probes (see Lab 2). 3. Examine the result by choosing Results > GoldenGate Results > opamp_open_tb_DC. In the DC Analysis Result window, choose Plot type waveform Probes Vout Plot mode Append Then click Plot. The x axis variable should be Voffset. It may be necessary to perform several sweeps in order to nd a precise enough value.

LABORATORY 3 : SIMULATION OF AN OPERATIONAL AMPLIFIER

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Figure 10: Twostage operational amplier. Do the simulated I5 , I7 , gm1 2 , and gm7 match the calculated values? Adjust the dimensions of the transistors if needed. 4. Verify your design by measuring f b a s , 0 and m with an AC measurement. Change your test bench and connect the earlier simulated offset voltage between the inputs. Set AC Magnitude to 1V and sweep between 10 Hz and 1 GHz. With the command Modify > Mag or Phase in the AC Analysis Results window you can get a pair of curves from which these data can be extracted. 5. Make a new closed-loop test bench. Close the feedback loop (g. 11) and nd A s . 6. Now apply a symmetrical 0.5V input step, and check the value of SR with a transient analysis. Use vpulse from the library AnalogLib. 7. Increase and decrease the capacitive load by a factor of 10 and repeat the transient analysis. What happens to the output?

Laboratory Report
Compose a report containing the difference of calculated and simulated values. Include the values of f b a s , 0 , m , A s , and SR. The report should also answer the questions in the homework section, and explain the results. Add plots of the interesting curves.

LABORATORY 3 : SIMULATION OF AN OPERATIONAL AMPLIFIER

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Figure 11: Closed loop conguration.

LABORATORY 3: DESIGN EXAMPLE

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Laboratory 3: Design example

Below an approach is given to design a two-stage operational amplier. Besides the text book by Gray, Hurst, Lewis and Meyer ("Analysis and Design of Analog Integrated Circuits"), other useful references are:

D. A. Johns and K. Martin: "Analog Integrated Circuit Design", John Wiley

& Sons, 1997, chapter 5.

B. Razavi: "Design of Analog CMOS Integrated Circuits", McGraw-Hill,

2001.

Design of a two-stage operational amplier

For the design example below, the body effect is partly ignored, and it is assumed that VDS 1. Long-channel approximations are used. The specications for the closed-loop circuit of g. 12 are the following: 8

A s
2 in  band 0
3dB CL

SR 30 V s m 70 R1 100 M
8 Note:

2  19  106 rad s

CL 1 5 pF C1 C2 1 pF
The specications and resulting values are different from the laboratory assignment.

R1 C2 C1

Vout Vin CL

Figure 12: Non-inverting amplier.

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We start by choosing CC 2 pF , which is approximately the same value as the total capacitance between the opamp output and ground. First, let us look at the current levels in the stages. The slew-rate specications determine the value of the currents in both the input and output stage: If the rst stage is limiting the slew rate, we have SR I5 CC and if the second stage is limiting the slew rate we have SR I7 CC  CL  C1  C2 . And thus: I5 SRCC 30 V s  2 pF 60A I7 SR CC  CL  C1  C2
120A Second, the transconductances are determined by bandwidth, gain and phase margin considerations. For a compensated opamp we can use Eq. 9.47 in the text book, combined with the schematic in g. 10: p1  p2  1 gm7 R2 R1CC

g m7 Cgs7  CL  C1    C2 1 p3  R16Cgs7

1 gm7

1  R16 CC

In the above equations some parts have been neglected such as transistor parasitic capacitance other than Cgs . Resistances R1 and R2 are given by: R1 ro2  ro4 R2 ro6  ro7 and R16 is the resistance of Q16 in the linear region (eq. 2.53): R16 L16 1  W16 kn  VGS16  Vt  VDS16

The opamp should be designed so that the open loop -3dB bandwidth is mainly determined by the rst pole. The third pole is usually at such high frequencies that it can be neglected, and the zero should be put at innity by designing Q 16 right.

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The transconductances of the input differential pair, g m1 2 are related to the GainBandwidth product (GWB, or unity-gain frequency, see eq. 9.49) of the open-loop opamp by the equality GBW  Hz a0 f p1 as well as GBW  A0 0  2 g m1 2 1 CC 2 1 0 fb 2

(combine Fig. 9.2, Eq. 9.47a and 9.50 in the book). Thus, g m1 2 0CC fb 2  19  106 2  10 0 5

12

 480S

Now we can nd the dimensions of Q1 2 :

W L 1 2 

g2 m1 2 2k p I5 2

480 2 38 2  100  10 6  60  10 6 2

This can be rounded off to W L 1 2  40. The phase margin 9 is impacted by the second pole: m 0
180  arctan

0  arctan 0 p1 p2

Thus, for a phase margin of at least 70 we need to place p2 at least at 30 . We can now derive a relation for gm7 . Using the above equation for p2 , and assuming that Cgs7 is in the range of 100fF, we can derive that gm7 30 Cgs7  CL  C1    C2
3  2  20  106  2 2  10 We can now nd the dimensions of Q7 :

12

750 S

W L

g2 m7 2kn  I7

750 2 2  400  10 6  120cdot 10

 6

This is quite a small ratio, and we can afford to increase the above ratios (rather arbitrarily), without loading the output of the differential stage too much: W L 7 50. The new value for gm7 becomes 2 2 mS. This will also increase the phase margin.
phase margin is dened as the phase compared to loop gain  T  j0   is 1.
9 The

180  for the frequency 0 where the

LABORATORY 3: DESIGN EXAMPLE

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Since the mirror-load transistor pair Q 3  Q4 ideally has the same gate-source voltage as Q7 , we can write the relation (see also Eq. 6.62, 6.63 in the textbook):

from which it follows that

W L 7 W L 3 4

I7 I5 2

W L 3 4

I5 2 30  10 6 W L 7 50  12 5 I7 120  10 6

Q16 is working in the linear region, so we easily can implement a resistance of suitable value.10 Now that we know the dimensions of Q7 , we set Ron1 16 gm7 In the linear region, we have 11 (see Eq. 2.53 in the textbook)

 W L Ron1 16 kn
Note that VS16 VG7 Vt 7 

16

VGS16  Vt 16 

2I7  W L kn

0 3  0 11 0 41 V "! !

With VG16 =1.2 V we get VGS16 =0.79 V. Moreover, Vt 16 Vt 0n  Thus,

2 f n  VS16 

2 f n  0 3  0 58

0 7  0 41 

0 7  0 43V

W L

16

kn  VGS16  Vt 16

g m7

2 2  10 3 15 400  10 6 0 79  0 43

Finally, the current sources Q5 and Q6 can be made so large that they require a small gate overdrive Vov . If we set Vov to 0 14 V , we obtain

and

W L

2I5 60 2 k pVov 2I7 120 2 k pVov

W L

16 is made somewhat larger), in order to increase the phase margin. This is easier to do after simulating the transfer function of the amplier, since the location of the zero depends on the position of the non-dominant poles/zeros. 11V DS16 is ignored; We assume a small AC signal.

10 Alternatively, the zero can be positioned at a nite frequency (i.e., R

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For convenience we choose W L 8 = W L 5 and Ibias =I5 . As usual, it is good practice to choose transistor lengths and widths (much) larger then the smallest allowed by the process, since in this way we obtain a better match between transistors, and the transistors behave more in accordance with the long-channel approximation. A possible choice is a common length of 0 5 m, resulting in the following dimensions: Transistor Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q16 W 20 20 6 6 30 60 25 30 7 5 L 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5

Now we can try to estimate the dc-gain of the opamp: ao gm1 2 ro2    ro4 # gm7 ro6    ro7  From the book (Eq. 1.163, 1.164 and 1.194) we see that ro dXd dVDS

1L ef f
ID

where the effective transistor length L e f f = L - 2Ld - 2Xd . Thus, ro2 ro4 ro6 ro7 and thus ao

6 6 1 0 485  10 0 04  10  30  10 6 6 6 1 0 485  10 0 08  10  30  10 6 6 6 1 0 485  10 0 04  10  120  10 6 6 6 1 0 485  10  0 08  10 120  10 6

404k 202k 101k 51k

480  10

6  135  103 2 2  10 3  34  103 $ 4 8  103