ELEC 518: RF/Microwave Circuit Design and Measurement

Lab3: Amplifier Design, Part II

1.0 Overview The third laboratory introduces the design of a low-noise amplifier (LNA) with low noise figure and high transducer gain at frequencies between 2 GHz and 4 GHz. Given a GaAs FET transistor, matching networks are designed to fulfill the design specification. Simulation and measurement are involved to verify the LNA design.

2.0 Design Specifications

Group# 1,6 2,7 3,8 4,9 5,10 Low-noise amplifier specifications 2-2.5GHz, S21>10dB, NF<1.6dB optimize S11 2.5-3GHz, S21>9dB, NF<1.7dB optimize S21 2-3GHz, S21>9dB, NF<1.8dB optimize NF 3-3.5GHz, S21>8dB, NF<1.9dB optimize S11 3.5-4GHz, S21>7dB, NF<2dB optimize S21

3.0 Design You will design a low-noise amplifier using transmission line matching techniques. The design will properly check stability, noise and gain considerations jointly. 1. Get your groups amplifier specification from above Table. Pay special attention to the last part of your specification, which tells you what to optimize. The lownoise amplifier shown in Figure 1 consists of a NE76184AS GaAs FET transistor for power amplification, input and output matching networks to meet both the noise figure and transducer-gain design specification, and 2 dc-decoupling capacitors to isolate dc bias of the amplifier from the outside world. In addition, input and output biasing networks implemented by microstrip lines are adopted to provide dc bias of gate and drain of the GaAs FET, and also provide ac open to the amplifier at the design frequency range.

Figure 1. Architecture of the low-noise amplifier LNA.

2. DC simulation You can choose either bias current of 10mA or 30mA, but once youve made the decision, stick with it.

Figure 2. An example of schematic for DC simulation.

3. DC biasing network To provide gate and drain bias of the transistor, biasing network shown in Figure 3 is adopted. The biasing network consists of a /4-open stub; a /4-short stub and several bypass capacitors. Perform simulation in ADS. ? mil Open stub

Short stub

mil

Figure 3. Implementation of the bias network

4. FET modeling (for I = 30mA) For the GaAs FET transistor NE76184AS, its scattering and noise-figure parameters are provided in data sheet. However, from the measurement results of the transistor, additional inductors are added to all the terminals of the transistor as shown in Figure 4. This model also includes the effect of vias which connect the two source leads of transistor to ground plate.

Figure 4. Modified model for the GaAs FET transistor NE76184AS.

5. Perform stability, gain and noise analysis on the NE76184AS for all frequencies.
S-PARAMETERS
S_Param SP1 Start=4 GHz Stop=5 GHz Step=200 MHz CalcNoise=yes Term Term1 Num=1 Z=50 Ohm
GaCircle NsCircle

GaCircle GaCircle1 GaCircle1=ga_circle(S,10,51)

NsCircle NsCircle1 NsCircle1=ns_circle(2,NFmin,Sopt,Rn/50,51) Term Term2 Num=2 Z=50 Ohm

sp_nec_NE76184A_1_19940401 SNP1 Bias="Fet: Vds=3V Ids=10mA" Frequency="{0.10 - 18.00} GHz" Noise Frequency="{1.00 - 12.00} GHz"

Figure 5. An example of schematic in ADS simulation 6. Output matching network For a low-noise amplifier, noise figure is the most critical parameter and it can be expressed as follows
NF = NFmin + s + opt 4 RN Z 0 (1 s 2 ) 1 + opt

(1)

where opt is optimal source reflection coefficient and RN is equivalent noise resistance of transistor. Equation (1) shows that input-matching network is more critical for low noise design. To simplify the LNA design, the LNA output is * . designed with conjugate matched, i.e. L = out 7. Input matching network Follow the design example in textbook and design an LNA which meets your specifications. Finally, the whole circuit included all parasitics (as far as possible) is simulation with the optimization function in ADS again. 8. Layout the circuit in ADS. The whole amplifier is to be fabricated on a PCB. The pads for de-decouple capacitors are drawn according to the packages and they are put very close to minimize parasitics. Between the LNA and SMA connector, a ~400-mil microstrip line is included for connector soldering. The gate and drain biasing networks are separated as far as possible to reduce coupling in between. To

provide a wide band ac ground to the input terminal of the gate and drain bias of GaAs FET transistor, several by-pass capacitors are connected in parallel.

Figure 6. An example of PCB layout (* the FET lead is only 1mm long) 9. Build and measure the circuit in lab, focusing on learning noise figure measurements. 10. Verify and optimize circuit behavior in the lab. Notes: DC bias network -Use microstrip line because at high frequency, the lumped elements will be bypassed -Use Transmission line 4
z in (d ) = z o z L + jz o tan d 2 where = z o + jz L tan d

For z L = (o.c), z in = jz o cot d if d = , z in = 0 4 But l is dependent, therefore, at a frequency range, not exactly zero. Therefore, for short, we want z o to be small to reduce the offset. Target: 15, by increase W, but W cannot be large otherwise no longer a ML. For z L = 0 , z in = jz o tan d if d = , z in = 4 Therefore, we want z o to increase by decrease W (practical limit exist). Target=100, W~ 25mil