TLE6270 Data Sheet and App Note

Data Sheet, V1.
3, December 2008
TLE6270R
Quad Low Side Injector Driver
Automotive Power
TLE6270R Quad Low Side Injector Driver

Table of Contents
Table of Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 4 4
2 3 3.1 3.2 4 4.1 4.2 4.3 5 5.1 5.2 5.3 5.4 5.4.1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of Functionalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Control Configurations according to NON and Pch Signals . . . . . . . . . . . . . . . . . . . . . . Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Failures Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF State open load Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF State Overvoltage Functionality: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS Diag Filter Functionality: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Control Circuit Functionality: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCn/OLn Definition Circuit Table: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Failures Information (via SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Failure Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Coder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Coder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDO Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . All Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T1, T4 Power Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Control Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic and Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 12 13 14 15 16 16 16 16 17 17 17 17 18 19 19 20 21 21 21 21 22 22 22 23 25 26 26 27
5.4.2
5.5 5.5.1 5.5.2 5.6 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 7.1 7.2
Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Typical Laws . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Output Timings Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Sheet
V1.3, 2008-12-23

Table of Contents 8 8.1 8.2 9 10 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Principle Diagram of Injection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Typical Waveform Diagrams for One and Two Outputs Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Green Product (RoHS compliant) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Data Sheet
V1.3, 2008-12-23
Quad Low Side Injector Driver
TLE6270R
1
Features
Overview
Four integrated Low Side Switches, control logic and -outputs for external High Side Switches Programmable Peak and Hold output current control to adapt to application requirements. Detailed diagnostic of defective or missing injector connections Serial Peripheral Interface (SPI) for diagnostics and control of the device Short Circuit-, ESD and Overtemperature Protection Undervoltage Reset Green Product (RoHs compliant) AEC Qualified
PG-DSO-36
Application Gasoline Direct Injection
General Description TLE6270R is specially suited for Gasoline Direct Injection Systems in Automotive Applications. The device controls the external High Side Transistors to supply the injectors alternating with battery Voltage and a boosted high voltage according the requirement of the applied injectors. The device incorporates the Low Side driver Transistors for four Injector Channels. Product Summary Parameter Output channels Continuous output voltage max. Clamping voltage typ. Peak current typ. Hold current typ. On resistance max. at 150 C Symbol Value 4 80 87 11.50 2.30 300 Unit V V A A m
VOUT VCLP IP_C IH RON
Type TLE6270R Data Sheet
Package PG-DSO-36 4
Marking TLE6270R V1.3, 2008-12-23

Overview
80V Batt
5 K 5V
HS diagnosis circuitry
Loads
5 K
HS diagnosis circuitry
Loads
Bank A Inputs
Bank B
Micro controller
SPI Reset
TLE 6270 R
External oscillator Programming resistors

Figure 1 Application Diagram
Data Sheet
V1.3, 2008-12-23

Block Diagram
Block Diagram
Vcc
5V
NRES
OUT1A
5V
OUT4A
5V
OUT1B
5V
OUT4B
5V
5V
UNDER VOLTAGE RESET
RST
5V
NON1A NON4A PChA
5V
CTL4A
T1_A
5V
T4_A
T1_B
T4_B
CTL1A
GROUP_A POWER SWITCHES CONTROL including FAILURES PROTECTION
NCTL2A NCTL3A Pgr_IPC Pgr_IP Pgr_IH
PEAK
OVER TEMP.
OVER TEMP.
OVER TEMP.
OVER TEMP.
HOLDx
RST
HS_DiagA
5V
GROUP_A FAILURES DETECTION
CLK SDI SDO
5V
SPI INTERFACE for FAILURES INFORMAT

5V
DIAGNOSTIC CONTROL
OSCILLATOR
NCS
GROUP_B FAILURES DETECTION
HS_DiagB
5V
NON1B NON4B PChB NCTL2B NCTL3B
CTL4B
5V
5V
CTL1B
GROUP_B POWER SWITCHES CONTROL including FAILURES PROTECTION
PEAK
HOLDx
RST
Logic blocks OSC block
LP_GND
OSC1
OSC2
GND1A
GND4A
GND1B
GND4B
Figure 2 Data Sheet
Block Diagram 6 V1.3, 2008-12-23

Pin Configuration
3
3.1
Pin Configuration
Pin Assignment
GND OUT 1A OUT 1A Pgr_IH NCTL 2A NCTL 3A Vcc Pgr_IPC Pgr_IP LP_GND OSC 1 OSC 2 NCTL 3B NCTL 2B NON 1B OUT 1B OUT 1B GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
GND OUT 4A OUT 4A NON 4A PCh A HS_Diag A NON 1A NCS CLK SDI SDO NRES HS_Diag B PCh B NON 4B OUT 4B OUT 4B GND
Figure 3
Pin Configuration P-DSO-36
Data Sheet
V1.3, 2008-12-23

Pin Configuration
3.2
Pin 7 10 1 18 19 36 2 3 34 35 16 17 20 21 30 33 15 22 32 23 8 9 4 5 6 14 13 31 24 25 27 26 28 29 11 12
Pin Definitions and Functions

Symbol Function 5 V Power Supply Low Power Ground High Power Ground High Power Ground High Power Ground High Power Ground OUTPUT channel 1A OUTPUT channel 1A OUTPUT channel 4A OUTPUT channel 4A OUTPUT channel 1B OUTPUT channel 1B OUTPUT channel 4B OUTPUT channel 4B Control input channel 1A Control input channel 4A Control input channel 1B Control input channel 4B Pre-charge input group A Pre-charge input group B IPC programming input1) IP programming input IH programming input Control output high side 2A Control output high side 3A Control output high side 2B Control output high side 3B High side diagnostic input A High side diagnostic input B Reset input Serial Data Input Serial Data Output Clock input for serial interface Chip-select input External resonator input External resonator output Note: Has to be connected to GND on the PCB
VCC
LPGND GND GND GND GND OUT1A OUT1A OUT4A OUT4A OUT1B OUT1B OUT4B OUT4B NON1A NON4A NON1B NON4B PChA PChB Pgr_IPC Pgr_IP Pgr_IH NCTL2A NCTL3A NCTL2B NCTL3B HS_Diag A HS_Diag B NRES SDI SDO CLK NCS OSC1 OSC2 Case
1) If there is no pre-charge resistor this pin has to be connected to VCC on the PCB
Data Sheet
V1.3, 2008-12-23

General Product Characteristics
4
4.1

Absolute Maximum Ratings
Absolute Maximum Ratings 1) TJ = -40 C to +150 C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. 4.1.1 Outputs 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 Continuous output voltage Continuous output current, one output active Peak output current Clamping energy repetitive pulse Clamping energy single pulse Continuous voltage Parameter Supply voltage Symbol Limit Values Min. Max. 7 80 5 20 30 130 7 V V A A mJ mJ V see Chapter 5.5 all T, see Figure 4 all T, see Figure 4 -0.3 -1.5 -5 -10 -0.3 Unit Conditions
VCC VOUT IOUTC IOUTP WOFFr WOFFs VIN
Inputs and NCTL, SDO outputs All pins ESD Susceptibility 4.1.8 Electrostatic discharge
VESD
-2000
2000
R = 1.5 k; C = 100 pF;

HBM2)
Operating Range 4.1.9 4.1.10 Operating Temperature Range Storage Temperature Range
TJ TJ
-40 -55
150 150
C C
1) 1)
1) Not subject to production test, specified by design. 2) ESD susceptibility, HBM according to EIA/JESD 22-A114B
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as outside normal operating range. Protection functions are not designed for continuous repetitive operation.
P 100ns 240 W 90% f=1 kHz
520 W 90% P 100ns
10% 250 us t
10% 500 us t
Figure 4 Data Sheet
Energy Repetitive Pulse and Energy Single Pulse 9 V1.3, 2008-12-23

4.2
Pos. 4.2.1 4.2.2
Functional Range
Parameter Supply voltage Junction temperature continuous Symbol Min. Limit Values Max. 5.5 150 V C Permanent operation 4.5 -40 Unit Conditions
VS Tj1
Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Pos. 4.3.1 Parameter Junction to Case
1)
Symbol Min.
Limit Values Typ. Max. 2
Unit K/W
Conditions
RthJC
1) Not subject to production test, specified by design.
Data Sheet
10
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Functional Description
5
5.1

List of Functionalities
The device performs the following functionalities: Load control 4 low side power transistors driven by 4 parallel CMOS compatible inputs. Output current control output current comparators and logic circuit to generate high side switches control signals NCTL2 and NCTL3. current thresholds programmable by external resistor. Diagnostic of defective or missing injector connections and overtemperature comparators and logic circuit to interpret unexpected current, voltages and HSDiag input status as short circuit or disconnection of the injector. 4 thermal sensors for independent overtemperature detection on the 4 channels. Protection all inputs/outputs: protection against ESD (all input and output pins) T1, T4, internal power transistors: protection against overvoltage and Transients (Schaffner test pulses) external transistors connected via NCTL2 and CLT3: protection against overvoltage and Transients (Schaffner test pulses) Reset external reset (reset pin) internal reset (undervoltage reset) Electro Magnetic Compatibility (EMC)
These functionalities are described in the next chapters.
5.2
Load Control
Each output transistor is switched on and off by an individual control signal (NON input). In normal operation, when NON is low, the transistor is ON and when NON is high the transistor is OFF. Also after power up, the outputs must have the status defined by the NON input. The logic level of the input is CMOS compatible. As there is an internal pull-up, the output transistor is switched off when the input is not connected. It is possible to drive two separate loads simultaneously as far as they do not belong to the same bank.
Data Sheet
11
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5.3
Output Current Control
From the output current comparators and inputs signals, a logic circuit controls the 4 current levels IPC, IP, IH and ID by commanding the high side drivers T2 and T3 via NCTL2 and NCTL3 (see Chapter 8). T2 and T3 are OFF when NCTL2 and NCTL3 are at high level. IPC level is controlled between high and low values IPC value can be programmed through Pgr_IPC pin IP level the transition from IPC to IP is controlled by PCh pin IP value can be programmed through Pgr_IP pin IH level is controlled between high and low values the transition from IP to IH starts when peak level is reached IH value can be programmed through Pgr_IH pin ID level is controlled between high and low values. ID is equal to IH. the transition from IH to ID is controlled by NON1 or NON4 and PCh pins the damp pulse is not present if there is no damp pulse command at NON1/4 Currents values according to programming resistors (see also graph in Chapter 7) R_Pgr_IP = kP / IP R_Pgr_IPC = kPC / IPC R_Pgr_IH = kH / IH
The theoretical Design calculation leads to kP = 140000 = 8 kPC = 4 kH. Note: If Pgr_IPC pin has no resistor and is connected to VCC then there is no pre-charge and no damping. Then the Pch signal is not used and the output is controlled directly by the NON input.
Data Sheet
12
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Functional Description Current Control Configurations according to NON and Pch Signals
NON PCh
IOUT
Figure 5
Pre-charge Peak Hold Damp

NON PCh
IOUT
Figure 6
Peak Hold Damp

NON PCh
IOUT
Figure 7
Pre-charge Peak Hold

NON PCh
IOUT
Figure 8
Peak - Hold
NON PCh
IOUT
Figure 9 Data Sheet
Peak - Hold, if Pgr_IPC pin has no resistor and is connected to VCC 13 V1.3, 2008-12-23

5.4
Diagnostic
The TLE6270R detects too high output current and too short or too long time to reach the peak current in ON state, too high output voltage in OFF state. It is also informed of too high current in the high side transistors via the HS_Diag pin. According to these comparator outputs and the NON signals, a logic circuit defines the failures (failure detection). When the failure is dangerous for the ECU, the engine management system, the vehicle or the car driver, all transistors T1, T2, T3, T4 are immediately switched off for protection (failure protection). Then, for limp home and for repairing, the failures are read by the microcontroller via SPI (failure information).
GROUP_A FAILURES PROTECTION
SDI
GROUP_A FAILURES DETECTION
overcurrent 1A & 4A overtemperature 1A & 4A HS_DiagA pin peak current overtime 1A & 4A VOL 1A & 4A
CLK
SPI INTERFACE for FAILURES INFORMAT
overcurrent 1B & 4B
GROUP_B FAILURES DETECTION
overtemperature 1B & 4B HS_DiagB pin peak current overtime 1B & 4B VOL 1B & 4B
SDO
SDO driver
NCS
GROUP_B FAILURES PROTECTION
IN1 (NON1 inverted)

DIAGNOSTIC CONTROL
IN4 (NON4 inverted)
RST
Figure 10
Diagnostic Schematic
Data Sheet
14
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5.4.1
Failures Detection
For information only: Table 1 describes for each problem the detection mode and the failure detected (for exact detail, see Table 2). Table 1 Connector Point HS Failures Detection Problem HS short to battery HS short to ground HS open circuit LS1 LS1 short to battery T1 overtemperature LS1 short to ground LS1 short to HS LS1 open circuit LS4 LS4 short to battery T4 overtemp LS4 short to ground LS4 short to HS LS4 open circuit Failure Detection Mode Failures Detected
HS_Diag L H or OUT1/4 peak current overtime INJ1_SC and INJ4_SC HS_Diag L H or OUT1/4 peak current overtime INJ1_SC and INJ4_SC peak overtime and OUT1/4 OFF overvoltage OUT1 overcurrent OUT1 overtemperature HS_Diag L H or OUT1 peak current overtime OUT1 overcurrent or peak current undertime peak overtime and OUT1 OFF overvoltage OUT4 overcurrent OUT4 overtemperature HS_Diag L H or OUT4 peak current overtime OUT4 overcurrent or peak current undertime peak overtime and OUT4 OFF overvoltage INJ1_OL and INJ4_OL INJ1_SC INJ1_SC INJ1_SC INJ1_SC INJ1_OL INJ4_SC INJ4_SC INJ4_SC INJ4_SC INJ4_OL
IN1 IN4 IN1 + IN4 OUT1 overcurrent, OUT1 overtemp, HS_Diag L->H Peak current1 undertime => X1problem memory
Peak current1 overtime => Y1 problem memory
DIAGNOSTIC CONTROL tOL OFF state overvoltage

=> Z1 problem memory
Z1 Y1 X1 SC/OL definition circuit SC1 OL1 SPI
Figure 11
Diagram of INJ1 Failures Detection
Data Sheet
15
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Functional Description OFF State open load Functionality The TLE6270GR is able to detect a missing load in OFF-state using a pull-up resistor connected at the output when the both outputs of the correspoding bank are turned off. For the correct functionality of this feature a 5K resistor has to be connected in parallel with the freewheeling diode of each bank. OFF State Overvoltage Functionality: Comparator: There is one comparator for two channels. A low level on the comparator output (called VOFF) means no failure. The voltage on OUT1 (resp. OUT4) is checked at the OFF state between OUT1 and OUT4 ON states (resp. between OUT4 and OUT1 ON states). Filter time: For OUT1 (resp. OUT4), the filter time starts: at H L transition on IN1 (resp. IN4) if VOFF is high when this first filter time is finished at every L H transition on VOFF
HS Diag Filter Functionality:
Min. 50ns, max .250ns
Figure 12
HS Diag Filter Functionality (optionally only one out of NCTL2 or NCTL3 can be on at the same time)
Diagnostic Control Circuit Functionality: The SC1 (resp.4) and OL1 (resp.4) failures are transferred in the SPI on IN1 and IN4 positive edges. Just after, the X1, Y1, Z1 (resp. X4, Y4, Z4) problem memories are reset.
Data Sheet
16
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Functional Description SCn/OLn Definition Circuit Table: Table 2 SC/OL Definition Circuit Memories Xn 0 0 0 0 1 1 1 1 Yn 0 0 1 1 0 0 1 1 Zn 0 1 0 1 0 1 0 1 SCn 0 0 1 0 1 1 1 1 Failures OLn 0 0 0 1 0 0 0 0 valid for n=1 or n=4
5.4.2
Failures Information (via SPI)
The failures detected are communicated to the microcontroller via a Serial/Peripheral Interface (SPI) in order to minimize the pin number. The SPI contains a failure register, a coder, a shift register, and a SDO driver:
INJ1A_SC_stored
INJ1A_SC INJ1A_OL INJ4A_SC
CLK SDI SDO

SDO DRIVER
D7 D6 D5
INJ1A_OL_stored INJ4A_SC_stored INJ4A_OL_stored
SHIFT REGISTER
D4 D3 D2 D1 D0 FSL
CODER
INJ1B_SC_stored INJ1B_OL_stored INJ4B_SC_stored INJ4B_OL_stored
FAILURE REGISTER
INJ4A_OL
INJ1B_SC INJ1B_OL INJ4B_SC INJ4B_OL
NCS
DIAGNOSTIC_CONTROL
Figure 13
Failures Information
Failure Register Each failure is stored in an individual register (this cannot be done directly in the shift register because a failure can occur while the shift register is being read). If the failure occurs, it remains until the SPI is read. The failure register is cleared when the SPI is read (FR_CLEAR signal). Output Coder The SC and OL failures of the 4 outputs are coded on an 8 bit word described hereafter:
Data Sheet
17
V1.3, 2008-12-23

D7
D6
D5
D4
D3
D2
D1
D0
FSL
Failure indicator bit

(only valid during NCS = LOW to the first L to H CLK change ) 1 = failure stored 0 = no failure
Status INJ4B
11 = no failure 10 = short circuit 01 = shortcircuit
Status INJ1B Status INJ4A Status INJ1A
Figure 14
Output Coder
Table 3
Failures Coding and Priorities Failure SPI Bits FSL 0 1 1 1 Di+1 1 0 1 1 Di 1 1 0 0
valid for i=0 or i=2 or i=4 or i=6 SC 0 0 1 1 OL 0 1 0 1
The first bit of the shift register (FSL) is set to high level if there is a failure stored in the failure register. Input Coder
t1 and t2 times are coded on 3 bit and 5 bit respectively as described hereafter:
Data Sheet
18
V1.3, 2008-12-23

D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB MSB
LSB
t1 time
000: default value = 192 s LSB = 32s 111 = 416 s
t2 time
00000 : default value = 0s LSB = 2s 111 = 62s
Figure 15
Input Coder
Table 4 describes the time coding: Table 4 D7 X X X 0 0 1 1 1 1 1 X X X X 0 0 X 0 0 X 0 0 X 0 1 1 X X 1 X X 1 X X X X Time Coding D6 D5 X X D4 X X D3 X X D2 0 0 D1 0 0 D0 0 1 Time
t1 = 192 s t1 = 224 s
t1 = 416 s t2 = 0 s t2 = 2 s
t2 = 62 s
Shift Register The serial output of the diagnostic shift register is SDO. The serial input is SDI. With the H/L change on NCS the first bit of the diagnostic shift register is transmitted to the SDO output. The CLK pin clocks the diagnostic shift register. New SDO data will appear on every CLKs rising edge and new SDI data will be latched into the shift register on every CLKs falling edge. With the first positive pulse of the CLK the failure register will be cleared by FR_CLEAR. There is no bus collision at a small spike at the NCS. The CLK is always LOW, while the NCS signal is changing. SPI Control The SPI control block monitors the data transfer from failure register to shift register and clear these register. This is done with the FR_SR_TRANS and FR_CLEAR signals as described in the following diagram:
Data Sheet
19
V1.3, 2008-12-23

NCS CLK SDO SDI SPI Internal signals FR_SR_TRANS note: FR_SR_TRANS means failure transfer from the failure register into the shift register
FSL D0-OUT D1-OUT D2-OUT D3-OUT D4-OUT D5-OUT D6-OUT D7-OUT D0-IN D1-IN D2-IN D3-IN D4-IN D5-IN D6-IN D7-IN
FR_CLEAR note: FR_CLEAR means clear of the failure stored of the failure register
Figure 16 SDO Driver
SPI Control
The SDO driver drives the data on the diagnostic line. SDO is tri-stated when NCS is high.
Data Sheet
20
V1.3, 2008-12-23

5.5 5.5.1
Protections All Inputs/Outputs
All pins are protected against ESD 2kV Human body model.
5.5.2
T1, T4 Power Transistors
Protection against damaging failures Protection against Damaging Failures Transistors switched off T1, T4 (internally) and T2, T3 (via NCTL2, NCTL3) T1, T4 (internally) and T2, T3 (via NCTL2, NCTL3) T1, T4 (internally) and T2, T3 (via NCTL2, NCTL3) T1, T4 (internally) and T2, T3 (via NCTL2, NCTL3) T1, T4 (internally) and T2, T3 (via NCTL2, NCTL3) and t2 starts.
Table 5
Problem detected T1 or T4 overcurrent T1 or T4 overtemperature HS_Diag L H T1 or T4 peak current undertime T1 or T4 peak current overtime
Note: The protection latches are reset when the NON input is at high level. Protection against overvoltage A clamping circuit limits the output voltage to a defined value (Vclp) in order to avoid the breakdown of the output transistor when the solenoid load is switched off. Protection against turn on due to fast voltage ramp on output. A very fast voltage slope on the output can turn on the power transistor (capacitive effects) especially when the normal gate pull-down structure is not active (IC not supplied, VCC too low ). In this case, the transistor is turned off immediately. This function is guaranteed for VCC between 0 and 5.5 V.
5.6

Reset
There are two different reset functions: Undervoltage reset NRES reset pin
If one or several of the following conditions are present:
VCC lower than VCCRES, NRES pin at low level,
the low side T1, T4 are switched off, NCTL2 and NCTL3 set to high level, all diagnostic registers are reset and the SDO is tri-stated.
Data Sheet
21
V1.3, 2008-12-23

Electrical Characteristics
6
6.1
Supply Current
Electrical Characteristics: Supply Current
VCC = 4.5 V to 5.5 V, TCASE = -40 C to +125 C, all voltages with respect to ground, positive current flowing into
pin (unless otherwise specified) Pos. 6.1.1 6.1.2 6.1.3 Parameter Standby current Operating mode Operating mode and reverse output current Symbol Min. Limit Values Typ. Max. 10 20 20 mA mA mA without load Unit Conditions
ICC_STB ICC_OM ICC_OM_REV
Iout = 4 A on two
outputs
Ioutp = -1 A on one
output, Iout = 4 A on two other outputs
6.2
Inputs
Electrical Characteristics: Inputs (NONx, PChx, NRESx, NCS, CLK, SDI, HS_Diag)
pin (unless otherwise specified) Pos. 6.2.1 Parameter Low level Symbol Min. Limit Values Typ. Max. 0.2 V -0.3 Unit Conditions
VINL
VCC
0.7
High Level 6.2.2 6.2.3 All inputs except HS_Diag HS_Diag
VINH VHS_DiagH
VCC
0.3
VCC +
0.3 7
V V
VCC
0.85 0.2 -100 20 -200 -20 100 200 V V A A A 0 < VIN < 0.9 VCC 500 mV < VIN < VCC
Hysteresis 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 NONx, Pchx, NRESx NCS, CLK, SDI All inputs except HS_Diag pull-up current HS_Diag pull-down current IIN during reverse output current
VHYST VHYST_SPI IIN IIN IIN
Input Current
Ioutp = -1 A on one output
Data Sheet
22
V1.3, 2008-12-23

6.3
Outputs
Electrical Characteristics: Serial Data Output (SDO)
pin (unless otherwise specified) Pos. 6.3.1 6.3.2 6.3.3 Parameter High output level Low output level Tristate leakage current Symbol Min. Limit Values Typ. Max. 0.4 10 V V A Unit Conditions
VSDOH VSDOL ISDOL
VCC 0.4 -10
ISDO = -2 mA ISDO = 3.2 mA

NCS = HIGH; VSDO = 0 VCC
Electrical Characteristics: Control HS Outputs (NCTLx)
VCC = 4.5 V to 5.5 V, TCASE = -40 C to +125 C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
Pos. 6.3.4 6.3.5 6.3.6 6.3.7 Parameter High output level Low output level Peak current at L H transition Peak current at H L transition Symbol Min. Limit Values Typ. Max. 0.1 -35 V V mA mA Unit Conditions
VNCTLH VNCTLL IP_NCTL_LH IP_NCTL_HL
VCC - 1
40
INCTL = -10 mA INCTL = 1 mA VNCTL = VCC - 4 V VNCTL = 4 V
Electrical Characteristics: Power Outputs (OUTx)
Pos. 6.3.8 Parameter ON resistance at VCC = 5 V Symbol Min. Limit Values Typ. Max. 300 m
1)
Unit
Conditions
RDSON1
Iout = 5 A; VCC = 5 V; Tj = 150 C

80 87 94 94 V V V A V/s
1)
6.3.9 6.3.10 6.3.11 6.3.12 6.3.13
Clamp voltage
VCLP1
IOUT = 4 A
test current 100 mA
Clamp voltage at -1 A on neighbor VCLPR output Matching clamp voltage Leakage current Neg. output voltage ramp (75% Vbat 25% Vbat, inductive load)
VCLPM IOUTL OVRn
VCLP - 7
20
VCLP +
7 10 100
VOUT = 18 V
see Chapter 7.2
1)2)
6.3.14
Pos. output voltage ramp OVRp (25% Vbat 70 V, inductive load)
100
200
V/s
see Chapter 7.2

1)2)3)
Data Sheet
23
V1.3, 2008-12-23

Electrical Characteristics Electrical Characteristics: Power Outputs (OUTx) (contd)
Pos. 6.3.15 Parameter Turn ON delay (NON 50%; Vout = 25% Vbat inductive load) Turn OFF delay (NON 50%; Vout = 70 V, inductive load) Symbol Min. tdON Limit Values Typ. Max. 1.5 s see Chapter 7.2
1)2)
Unit
Conditions
6.3.16
tdOFF
1.5
see Chapter 7.2

1)2)
1) Characteristics tested in different conditions than the specification and guaranteed by correlation. 2) Measured with resistive load. 3) The design is optimized for low EM emissions (no clamp overshoot).
Electrical Characteristics: Power Outputs Reverse Diode
Pos. 6.3.17 6.3.18 Parameter Reverse voltage drop Reverse voltage drop Symbol Min. Limit Values Typ. Max. 1.5 1.5 V V for Iout = -5.0 A (200 s pulse) for Iout = -2.5 A (200 s pulse) 0.8 0.6 Unit Conditions
VRDa VRDb
Data Sheet
24
V1.3, 2008-12-23

6.4
Current Control
Electrical Characteristics: Current Control1)
pin (unless otherwise specified) Pos. Parameter Symbol Min. Limit Values Typ. Max. 13.0 13.0 +17% A A Unit Conditions
IP Current (with RIP = 13.5 k) IP_C 8.5 6.4.2 Absolute value at 25 C and 125 C IP_RH 10 6.4.3 Matching at -40/25 C IPX-IPY_C -17% IP 6.4.4 Matching at 125 C IPX-13% IPY_RH IP 6.4.5 Matching temp drift (IPX-IPY) -2% IP IH Current (with RIH = 14.8 k) 6.4.6 Absolute value at -40 C IH_C 1.4 6.4.7 Absolute value at 25 C and 125 C IH_RH 1.8 6.4.8 Static hysteresis IH2 7% IH
6.4.1 6.4.9 6.4.10 6.4.11 Matching at -40/25 C Matching at 125 C Matching temp drift Absolute value at -40 C
IP = kP / RIP
see Chapter 7.1
2)
IP
+13%
IP
+2%
IP
2.6 2.8 17% A A
IH = kH / RIH
see Chapter 7.1
2)
IH
+17%
IHX-IHY_C -17% IH IHX-13% IHY_RH IH (IHX-4% IHY) IH

0.6 0.7 7% 12.5% IPC
IH
+13%
IH
+4%
IH
1.25 1.25 15% A A
IPC Current (with RIPC = 17.4 k)

6.4.12 6.4.13 6.4.14 6.4.15 6.4.16 6.4.17
IPC_C Absolute value at 25 C and 125 C IPC_RH Static hysteresis IPC2

Matching at -40/25 C Matching at 125 C Matching temp drift
Absolute value at -40 C
IPC = kPC / RIPC

see Chapter 7.1
2)
IPC IPC
IPC
+17%
IPCXIPCY_C IPCXIPCY_RH (IPCXIPCY)
-17% -13%
IPC
+13%
IPC
-4%
IPC
+4%
IPC
IPC
1) No reverse current on any outputs are allowed. External measures against reverse current must be applied. 2) Parameter specified by design, not subject to production test.
Data Sheet
25
V1.3, 2008-12-23

6.5
Current Control Timings
Electrical Characteristics: Current Control Timings (Load capacitor at NCTLx = 100 pF)
pin (unless otherwise specified) Pos. Parameter Symbol Min. NCTL2 Current Control Delay 6.5.1 6.5.2 delay from Pch14 50% VCC to NCTL2 50% VCC delay from HS_diag 50% VCC to NCTL2 50% VCC delay from HS_diag 50% VCC to NCTL3 50% VCC tdNCTL2a tdNCTL2c 200 500 ns ns Limit Values Typ. Max. Unit Conditions
NCTL3 Current Control Delay 6.5.3 tdNCTL3c 500 ns
6.6
Diagnostic and Protections
Electrical Characteristics: Diagnostic and Protections
Pos. 6.6.1 6.6.2 6.6.3 6.6.4 6.6.5 6.6.6 6.6.7 6.6.8 6.6.9 6.6.10 6.6.11 Parameter Overcurrent threshold Overtemperature threshold Symbol Min. Limit Values Typ. Max. A C ns s k V ms s s V s
1)
Unit
Conditions
IOFF
1.18
IP
155 50 8 40 0.6
1.4 IP 1.62
IP
TOFF HS diag input: filter and setup time tHS Overcurrent / Overtemperature tOFF
Shutdown filter and delay time Pull-up resistor OFF state overvoltage threshold OFF state overvoltage filter and delay time Peak current overtime threshold Peak current undertime threshold
185 250 18 150 0.7
2)3)
1)
RPULL-UP VOL tOL tPmax tPmin VCCRES trpON
VCC
3.5 10 3.35
VCC
4.5 60 3.95 100
t1

VCC undervoltage
Undervoltage protection Max ON-time after a output voltage ramp from: 0 V to 25 V at VCC = 0 V to 5.5 V
1) Not subject to production test, specified by design. 2) Characteristics tested at wafer level only (with special testpads), not on packaged parts. 3) Characteristics tested in different conditions than the specification and guaranteed by correlation.
Data Sheet
26
V1.3, 2008-12-23

6.7
SPI Timings
Electrical Characteristics: SPI Timings (see Figure 17), Load capacitor at SDO = 100 pF
pin (unless otherwise specified) Pos. 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6 Parameter Clock frequency (50% duty cycle) Minimum time CLK = HIGH Minimum time CLK = LOW Propagation delay CLK to data at SDO valid NCS = LOW to data at SDO valid CLK low before NCS low (setup time CLK to NCS change H/L) CLK change L/H after NCS = low SDI input setup time (CLK change H/L after SDI data valid) SDI input hold time (SDI data hold after CLK change H/L) CLK low before NCS high CLK high after NCS high NCS L/H to output data float Capacitance at SDI, SDO, CLK, NCS NCS filter time (pulses tfNCS will be ignored) Symbol Min. Limit Values Typ. Max. 3 100 100 MHz ns ns ns ns ns
1)
Unit
Conditions
fCLK tCLH tCLL tPCLD tCSDV tSCLCH
100 100 100
1)
6.7.7 6.7.8
tHCLCL tSCLD
100 20
ns ns
6.7.9
tHCLD
20
ns
6.7.10 6.7.11 6.7.12 6.7.13 6.7.14
tSCLCL tHCLCH tPCHDZ Cx tfNCS
150 150 10
100 15 40
ns ns ns pF ns

1) 1)
Ceramic Capacitor
1)
1) Not subject to production test, specified by design
NCS
tsclcl tsclch thclcl tclh tcll thclch
CLK
tcsdv tpcld tpchdz
SDO
FSL
tscld
D0-OUT
thcld
D7-OUT
SDI
D0-IN
D1-IN
D7-IN
Figure 17
SPI Timings
Data Sheet
27
V1.3, 2008-12-23

Electrical Characteristics: Internal Clock (see SMD ceramic resonator specification n S108 058 007 / 65 92 36.20.89, Figure 18)
pin (unless otherwise specified) Pos. 6.7.15 6.7.16 Parameter External resonator frequency Internal frequency tolerance Symbol Min. Limit Values Typ. 8 Max. +3% MHz -3% Unit Conditions
fOSC fOSC
fOSC
Electrical Characteristics: Programmable Timings
Pos. Parameter Symbol Min. Limit Values Typ. 3 192 32 416 5 0 2 62 Max. s s s s s s (0, 0, 0) (1, 1, 1) (0, 0, 0, 0, 0) (1, 1, 1, 1, 1) Unit Conditions
t1 Time
6.7.17 6.7.18 6.7.19 6.7.20 Number of coding bit via SPI t1_0 t1_lsb t1_max t2_0 t2_lsb t2_max
t1 default value t1 LSB (Least Significant Bit) t1 max value

Number of coding bit via SPI
t2 Time
6.7.21 6.7.22 6.7.23 6.7.24
t2 default value t2 LSB (Least Significant Bit) t2 max value
Attention: To avoid any unknown logic state, t1 and t2 values must be latched at the end of t2 time. Moreover, one latch is needed for each group (A and B) for overlapping reasons. At last, as t1 and t2 can be whenever changed, t1 and t2 should be stored in TLE6270R to release the SPI bus prior to being taken into account by the internal counters.
Resonator
Nominal Oscillating Frequency Oscillating Frequency Tolerance Built-in Capacitance value Resonant Impedance Maximum Resonant Impedance Variation by Temperature Change Insulation Resistance Withstanding Voltage Absolute Maximum Voltage Maximum DC Voltage Maximum Input Voltage Temperature Characteristic (-40 to +125C) Operating Temperature Range Storage Temperature Range 8.000MHz +/-0.5% 30pF +/-20% 40Ohm max. 10Ohm max. at 170C, 6sec. 500MOhm min (at 10VDC) 100VDC, 5 sec. max. 6VDC 15Vpp +/-0.4% max. -40 to +125C -55 to +125C
Application Diagram
Figure 18 Data Sheet
Application Hint: Example of Resonator 28 V1.3, 2008-12-23

Diagrams
7
7.1
Diagrams
Typical Laws
IP=f(RIP) 13 12,5 12 IP 11,5 (A) 11 10,5 10 9,5 9 11,0 12,0 13,0 14,0 15,0 16,0 17,0 18,0 y = 155/x
RIP (kohm)
Figure 19
IP(RIP) (temp = 25 C)
IPC=f(RIPC)
y = 17,4/x 1,2 1,15 1,1 IPC (A) 1,05 1 0,95 0,9 0,85 0,8 14,0 15,0 16,0 17,0 18,0 RIP (kohm) 19,0 20,0 21,0 22,0
Figure 20
IPC(RIPC) (temp = 25 C)
IH=f(RIH)
3,6 3,4 3,2 3 IH 2,8 (A) 2,6 2,4 2,2 2 1,8 9,0 10,0 11,0 12,0 13,0 14,0 RIH (kohm) 15,0 16,0 17,0 18,0 19,0
y = 32,5/x
Figure 21
IH(RIH) (temp = 25 C)
Data Sheet
29
V1.3, 2008-12-23

Diagrams
7.2
Output Timings Diagram
NONx VOUT
VBAT OVRn 75%.VBAT tON tOFF 70V
VCLP
25%.VBAT OVRp
Figure 22
Output Timing
Data Sheet
30
V1.3, 2008-12-23

Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.
8.1
Principle Diagram of Injection System

80V Batt
T3A T2A
T3B T2B
D3A RHSB 5 K RHSB 5 K
D3B
LDO
1K 2.2nF 6V
1K 2.2nF 6V
Loads 5V
CEMI CEMI CEMI
Loads
CEMI
OUT1A
OUT4A
OUT1B
OUT4B
HS_DiagA
5V
5V
5V
5V
Inputs
NON1A NON4A PChA NON1B NON4B PChB
Micro controller
SPI
CLK SDI NCS SDO Prg_IPC
CTL1A
CTL4A
CTL1B
CTL4B
Bank A
Prg_I P Prg_IH OSC1 OSC2
Bank B
NRES
TLE 6270 R
External oscillator Programming resistors

Figure 23 Application Diagram
Note: All values mentioned are typical values. Note: In order to program different t1 and t2 times the resonator frequency could be adjusted Data Sheet 31 V1.3, 2008-12-23
HS_DiagB
CTL2B CTL3B
CTL2A CTL3A
Vcc

8.2
Typical Waveform Diagrams for One and Two Outputs Control

tPC t1 t2 ti tWD tD
NON1 PCh_14
IP
IOUT1
IPC IPC
IH IH
ID ID
VCLP
VOUT1
NCTL3 NCTL2 CTL1
Figure 24
Waveform Diagram for One Output Control
tpc is typically 1 ms. It can be set to 100 ns minimum. twd is typically 200 s. td is typically 150 s.
NON1 NON4 PCh_14
IOUT1
IOUT4
NCTL3 NCTL2 CTL1 CTL4
Figure 25
Waveform Diagram for Two Outputs Control
Note: For each group (A or B), there is no overlapping between the channels 1 and 4. Data Sheet 32 V1.3, 2008-12-23

Package Outlines
Package Outlines
3.5 MAX.
11 0.15 1)
3.25 0.1
B
0.25
+0.07 -0.02
0 +0.1
1.1 0.1
2.8
0.65
15.74 0.1 (Heatslug) 36x 0.25 M A B C
1.3
6.3 (Mold)
14.2 0.3
0.1 C
Heatslug 0.95 0.15 0.25 B
0.25 +0.13
Bottom View
3.2 0.1 (Metal)
36
19
19
36
Index Marking
1 x 45
18
10
15.9 0.1 1) (Mold)

1)
13.7 -0.2 (Metal)
Heatslug
Does not include plastic or metal protrusion of 0.15 max. per side
GPS09181
Figure 26
P-DSO-36 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet 33
5.9 0.1 (Metal)

Dimensions in mm V1.3, 2008-12-23
5 3

Revision History
10
Version 1.3
Revision History
Date 2008-10-22 Changes Updated data sheet to newest template revision Figure 1: changed Chapter 5.2: added details Chapter 5.4.1: added paragraph regarding open load detection Table 2: modified Table 3: modified Figure 15: modified Table 4: modified Chapter 8: application information chapter moved Figure 23: changed and second note added All pages: editorial changes Initial version of RoHS-compliant derivate of TLE6270R Datasheet converted to green Updated Product Summary Page Parameter 4.1.3 removed release for internal correction loop corrections after internal correction loop release Target Datasheet
1.1 0.31 0.1 0.1a 0.2
2008-08-25 2007-01-30 2006-05-06 2006.05.30 2006-06
Data Sheet
34
V1.3, 2008-12-23
Edition 2008-12-23 Published by Infineon Technologies AG 81726 Munich, Germany 2009 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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Data Sheet, V1.

TLE6270R Quad Low Side Injector Driver

TLE6270R Quad Low Side Injector Driver

Quad Low Side Injector Driver

Application Gasoline Direct Injection

VOUT VCLP IP_C IH RON

Type TLE6270R Data Sheet

Marking TLE6270R V1.3, 2008-12-23

TLE6270R Quad Low Side Injector Driver

External oscillator Programming resistors

TLE6270R Quad Low Side Injector Driver

UNDER VOLTAGE RESET

NON1A NON4A PChA

NCTL2A NCTL3A Pgr_IPC Pgr_IP Pgr_IH

GROUP_A FAILURES DETECTION

CLK SDI SDO

SPI INTERFACE for FAILURES INFORMAT

GROUP_B FAILURES DETECTION

NON1B NON4B PChB NCTL2B NCTL3B

Logic blocks OSC block

Figure 2 Data Sheet

Block Diagram 6 V1.3, 2008-12-23

TLE6270R Quad Low Side Injector Driver

Pin Configuration P-DSO-36

TLE6270R Quad Low Side Injector Driver

Pin Definitions and Functions

TLE6270R Quad Low Side Injector Driver

General Product Characteristics

VCC VOUT IOUTC IOUTP WOFFr WOFFs VIN

R = 1.5 k; C = 100 pF;

Figure 4 Data Sheet

Energy Repetitive Pulse and Energy Single Pulse 9 V1.3, 2008-12-23

TLE6270R Quad Low Side Injector Driver

Limit Values Typ. Max. 2

1) Not subject to production test, specified by design.

TLE6270R Quad Low Side Injector Driver

These functionalities are described in the next chapters.

TLE6270R Quad Low Side Injector Driver

Output Current Control

TLE6270R Quad Low Side Injector Driver

Pre-charge Peak Hold Damp

Peak Hold Damp

Pre-charge Peak Hold

Figure 9 Data Sheet

TLE6270R Quad Low Side Injector Driver

GROUP_A FAILURES PROTECTION

SPI INTERFACE for FAILURES INFORMAT

IN1 (NON1 inverted)

IN4 (NON4 inverted)

TLE6270R Quad Low Side Injector Driver

Peak current1 overtime => Y1 problem memory

DIAGNOSTIC CONTROL tOL OFF state overvoltage

Z1 Y1 X1 SC/OL definition circuit SC1 OL1 SPI

Diagram of INJ1 Failures Detection

TLE6270R Quad Low Side Injector Driver

HS Diag Filter Functionality:

Min. 50ns, max .250ns

TLE6270R Quad Low Side Injector Driver

Failures Information (via SPI)

INJ1A_SC INJ1A_OL INJ4A_SC

CLK SDI SDO

INJ1A_OL_stored INJ4A_SC_stored INJ4A_OL_stored

INJ1B_SC INJ1B_OL INJ4B_SC INJ4B_OL