MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Octal Bus Transceiver

The MC74VHC245 is an advanced high speed CMOS octal bus transceiver fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. It is intended for twoway asynchronous communication between data buses. The direction of data transmission is determined by the level of the DIR input. The output enable pin (OE) can be used to disable the device, so that the buses are effectively isolated. All inputs are equipped with protection circuits against static discharge. High Speed: tPD = 4.0ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4A (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.5V Operating Range Low Noise: VOLP = 1.2V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 308 FETs or 77 Equivalent Gates

MC74VHC245

DW SUFFIX 20LEAD SOIC PACKAGE CASE 751D04

DT SUFFIX 20LEAD TSSOP PACKAGE CASE 948E02

APPLICATION NOTES 1. Do not force a signal on an I/O pin when it is an active output, damage may occur. 2. All floating (high impedence) input or I/O pins must be fixed by means of pull up or pull down resistors or bus terminator ICs. 3. A parasitic diode is formed between the bus and VCC terminals. Therefore, the VHC245 cannot be used to interface 5V to 3V systems directly. LOGIC DIAGRAM
A1 A2 A3 A DATA PORT A4 A5 A6 A7 A8 DIR OE 2 3 4 5 6 7 8 9 1 19 18 17 16 15 14 13 12 11 B1 B2 B3 B4 B5 B6 B7 B8 B DATA PORT

M SUFFIX 20LEAD SOIC EIAJ PACKAGE CASE 96701 ORDERING INFORMATION MC74VHCXXXDW SOIC MC74VHCXXXDT TSSOP MC74VHCXXXM SOIC EIAJ

PIN ASSIGNMENT
DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8

FUNCTION TABLE
Control Inputs OE L L H DIR L H X O Operation i Data Transmitted from Bus B to Bus A Data Transmitted from Bus A to Bus B Buses Isolated (HighImpedance State)

6/97

Motorola, Inc. 1997

REV 1


MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage DC Input Voltage 0.5 to + 7.0 0.5 to + 7.0 Vout IIK DC Output Voltage 0.5 to VCC + 0.5 20 20 25 75 500 450 Input Diode Current mA mA mA mA IOK Iout Output Diode Current DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature SOIC Packages TSSOP Package mW Tstg 65 to + 150

MC74VHC245

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.

_C

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolutemaximumrated conditions is not implied. Derating SOIC Packages: 7 mW/_C from 65_ to 125_C TSSOP Package: 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin Parameter Min 2.0 0 0 Max 5.5 5.5 Unit V V V DC Supply Voltage DC Input Voltage Vout TA DC Output Voltage VCC + 85 100 20 Operating Temperature 40 0 0

_C

tr, tf

Input Rise and Fall Time

VCC = 3.3V 0.3V VCC =5.0V 0.5V

ns/V

DC ELECTRICAL CHARACTERISTICS

S b l Symbol VIH

P Parameter

T Test C Conditions di i

VCC V

TA = 25C Typ

TA = 40 to 85C Min Max

Min

Max

U i Unit V

Minimum HighLevel Input Voltage

2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5

1.50 VCC x 0.7

1.50 VCC x 0.7

VIL

Maximum LowLevel Input Voltage Minimum HighLevel Output Voltage

0.50 VCC x 0.3

0.50 VCC x 0.3

VOH

Vin = VIH or VIL IOH = 50A

1.9 2.9 4.4

2.0 3.0 4.5

1.9 2.9 4.4

Vin = VIH or VIL IOH = 4mA IOH = 8mA Vin = VIH or VIL IOL = 50A

2.58 3.94

2.48 3.80

VOL

Maximum LowLevel Output Voltage

0.0 0.0 0.0

0.1 0.1 0.1

0.1 0.1 0.1

Vin = VIH or VIL IOL = 4mA IOL = 8mA Vin = 5.5 V or GND (DIR, OE)

0.36 0.36

0.44 0.44

Iin

Maximum Input Leakage Current

0 to 5.5

0.1

1.0

MOTOROLA

VHC Data Advanced CMOS Logic DL203 Rev 1


DC ELECTRICAL CHARACTERISTICS
Symbol IOZ Parameter Test Conditions VCC V 5.5 5.5 TA = 25C Typ TA = 40 to 85C Min Max 2.5 40.0 Min Max Unit A A Maximum ThreeState Leakage Current Maximum Quiescent Supply Current Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND 0.25 4.0 ICC

MC74VHC245

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

S b l Symbol tPLH, tPHL P Parameter

TA = 25C Typ 5.8 8.3 4.0 5.5

TA = 40 to 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max

T Test C Conditions di i

Min

Max 8.4 11.9 5.5 7.5

U i Unit ns

Maximum Propagation Delay, A to B or B to A

VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V RL = 1 k VCC = 5.0 0.5V RL = 1 k VCC = 3.3 0.3V RL = 1 k VCC = 5.0 0.5V RL = 1 k VCC = 3.3 0.3V (Note 1.) VCC = 5.0 0.5V (Note 1.)

CL = 15pF CL = 50pF CL = 15pF CL = 50pF

10.0 13.5 6.5 8.5

tPZL, tPZH

Output Enable Time OE to A or B

CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF

8.5 11.0 5.8 7.3

13.2 16.7

15.5 19.0 10.0 12.0 18.0 11.0 1.5 1.0 10

ns

8.5 10.6

tPLZ, tPHZ

Output Disable Time OE to A or B

11.5 7.0

15.8 9.7 1.5 1.0 10

ns

tOSLH, tOSHL

Output to Output Skew

pF ns

Cin

Maximum Input Capacitance DIR, OE Maximum ThreeState I/O Capacitance

4 8

pF pF

CI/O

Typical @ 25C, VCC = 5.0V 21

CPD

P Power Dissipation Di i i C Capacitance i (N (Note 2 2.) )

pF F

1. Parameter guaranteed by design. tOSLH = |tPLHm tPLHn|, tOSHL = |tPHLm tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 8 (per bit). CPD is used to determine the noload dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.

NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)

TA = 25C S b l Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage P Parameter Typ 0.9 0.9 Max 1.2 1.2 3.5 1.5 U i Unit V V V V

VHC Data Advanced CMOS Logic DL203 Rev 1

MOTOROLA

MC74VHC245
SWITCHING WAVEFORMS
VCC DIR 50% GND VCC OE A or B 50% GND tPLH B or A 50% VCC A or B tPHL A or B VCC 50% VCC tPZL 50% VCC tPZH 50% VCC tPHZ tPLZ 50% VCC GND HIGH IMPEDANCE VOL +0.3V VOH 0.3V HIGH IMPEDANCE

Figure 1.

Figure 2.

TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.

CL*

CL*

* Includes all probe and jig capacitance

* Includes all probe and jig capacitance

Figure 3.

Figure 4.

MOTOROLA

VHC Data Advanced CMOS Logic DL203 Rev 1

MC74VHC245
EXPANDED LOGIC DIAGRAM

A1

2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 B8 B7 B6 B5 B4 B3 B2 B1

A2

A3

A4

A5

A6

A7

A8

DIR

OE

19

INPUT EQUIVALENT CIRCUIT

DIR, OE A, B

BUS TERMINAL EQUIVALENT CIRCUIT

INPUT

I/O

VHC Data Advanced CMOS Logic DL203 Rev 1

MOTOROLA

MC74VHC245
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D04 ISSUE E
A
20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029

B
1 10

10X

P 0.010 (0.25)
M

20X

D
M

0.010 (0.25)

T A

J
S

F R X 45 _ C T
18X SEATING PLANE

DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E02 ISSUE A

20X

K REF
M

0.15 (0.006) T U

0.10 (0.004)

T U

2X

L/2

20

11

L
PIN 1 IDENT 1 10

B U

J J1

SECTION NN 0.25 (0.010) M

K K1

N 0.15 (0.006) T U
S

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_

A V N F

DETAIL E C D 0.100 (0.004) T SEATING

PLANE

W G

DETAIL E

DIM A B C D F G H J J1 K K1 L M

MOTOROLA

VHC Data Advanced CMOS Logic DL203 Rev 1

MC74VHC245
OUTLINE DIMENSIONS
M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 96701 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 0.81 INCHES MIN MAX 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 0.032

20

11

LE Q1 M_ L DETAIL P

E HE

10

Z D e VIEW P A

b 0.13 (0.005)
M

A1 0.10 (0.004)

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VHC Data Advanced CMOS Logic DL203 Rev 1

MC74VHC245/D MOTOROLA