6.

012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-1

Lecture 9 - MOSFET (I) MOSFET I-V Characteristics March 6, 2003 Contents: 1. MOSFET: cross-section, layout, symbols 2. Qualitative operation 3. I-V characteristics

Reading assignment: Howe and Sodini, Ch. 4, 4.1-4.3 Announcements: Quiz #1, March 12, 7:30-9:30 PM, Walker Memorial; covers Lectures #1-9; open book; must have calculator.

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-2

Key questions How can carrier inversion be exploited to make a transistor? How does a MOSFET work? How does one construct a simple rst-order model for the current-voltage characteristics of a MOSFET?

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-3

1. MOSFET: layout, cross-section, symbols

body source gate n+ p+ n+ p n+ polysilicon gate drain

inversion layer channel

gate oxide

p+

n+

n+

n+

n+

Key elements: inversion layer under gate (depending on gate voltage) heavily-doped regions reach underneath gate inversion layer electrically connects source and drain 4-terminal device: body voltage important

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-4

2 Circuit symbols Two complementary devices: n-channel device (n-MOSFET) on p-Si substrate (uses electron inversion layer) p-channel device (p-MOSFET) on n-Si substrate (uses hole inversion layer)

IDn

D + VDS > 0 G

IDn

D + S + _ B G IDp VSG

S _

G +

VSB
B VSD > 0 D G IDp B

B + VBS VGS _ _ S

(a) n-channel MOSFET

(b) p-channel MOSFET

Drain

n+ Bulk or Body

Source

p+ Bulk or Body

Gate

Gate Drain

n p+

Source

n+

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-5

2. Qualitative operation Water analogy of MOSFET: Source: water reservoir Drain: water reservoir Gate: gate between source and drain reservoirs
VDS VGS G ID VGS VDS

S n+

D n+

water

inversion layer depletion region p

source

gate

drain

Want to understand MOSFET operation as a function of: gate-to-source voltage (gate height over source water level) drain-to-source voltage (water level dierence between reservoirs) Initially consider source tied up to body (substrate or back).

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-6

Three regimes of operation: 2 Cut-o regime: MOSFET: VGS < VT , VGD < VT with VDS > 0. Water analogy: gate closed; no water can ow regardless of relative height of source and drain reservoirs.

VGS<VT S

VGD<VT D

n+ p depletion region

n+ no inversion layer anywhere

no water flow

ID = 0

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-7

2 Linear or Triode regime: MOSFET: VGS > VT , VGD > VT , with VDS > 0. Water analogy: gate open but small dierence in height between source and drain; water ows.
VGS>VT S G VGD>VT D

n+ p depletion region inversion layer everywhere

n+

Electrons drift from source to drain electrical current! VGS |Qn| ID VDS Ey ID
ID small VDS ID small VDS

VGS>VT

VDS

0 0 VDS

0 VT VGS

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-8

2 Saturation regime: MOSFET: VGS > VT , VGD < VT (VDS > 0). Water analogy: gate open; water ows from source to drain, but free-drop on drain side total ow independent of relative reservoir height!
VGS>VT S G VGD<VT D

n+ p depletion region

n+

inversion layer "pinched-off" at drain side

ID independent of VDS : ID = IDsat

VGDsat=VT ID saturation

linear

0 0 VDSsat=VGS-VT VDS

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-9

3. I-V characteristics Geometry of problem:

VDS ID G VGS>VT

S n+ VBS=0 p

D n+

inversion layer depletion region 0 B y

2 General expression of channel current Current can only ow in y -direction: Jy = Q n ( y ) v y ( y ) Total channel current: Iy = W Qn(y )vy (y ) Drain terminal current is equal to minus channel current: ID = W Qn(y )vy (y )

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-10

ID = W Qn(y )vy (y ) Rewrite in terms of voltage at channel location y , Vc(y ): If electric eld is not too big: vy (y ) nEy (y ) = n dVc(y ) dy

For Qn(y ) use charge-control relation at location y : Qn(y ) = Cox[VGS Vc(y ) VT ] for VGS Vc(y ) VT . All together: ID = W nCox(VGS Vc(y ) VT ) dVc(y ) dy

Simple linear rst-order dierential equation with one unknown, the channel voltage Vc(y ).

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-11

Solve by separating variables: ID dy = W nCox(VGS Vc VT )dVc Integrate along the channel in the linear regime: -for y = 0, Vc(0) = 0 -for y = L, Vc(L) = VDS (linear regime) Then: ID or: W VDS ID = nCox(VGS VT )VDS L 2
L 0 dy

= W nCox

VDS (VGS 0

Vc VT )dVc

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-12

For small VDS : ID Key dependencies: VDS ID (higher lateral electric eld) VGS ID (higher electron concentration) L ID (lower lateral electric eld) W ID (wider conduction channel)
ID small VDS ID small VDS

W nCox(VGS VT )VDS L

VGS>VT

VDS

0 0 VDS

0 VT VGS

This is the linear or triode regime.

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-13

In general, ID = W VDS nCox(VGS VT )VDS L 2

Equation valid if VGS Vc(y ) VT at every y . Worst point is y = L, where Vc(y ) = VDS , hence, equation valid if VGS VDS VT , or: VDS VGS VT

ID

VDS=VGS-VT

VGS

VGS=VT 0 0 VDS

term responsible for bend over of ID : VDS 2

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-14

To understand why ID bends over, must understand rst channel debiasing:

|Qn| Cox(VGS-VT)

0 0 |Ey| L

0 0 Vc VDS L y

0 0 VGS-Vc(y) VGS
local gate overdrive

VDS

VT 0 L y

Along channel from source to drain: y Vc(y ) |Qn(y )| |Ey (y )| Local channel overdrive reduced closer to drain.

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-15

Impact of VDS :
|Qn|
VDS=0

VDS 0 0 L y

|Ey|
VDS
VDS=0

0 0 Vc L y

VDS
VDS=0

0 0

As VDS , channel debiasing more prominent ID rises more slowly with VDS

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-16

1.5 46.5 NMOSFET Output characteristics (VGS = 0 3 V, VGS = 0.5 V ):

Zoom close to origin:

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-17

Transfer characteristics (VDS = 0.1 V ):

6.012 - Microelectronic Devices and Circuits - Spring 2003

Lecture 9-18

Key conclusions The MOSFET is a eld-eect transistor: the amount of charge in the inversion layer is controlled by the eld-eect action of the gate the charge in the inversion layer is mobile conduction possible between source and drain In the linear regime: VGS ID : more electrons in the channel VDS ID : stronger eld pulling electrons out of the source Channel debiasing: inversion layer thins down from source to drain current saturation as VDS approaches: VDSsat = VGS VT