Single Cycle Processor

This processor takes exactly ONE clock period to execute an instruction. Well design it in stages, from very simple to more complicated: 1. 2. 3. 4. 5. 6. 7. Executes only add $1,$2,$3 Executes add $r1,$r2,$r3, where $r1,$r2,$r3 are any registers Executes any arithmetic R-Type instruction Executes sw Executes lw Executes j Executes beq

Design approach: What do the instructions do? Implement hardware.

Galen Sasaki

EE 361 University of Hawaii

Single Cycle MIPS: Whoa

Instruction [25 0] 26 Shift left 2 Jump address [31 0] 28 0 M u x ALU Add result Add 4 Instruction [31 26] Control RegDst Jump Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite Read register 1 Shift left 2 1 1 M u x 0 PC+4 [31 28]

PC

Read address Instruction [31 0] Instruction memory

Instruction [25 21] Instruction [20 16] 0 M u x 1

Read data 1 Read register 2 Registers Read Write data 2 register Write data

Instruction [15 11]

0 M u x 1

Zero ALU ALU result

Address

Read data Data memory

Write data Instruction [15 0] 16 Sign extend 32 ALU control

1 M u x 0

Instruction [5 0]

Galen Sasaki

EE 361 University of Hawaii

Machine 1: Only add $1,$2,$3

Reg 2 Reg 3 Registers are a bank of 32 D flip flops (clock not shown) Adder takes two 32-bit numbers and outputs the sum of 32-bits. Adder Reg 1 The registers have different functions: Registers 2 and 3 hold their values, and are read from Register 1 is written to

Galen Sasaki

EE 361 University of Hawaii

New Register
Another Register with Load control: It loads if Load = 1, and holds if Load = 0 Input Load Register Output An implementation of 1-bit register D flipflop Input 0 M 1 U X Clock Load
Galen Sasaki

Clock

// 3-bit register module Reg3(in,out,load,clock); input [2:0] in; input load, clock; output [2:0] out; reg [2:0] out; always @(posedge clock) begin if (load == 1) out = in; end endmodule Multiplexer (MUX) Output = Input 0 if Select = 0 Output = Input 1 if Select = 1

Output

EE 361 University of Hawaii

Multiplexer
0 1 2 3 M U X // 4:1 multiplexer module Mux4(in0, in1, in2, in3, select, out); input [31:0] in0, in1, in2, in3; input [1:0] select; output [31:0] out; reg [31:0] out; always @(in0 or in1 or in2 or in3 or select) case (select) 0: out = in0; 1: out = in1; 2: out = in2; 3: out = in3; endcase endmodule
5

Select Typically an n:1 multiplexer has n inputs and one output, where n is a power of 2. Its a combinational circuit. Function: Output = Input k, if select = k, (k = 0, 1, 2, ...)
Galen Sasaki

EE 361 University of Hawaii

New add $1,$2,$3 Processor

0 0 load load Reg 2 Reg 3 Step 2. Add the values Step 1. Get the register values

Adder 1 load Reg 1

Step 3. Store the sum

Galen Sasaki

EE 361 University of Hawaii

Machine 2: add $r1,$r2,$r3

Add any registers New parts
Instruction memory (stores programs) Program counter (PC) Register file
Multiplexer Demultiplexer

Galen Sasaki

EE 361 University of Hawaii

add $r1, $r2, $r3

program counter PC PC is incremented by 4 every clock cycle Instruction Memory Register file $r2 $r3 $r1

r2 r3 r1 0

32

Galen Sasaki

EE 361 University of Hawaii

Instruction Memory
To simplify the discussion, lets suppose The memory is ROM 32-bits wide 1024 memory words (instructions)
\\ Example Instruction Memory module InstrMemory(addr,instr); input [31:0] addr; output [31:0] instr; reg [31:0] instr; always @(addr[11:2]); case(addr[11:2]) 0: instr={6d0,5d2,5d3,5d1,5d0,6d32}; 1: instr={6d0,5d5,5d6,5d4,5d0,6d32}; 2: instr={6d0,5d8,5d9,5d7,5d0,6d32}; 3: . . endcase endmodule

PC

Instruction Memory

instr[31:0]

Address 0 4 8 12

0 0 0 0

Contents 2 3 1 0 5 6 4 0 8 9 7 0 11 12 10 0

32 32 32 32

Instruction add $1,$2,$3 add $4,$5,$6 add $7,$8,$9 add $10,$11,$12

Galen Sasaki

EE 361 University of Hawaii

Register File
Store (Input) load Register file $3 Store $0 $1 How do we select registers which one read from and which to write to?
10

Reg

Read (Output)

clock

$2

Read

load
Galen Sasaki

clock

EE 361 University of Hawaii

Register File
Devices to select things Write addr Read addr Multiplexer (MUX) Demultiplexer (DMUX or DEMUX) Register file $3 Write data $0 $1 $2
input Y0

Read data

D M U X

Y1 Y2 Y3

load

clock Yk = input, 0,

select

if select = k otherwise

Galen Sasaki

EE 361 University of Hawaii

11

Register File
Reading from a register Write Addr (select) $0
0 1 load 2 3 load

Writing to a register
load

Read Addr (select)

$0
load

Write data

$1 $2

D M U X

$1 load $2

0 1 2 3

M U X

Read data

$3 Clock not shown but its tied to all registers

Galen Sasaki EE 361 University of Hawaii

$3

12

Register File for MIPS

add $r1,$r2,$r3
5 bits wide $r2 addr (r2) $r3 addr (r3) Register File $0,$1,.., $31 A register file is an array of registers that can be accessed by providing the addresses of the registers to be accessed. 32 bits wide $r2 data $r3 data

$r1 addr (r1)

$r1 data

Clock Write (load) Write = 1 causes register $r1 to load at the next clock transition. Otherwise, no registers load.
Galen Sasaki EE 361 University of Hawaii 13

Register File
$r1 data load 0 1 D 2 M U X 31 $r1 addr Register 2 Register 0 Register 1

$r2 addr

M U X

$r2 data

write

Register 31

M U X

$r3 data

$r3 addr Demultiplexer function: Output k = input, if select = k All other outputs are 0
Galen Sasaki

Clock is not shown, but its connected to all registers

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Verilog
// Register file module RegisterFile(writeaddr,writedata,readaddr1,readdata1,readaddr2,readdata2,write,clock); input [4:0] writeaddr, readaddr1, readaddr2; input [31:0] writedata; input write,clock; output [31:0] readdata1,readdata2; readaddr1 readdata1 reg [31:0] RegCell [0:31]; readaddr2 readdata2 always @(posedge clock) Register begin File if (write == 1) RegCell[writeaddr] = writedata; writeaddr writedata end assign readdata1 = RegCell[readaddr1]; assign readdata2 = RegCell[readaddr2]; endmodule
Galen Sasaki EE 361 University of Hawaii

write
15

Verilog
How do we deal with $0 = 0? The statement assign readdata1 = RegCell[readaddr1]; should be changed to always @(readdr1 or RegCell[readaddr1]) begin if (readaddr1 == 0) readdata1 = 0; else readdata1 = RegCell[readaddr1]; end

Galen Sasaki

EE 361 University of Hawaii

16

add $r1, $r2, $r3

0 r2 r3 r1 0 32 Step 2. Get $r2 and $r3 r2 r3 r1 Step 4. Update PC Step 1. Fetch Inststruction

Step 3. Add $r2 and $r3 +

PC

Instruction Memory

Register File $0-$31

program counter (32-bit register, always loading)

Step 4. Store sum.

Galen Sasaki

EE 361 University of Hawaii

17

Machine 3: Arithmetic R-Type

Arithmetic R-Type Instructions: add, sub, or, and, and slt. or and and are bitwise logic operations. operation $r1,$r2,$r3 0 r2 r3 r1 0 funct Step 1. Fetch Instr. funct field 1 RegWrite + 4 PC Instruction Memory r2 r3 r1 $r2 Register File ALU $r3 result Controller Step 2. Access reg. values. Select ALU Step 3. ALU computes result Step 4. Store result Update PC
18

ALU is a combinational circuit that is the calculator for the CPU

Galen Sasaki EE 361 University of Hawaii

Arithmetic Logic Unit (ALU)

Function Table ALU Control Input Function 000 AND 001 OR 010 add 110 subtract 111 set on less than A B

AND Control Input (select)

slt sub

OR

add

result
Galen Sasaki EE 361 University of Hawaii 19

Arithmetic Logic Unit (ALU)

Function Table ALU Control Input Function 000 AND 001 OR 010 add 110 subtract 111 set on less than Control Input (select) Well do a more detailed design of this later in the semester.
Galen Sasaki EE 361 University of Hawaii

AND 0

OR 1

add 2 MUX

sub 6 7

slt

result
20

Arithmetic Logic Unit (ALU)

Function Table ALU Control Input Function 000 AND 001 OR 010 add 110 subtract 111 set on less than // ALU module module ALU(a,b,result,select); input [31:0] a, b; input [2:0] select; output [31:0] result; reg [31:0] result; always @(a or b or select) begin case (select) 0: result = a & b; 1: result = a | b; 2; result = a + b; 6: result = a - b; 7: result = (a-b)>>31; default: result = 0; endcase endmodule
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Galen Sasaki

Controller
Instruction funct field Conroller ALU

Controller Truth Table Input Output 000000 xxx 000001 xxx 100000 [32] 100001 [33] 100010 [34] 100011 [35] 100100 [36] 100101 [37] 101010 [42]
Galen Sasaki EE 361 University of Hawaii

ALU Function Table ALU Control Input Function 000 AND 001 OR 010 add 110 subtract 111 set on less than

R-Type Instruction Function Field Instruction Function Field add 32 sub 34 and 36 or 37 slt 42

22

Machine 4: sw
store word: sw $r1,const($r2) Register File PC Instruction Memory $r2 $r1

43 r2 r1

const

sign ext + ALU address data Data Memory RAM data in

23

Galen Sasaki

EE 361 University of Hawaii

Random Access Memory (RAM)

Very much like a register file only bigger, much bigger. Address RAM DataIn DataOut // module for RAM module RAM(address,dataout,datain,write, clock); input [9:0] address; input [31:0] datain; input write,clock; output [31:0] dataout; reg [31:0] dataout; reg [31:0] Mem[0:1023]; always @(posedge clock) if (write==1) Mem[address] = datain; always @(Mem[address]) dataout = Mem[address]; endmodule
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clock

Write

Write = 1 --> RAM[Address] = DataIn Write = 0 --> hold DataOut = RAM[Address]

Galen Sasaki

EE 361 University of Hawaii

Machine 4: sw
store word: sw $r1,const($r2) Arithmetic R-Type Instructions: oper $r1,$r2,$r3 43 r2 r1 const 0 r2 r3 r1 0 funct Step 1. Fetch Instr. add $r2 + 4 const Comments: Need a MUX in front of ALU RegWrite depends on opcode constant is 16 bits --> needs to be 32-bits
Galen Sasaki

opcode, funct field 0 RegWrite PC Instruction Memory r2 r1 Register File

Controller

ALU $r1

Step 2. Access reg. values. Select ALU to add Step 3. ALU computes address Step 4. Store into memory Update PC
25

data in Data Memory address

EE 361 University of Hawaii

sw
store word: sw $r1,const($r2) 43 r2 r1 const opcode, funct field Controller 0 RegWrite r2 Instruction Memory r1 Register File $r2 $r1 ALU Address

1 MemWrite Data Memory WriteData

Const [ sign ext] Mux

Galen Sasaki EE 361 University of Hawaii 26

sw
store word: Controller If opcode = 0 then RegWrite = 1 ALUSrc = 0 MemWrite = 0 ALUselect depends on funct Else if opcode = 43 RegWrite = ALUSrc = MemWrite = ALUselect = opcode, funct field Controller RegWrite r2 Instr r1 Register File $r2 $r1 0 1 ALU ALUSrc sw $r1,const($r2) 43 r2 r1 const

MemWrite Address Data Memory

WriteData const Sgn Ext

27

Galen Sasaki

EE 361 University of Hawaii

Verilog Break
Concatenation: Syntax: { }, separated by commas Example: x = {y0, y1, 0, 0, 1, y3}; Sample Application: Composing a word made up of fields Reptition: Syntax: {repetition_number{exp1, exp2,, expn}} Example: x = {3{1,y0,y1,0}}; This is the same as x = {1,y0,y1,0, 1,y0,y1,0, 1,y0,y1,0}; Sample Application: Sign or zero extension Shifting: Syntax: x << constant or y >> constant. (Fills with zeros) Example: y = x << 2 Then y is a shifted version of x by 2 bit positions. Sample Application: Shifting, multiplying, or dividing.
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Machine 5: lw
load word: lw $r1,const($r2) Register File PC Instruction Memory $r2 $r1

35 r2 r1

const

sign ext + ALU address data Data Memory RAM data in

29

Galen Sasaki

EE 361 University of Hawaii

Machine 5: lw
load word: Step 1. Fetch Instruction Step 2. Get registers Controller processes Step 3. Compute address Step 4. Access memory Step 5. Store in register
Galen Sasaki EE 361 University of Hawaii 30

lw

$r1,const($r2)

35 r2 r1

const

opcode, funct field Controller 1 ALUSrc RegWrite 1 $r2 r2 Instr r1 Register File $r1 0 1 ALU (+)

0 MemWrite Address Data Memory

WriteData Sgn const Ext ReadData

lw
load word: lw $r1,const($r2) 35 r2 r1 const add opcode, funct field Controller RegDst = 0 RegWrite = 1 ALUSrc =1 r2 Instr r1 0 r3 1 Register File (write data) Sgn const Ext $r2 $r1 0 1 ALU

MemWrite = 0 Address Data Memory

WriteData ReadData

0 1 MemtoReg = 1

Galen Sasaki

EE 361 University of Hawaii

31

Machine 6: j
j addr J-type instruction

PC 4 +

Instruction Memory

Address (26 bits) Shift left by 2 bits (add the last 2 zeros back) address is 28 bits

first 4 bits 28 bits of address

Galen Sasaki

EE 361 University of Hawaii

32

jump
PC + [<< 2] 4 x opcode, funct field Controller RegDst =x RegWrite = 0 ALUSrc =x r2 Instr Instr Memory r1 0 r3 1 Register File (write data) Sgn const Ext $r2 $r1 0 1 ALU
[31-28] 0 1

jump = 1

MemWrite = 0 Address Data Memory

WriteData ReadData

0 1 MemtoReg = x

Galen Sasaki

EE 361 University of Hawaii

33

Machine 7: beq
beq $r1,$r2,offset 4 r1 r2 offset Register file PC Instruction Memory $r1 $r2 I-type instruction

4 1 0 Zero

4 r1 r2 offset Check if zero <<2

ALU

default target branching address

Galen Sasaki

Sign ext +

Zero = 1, if output = 0 0, if not 0

EE 361 University of Hawaii

34

Single Cycle MIPS

Instruction [25 0] 26 Shift left 2 Jump address [31 0] 28 0 M u x ALU Add result Add 4 Instruction [31 26] Control RegDst Jump Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite Read register 1 Shift left 2 1 1 M u x 0 PC+4 [31 28]

PC

Read address Instruction [31 0] Instruction memory

Instruction [25 21] Instruction [20 16] 0 M u x 1

Read data 1 Read register 2 Registers Read Write data 2 register Write data

Instruction [15 11]

0 M u x 1

Zero ALU ALU result

Address

Read data Data memory

Write data

1 M u x 0

1. Branch address computation 2. Check condition

Galen Sasaki

Instruction [15 0]

16

Sign extend

32 ALU control

Instruction [5 0]

EE 361 University of Hawaii

35

Control: Truth Table

Control line RegDst Branch MemRead MemtoReg ALUSel MemWrite ALUSrc RegWrite add sub and Instruction or slt sw lw beq

Galen Sasaki

EE 361 University of Hawaii

36

Controller Implementation
We can make this smaller Instruc[31-26] Instruc[15-0] Controller RegDst Branch MemRead MemtoReg ALUsel MemWrite ALUSrc RegWrite RegDst Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite

Instruc[31-26] Controller

Two smaller controller circuits

ALUOp 00 01 10

Means Instr. add sw/lw sub beq R-type depends on funct field

Input Function ALU ALUsel 000 AND Control 001 OR Instruc[15-0] 010 add 110 subtr 111 set on less than
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Galen Sasaki

Single Cycle MIPS

Instruction [25 0] 26 Shift left 2 Jump address [31 0] 28 0 M u x ALU Add result Add 4 Instruction [31 26] Control RegDst Jump Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite Read register 1 Shift left 2 1 1 M u x 0 PC+4 [31 28]

PC

Read address Instruction [31 0] Instruction memory

Instruction [25 21] Instruction [20 16] 0 M u x 1

Read data 1 Read register 2 Registers Read Write data 2 register Write data

Instruction [15 11]

0 M u x 1

Zero ALU ALU result

Address

Read data Data memory

Write data Instruction [15 0] 16 Sign extend 32 ALU control

1 M u x 0

Instruction [5 0]

Galen Sasaki

EE 361 University of Hawaii

38