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A Mahesh Kumar, V. Sreehari, M.B. Srinivas Birla Institute of Technology and Science Hyderabad Campus, India

## Outline of the Presentation

Introduction
An ADC is a circuit which converts analog signal Continuous form) to digital form (Discrete form) (

Introduction
Continuously varying analog signals are sampled at a fixed rate. Sampled values are then expressed as a digital number, using a binary numbering system. A t Analog-to-Digital Converter
Basic illustration of Analog to digital conversion

V t

Introduction
Every signal that can be measured is an analog signal f(t) i.e., continuous in time. Samples of the signal f(t) are taken at specified time intervals T.

Introduction
Sample and hold circuit needed for rapidly changing signals (not compulsory, though) A simple sample-and-hold circuit,

Introduction

A t Analog i/p signal

V t

A t

Sampled signal

## Digital o/p signal

Introduction

Introduction

Introduction
Fundamental Characteristics of ADC are sampling and quantization
Sampling - Convert a continuous time input signal to a discrete time representation. The input signal must be band limited to no more than Fs to prevent aliasing. Quantization - Convert a continuous amplitude input signal to a discrete amplitude representation.

Introduction
Sampling Time domain Frequency domain

Introduction
Nyquist-Rate Sampling sampling at twice the signal
frequency; Otherwise, aliasing will occur. There are two ways to prevent aliasing: To sample fast enough to cover all spectral components, including the ones outside band of interest (parasitics) To adequately filter all undesired signals (limit fin,max through filtering) so the ADC does not digitize them.

Introduction
Oversampling (Upsampling)
Signal is sampled at a rate greater than Nyquist rate. If the signal has bandwidth of fB, then fs>> fB - Relaxes requirements on the preceding antialias filter - Oversampling also helps to reduce the quantization noise.

Introduction
Subsampling (Downsampling or undersampling)
Sampling at a rate less than the Nyquist rate results in aliasing in frequency domain. If the signal is centered at an intermediate frequency and band-limited, it is not necessarily destructive. Subsampling can be exploited to mix a narrowband RF or IF signal down to a lower frequency.

Performance Parameters
Resolution indicates no. of discrete values an ADC can produce For example, An ADC that encodes an analog input to one of 256 discrete values has a resolution of 8 bits. (2^8 = 256). Higher the resolution, more accurate the measurement. Voltage Resolution = overall voltage measurement range divided by no. of discrete values. For example, If full scale measurement is 0 to 10 V and ADC resolution is 12 bits i.e., 2^12 = 4096 levels Voltage resolution = (10-0)/4096 = 2.44 mV.

Performance Parameters
Performance of ADC is studied by its Static and Dynamic parameters. Static Parameters: Describe the difference between the actual points and the ideal points in the staircase transfer function of ADC when converting DC signals Static parameters are Offset error, Gain error, Full scale error, DNL (Differential Non-linearity), and INL ( Integral N0nlinearity).

Performance Parameters
Offset Error
Offset error is the difference between the nominal and actual offset points as shown below

Performance Parameters
Gain Error Difference between the actual and ideal gain points when offset has been reduced to zero, measured at the rightmost

Performance Parameters
Full Scale Error Full scale error is a measure of how far the last code transition is from the ideal full scale maximum voltage.

Performance Parameters
DNL (Differential Non-linearity)
Maximum deviation in the difference between two successive threshold points from 1LSB.

Performance Parameters
INL (Integral Non Linearity):
Maximum deviation of the transition point from the straight line passed through the end points or best-fit. It is referred to as the relative accuracy of a converter. If max INL is less than 0.5LSB, the ADC is guaranteed to be monotonic.

Performance Parameters
Dynamic parameters are related to AC specifications such as resolution, sampling frequency and input signal frequency. Important dynamic parameters are
Signal-to-Quantization Noise Ratio Signal-to-noise ratio (SNR) Signal-to-noise and distortion ratio (SNDR) Effective number of bits (ENOB) Total harmonic distortion (THD) Spurious-free dynamic range (SFDR)

Performance Parameters
Signal-to-Quantization Noise Ratio
The ratio of the signal power to the quantization noise power at the output, usually for a sinusoidal input signal.

Performance Parameters
SNR (Signal-to-Noise Ratio) is given by the total noise
power (includes all bins except DC, signal, and 2nd through 7th harmonic)

Performance Parameters
Signal-to-(Noise+Distortion) Ratio (SNDR) is the ratio
of the signal power to the noise and distortion power (includes all bins except DC and signal) at the output for a full scale sinusoidal input. SNDR depends on the amplitude and the frequency of the sinusoidal input tone

Performance Parameters
ENOB (Effective Number of Bits) is a global indication
of ADC accuracy at a specific input frequency and sampling rate. ENOB Obtained by measuring the peak of SNDR and is defined by:

Performance Parameters
Total Harmonic Distortion (THD) is the rms sum of all
harmonics in the output signals FFT spectrum. By convention, total distortion power consists of 2nd through 7th harmonic. In communications and RF applications, THD is often a more important figure of merit for ADC than DC- nonlinearity.

Performance Parameters
Spurious Free Dynamic Range (SFDR) is the difference
between the maximum signal component and the largest distortion component in dB. SFDR is important because noise and harmonics restrict a data converters dynamic range. SFDR is very important for high frequency applications, where a spurs can be interpreted as adjacent channel information.

It is used for high-speed and very large bandwidth applications.

Disadvantages Large number of comparators Limited number of bits ( i.e., Low Resolution) Area & Power consumption. Larger input capacitance. Dynamic performance is poor. Applications Radar processing, digital oscilloscopes, high-density disk drives, digital video, memory application.

implemented with two half resolution flash ADCs and a digital-to-analog converter (DAC). In this, number of comparators is reduced by a large number. Disadvantages DAC Inaccuracy Calibration techniques Area, power & speed

## Applications Telecommunication, Ethernet, video, control applications

Pipelined ADC can be implemented with at least two or
more low resolution flash ADCs . Each stage has a S/H circuit to hold the amplified residue from the previous stage. The final binary output is obtained after passing through digital error correction logic.

Disadvantages Limitations due to several clock cycles needed Latency Medium Speed.

## Applications Digital imaging, communications.

Data

transmission,

satellite

SAR ADC is commonly called successive approximation
converter. Architecture of the SAR ADC consists of one comparator, a DAC, and a successive approximation register.

Disadvantages Limited Sampling rates Low Input Bandwidth Low speed DAC linearity Applications Data-acquisition applications, Touch Screens, Pressure Measurements, Medical Imaging, Multi-channel applications.

SIGMA DELTA ADC is also called an over-sampling
ADC. It consists of two main blocks : One is the sigma delta modulator that includes an integrator, a comparator, and a single-bit DAC and the second a digital filter.

Limited Sampling rates Low speed DAC linearity Over Sampling Ratio (OSR)

Applications
Wireless infrastructure, Digital Temperature sensing applications. audio processing,

A Summary of the ADC features

In Conventional ADC designs, once the ADC is designed its resolution is fixed. Power consumption of the ADCs increases with resolution

Peak detector circuit and sub-flash architecture are introduced to make ADC resolution Adaptive CMOS decoder circuit of the ADC is designed with symmetry for high speed conversion, small area and low power consumption

Peak Detector Circuit for Reconfigurability A Novel peak detector circuit is introduced to make the ADC resolution adaptive based on the input analog signal voltage level It consists of an amplifier, three diodes (D1, D2, D3), comparators and multiplexers. Peak value of the input analog signal is stored on the output capacitor labeled as Vc. Peak detector circuit is used to generate control signals to ADC to select the mode of operation as 4-bit or 6-bit or 8-bit based on analog input signals and reference voltages V1, V2 and V3.

Peak Detector Circuit for Adaptive Resolution

Vin

+ _ MUX1

D1

K1

D2

K2

D3

K3

+ _ comp1

MUX2 V1

+ _

MUX3 V2

+ _

V3

comp 2

comp3 Vc

V1

V2

V3

C 1 8 bit

C2

6bit

C3

4bit

## Digital Logic Bias Block

A1

A2

A3

Peak Detector Circuit - Operation The operation of the peak detector circuit is described in the table below: Input Voltage Condition Vin<V3 Code for stages (Ex: Comparators) C1 1 C2 1 C3 0 Code for out stages (Encoders & MUXs) A1 1 A2 1 A3 0

Vin<V2
Vin<V1

1
0

0
0

0
0

1
0

0
1

1
1

Note: C1, C2, C3 are used for PMOS devices to turn ON/OFF and their complements are used for NMOS devices in ADC.

Peak Detector Circuit (OTA) A gain boosting folded cascode OTA circuit is used in peak detector circuit to provide high gain and fast settling time i.e., peak detector should track input signal variations very fast and generate digital code to inverters/buffers, encoder and multiplexer circuits.

Sub-Flash Architecture Sub Flash Circuit in the design makes the ADC resolution Adaptive w.r.t input signal voltage level Comparators and resistor-bias circuits are dynamically controlled with digital bits generated from sub flash circuit Power consumption changes w.r.t resolution.

Sub-flash Circuit Block Diagram

V3 Vin

+ _ COMP3

C3

DIGITAL LOGIC

V2

+ _ COMP2

C2

V1

+ _ COMP1

C1

Operation of the Sub-flash circuit is described in Table below A1, A2 and A3 bits for encoder and MUX are generated from C1, C2 and C3 bits using separate logic

C1 1 1

C2 1 0

C3 0 0

V1<Vin

## Reference Circuits for the ADC

Bandgap Reference Circuit (BGR) BGR circuit is used to generate constant reference which is independent of process, voltage and temperature. The building blocks for BGR circuit are start up circuit, error amplifier and bandgap core.

Bandgap Reference Circuit (BGR) BGR circuit involves adding two voltages that have temperature coefficients of opposite sign with suitable multiplication constants generating a reference voltage. The resulting voltage obtained is independent of temperature. Complementary to Absolute Temperature (CTAT)

## The reference voltage at the output is

Vout VBE 2 R2 R3 R3 VBE
VBE 2 (VT ln n) 1 R2 R3

BGR OTA BGR circuit opamp is designed for high gain, fast settling and good stability to generate a reference voltage of 1.21V with less than 2% error.
AVDD MCS12 Vbias1 8u/1u 16u/1u MCS22

MCS21

Vp 9u/2u

M1

M2 9u/2u

Vn

OUT 2P

## 2K M5 19.2u/2u M3 4.8u/2u 4.8u/2u M4

AVSS

Voltage Regulator Circuit Voltage regulator circuit is used to generate V1, V2 and V3 voltages that are used in peak detector circuit to compare analog input levels It consists of Error Amplifier, Pass transistor and feedback network as shown below
AVDD + _ R1 V2 R2 R3 V1 R4 AVSS BGIN MP 50U/0.3U V3

Voltage Comparator (Inverter-based & comparatorbased) Multiplexer-based Encoder circuit Complete Design [Integration of blocks]

Voltage Comparator (Inverter-based) Comparator is the most important component in the adaptive flash ADC architecture, shown below

## Proposed Inverter & its Voltage Transfer Characteristics

Features of the Inverter Programmable CMOS Inverter as comparator It consists of controllable inputs Vctrlp and Vctrln to operate the inverter in active or stand-by mode Threshold voltages of the inverters are used as reference voltages to quantize the analog input signal The proposed 8-bit design has 255 CMOS inverters with different thresholds, designed based on input dynamic range. At the input, the analog signal quantization level is set by Vm that depends on the W/L ratios of PMOS and NMOS transistors
Vm r (VDD | VTp |) VTn 1 r

with r

kp kn

PMOS & NMOS transistor dimensions for desired switching threshold voltage
Switching Threshold Voltage
102.7mV 105mV 107.7mV . 450mV . 795mV 797.3mV 800mV

## PMOS Dimensions (M1)

5um/0.06um 5um/0.06um 5um/0.06um . 5um/0.06um . 9.9um/0.06um 9.95um/0.06um 10um/0.06um

## NMOS Dimensions (M2)

10um/0.06um 9.95um/0.06um 9.9um/0.06um . 5u/0.06um . 5um/0.06um 5um/0.06um 5um/0.06um

Voltage Comparator (Conventional Comparator)
CLK

C1B

P3

P1

P1

P2

P2

P3

C1B

INP

N1

N1

INN

OUTP OUTN

N2

N2

## C1 and C1B are used to control resolution

Encoder Circuit The Encoder circuit is based on 2:1 multiplexers connected as a tree. Has Regular structure, Low Hardware cost and shortest critical path b3 0
0 0 1 0 0 0 0 0 0 0

S A A b3
1 1 1 1 1 1 1 (b) (c)

S B B S

0 0 0 0 0 0 1 1 1 1 1 1 1

1 0 1 0 1 0 1 0 1 0 1 0 (a) 1 0 1 0 1 0

b2

0 1 1 1 1 1 1 1

1 0

b1 b0

b2
1 1 1

b1

b0

Encoder Circuit Advantages Gain Boosting, Symmetry, Low leakage, Low power dissipation and Minimum area. Comparison of different types of encoders. Type of Encoder Wallace tree 4-level folded Multiplexer based No of MUXs 171 MUX 81 MUX 57 MUX Critical Path 18 tmux 12 tmux 5 tmux

C15 4bit C2 4

C1

C1 C2 C3 Vin

## A3 A2 peak detector circuit

A1

Vref
A1 MP1

CLK _ ENCODER

Vin

+ _

C255

8
8-bit

Vref
A2 MP2

+ _ +

C64

C63

6 3 to 1 8
6-bit

_ Vref
A3 MP3

Mux (8)

+ _

C16

C15

+
4-bit

_
C1

+
Vref
C3 C2 C1 Vin A1 A2 A3

## peak detector circuit

Flash ADC Circuit (with sub-flash architecture)
Vref
A1 MP1

CLK _

Vin

+ _

C255

Vref
A2 MP2

+ _ + _

C64

C63

## ENCODER 8 & MULTIPLEXER

C16

Vref
A3 MP3

+ _

C15

+ _
C1

+
Vref
C3 C2 C1 Vin A1 A2 A3

## BIAS & SUB-FLASH BLOCKS

Operation Lowest Analog Input Voltage : The control signals C1 = C2 = C3 = 0 will turn on all the 256 inverters while pattern A1=0, A2=A3=1 will select the 8-bit encoder and the output multiplexer such that the ADC operates as an 8-bit converter. Thus the lowest magnitude input signal results in the ADC to operate in 8-bit mode. Medium Analog Input Voltage : The control signals C1, C2, C3 will turn on inverters from 0 to 63 while the inverters numbered from 64 to 255 are turned off. The control signals A1, A2 and A3 will select 6-bit encoder and output multiplexer such that the proposed ADC operates as a 6-bit converter.

Highest Analog Input Voltage : The control signals C1, C2, C3 will turn on inverters from 0 to 15 while the inverters numbered from 16 to 255 are turned off. The control signals A1, A2 and A3 will select 4-bit encoder and output multiplexer such that the proposed ADC operates as a 4-bit converter.

Example : 6-bit Flash ADC circuit

Complete Block Diagram

Block diagram with peak detector
12 bit A1 A2 A3 Peak detector block for Variable resolution

## On Chip Digital Logic with Error Correction Circuit

C1 C2 C3

2 -bit

2 - bit

2 -bit

2 -bit S3 CS C2 C3

2 -bit

2 -bit

## V 3 V 2 V1 C1 C1 Analog input AMP CS S1 V 3 V 2 V1 Vref Stage1 Stage2 C1 C2

CS S2

C3

Stage3

Stage4

Stage5

Stage12

On - chip Voltage / current Clock CS - > Reference bias Complementary Switch Clock Generator

Block diagram with sub-flash circuit
12 bit A1 A2 A3 Sub-Flash block for Variable resolution

## On Chip Digital Logic with Error Correction Circuit

C1 C2 C3

2 -bit

2 - bit

2 -bit

2 -bit S3 CS C2 C3

2 -bit

2 -bit

CS S2

C3

Stage3

Stage4

Stage5

Stage12

## CS - > Complementary Switch

Simulation Results

Simulation Results
Bandgap Reference Circuit Montecarlo simulation of Bandgap reference circuit for 6sigma variation under DC-temperature sweep, with temperature ranging from -40 C to 125C. The Output reference voltage variations is +/- 3%.

## Typical Reference Voltage =1.18V

Simulation Results
Bandgap Reference Circuit AC analysis of the op-amp in the band-gap reference circuit to find gain, phase margin and unity gain-bandwidth for PVT corners

## DC Gain=100dB, PM=65deg, UGB=24MHz

Simulation Results
Voltage Regulator Circuit Transient analysis of the voltage regulator circuit to find variation in V1, V2 and V3 reference voltages for PVT corners

Simulation Results
Voltage Regulator Circuit AC analysis of the op-amp in the voltage regulator circuit to find gain, phase margin and unity gain-bandwidth for PVT corners

## DC Gain=78dB, PM=80deg, UGB=65MHz

Simulation Results
Peak Detector Circuit Peak Detector circuit output for three voltages required for variable resolution of ADC

Simulation Results
Peak Detector Circuit AC analysis of the op-amp in the peak detector circuit to find gain, phase margin and unity gain-bandwidth for PVT corners

## DC Gain=68dB, PM=45deg, UGB=415MHz

Simulation Results

Transient analysis of the flash ADC has been performed by generating a ramp input going from 0 to 2.5V. Digital codes have been obtained correctly, going from 0 to 255 for 8-bit output, indicating that the ADCs working is functionally correct.

Simulation Results

Simulation Results
0.5 0.4 0.3 0.2

## DNL of the ADC in 8-bit mode is +/- 0.4.

1 12 23 34 45 56 67 78 89 100 111 122 133 144 155 166 177 188 199 210 221 232 243 254

DNL (LSB)

0.4 0.3

INL (LSB)

## INL of the ADC in 8bit mode is +/- 0.36.

0.2 0.1 0 1 -0.1 -0.2 -0.3 -0.4 OUTPUT CODE 12 23 34 45 56 67 78 89 100 111 122 133 144 155 166 177 188 199 210 221 232 243 254

Simulation Results
Flash ADC (SNR & SNDR) FFT of the ADC output sine wave is shown below from which SNR and SNDR values have been obtained at different input frequency ranges

Simulation Results
Flash ADC (ENOB) Effective number of bits (ENOB) of the adaptive flash ADC is given in table below
I/P Frequency 200MHz ENOB for 6-bits 5.45 ENOB for 8-bits 7.65

300MHz
400MHz 500MHz 600MHz 700MHz

5.50
5.45 5.40 5.35 5.30

7.60
7.55 7.50 7.45 7.40

800MHz

5.25

7.35

Simulation Results

Simulation Results
Adaptive Flash ADC Comparator based 8-bit ADC 4-bit DNL (LSB) INL (LSB) 0.3 0.28 6-bit 0.36 0.32 8-bit 0.4 0.36 0.8 0.5 Characteristic

Input frequency
SNR SNDR ENOB

1.6Gs/sec
25dB 24.5dB 3.77

1.2Gs/sec
35.2dB 34.6dB 5.45

800Ms/sec
47dB 46.3dB 7.4

800Ms/sec
44.6dB 44dB 7.0

Avg.Power(mw)
Layout Area (um2) Power supply (v)

3.5mw
2.5

9mw
850 x 850 2.5

21.5mw
2.5

70mw
1400 x 1400 2.5

Simulation Results

Simulation Results
DNL of the ADC in 6-bit mode is +/- 0.4.

## INL of the ADC in 6bit mode is +/- 0.36.

Simulation Results
Semi Flash ADC FFT of the ADC output sine-wave is plotted below from which SNR and SNDR values have been obtained at different input frequency ranges

Simulation Results
Semi Flash ADC Effective number of bits (ENOB) of the adaptive semi-flash ADC is given in Table below
I/P Frequency 100MHz No of bits 12 ENOB 11.25

200MHz
300MHz 400MHz 500MHz 600MHz

12
12 12 12 12

11.10
10.95 10.80 10.65 10.50

Simulation Results
Inverter based Semi Flash ADC DESIGN Comparator based 8-bit ADC 12-bit DNL (LSB) INL (LSB) Input frequency SNR SNDR ENOB Avg.Power(mw) Layout Area (um2) 0.4 0.35 0.8Gs/sec 68.5dB 66.7dB 10.8 16mw 10-bit 0.36 0.32 0.9Gs/sec 59.43dB 58.35dB 9.4 12mw 650 x 650 8-bit 0.3 0.28 1Gs/sec 47.8dB 46.91dB 7.5 8mw 0.8 0.5 800Ms/sec 44.6dB 44dB 7.0 40mw 900 x 900

Characteristic

Simulation Results
DNL of the pipelined ADC in 12-bit mode is +/- 0.25.

## INL of proposed ADC in 12-bit mode is +/- 0.50.

Simulation Results
Pipelined ADC The FFT of the ADC output sine-wave is plotted from which SNDR values have been obtained

Simulation Results
Pipelined ADC Effective number of bits (ENOB) of the proposed ADC is given in Table below
I/P Frequency No of bits ENOB

1KHz
10KHz 1MHz 10MHz

12
12 12 12

11.5
11.37 11.23 11.18

Simulation Results
8-bit 10-bit 12-bit

Characteristic
DNL (LSB) INL (LSB) Input frequency SNR SNDR ENOB Power (mW) 0.18 0.38 150Ms/sec 48.3dB 47.75dB 7.64 16mW 0.22 0.45 150Ms/sec 59.6dB 58.46dB 9.42 20mW 0.25 0.5 150Ms/sec 71.5dB 69.1dB 11.18 24mW