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EE 457 Discussion: Exceptions

Interrupts and Faults
October 9, 2013
Suvil Deora
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Exceptions
Exceptions (as the name indicates) are rare events that are
triggered by the hardware and force the processor to execute an
exception handler.
Categories: Synchronous and Asynchronous.
Synchronous Exceptions: If the Exception is generated by an
program instruction then it is synchronized with that instruction. The
program stops at the faulting instruction and then resumed at the
faulting instruction.
Asynchronous Exceptions: Exceptions due to I/O interrupts and
hardware failure/malfunction are not synchronized with a specific
program instruction. They may stop program execution at any
instruction.
Precise and imprecise exceptions.

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Exceptions Examples
I/O Device interrupt: HW, AS, Interrupt?
Operating system call: User calls TRAP instruction, S, TRAP?
TRAP programmer initiated interrupt e.g., breakpoint.
Trap usually results in a switch to kernel mode, wherein the operating system
performs some action before returning control to the originating process.
Instruction Tracing and Breakpoints
Integer or floating-point exceptions
Page Faults: Kernel Takes care of it.
Misaligned memory access
Memory protection violation: In this case program is stopped.
Undefined instruction: Can be used to extend ISA.
Hardware failure/alarm: AS/S ?,
Power failure: salvage the computation as much possible.

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Exceptions Handler
Exception Handler (Interrupt Service routine) is a procedure written
specifically to handle a trap, exception, or interrupt. Although
different phenomenon them, the structure of an Exception Handler is
approximately the same for each of these.
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Branch/Jump v/s Exceptions
Branch/Jumps Exceptions
Planned in the Main Program They can occur ANY TIME
asynchronously
May not need to save PSW Need to save PSW
Starting address of the subroutine
is included in the call instruction
The address of Exception handler
is to be picked up from the vector
table based on the exception type.
At the end of the subroutine you
use RET instruction to retrieve the
return address
At the end of exception handler
you use special instruction such as
IRET which not only retrieves the
return address but also the PSW
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x86 Interrupt Nomenclature
Hardware Interrupt (external)
IRQ interrupt request from device
NMI non-maskable interrupt (HW error)
IPI inter-processor interrupt (in SMP)
Exception (internal, CPU-generated)
Fault (usually) correctable error
Trap programmer-initiated (not a error)
Abort severe error (CPU almost crashed)
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x86 Interrupt Vectors
Single hardware mechanism to handle all interrupt types - Every
Exception/Interrupt type is assigned a number: interrupt vector
When an interrupt occurs, the vector determines what code is
invoked to handle the interrupt.
Example: vector 14 ! page fault handler
vector 32 ! clock handler ! scheduler
0 Divide Error
2 Non-Maskable Interrupt
3 Breakpoint Exception
6 Invalid Opcode
11 Segment Not Present
12 Stack-Segment Fault
13 General Protection Fault
14 Page Fault
18 Machine Check
32-255 User Defined Interrupts
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X86 Interrupt latency
As a general rule for any processor, only at the end of the
completion of the execution of the current instruction the CPU
recognizes an interrupt request.
There are few exceptions to the above statement in 8086. eg WAIT
When Should the CPU start attending to an interrupt request.
Immediately (asynchronously)
At the end of the current clock
At the end of the current bus cycle
At the end of the current Instruction Cycle
At the end of the current Procedure
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X86 Interrupt latency
When Should the CPU start attending to an interrupt request.
Immediately (asynchronously)
At the end of the current clock
At the end of the current bus cycle
At the end of the current Instruction Cycle
At the end of the current Procedure

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Sources: Hardware Interrupts
Hardware Interrupt Types:
Non-Maskable Interrupt Never ignored
INTR Maskable Ignored when IF is 0
PIC: Programmable Interrupt Controller (8259A)
IRQ! Interrupt Vector mapping
IRQ priorities
selective masking

Why do we use PIC?
x86 CPU
PIC
8259A
!"#$
"%!
!
Hardware Interrupt Types:
Non-Maskable lnterrupt
- Never gnored
lNTR Maskable
- Ignored when IF s 0
!
PIC: !"#$"%&&%'() Interrupt
Controer (8259A)
!
IROIV mappng
!
IRO prortes
!
seectve maskng
!
APIC: Advanced PIC:
!
LAPIC + IOAPIC
!
MMIO, not PIO
!
SMP aware
!"#$%&'( *+$,-+$& ./0&$$#10'
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Sources: Software-generated Interrupts
Traps Programmed Interrupts
x86 provides INT instruction
Invokes the interrupt handler for vector N (0-255)
'INT 0x30' for system calls
Faults Software Exceptions: Processor detects an error
condition while executing an instruction.
Ex: divl %eax, %eax
Divide by zero if EAX = 0
Ex: movl %ebx, (%eax)
- Page fault or seg violation if EAX is un-mapped
virtual address.
Ex: jmp $BAD_JMP
General Protection Fault (jmp'd out of CS)
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Enabling / Disabling Interrupts
Maskable Hardware Interrupts
IF (interrupt enabled flag) is a part of EFLAGS
Clearing the IF flag inhibits processing hardware interrupts delivered on the INTR
line
Use the STI (set IF) and CLI (clear IF) instructions
IF affected by: interrupt/task gates, and IRET
Non-Maskable Interrupt
Invoked by NMI line from PIC
Always Handled immediately
Handler for interrupt vector 2 invoked.
No other interrupts can execute until NMI is done.
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Steps to Handle Interrupt
The CPU pushes the flags register onto the stack.
The CPU pushes a far return address (segment:offset) onto the
stack, segment value first.
The CPU determines the cause of the interrupt (i.e., the interrupt
number) and fetches the four byte interrupt vector from address
0:vector*4.
The CPU transfers control to the routine specified by the interrupt
vector table entry.
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Oder of Events (detailed)
Two interrupt ACK bus cycles are executed, separated by two idle clock
periods. The acknowledged device returns an interrupt number as a
byte of data. During the second ACK bus cycle this data byte is shifted
left by 2 bits and it becomes the interrupt vector starting address.
A read bus cycle is executed, during which CS register contents are
read from the first two interrupt vector bytes.
A read bus cycle is executed, during which new PC contents are read
from the third and forth IV bytes
A write bus cycle is executed, during which PSW is pushed onto the
stack
The interrupt (I) and Test Flag (TF) in the PSW are reset to 0. This
disables maskable or single step interrupts.
A write bus cycle is executed during which CS is pused on to the stack.
A write bus cycle is executed during which the PC is pushed onto the
stack.
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IDT: Interrupt Descriptor Table
IDT
Table of 256 8-byte entries
Each specifies a protected entry-point into the kernel
Located anywhere in memory
IDTR register
Stores current IDT
lidt instruction
Loads IDTR with address and size of the IDT.
Takes in a linear address.

lDT:
- Tabe of 256 8-byte entres (smar to the GDT).
- In |OS: Each specfes a protected entry-pont nto the kerne.
- Located anywhere n memory.
!"#$ register:
- Stores current IDT.
%&'( instruction:
- Loads !"#$ wth address and sze
of the IDT.
- Takes n a linear address.
!"#$ !&'())*+' "(,-).+'/) #012(
lDT:
- Tabe of 256 8-byte entres (smar to the GDT).
- In |OS: Each specfes a protected entry-pont nto the kerne.
- Located anywhere n memory.
!"#$ register:
- Stores current IDT.
%&'( instruction:
- Loads !"#$ wth address and sze
of the IDT.
- Takes n a linear address.
!"#$ !&'())*+' "(,-).+'/) #012(
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IDT Entries
Selector Segment Seector for dest. code segment
Offset Offset to procedure entry pont
P Segment Present Fag
DPL Descrptor Prvege Leve
D Sze of gate: 1 = 32 bts; 0 = 16 bts
]bit 40| 0 = nterrupt gate; 1 = trap gate
!"# %&'()*+
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MC68000 Modes
The MC68000 provides two states of privilege
User S-bit in SR is 1
Supervisor S-bit in SR is 0
Each state has its own stack pointer and stack
n User Stack Pointer
n Supervisor Stack Pointer
Microprocessor-based System Design
Ricardo Gutierrez-Osuna
Wright State University
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Privilege states
The MC68000 provides two states of privilege
Supervisor (S-bit in SR is 1)
User (S-bit in SR is 0)
Each state has its own stack pointer and stack
User Stack Pointer
Supervisor Stack Pointer
A few instructions are only available in supervisor mode
- AND #data,SR - MOVE An,SSP
- EOR #data,SR - RESET
- OR #data,SR - RTE
- MOVE <ea>, SR - STOP
- MOVE SSP, An
User
Mode
Supervisor
Mode
Transition may occur only
during exception processing
Transition may occur through four instructions:
MOVE to SR
ANDI to SR
EOR to SR
RTE
Any exception
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Thanks