IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO.

7, JULY 2010

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A High Efciency Flyback Converter With New Active Clamp Technique

Junming Zhang, Member, IEEE, Xiucheng Huang, Xinke Wu, Member, IEEE, and Zhaoming Qian, Senior Member, IEEE

AbstractThis paper proposes a yback converter with a new noncomplementary active clamp control method. With the proposed control method, the energy in the leakage inductance can be fully recycled. The soft switching can be achieved for the main switch and the absorbed leakage energy is transferred to the output and input side. Compared to the conventional active clamp technique, the proposed methods can achieve high efciency both for heavy-load and light-load condition, and the efciency is almost not affected by the leakage inductance. The detailed operation principle and design considerations are presented. Performance of the proposed circuit is validated by the experimental results from a 16 V/4 A prototype. Index TermsActive clamp, yback, high efciency, noncomplementary control.

I. INTRODUCTION ITH MORE and more emphasis on the environment protection and energy saving, the efciency and standby power loss of the power supply are much concerned. For external power supplies, such as adaptors, the average efciency instead of the full-load efciency is more important to save the energy. Therefore, both the light-load efciency and full-load efciency need to be carefully considered, which creates new challenge for the power supply design. Flyback converters are widely adopted for low-power ofine application due to its simplicity and low cost. Usually, an RCD clamp circuit is necessary to dissipate the leakage energy during the switch is OFF. And a well-coupled transformer with minimized leakage inductance is critical to achieve the high efciency and to minimize the voltage spikes across the switch. However, a labor-intensive manufacturing process is required to produce these well-coupled transformers as well as passing the safety regulation. How to further improve the efciency of a yback converter still challenges the power supply designers. The rst way to improve the efciency is reducing the leakage inductance energy loss. The conventional RCD clamp circuit absorbed the leakage energy and dissipated it in the snubber resistor. If the leakage inductance is large, the dissipated energy is much larger than the energy stored in the leakage inductance

Manuscript received September 28, 2009; revised December 11, 2009. Date of current version June 18, 2010. Recommended for publication by Associate Editor R. Burgos. The authors are with the College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China (e-mail: zhangjm@zju.edu.cn; shushuxiu@ zju.edu.cn; wuxinke@zju.edu.cn; qian@cee.zju.edu.cn). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2010.2042302

due to part of the magnetizing energy fed to the snubber circuit during the commutation time, which deteriorate the efciency. The lossless snubber for single-end converter was proposed to recycle the leakage energy, but the snubber parameters makes the circulating energy relative large during normal operation, which limited the efciency improvement [1]. The active clamp yback converter can recycle the energy in the leakage inductor and achieve soft switching for both primary and auxiliary switch [2][8]. Although it has good performance in efciency at full-load condition, it is sensitive to parameters variations. The variation of leakage inductance and snubber capacitor affects the conduction angle of the secondary-side rectier, which lowers the efciency. And the two active switches also increase the cost. Furthermore, the conventional complementary gate signal and constant frequency (CF) control method result in poor efciency at light-load condition, which also leads to lower average efciency. Other topologies with two active switches in half-bridge structure can absorb the leakage energy with pulsewidth modulation control or resonant control, such as asymmetrical half-bridge (AHB), asymmetrical yback, or LLC converter [9][14], [17], [18], they can achieve soft switching for main switches and high efciency, but most of them are not suitable for wide input range application as usually required for universal input condition without front-end power factor corrected (PFC) converter. Also, many control schemes are proposed to improve the efciency of the conventional yback converter. They mainly focus on how to reduce the switching loss. The efciency of conventional CF control usually is low due to the high-switching loss caused by high drain to source voltage across the switch. Many variable frequency (VF) control schemes are proposed in the recent years to improve the performance compared to the conventional CF control [15], [16]. The quasi-resonant (QR) control method operates the converter at critical continuous mode (CRM), and turns ON the switch at the minimal point of switch voltage to reduce the switching loss, such as NCP1207 from ON Semiconductor. In low-input voltage condition, zero voltage switching (ZVS) for primary-side switch can be achieved. And switching loss still exists in high-input condition. However, the switching frequency increases at light-load and high-input condition, which leads to a low-light-load efciency. The maximum switching frequency need to be clamped to reduce the electromagnetic interference (EMI) noise and burst mode operation is necessary to improve the light-load efciency [15]. In QR control, the ZVS of primary-side switch can be achieved if the secondary synchronous rectier is adopted. The reversed

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Fig. 1. Topology of the active clamp yback converter. (a) N-type clamp circuit. (b) P-type clamp circuit.

magnetizing current is used to achieve ZVS operation, there is circulating energy from secondary to the primary side and the save switching loss is offset by the increased conduction loss [16]. The OFF-time control scheme reduces the switching frequency when the load decreases by xing the primary-side peak current, which results in a very good light-load efciency and transformer core utilization, such as NCP1351 from ON Semiconductor. But the switching loss is larger due to valley switching was lost. To further optimize the operation performance, many mutlimode control schemes are also implemented by combining these mentioned control scheme with an optimized sequence, like QR at heavy load, CF/OFF-time control at light load and burst at very light-load condition, such as TEA1552 from NXP and UCC28600 from TI. But all these did not have much effect on the leakage energy. This paper presents a yback converter with a new active clamp control method to achieve soft switching and high efciency in whole load range, which is quite attractive for lowpower application with universal ac inputs, such as external adaptors. The power stage is shown in Fig. 1, which is the same as the conventional active-clamp circuit, but the control method and operation principle are different. In the proposed control method, the auxiliary switch is turned ON for a short time before the main switch is turned ON. And the recycled leakage energy is used to achieve the soft switching of the main switch, which dramatically reduce the circulating energy compared to the conventional active clamp yback. Furthermore, the proposed control scheme can be adopted to VF control to reduce the switching loss and improve light-load efciency. The detailed operation principle will be illustrated in Section II. The design considerations are given in Section III. Section IV will present the detailed experimental results from a 64 W (16 V/4 A) prototype with universal ac input. A comparison of the experimental results with the other control scheme is also provided to validate the advantages of the yback converter with proposed noncomplementary control signal.

Fig. 2. Steady-state operation waveforms with proposed noncomplementary control method. (a) DCM operation. (b) CCM operation.

II. PRINCIPLE OF OPERATION Fig. 1 shows the circuit conguration of the proposed active clamp yback converter, which is identical for the conventional active clamp yback. Lm is the transformer magnetizing inductance and Lk is the transformer leakage inductance. SW is the primary main switch, and DR is the output rectier diode. Auxiliary switch Sa can be a NMOS or PMOS, as shown in Fig. 1. Coss is the equivalent parasitic capacitance of Sw , Sa , and the parasitic winding capacitance of the transformer. The transformer turns ratio is N . The output voltage is Vo . To simplify analysis of the steady-state circuit operation, the clamp voltage is assumed to be constant. The theoretical waveforms at discontinuous conduction mode (DCM) and continuous conduction mode (CCM) operation are shown in Fig. 2. The N-type in DCM operation is used as example, the steady-state waveform and equivalent circuit are shown in Figs. 2(a) and 3, respectively. Each operation mode is described next. Mode 1 [t0 t1 ]: In this mode, primary-side switch Sw is ON and the auxiliary switch Sa is OFF. The energy is stored to the magnetizing inductor and the primary-side current Ip increases linearly, which is the same as the conventional yback converter. Mode 2 [t1 t2 ]: At t1 , when Sw turns OFF, Coss is charged up by the magnetizing current. Due to relative large magnetizing

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inductance, the drainsource voltage Vds S w of main switch Sw increases linearly. This mode ends when the drainsource voltage Vds S w reaches the input voltage Vin plus the clamp voltage Vc , i.e., Vin + Vc . Due to the large clamp capacitor, there is no parasitic ring or voltage spike, which helps to reduce the EMI noise and the voltage rating of Sw . During this mode, the secondary-side rectier DR may turn ON, which depends on the clamp voltage Vc and the ratio of the leakage inductance and the magnetizing inductance, i.e., m = Lk /Lm . Once the clamp voltage Vc is larger than (1 + m)N Vo , the secondary-side rectier diode DR turns ON rstly, and then, the leakage energy keeps to charge up the parasitic capacitor Coss . If the Vc is smaller than (1 + m)N Vo , the clamp voltage may charges up, once the Vc reaches (1 + m)N Vo , the secondary-side rectier DR turns ON. Based on the aforementioned assumption, here we simply assumed that the Vc is almost equals to (1 + m)N Vo , detailed discussion of clamp voltage Vc will be presented in the next section. Once the Vds S w reaches Vin + Vc , the secondary-side rectier DR also turns ON. Mode3 [t2 t3 ]: At t2 , the voltage Vds S w reaches Vin + Vc , the antiparalleled diode of Sa turns ON and the secondary-side rectier DR also turns ON. The energy stored in the magnetizing inductor starts to deliver to the output. And the energy in the leakage inductor is absorbed by the clamp capacitor. This mode can be treated as a primary to secondary commutation period. If the clamp capacitor is large enough and the circuit is lossless, the leakage inductor current Ip decreases linearly. Otherwise, the current may decay like a transient in a two-order circuit. The detailed expressions will be presented in the next section. During this mode, the difference between the magnetizing current and primary current is delivered to secondary side. As soon as the current in the leakage inductor reaches zero, this mode is nished. And all the magnetizing current is transferred to the secondary side, though part of them is absorbed by the clamp capacitor during this mode. Mode 4 [t3 t4 ]: At t3 , the current through leakage inductance is zero and the antiparalleled diode of Sa is OFF. The magnetizing energy is delivered to the load as conventional yback converter and the magnetizing current decreases linearly. Mode 5 [t4 t5 ]: At t4 , magnetizing current decreased to zero, and DR turns OFF. A parasitic resonance occurs between Lm and Coss as conventional yback at DCM condition. Mode 6 [t5 t6 ]: At t5 , auxiliary switch Sa is turned ON. The voltage across the magnetizing inductance Lm and leakage inductance Lk is clamped to Vc , and secondary winding is forward-biased, so DR is ON. The current through Lk increases reversely. The magnetizing current IL m increases reversely too, but the magnitude may be smaller than the leakage current. These negative current is used to achieve ZVS of main switch Sw . The absorbed leakage energy in Mode 3 is transferred to the output side and the leakage inductor again. The auxiliary switch ON time determines the circulating energy and clamp voltage. Detailed design consideration will be discussed in the next section.

Fig. 3. Equivalent circuits in steady-state operation. (a) Mode 1 [t0 t1 ]. (b) Mode 2 [t1 t2 ]. (c) Mode 3 [t2 t3 ]. (d) Mode 4 [t3 t4 ]. (e) Mode 5 [t4 t5 ]. (f) Mode 6 [t5 t6 ]. (g) Mode 7 [t6 t7 ]. (h) Mode 7B [t6 t7 ]. (i) Mode 8 [t7 t8 ].

Mode 7 [t6 t7 ]: At t6 , the auxiliary switch Sa turns OFF. The negative current Ip discharges the parasitic capacitor Coss . If the leakage energy is larger than the energy in the parasitic capacitor Coss , the secondary DR keeps ON, the difference between Ip and IL m is fed to the secondary side. Once the leakage energy is smaller than the parasitic capacitor, the magnetizing inductor also helps to realize the soft switching. As soon as the leakage inductor current Ip reaches IL m , the secondary DR is OFF, and both the magnetizing inductor and the leakage inductor discharge Coss , as shown in Fig. 3(h) (referred as Mode 7B). Mode 8 [t7 t8 ]: At t7 , the output capacitor Coss voltage decreased to zero and the antiparallel diode of main switch Sw turns ON. If the leakage inductor current Ip is still larger than IL m , the equivalent circuit is shown in Fig. 3(i). If the leakage inductor current Ip reaches IL m during Mode 7, the equivalent circuit is same as Fig. 3(h). The primary-side switch Sw should be turned ON before the primary current Ip changes the polarity.

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Fig. 4.

Simplied steady-state operation waveforms under DCM.

magnetizing inductor is clamped by the reected output voltage. Based on assumption that the clamp voltage is constant and circuit is ideal, the current slew rate di/dt of the leakage inductor is exactly the same during these two modes. Thus, based on the charge balance of the clamp capacitor, the area of the triangle current waveform during these two modes is also the same. Also, the time duration Tcom for leakage current decreasing to zero is proportional to the peak current Ipk . And the negative peak current Ip -neg is proportional to the time duration Ta . The primary current Ip and Tcom should be satised 2 2 1 Ipk = 1 Ip -neg Ipk = Ip -neg 2 di/dt 2 di/dt (1) Tcom = Ta . Ipk and Ip -neg represents the positive and negative peak value of the primary-side current. The primary peak current Ipk is determined by the load condition. The clamp voltage can be expressed as follows: Vc = N V o + Lk Ipk . Ta (2)

For CCM condition shown in Fig. 2(b), Mode 5 does not exist anymore, and other modes are almost the same as those described earlier. Also, due to CCM operation, only the leakage energy can be used to achieve ZVS. Based on the aforementioned description, the proposed circuit can be applied to any control scheme to recycle the leakage energy, such as CF or VF. III. DESIGN CONSIDERATIONS Based on the steady-state operation mode analysis discussed in Section II, there is an extra power deliver period when the auxiliary switch is ON. But the energy delivered to the load usually is quite small, which will not affect the output. Therefore, the design considerations for the main power stage, such as transformer, primary switch, and secondary rectier is almost the same as conventional yback converter, which will not be elaborated here. The relationship of the key parameters of the clamp circuit will be discussed in this section, such as ZVS operation range, clamp capacitance, auxiliary switch ON time, and the clamp voltage. We still use DCM operation shown in Fig. 2(a) as an example. The conclusion can be adopted to CCM directly. A. Ideal Condition We simply assume that the clamp voltage almost constant in the steady-state operation, which is usually true with a relative large clamp capacitor. Also, the resonant period for the leakage inductance Lk and clamp capacitor Cc is much longer than the auxiliary switch Sa ON time Ta , which means the charge and discharge of leakage current can be simply assumed to be linearly. Also, the circuit has no power dissipation. Since the switching transient period [t1 t2 ] and [t6 t7 ] is usually very short, in steady-state analysis, the transient period can be neglected to simplify the analysis. The simplied waveforms are shown in Fig. 4. The clamp voltage is self-balanced based on the charge balance or energy balance, which means that the charge into the clamp capacitor during Mode 3 should be equal to the charge out of the clamp capacitor during Mode 6 for balancing. Based on the equivalent circuit shown in Fig. 3 for Mode 3 [t2 t3 ] and Mode 6 [t5 t6 ], the secondary-side rectier diode is ON and the

From (2), it is clear that the clamp voltage depends on the leakage inductance, primary peak current, and auxiliary switch ON time Ta . The Sa ON time Ta also affects the circulating energy. The magnetizing energy stored to the clamp capacitor during Mode 3 [t2 t3 ] and the energy is transferred back to the output during Mode 6 [t5 t6 ], which is the circulating energy and the amount can be calculated as follows: N Vo Ip -neg Ta . (3) Ecir = 2 A large Sa ON time leads to large circulating energy, though it helps to reduce the clamp voltage. The percentage of the circulating energy to the total output power is given as follows: Cir% = Ta Ts -ON (4)

where Ts -ON is the secondary-side rectier diode ON time. Under CRM operation, the equation can be simplied as follows: Cir% = N Vo + Vin Ta . N No Ts (5)

In the universal input condition, most VF control scheme (QR or OFF time) operates the converter under CRM mode at full-load and minimal input condition, which determines the maximum circulating energy. Once the load decreased or voltage increased, the converter operated in DCM mode, the circulating energy almost keeps constant. The circulating energy will cause extra conduction loss, which will offset the saved power loss using the proposed method. A small auxiliary switch ON time will reduce the circulating energy, and the clamp voltage will increase. There should be some tradeoff. Based on the previous analysis and assumption, we can discuss the parameters and control method selection for performance optimization. 1) ZVS Operation Range: During the switching transient, i.e., Mode 7, a more simple equivalent circuit is shown in

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Fig. 5. Switching transient with large and small leakage energy for ZVS. (a) Simplied equivalent circuit for Mode 7. (b) Large leakage energy. (c) Small leakage energy.

Fig. 5(a). In this mode, the leakage inductor current Ip value decreases. If the leakage energy EL k is larger than the parasitic capacitor energy EC o s s , the ZVS operation of primary switch Sw can be achieved easily EL k = 1 1 2 2 Lk Ip -neg EC o s s = Coss (Vin + N Vo ) . 2 2 (6)

ZVS operation. Equation (6) is a necessary to achieve ZVS operation of Sw . 2) Optimized Control Scheme: From (6), it is preferred that the negative peak current keeps constant with load variation. Usually, the peak current is adjusted to regulate the output power, such as QR and CF control scheme, which means the ZVS condition may not satised at light-load condition. For the OFFtime control method, the peak magnetizing current is xed and the switching frequency is used to regulate the output power. Therefore, OFF-time control method is preferred for the proposed control scheme to achieve soft switching at any load condition. 3) Auxiliary switch ON time Ta : Auxiliary switch ON time decides the circulating energy and the clamp voltage as given in (2) and (5). The ON time Ta can be designed by the desired maximum clamp voltage at the full-load condition. It is an important parameter, which also affects the selection of clamp capacitance as analyzed next. 4) Leakage Inductance Lk and Dead Time Td : For simplicity, we need to select the leakage inductance to satisfy (6) for ZVS operation. With preferred OFF-time control, the Ip neg in the equation is determined by the maximum switching frequency at full-load condition. Therefore, the required dead time Td should be smaller than the quarter the resonant period Td 2 4 Lk Coss . (9)

Ip neg is given in (1) and the value is related to the load condition. More detailed transient waveforms is shown in Fig. 5(b) if EL k > EC o s s . Once the drainsource voltage Vds S w of main switch reaches zero, the leakage current drops fast due to the voltage applied to Lk becomes Vin + N Vo . When leakage current Ip reaches the magnetizing current IL m , both of them increase linearly through the antiparalleled diode of main switch Sw , as shown in Mode 8 of Fig. 3. Under DCM operation or critical DCM operation (available for almost all VF control schemes), the magnetizing current increases reversely (secondary-side rectier diode DR is ON) during Mode 6 and Mode 7. The ZVS of Sw can be maintained even EL k is smaller than EC o s s due to the magnetizing energy EL m , which helps to realize ZVS of Sw , as shown in Fig. 5 (c). The expression is shown as follows: 1 1 1 2 2 2 Lk Ip -neg + Lm IL m -neg Coss (Vin + N Vo ) 2 2 2 N Vo Ta = Cir%Ipk IL m -neg = Lm (7) (8)

As explained earlier, the magnetizing current also helps to achieve the ZVS under CRM or DCM operation, which may need a larger dead time. Thus, the dead time may slightly larger than the calculated value given by (9). But too large dead time will decrease the equivalent switching frequency, which results in higher peak current for full-load condition and results in higher conduction loss. In practical design, 200500 ns is a suitable value for proper operation. 5) Clamp Capacitance Cc : The previous analysis is based on the assumption that the clamp voltage is almost constant and the resonant period formed by the leakage inductor and clamp capacitor should be much longer than the auxiliary switch ON time. Usually, the voltage ripple should be within 5% or 10% to treat it as constant. The clamp capacitance can be expressed as follows: Cc Ipk Ta 2Vc ripple% (10)

where IL m -neg is negative peak value of magnetizing current, which is proportional to the peak current (load condition) and circulating energy. Due to relative large magnetizing inductance, even a very small negative magnetizing current can achieve ZVS of Sw if the dead time is sufcient. However, in the real application, the larger dead time will results in low-equivalent switching frequency, which will deteriorate the overall efciency. Also, increasing the auxiliary switch ON time helps to increase the negative magnetizing current to help ZVS operation, and it causes extra conduction loss, which may offset the saved switching loss. For CCM operation, the magnetizing current may not change the polarity, only the leakage energy can be used to realize the

where Vc is given in (2) and ripple% is the maximum allowed clamp voltage ripple percentage, such as 5% or 10%. It is clear that smaller Ta helps to reduce the clamp capacitance. Also, the resonant period should be several times larger than the auxiliary switch ON time to treat it as a linear charge/discharge as given in (11). Usually, k should be above 5. 2 Lk Cc kTa . (11)

Based on these two equations, we can determine the clamp capacitance. Though large capacitance makes the operation more close to the ideal condition, it does not help much for the clamping performance and usually causes high cost and bulky

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where Ip 0 and Vc 0 are the initial current and voltage value at the beginning of the Mode 3 and Mode 6. During Mode 6, Ip 0 = 0 and Ip 0 = Ipk during Mode 3. The clamp voltage should be estimated using charge balance during Mode 3 and Mode 6
Ta

Fig. 6.

Simplied equivalent circuit for Mode 3 and Mode 6.

ip (t)dt|M o de3 =
0

Tc o m

ip (t)dt|M o de6 .

(17)

volume. For practical application, the clamp capacitance is usually ranges from tens to hundreds of nanofarad. 6) Auxiliary Switch Sa : For the auxiliary switch Sa , the current rating is quite small, and the rms current ratio of the auxiliary switch Sa to main switch Sw is given in (12). Theoretically, a very small current rating MOSFET can be used. But the ON resistance will affect the negative peak current Ip -neg , which will be discussed later. Compared to the conventional active clamp yback with complementary gate drive signal, the ZVS operation of auxiliary switch is lost. Due to the small device rating, the turning ON switching loss is small Irm s S a = Irm s S w Ta TON (12)

Tcom can be calculated using (13)(16) when current drops to zero, which is a function of Vc . It is not possible to get a simple expression to calculate Vc like (2). For engineering design, it is still acceptable to estimate Vc using (2). From the current equation given earlier, the negative peak current Ip -neg will be damped by the equivalent resistor. It is a typical transient response of a two-order circuit. It can be divided into overdamping, critical damping, and underdamping condition. The maximum auxiliary switch ON time and related peak negative current are given as follows: ln(s2 /s1 ) Ta m ax = s s Lk 1 2 if Rloss > 2 Cc Ip -neg m ax = (Vc 0 N Vo ) es 2 T a m a x s1 Lk 2Lk Ta m ax = R loss (Vc 0 N Vo ) 1 Ip -neg m ax = e Rloss d Ta m ax = 2 (18) Lk Cc

where Irm s S w and Irm s S a are the rms current of the main switch Sw and auxiliary switch Sa , respectively. B. Nonideal Condition These assumptions mentioned earlier are only used to simply the analysis, which is usually satised in the practical design. In this part, we will further discuss the circuit operation and parameters design if the assumption is not validated anymore. In the previous analysis, we simply assume the whole circuit has no power dissipation. It is usually not true for practical application. Firstly, we will discuss the inuence of the circuit power loss on the circuit operation. During Mode 3 and Mode 6, a simple equivalent circuit is given in Fig 6, an equivalent resistor Rloss is used to represent the circuit power loss. Though the charge balance is still valid, the negative peak current Ip -neg is not equal to Ipk anymore, i.e., (1) is not valid any more. Also, the time Ta is not equal to Tcom . The negative current can be given as follows: ip (t) = (Vc 0 N Vo ) s 1 t (e es 2 t ) Lk (s2 s1 ) vc (t) = Ip 0 (s1 es 1 t s2 es 2 t ) (s2 s1 ) (13)

if Rloss = 2

(19)

(V N Vo ) bT a m a x Ip -neg m ax = c 0 e Lk d

if Rloss < 2

Lk Cc (20)

Vc 0 N V o (s2 es 1 t s1 es 2 t ) (s2 s1 ) Ip 0 (es 1 t es 2 t ) Cc (s2 s1 ) Rloss + 2Lk Rloss 2Lk Rloss 2Lk Rloss 2Lk
2

(14)

s1 = s2 =

1 Lk Cc 1 Lk Cc

(15)

(16)

where d = (1/Lk Cc )2 b2 and b = Rloss /(2Lk ). To achieve soft switching of main switch, the negative peak current is much concerned. In the ideal condition, the Ip -neg always equals to Ipk as analyzed before. The extra damping effect caused by the circuit power loss reduces the negative peak value, which will affect the ZVS range as given in (6). For straightforward understanding of the damping effect, the current under these three conditions mentioned earlier during Mode 6 are shown in Fig. 7 by (13). It is preferred that the auxiliary switch ON time Ta is nished when the current reaches its negative peak value as given in (18)(20). In Fig. 7, the current value is normalized to the negative peak current Ip -neg (equals to Ipk ) in ideal condition as the base value, i.e., Ip 0 in (13) of Mode 3. In the calculation, Ipk (Ip -neg ) is 3 A and Vc 0 is 1 V higher above the reected output voltage N Vo . From Fig. 7, it is clear that maximum negative current value decreases a lot if the damping is large with the same parameters. Secondary, we will consider the clamp capacitor is not large enough, and the clamp voltage will change a lot. If the auxiliary switch ON time is smaller than Ta -m ax given in (20), the equation and analysis given for nonideal condition is still valid. If the auxiliary switch ON time Ta is larger than quarter the resonant

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TABLE I KEY PARAMETERS OF THE EXPERIMENTAL PROTOTYPE

Fig. 7. 10 F.

Current waveforms and the damping effect at L k = 1 H, C c =

Fig. 8.

Transformer structure for the prototype.

period, the leakage current will decrease with increased Ta , as shown in Fig. 7, which is not preferred for ZVS operation and circuit operation. If the clamp voltage at the end of Mode 1 is larger than (1 + m)N Vo , part of the leakage energy will be absorbed by the primary-side parasitic capacitor Coss to raise the voltage to Vc and turns ON the antiparalleled diode of Sa . Therefore, the charger absorbed by the clamp capacitor during Mode 3 is slightly reduced, which will leads to a reduced negative peak current both at ideal and nonideal conditions. Usually, the value is small in practical application. IV. EXPERIMENTAL RESULTS To verify the theoretical analysis of the proposed topology, the simulation results under ideal condition and nonideal condition are presented in Fig. 9 using PSIM software. A 16 V/4 A prototype with universal ac input is built to verify the simulation and theoretical analysis. The OFF-time control is adopted in the prototype with the controller NCP1351 from ON. The transformer core is PQ26/20 with PC40 equivalent material. The transformer is built with interleaving structure as shown in Fig. 8. The primary-side winding has four strands in parallel (with AWG28 magnet wire, OD = 0.31 mm), six turns per layer, and total four layers in series. The secondary winding has six strands in parallel (with AWG28 magnet wire), four turns per layer, and three layers in parallel. Due to the separator for creep distance is not used in the transformer bobbin, therefore, the leakage inductance is small. The auxiliary winding is only

three turns with 2 AWG28 wire in parallel. A PMOS is used as auxiliary switch for simple gate drive. The key parameters of the prototype are given in Table 1. The key parameters in simulation are also the same as the prototype unless otherwise noted. The designed maximum frequency is 65 kHz at full-load condition. The circuit operated under CRM at full-load and low-input condition. And the switching frequency is only related to the load condition due to OFF-time control with xed peak current. The minimum frequency will be several hundreds hertz under very light-load condition, which is almost inaudible. From Fig. 9, it is clear the negative peak current is not depended on the auxiliary switch time Ta under ideal condition. If the clamp circuit power loss is considered, the negative peak current is much reduced as given in (18)(20), which is also shown in Fig. 9 (b) and (d). In the simulation, the leakage energy is much smaller than the parasitic capacitor energy. If the auxiliary switch ON time Ta is small with a xed dead time (here 500 ns), the ZVS operation may lost. With a large Ta (here 1 s) as shown in Fig. 9(a) and (b), the ZVS operation can be maintained due to the magnetizing energy as mentioned earlier. The main experimental results are given in Figs. 1015. The auxiliary switch ON time is set to 400 ns. Fig. 10 shows the gate drive signal, drain to source voltage (Vds S w ) of Sw and the primary-side current Ip at different load and input condition. It is clear that the soft switching of Sw is achieved at any load and input condition with OFF-time control. The parasitic ring is eliminated by the clamp capacitor. With the parameters used in the prototype, the maximum voltage stress of main switch is about 500 V at high line (ac 265 V), which is much smaller than maximum 570 V of the conventional yback converter with RCD clamp (R = 100 k and C = 2.2 nF) at the same condition. If the leakage inductance is larger, the voltage rating for the conventional yback with RCD clamp circuit will be much higher. But in the proposed converter, it will be well limited as shown in Fig. 15. Thus, a lower voltage rating MOSFET can be used as primary switch for better efciency with the proposed control scheme. The equivalent circuit loss resistance is dominated by the auxiliary switch ON resistance, i.e., around 5 . Based on the parameters given in Table I, the circuit is almost critical damping

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Fig. 9. Simulation waveforms for the proposed active clamp yback converter, L k = 1 H, C c = 1 F, C o ss = 120 pF, T d = 400 ns (dead time), V in = 400 V. (a) T a = 1 s and R lo ss = 0 (ideal condition). (b) T a = 1 s and R lo ss = 1 (nonideal condition). (c) T a = 0.5 s and R lo ss = 0 (ideal condition). (d) T a = 0.5 s and R lo ss = 1 (nonideal condition).

condition. With (2) and (19), we can get the negative peak current is about 37% of the peak current, which is quite matched by the experimental results shown in Fig. 10. Fig. 11 shows the waveforms of the primary current Ip , clamp current Ic , and secondary current Is at different load conditions. The leakage energy is absorbed and transferred to the output side and input side when auxiliary switch Sa turns ON. The more detailed waveform at main switch turns OFF and auxiliary switch turns ON is shown in Figs. 12 and 13, respectively. The commutation period shown in Fig. 12 determines the circulating energy. Based on the tested waveforms, the soft switching of Sw is achieved, but high dv/dt may exist in certain condition when Sa turns ON due to hard switching. Also, there is a narrow current pulse in the output side when Sa turns ON, as shown in Fig. 11. We tested the EMI performance of the proposed converter, which is almost the same to the conventional RCD clamp yback without any input EMI lter. The dv/dt and narrow current pulse does not have much effect of the EMI performance. And the narrow current pulse still has lower di/dt than the current slew rate when Sw turns OFF. Also, with the ac ripple on the dc bus, it looks like nature frequency dithering with VF control, which also helps to reduce the dv/dt of Sa due to the turn ON point of Sa always changing. Due to the complex mechanism of the EMI coupling path and noise source, the effect on the EMI performance may need further investigation [19], [20]. The clamp voltage Vc versus the auxiliary switch ON time Ta and leakage inductance Lk is given in Figs. 14 and 15, respectively. Due to the PFET is used as auxiliary switch, the clamp capacitor voltage also includes the input voltage, which is excluded in the gures. From Fig. 14, the calculated clamp voltage using (2) quite matches the measured one. The difference is less than 5%. Fig. 15 shows the clamp voltage versus the leakage inductance with a xed auxiliary switch ON time. It is clear that the calculated value is very close to the measured one with different leakage inductance. The small difference in the high-leakage inductance is caused by the voltage ripple in the clamp capacitor due to high-leakage energy. During the test, an extra inductor is connected in series with the transformer primary winding to adjust the leakage inductance. The measured efciency of the prototype is shown in Figs. 1619. The average efciency is measured and calculated at 25%/50%/75%/100% load condition. Fig. 16 shows the average efciency comparison of the proposed converter with QR yback (controller by NCP1207 A from ON) and OFF-time yback with same parameters at different input voltage. The RCD clamp circuit is used for QR and OFF-time-controlled yback with a 100 k resistor and 4.7 nF capacitor. The voltage rating of Sw is much higher than the proposed circuit. The average efciency decreases with increased input voltage due to switching loss and leakage energy loss in the conventional QR yback. Fig. 17 shows the average efciency comparison of the proposed converter and the conventional active clamp yback converter at different input voltage. For proper operation of the conventional active clamp yback, the leakage is increased to

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Fig. 10. Switching waveforms and primary-side current at different input and load condition. (a) V in = 90 V a c and full load (Io = 4 A). (b) V in = 90 V a c and light load (Io = 1 A). (c) V in = 220 V a c and full load (Io = 4 A). (d) V in = 220 V a c and light load (Io = 1 A).

Fig. 11. Primary-side current Ip , secondary-side current Is , and clamp circuit current Ic at different load. (a) Light-load condition (Io = 1 A). (b) Full-load condition (Io = 4 A).

Fig. 12.

Transition between Ip and Is at S w turns OFF.

Fig. 13.

Vd s

Sw

, Ip , and Is waveform at S a turns ON.

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Fig. 14.

Clamp voltage V c versus T a , L k = 1.5 H, and Ip k = 3 A.

Fig. 18.

Efciency versus output current.

Fig. 15.

Clamp voltage V c versus L k , T a = 350 ns, and Ip k = 3 A.

Fig. 19.

Average efciency with different leakage inductance.

Fig. 16.

Average efciency comparison with QR and OFF-time yback.

Fig. 20.

No-load power loss.

Fig. 17. yback.

Average efciency comparison with conventional active clamp

4.5 H. From Fig. 17, it is clear that the conventional one has low-average efciency due to low-light-load efciency. And the efciency drops fast with input voltage due to large circulating energy. Fig. 18 shows the efciency versus output current of the proposed converter. The efciency keeps a high level in the entire load range, especially the light-load efciency due to OFF-time control. Fig. 19 shows the average efciency versus the leakage inductance. It is clear that the efciency is not sensitive to the leakage inductance variation, which makes it very attractive for applications with low cost transformers. Also, the switch voltage rating can keeps constant with proper designed auxiliary switch ON time.

Fig. 21.

Input power at 0.5 W output power.

The standby (no load) power loss is shown in Fig. 20, the control circuit power loss is also included. It is well below current 300 mW limitation. The input power at 0.5 W load is shown in Fig. 21. As a comparison, the standby power loss and input power at 0.5 W load for conventional RCD clamp yback with same parameters and OFF-time control is also presented. It is clear that the proposed converter has higher light-load efciency and lower standby power loss.

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V. CONCLUSION This paper proposes a high efciency yback converter with new active clamp control method. The proposed circuit has very attractive features, such as low device stress, soft switching operation, and high efciency both for full-load and light-load condition. It can be adopted to various control schemes, such as CF and VF. Also, it is not sensitive to leakage inductance variation. All the advantages make it suitable for low-power ofine application with strict efciency and standby power requirement. A detailed theoretical analysis for the parameters design is presented in the paper. A 16 V/4 A prototype with universal input and OFF-time control scheme is built and compared to various yback converter with dissipative clamp circuit or conventional active clamp yback. The experimental results conrm the theoretical analysis and the advantages mentioned earlier. REFERENCES
[1] T. Ninomiya, T. Tanaka, and K. Harada, Analysis and optimization of a nondissipative LC turn-off snubber, IEEE Trans. Power Electron., vol. 3, pp. 147156, Apr. 1988. [2] C. T. Choi, C. K. Li, and S. K. Kok, Control of an active clamp discontinuous conduction mode yback converter, in Proc. IEEE Power Electron. Drive Syst. Conf., 1999, vol. 2, pp. 11201123. [3] R. Watson, F. C. Lee, and G. Hua, Utilization of an active-clamp circuit to achieve soft switching in yback converters, IEEE Trans. Power Electron., vol. 11, no. 1, pp. 162169, Jan. 1996. [4] Y.-K. Lo and J.-Y. Lin, Active-clamping ZVS yback converter employing two transformers, IEEE Trans. Power Electron., vol. 22, no. 6, pp. 24162423, Nov. 2007. [5] G.-B. Koo and M.-J. Youn, A new zero voltage switching active clamp yback converter, in Proc. IEEE Power Electron. Spec. Conf., 2004, pp. 508510. [6] P. Alou, A. Bakkali, I. Barbero, J. A. Cobos, and M. Rascon, A low power topology derived from yback with active clamp based on a very simple transformer, in Proc. IEEE Appl. Power Electron. Conf., 2006, pp. 627632. [7] E. H. Wittenbreder, Zero voltage switching pulse with modulated power converters, U.S. Patent 5402329, Mar. 1995. [8] D. A. Cross, Clamped continuous yback power converter, U.S. Patent 5570278, Oct. 1996. [9] T. M. Chen and C.-L. Chen, Analysis and design of asymmetrical half bridge Flyback converter, IEE Proc.-Electr. Power Appl., vol. 149, no. 6, pp. 433440, Nov. 2002. [10] B.-R. Lin, C.-C. Yang, and D. Wang, Analysis, design and Implementation of an asymmetrical half-bridge converter, in Proc. IEEE Int. Conf. Ind. Technol., 2005, pp. 12091214. [11] D. Fu, B. Lu, and F. C. Lee, 1 MHz high efciency LLC resonant converters with synchronous rectier, in Proc. IEEE Power Electron. Spec. Conf., 2007, pp. 24042410. [12] D. Huang, D. Fu, and F. C. Lee, High switching frequency high efciency CLL resonant converter with synchronous rectier, in Proc. IEEE Energy Convers. Congr. Expo., 2009, pp. 804809. [13] D. Fu, F. C. Lee, Y. Liu, and M. Xu, Novel multi-element resonant converters for front-end dc/dc converters, in Proc. IEEE Power Electron. Spec. Conf., 2008, pp. 250256. [14] D. Fu, F. C. Lee, Y. Qiu, and F. Wang, A novel high-power-density three-level LCC resonant converter with constant-power-factor-control for charging applications, IEEE Trans. Power Electron., vol. 23, no. 5, pp. 24112420, Sep. 2008. [15] Y. Panov and M. M. Jovannovic, Adaptive off-time control for varaiablefrequency, soft-switched yback converter at light loads, IEEE Trans. Power Electron., vol. 17, no. 4, pp. 596603, Jul. 2002. [16] M. T. Zhang, M. M. Jovanovic, and F. C. Lee, Design considerations and performance evaluations of synchronous rectications in yback converters, IEEE Trans. Power Electron., vol. 13, no. 3, pp. 538546, May 1998. [17] D. Fu, Y. Liu, F. C. Lee, and M. Xu, A novel driving scheme for synchronous rectiers for LLC resonant converters, IEEE Trans. Power Electron., vol. 24, no. 9, pp. 13211329, May 2009.

[18] D. Fu, Y. Liu, F. C Lee, and M. Xu, An improved novel driving scheme of synchronous rectiers for LLC resonant converters, in Proc. IEEE Appl. Power Electron. Conf., 2008, pp. 510516. [19] D. Fu, P. Kong, S. Wang, F. C. Lee, and M. Xu, Analysis and suppression of conducted EMI emissions for front-end LLC resonant dc/dc converters, in Proc. IEEE Power Electron. Spec. Conf., 2008, pp. 11441150. [20] F. C. Lee, S. Wang, P. Kong, C. Wang, and D. Fu, Power architecture design with improved system efciency, EMI and power density, in Proc. IEEE Power Electron. Spec. Conf., 2008, pp. 41314137. Junming Zhang (M10) was born in Zhejiang, China, in 1975. He received the M.S. and Ph.D. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 2000 and 2004, respectively. He is currently an Associate Professor in the College of Electrical Engineering, Zhejiang University. His research interests include power electronics system integrations, power factor corrected techniques, dc/dc converter, synchronous rectier, and high-power inverters. He holds one patent.

Xiucheng Huang was born in Zhejiang, China, in 1986. He received the B.S. degree in electrical engineering from Zhejiang University, Hangzhou, China, in 2008, where he is currently working toward the M.S. degree in electrical engineering. His current research interests include soft switching of power conversion, high efciency dc/dc converters, and synchronous rectier.

Xinke Wu (M09) was born in Jiangsu Province, China, in 1978. He received the B.S. and M.S degrees in electrical engineering from Harbin Institute of Technology, Harbin, China, in 2000 and 2002, respectively, and the Ph.D. degree in electrical engineering from Zhejiang University, Hangzhou, China, in 2006. He is currently an Assistant Professor in the College of Electrical Engineering, Zhejiang University. His research interests include soft switching of power conversion, power factor correction, high efciency dcdc converter, and power electronics system integration.

Zhaoming Qian (SM92) received the M.S. degree in radio engineering from the Electrical Engineering Department, Zhejiang University, Hangzhou, China, in 1961, and received the Ph.D. degree in applied science from Catholic University of Leuven and the Interuniversity Microelectronics Center (IMEC), Leuven, Belgium, in 1989. Since 1961, he has been teaching and involved in research work on electronics and power electronics in Zhejiang University, where he was a Professor of the Electrical Engineering Department in 1992. He is currently the Deputy Director of the National Engineering Research Center for Applied Power Electronics as well as of the Scientic Committee of National Key Laboratory of Power Electronics, both at Zhejiang University. He has authored or coauthored one book on EMC design and more than 200 papers. His current research interests include power electronics and its industrial applications, power electronic system integration, and electromagnetic compatibility in power electronic systems. Dr. Qian received Excellent Education Awards from the China Education Commission and from Zhejiang University in 1993, 1997, and 1999, respectively, and the Science and Technology Development Awards from the China Education Commission in 1999 and 2003, respectively.