COMPUTER ARCHITECTURE IMPORTANT QUESTIONS FOR PRACTICE

1. How many bits wide memory address have to be if the computer had 16 MB of memory? (use the smallest value possible) 2. A digital computer has a common bus system for 16 registers of ! bits each" #he bus is constructed with multiple$ers" (i) How many selection inputs are there in each multiplier? (ii) %hat si&es of multiple$ers are needed? (iii) How many multiple$ers are there in the bus? 3. '$plain what is (MA? 4. %hat is pipelining? 5. %hat is cache? 6. %hat is cache coherency and how is it eliminated? 7. %hat is write bac) and write through caches? 8. %hat are different pipelining ha&ards and how are they eliminated? 9. %hat are different stages of a pipe? 10. How do you improve the cache performance" 11. (ifferent addressing modes" 12. *omputer arithmetic with two+s complements" 13. %hat are the types of memory management? 14. '$plain the difference between hardwired and control and micro programmed control" 15. '$plain the overflow condition in arithmetic shift micro operation" 16. %hat are the two instructions needed in the basic computer in order to set ' flip,flop to 1? 17. #he following transfer statements specify a memory" '$plain a memory operation in each case(i) M.A/0/

(ii)

/!M.A/0

18. (efine the following(i) Microcode (ii) Microinstruction (iii) Micro operation

(iv)Micro 1rogram 19. '$plain the importance of different addressing modes in computer architecture with suitable e$ample" 20. %hat is an instruction format? '$plain different types of instruction formats in detail"

21. (esign an arithmetic circuit with one selection variable 2 and two n,bit data inputs A 3 B" #he circuit generates the following four arithmetic operations in con4unction with the input carry *in" (raw the logic diagram for the first two stages"
22. '$plain shift micro operation in detail" Also draw and e$plain 5,bit combinational circuit"

23. '$plain 6lynn7s classification of computers" 24. %hat is the difference between isolated 89: and memory mapped 89:? 25. %hy does (MA have priority over the *1; when both re<uest a memory transfer? 26. (erive an algorithm for evaluating the s<uare root of a binary fi$ed point number" 27. '$plain in detail /82* pipeline" %hy is the cache miss penalty= greater in deeply pipelined processor? 28. %hat is direct memory access ((MA)? %hy are the read and write control lines in a (MA controller bi directional? 29. 6ormulate a hardware procedure for detecting an overflow by computing the sign of the sum with the signs of the augends and addend" #he numbers are in signed !>s complement representation" 30. %hat is the basic advantage of using interrupt initiated data transfer over transfer under program control without an interrupt? 31. %hat is asynchronous data transfer? '$plain in detail" 32. '$plain vector processing" %hat is the difference between vector 3 array processing? 33. %hat is the difference between serial and parallel transfer? '$plain with the re<uired e$ample" 34. '$plain the hardware implementation of logic micro operation for A?(= :/= @:/ and *omplement logic gate" 35. %hat is the difference between micro processor and a micro program? 36. %hy should the sign of the remainder after a division be the same as the sign of the dividend? 37. A digital computer has a common bus system for 16 register of ! bits each" #he bus is *onstructed with multiple$ers" (i) How many selection inputs are there in each multiple$er?

(ii) %hat si&es of multiple$ers are needed? (iii) How many multiple$ers are there in the bus?

38. '$plain the circuit of Accumulator logic" 39. %hat is the difference between a direct and indirect address instruction? How many references to memory are needed for each type of instruction to bring an operand into a processor register? 40. A computer has 16 register= an AA; with ! operations and a shifter with eight operations all *onnected to a common bus system" (i) 6ormulate a control word for a micro operation" (ii) 2pecify the number of pits in each field on the control word and give a general encoding scheme" 41. *onvert the following arithmetic e$pressions from infi$ to reverse polish notation-, (i) ABBC*B(C'B6 (ii) ABBCAB(BB(C*B') (iii) AB.BC*B*(C'096B(DCH)

42. (raw a space time diagram for a si$,segment pipeline showing the time it ta)es to process eight #as)s" 43. (esign an array multiplier that multiplies two 5,bit numbers" ;se A?( gates and binary adders" 44. '$plain memory hierarchy in a computer system" 45. '$plain *ache *oherence" 46. %rite the format of memory reference 3 89: reference instruction" 47. (ifferentiate between mas)ing and selective clear" 48. '$plain tri state buffer with their application"
49. An instruction is stored at location EE with its address field at location E1" #he address

field at location E1" #he address field has the value 5EE" A processor register /1 contains the number !EE" 'valuate the effective address if the addressing mode of the instruction is (i) (irect

(ii) 8mmediate (iii) /elative

(iv) /egister indirect (v) 8nde$ with /1 as the inde$ register

50. (raw and e$plain the diagram of micro program se<uencer"

51. '$plain the following(i)

(ii)

(iii) (iv) (v)

6unctions of peripherals interface Modes of transfer in (MA 2peedup ratio (ivide overflow (ifference between /82* 3 *82*

52. A no pipeline system ta)es FE ns to process a tas)" #he same tas) can be processed in 6 segment pipeline with a cloc) cycle of 1E ns" (etermine the speedup ratio of pipeline for 1EE tas)s" %hat is ma$imum speedup ratio? 53. '$plain ha&ards to the instruction pipeline with their solution"
54. '$plain Booth7s algorithm for multiplying binary integer in signed !7s complement

representation" 55. (esign the hardware of addition 3 subtraction of fi$ed point signed magnitude numbers" 56. (esign the hardware of addition 3 subtraction of fi$ed point signed magnitude numbers"
57. %hat is vector processing?

58. How many types of address se<uence are re<uired in a control memory? '$plain with the diagram of a control memory and it7s associated hardware" 59. %ith the help of flow chart= discuss the hardware divide algorithm" '$plain how the divide overflow conditions are handled? 60. /egister A holds binary" (etermine the register B operand and the logic micro operation to be performed in order to change the value (i) E11E11E1 (ii) 1?
62. %rite a program to evaluate the arithmetic statement-

111111E1

61. %hat are the two instruction needed in the basic computer in order to set the ' flip flop to

%G(ACB,*C((H',6))9(DCHBI)
63. %hat do you mean by instruction cycle and interrupt cycle? (raw the flowchart for

instruction *ycle"
64. %hat do you mean by fi$ed point representation? '$plain the various integer

representations with suitable e$ample"

65. %hat is input,output interface? (raw and e$plain bloc) diagram of input,output

interface"
66. '$plain register transfer language" 67. '$plain priority interrupt in detail" 68. '$plain architecture of computer system" 69. (efine strobe control" 70. '$plain the organi&ation of virtual memory" 71. '$plain *AM"

72. '$plain memory,reference instructions"

73. '$plain data transfer and manipulation instruction"

74. (efine the following(i) (ii) (iii) *rossbar switch Multistage switch Hypercube connection

75. '$plain interprocessor communication and synchroni&ation" 76. '$plain daisy chain priority" 77. '$plain decimal arithmetic unit" 78. '$plain branch instructions" 79. (etermine the number of cloc) cycles that it ta)es to process !EE tas) in a si$ segment pipeline" 80. %hy does (MA have priority over *1; when both when both re<uest a memory transfer?