DOC/LP/01/28.02.

02
LESSON PLAN
SubCode/Name:EC2303-COMPUTER ARCHITECTURE &
ORGANIZATIO
N
Unit : I

Branch : EC

LP EC2303
LP Rev. No: 01
Date: 01/07/2011

Semester: V
Page 01 of 06

UNIT I :
INTRODUCTION
Syllabus:
Computing and Computers, Evolution of Computers, VLSI Era, System DesignRegister Level, Processor - Level, CPU Organization, Data Representation, Fixed Point
Numbers, Floating Point Numbers, Instruction Formats, Instruction Types. Addressing
modes.
Objective:
To have a thorough understanding of the basic structure, design and operation of a
digital computer.
Session
No.
1.

Topics to be covered

Time

Ref

Functional units of a computer and basic operational

concepts

50m

1(1-11)

2.

Evolution of Computers The different Generations

50m

BB

3.

VLSI Era ICs, Processor Architecture, System

Architecture
System Design System representation, Design Process,
the gate level
Register Level Register level components,
programmable logic devices, register level design
Processor Level Processor level components,
processor level design
CPU Organization Fundamentals, additional features
Data Representation - Fixed Point Numbers, Floating
Point Numbers
Instruction Formats, Instruction Types.

50m

1(12-34),
2 (19-21),
5(1-37)
1(35-55)

BB

50m

1(64-82)
5(38-80)
1(83-113)

50m

1(114-125)

BB

50m
50m

1(137-159)
1(160-177)

BB
BB

50m

BB

Addressing modes

50m

1(178-210),
2(48-56)
1(178-210),
2(48-56)

CONTINUOUS ASSESSMENT TEST 1

50 m

4.
5.
6.
7.
8.
9.
10.

50m

Teaching
Method
BB

BB

BB

BB

DOC/LP/01/28.02.02
LESSON PLAN
SubCode/Name:EC2303-COMPUTER ARCHITECTURE &
ORGANIZATI
ON
Unit : II

Branch : EC

LP EC2303
LP Rev. No: 01
Date: 01/07/2011

Semester: V
Page 02 of 06

UNIT II :
DATA PATH DESIGN
Syllabus:
Fixed Point Arithmetic, Addition, Subtraction, Multiplication and Division,
Combinational and Sequential ALUs, Carry look ahead adder, Robertson algorithm, booths
algorithm, non-restoring division algorithm, Floating Point Arithmetic, Coprocessor, Pipeline
Processing, Pipeline Design, Modified booths Algorithm.
Objective:
To discuss in detail the operation of the arithmetic unit including the algorithms &
implementation of fixed-point and floating-point addition, subtraction, multiplication &
division.
Session
No.

Topics to be covered

Time

Ref

Teaching
Method

1(223-227)
2(369-371)
1(228-232)
2(371-375)
1(233-238)
2(383-389)
4(197-205)
1(238-239)
1(239-244)
2(380-382)
1(245-251)
2(390-392)
4(206-213)
1(252-255)
1(256-265)
1(266-271)
2(393-400)
4(219-233)
1(272-275)

BB

11

Fixed Point Arithmetic Basic adders and subtractors

50m

12

High Speed Adders Carry-lookahead adder

50m

13

Multiplication Twos complement Multiplier

50m

14
15

Robertson algorithm
Booths algorithm

50m
50m

16

Division algorithm

50m

17
18
19

Combinational ALUs
Sequential ALUs
Floating Point Arithmetic - Basic Operations, Floating
Point Units, Addition Algorithm

50m
50m
50m

20

Coprocessor, Pipeline Processing, Pipeline Design

CONTINUOUS ASSESSMENT TEST II

50m
50 m

BB
BB

BB
BB
BB
BB
BB
BB

DOC/LP/01/28.02.02

LESSON PLAN
SubCode/Name:EC2303-COMPUTER ARCHITECTURE &
ORGANIZATIO
N
Unit : III

Branch : EC

LP EC2303
LP Rev. No: 01
Date: 01/07/2011

Semester: V
Page 03 of 06

UNIT III :

CONTROL DESIGN

Syllabus:
Hardwired Control, Microprogrammed Control, Multiplier Control Unit, CPU Control
Unit, Pipeline Control, Instruction Pipelines, Pipeline Performance, Superscalar Processing,
Nano Programming.
Objective:
To study in detail the different types of control and the concept of pipelining
Session
No.
21
22

Time

Ref

Control Design Basic Concepts

Hardwired control Design Methods

50m
50m
50m
50m

25

Hardwired control Design Examples

Micro programmed control-micro instructions, micro
program sequencing
Micro programmed control

1(303-308)
1(308-331)
5(332-346)
1(308-331)
1(332-343)

26
27
28

Multiplier Control Unit

CPU Control Unit
Pipeline Control Instruction Pipeline

50m
50m
50m

29
30

Pipeline basics and performance

Superscalar Processing, Nano Programming

50m
50m

CONTINUOUS ASSESSMENT TEST - III

50 m

23
24

Topics to be covered

50m

1(332-343)
5(348-380)
1(344-353)
1(354-361)
1(364-371)
4(289-290)
1(371-383)
1(384-390)
2(481-486)

Teaching
Method
BB
BB
BB
BB
BB
BB
BB
BB
BB
BB

DOC/LP/01/28.02.02
LESSON PLAN

LP EC2303

SubCode/Name:EC2303-COMPUTER ARCHITECTURE &

ORGANIZATIO
N

LP Rev. No: 01
Date: 01/07/2011

Unit : IV

Branch : EC

Semester: V
Page 04 of 06

UNIT IV :

MEMORY ORGANIZATION

Syllabus:
Random Access Memories, Serial - Access Memories, RAM Interfaces, Magnetic
Surface Recording, Optical Memories, multilevel memories, Cache & Virtual Memory,
Memory Allocation, Associative Memory.
Objective:
To study the hierarchical memory system including cache memories and virtual
memory.
Session
No.
31

Topics to be covered

Time

Ref

Random Access Memories Organization, Design

50m

32

Serial - Access Memories Access methods, Organization,

50m

1(407-417)
2(292-308)
1(418-421)

33

Magnetic surface recording

Optical Memories, Multilevel Memories

50m

34

Cache Memories Main features, Organization, Operation

50m

35

Virtual memory-address translation methods

50m

36
37

Memory Allocation
Associative Memory

50m
50m

38
39
40

Non-preemptive allocation
Preemptive allocation
Replacement policies

50m
50m
50m

CONTINUOUS ASSESSMENT TEST - IV

50m

1(424-431)
2(352-357)
5(483-485)
1(452-457)
2(314-325)
4(335-345)
1(428-432)
2(337-343)
4(371-382)
5(496-513)
1(443-452)
1(458-462)
5(485-491)
1(443-452)
1(443-452)
1(443-452)

DOC/LP/01/28.02.02

Teaching
Method
BB
BB
BB
BB
BB

BB
BB
BB
BB
BB

LESSON PLAN
SubCode/Name:EC2303-COMPUTER ARCHITECTURE &
ORGANIZATI
ON
Unit : V

Branch : EC

LP EC2303
LP Rev. No: 01
Date: 01/07/2011

Semester: V
Page 05 of 06

UNIT V :

SYSTEM ORGANIZATION

Syllabus:
Communication methods, Buses, Bus Control, Bus Interfacing, Bus arbitration, IO
and system control, IO interface circuits, Handshaking, DMA and interrupts, vectored
interrupts, PCI interrupts, pipeline interrupts, IOP organization, operation systems,
multiprocessors, fault tolerance, RISC and CISC processors, Superscalar and vector
processor.
Objective:
To study the different ways of communicating with I/O devices and standard I/O
interfaces
Session
No.
41
42
43
44
45
46
47
48
49
50

Topics to be covered
Communication methods Basic Concepts, Buses
Bus Control, Interfacing, Arbitration
IO and system control - IO interface circuits, Handshaking
DMA Direct Memory Access
Interrupts - vectored interrupts
PCI interrupts, Pipeline interrupts
IOP organization, Operation systems
Multiprocessors
Fault Tolerance
RISC and CISC processors, Superscalar and vector processor
CONTINUOUS ASSESSMENT TEST -V

Time

Ref

50m
50m
50m
50m
50m
50m
50m
50m
50m
50m
50m

1(480-483)
1(491-504)
1(504-510)
1(511-515)
1(515-519
1(519-523)
1(525-538)
1(550-565)
1(567-578)
3(282-290)

Teaching
Method
BB
BB
BB
BB
BB
BB
BB
BB
BB
BB

DOC/LP/01/28.02.02
LESSON PLAN

LP EC2303

SubCode/Name:EC2303-COMPUTER ARCHITECTURE &

ORGANIZATION

LP Rev. No: 01

Branch : EC

Date: 01/07/2011

Semester: V

Page 06 of 06

Course Delivery Plan:

Week

I II

I II
1

I II

I II
2

I II

I II

I II I II
3

I II

10

11

12

I II I II
4

I II

13
I

Units

CAT I

CAT II

CAT III

CAT IV

CAT V

TEXTBOOKS:
1.

John P.Hayes, Computer architecture and Organisation, Tata McGraw-Hill, Third

edition, 1998.

2.

V.Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, Computer

Organisation, V edition, McGraw-Hill Inc, 1996.

REFERENCES:
3.

Morris Mano, Computer System Architecture, Prentice-Hall of India, 2000.

4.

Behrooz Parhami, Computer Architecture, Oxford Press.

5.

P.Pal Chaudhuri, , Computer organization and design, 2nd Ed., Prentice Hall of
India, 2007.

6.

G.Kane & J.Heinrich, MIPS RISC Architecture , Englewood cliffs, New Jersey,
Prentice Hall, 1992.
Prepared by

Approved by

Signature

Sd/-

Sd/-

Name
Designation
Date

GANESH VAIDYANATHAN S
ASSOCIATE PROFESSOR
01/07/2011

PROF. E.G. GOVINDAN

HOD/EC
01/07/2011