Sbc312 Hardware Reference Manual

GE
Intelligent Platforms
Hardware Reference Manual

SBC312 3U VPX Single Board Computer
Edition 1
Publication No. SBC312-HRM/1
Document History
Edition
1
Date
November 2010
Board Artwork Revision

Rev 1
Waste Electrical and Electronic Equipment (WEEE) Returns

GE Intelligent Platforms Limited is registered with an approved Producer Compliance Scheme (PCS) and,
subject to suitable contractual arrangements being in place, will ensure WEEE is processed in
accordance with the requirements of the WEEE Directive.
GE Intelligent Platforms Limited will evaluate requests to take back products purchased by our
customers before August 13, 2005 on a case by case basis. A WEEE management fee may apply.
2 SBC312 3U VPX Single Board Computer
About this Manual

Conventions
Numbers
Allnumbersareexpressedindecimal,exceptaddressesandmemoryorregister
data,whichareexpressedinhexadecimal.Whereconfusionmayoccur,decimal
numbershaveaDsubscriptandbinarynumbershaveabsubscript.Theprefix
0xshowsahexadecimalnumber,followingtheCprogramminglanguage
convention.Thus:
Onedozen=12D=0x0C=1100b
Themultipliersk,MandGhavetheirconventionalscientificandengineering
meaningsof*103,*106and*109respectively.Theonlyexceptiontothisisinthe
descriptionofthesizeofmemoryareas,whenK,MandGmean*210,*220and
*230respectively.
NOTE
When describing transfer rates, k, M and G mean *103, *106 and *109 not *210, *220 and *230.
InPowerPCterminology,multiplebitfieldsarenumberedfrom0tonwhere0isthe
MSBandntheLSB.PCIterminologyfollowsthemorefamiliarconventionthatbit0
istheLSBandntheMSB.
Text
Signalnamesendingwithatilde(~)ordenoteactivelowsignals;allothersignalsare
activehigh.NandPdenotethelowandhighcomponentsofadifferentialsignal
respectively.
Notices
Thismanualusesthefollowingtypesofnotice:
NOTE
Notes call attention to important features or instructions.
WARNING
Warnings alert you to the risk of severe personal injury.
CAUTION
Cautions alert you to system danger or loss of data.
TIP
Tips give guidance on procedures that may be tackled in a number of ways.
LINK
Links go to other documents or websites. The purple link color may also be used within a body of text
or paragraph to indicate a link (or hyperlink) to a different part of the same document.
About this Manual 3
Further Information
GE Intelligent Platforms Documents
ThisdocumentisdistributedviaCDROMandtheinternet.TheCDROMallows
privilegedaccesstoanInternetresourcecontainingthelatestupdateddocuments.
Alternatively,youmayregisterforaccesstoallmanualsviathewebsitewhoselink
isgivenbelow.
LINKS
PMC Installation Application Note, publication number HN4/2-99.
VPX I/O Modules Hardware Reference Manual, publication number VPXIOM-0HH.
AXISFlow Programmers Guide, publication number AXISFLOW-0HU.
Radstone Signal Processing Library Manual, publication number RSPL-0HL.
Vector Signal and Image Processing Library Manual, publication number VSIPL-0HL.
AXISView Applications Software User Guide, publication number AXISVIEW-0HU.
Third Party Documents

DuetothecomplexityofsomeofthepartsusedontheSBC312,itisnotpossibleto
includethedetaileddataonallsuchdevicesinthismanual.Alistofthespecifications
anddatasheetsthatprovideanyadditionalinformationrequiredfollows:
Specifications IEEE1101.11998
IEEEStandardforMechanicalCoreSpecificationsfor
Microcomputers.
IEEE1101.21992
ConductioncooledVMEmechanics.
IEEE1101.101996
AdditionalMechanicalSpecifications.
IEEEP1386.12001
StandardPhysicalandEnvironmentalLayersforPCI
MezzanineCards:PMC.
ANSI/VITA202001
ConductionCooledPMC.
ANSI/VITA322003
ProcessorPMC.
ANSI/VITA392003
PCIXforPMCandProcessorPMC.
ANSI/VITA42.02008
XMC.
ANSI/VITA42.32006 XMCPCIExpressProtocolLayerStandard.
ANSI/VITA46.02007 VPXBaseStandard.
VITA46.4(Draft)
PCIExpressonVPX.
VITA46.9(Draft)
XMCandPMCUserI/OMappingforVPX.
VITA46.11(Draft)
SystemManagementonVPX.
ANSI/VITA652010
OpenVPXSystemSpecification.
PCILocalBusSpecificationRevision2.1,PCISpecialInterestGroup.
Thesearethelatestversionsattimeofwriting;checkassociatedwebsitesforlater
updates.
NOTE
Registration may be required for access to these specifications.
Component QorIQP4080IntegratedProcessorHardwareSpecifications,Freescale
Information Semiconductor.
P4080QorIQIntegratedMulticoreCommunicationProcessorReferenceManual,
FreescaleSemiconductor.
AnIntroductiontotheQorIQPlatformsTrustArchitecture,Freescale
Semiconductor.
StandardforPhysicalConnectionforHighSpeedSerialTrace,Power.org.
89HPES32NT24xG2PCIExpressSwitchUserManual,IDT.
LatticeSemiconductorReferenceDesign1011UniversalAsynchronous
Receiver/Transmitter.
NOTE
Access to these documents may require a Non-Disclosure Agreement to be in place with the
component vendor. Contact the manufacturer for more information.
GE Web Site
InformationregardingallGEIntelligentPlatformsproductscanbefoundonthe
followingwebsite:
LINK
http://www.ge-ip.com/products/family/embedded-systems/
Third Party Web Sites

ManufacturersofmanyofthedevicesusedontheSBC312maintainFTPorweb
sites.Someusefulsitesare:
http://www.vita.com
ForVITAandANSI/VITAstandards.
http://www.ieee.com
ForIEEEstandards.
http://www.pcisig.org
ForPCIBusstandards.
http://www.freescale.com/
ForP4080processorinformation.
http://www.idt.com/
ForPCIExpressinformation.
NOTE
Registration may be required for access to standards.
About this Manual 5
Technical Support Contact Information

TechnicalassistancecontactdetailscanbefoundonthewebsiteSupportLocator
page.TheappropriatelocationisheadedDSP,SBCs,MultiprocessorsandGraphics
(formerlyRadstone).
LINK
http://www.ge-ip.com/support/embeddedsupport/locator.
QuerieswillbeloggedontheTechnicalSupportdatabaseandallocatedaunique
ServiceRequest(SR)numberforuseinfuturecorrespondence.
Alternatively,youmayalsocontactGEIntelligentPlatformsTechnicalSupportvia:
LINK
support.towcester.ip@ge.com
TELEPHONE
+44 (0) 1327 322760
Returns
Ifyouneedtoreturnaproduct,thereisaReturnMaterialsAuthorization(RMA)
requestformthatcanbeprintedoutandfilledin,availableviathewebsiteRepairs
page.
LINK
http://www.ge-ip.com/support/embeddedsupport/rmalocator.
FollowtheDownloadRMA Request Form (Word Doc)hyperlinkunderDSP,SBCs,

MultiprocessorsandGraphics(FormerlyRadstone).
Donotreturnproductswithoutfirstcontactingthefactory.
Contents
1 Introduction .............................................................................................................................................. 14
1.1 Safety Notices....................................................................................................................................................................................... 15
1.1.1 Flammability .....................................................................................................................................................................................................15
1.1.2 EMI/EMC Regulatory Compliance ...........................................................................................................................................................15
1.1.3 Cooling.................................................................................................................................................................................................................16
1.1.4 Handling..............................................................................................................................................................................................................16
1.1.5 Heatsink ..............................................................................................................................................................................................................16
2 Unpacking.................................................................................................................................................. 17
2.1 Box Contents Checklist .................................................................................................................................................................... 17
2.2 Identifying Your Board...................................................................................................................................................................... 18
3 Configuration ........................................................................................................................................... 19
3.1 Link Configuration .............................................................................................................................................................................. 19
3.2 Inspection ............................................................................................................................................................................................... 20
3.3 Link Descriptions................................................................................................................................................................................. 20
3.3.1 PMC 5V VIO Selection Link (P8) .................................................................................................................................................................20
3.3.2 Boot Area Selection (P9 Pins 1 to 4)........................................................................................................................................................20
3.3.3 MRAM Write Enable Link (P9 Pins 5 and 6)..........................................................................................................................................21
3.3.4 Flash Protection Unlock Link (P9 Pins 7 and 8)..................................................................................................................................21
3.3.5 JTAG Scanbridge Output Enable Link (P9 Pins 9 and 10) .............................................................................................................21
3.4 Software Board Configuration ..................................................................................................................................................... 22

3.4.1 P4080 Cores 4 to 7 Disable ........................................................................................................................................................................22
3.4.2 P4080 UART Configuration.........................................................................................................................................................................22
3.5 Mezzanine Installation...................................................................................................................................................................... 23

3.5.1 PMC Installation...............................................................................................................................................................................................23
3.5.2 XMC Installation...............................................................................................................................................................................................24
4 Installation and Power Up/Reset.................................................................................................... 25

4.1 Power Supply Requirements ......................................................................................................................................................... 25
4.2 Board Keying......................................................................................................................................................................................... 25
4.3 Board Installation Notes.................................................................................................................................................................. 25
4.4 Connecting to SBC312 ..................................................................................................................................................................... 26
4.5 Reset & Power-up Sequence......................................................................................................................................................... 26
5 Functional Description......................................................................................................................... 27
5.1 Features .................................................................................................................................................................................................. 28
5.2 Integrated Host Processor ............................................................................................................................................................. 29
5.2.1 PowerPC Processing Cores ........................................................................................................................................................................29
5.2.2 Trust Architecture...........................................................................................................................................................................................30
5.2.3 Memory Map.....................................................................................................................................................................................................30
5.2.4 Reset Configuration Word ..........................................................................................................................................................................30
5.2.5 Local Bus.............................................................................................................................................................................................................31
5.2.6 Local Bus Memory Map ...............................................................................................................................................................................31
5.2.7 Processor Power Management................................................................................................................................................................31
5.3 RAM............................................................................................................................................................................................................ 32
5.4 NOR Flash ............................................................................................................................................................................................... 33
5.4.1 Boot Flash...........................................................................................................................................................................................................34
5.4.2 User Flash...........................................................................................................................................................................................................34
5.4.3 Paged Flash Mode..........................................................................................................................................................................................34
5.4.4 Flash Sector Protection................................................................................................................................................................................35
Contents 7
5 Functional Description (continued)

5.5 SPI Serial Flash ..................................................................................................................................................................................... 36
5.6 NAND Flash Solid State Drive........................................................................................................................................................ 36
5.7 MRAM........................................................................................................................................................................................................ 36
5.8 VPX Interface......................................................................................................................................................................................... 37
5.8.1 OpenVPX Compatibility ................................................................................................................................................................................37
5.8.2 PCI Express.........................................................................................................................................................................................................37
5.8.3 REF_CLK ..............................................................................................................................................................................................................38
5.8.4 AUX_CLK .............................................................................................................................................................................................................38
5.8.5 Module Maskable Reset...............................................................................................................................................................................38
5.8.6 Global Discrete.................................................................................................................................................................................................39
5.9 I/O............................................................................................................................................................................................................... 39
5.9.1 Serial Communication Ports......................................................................................................................................................................39
COM1 and COM2.......................................................................................................................................................................................................................... 39
COM3 and COM4.......................................................................................................................................................................................................................... 40
Host-to-BMM Serial Port........................................................................................................................................................................................................... 41
5.9.2 Ethernet...............................................................................................................................................................................................................41
5.9.3 USB ........................................................................................................................................................................................................................42
5.9.4 SATA ......................................................................................................................................................................................................................42
5.9.5 GPIO ......................................................................................................................................................................................................................42
5.10 Mezzanines.......................................................................................................................................................................................... 44
5.10.1 PMC/XMC Site.................................................................................................................................................................................................44
5.10.2 PCI Mezzanine Cards (PMCs) ...................................................................................................................................................................44
5.10.3 PCI Express Mezzanine Cards (XMCs)..................................................................................................................................................44
5.10.4 I/O Routing ......................................................................................................................................................................................................45
5.11 PCI Express Infrastructure ........................................................................................................................................................... 47

5.11.1 P4080.................................................................................................................................................................................................................47
5.11.2 PCI Express Switch.......................................................................................................................................................................................48
5.12 I2C Buses............................................................................................................................................................................................... 49

5.12.1 Addressing.......................................................................................................................................................................................................49
5.12.2 I2C Bus 1............................................................................................................................................................................................................50
5.12.3 I2C Bus 2............................................................................................................................................................................................................50
5.12.4 I2C Bus 3............................................................................................................................................................................................................50
5.12.5 I2C Bus 4............................................................................................................................................................................................................50
5.12.6 I2C Reset ...........................................................................................................................................................................................................50
5.12.7 P4080 Config EEPROM ...............................................................................................................................................................................50
5.12.8 DIP Switch........................................................................................................................................................................................................51
5.12.9 Real Time Clock.............................................................................................................................................................................................51
5.12.10 Elapsed-Time Indicator...........................................................................................................................................................................51
5.12.11 Temperature Sensors ..............................................................................................................................................................................52
5.12.12 Power Manager..........................................................................................................................................................................................52
5.12.13 Board Management Microcontroller................................................................................................................................................53
5.13 Timers .................................................................................................................................................................................................... 54

5.13.1 Watchdog Timers.........................................................................................................................................................................................54
5.14 AXIS Support....................................................................................................................................................................................... 55
5.14.1 AXIS Timer........................................................................................................................................................................................................55

5.14.2 Mailboxes.........................................................................................................................................................................................................55
5.14.3 Semaphores ...................................................................................................................................................................................................55
5.15 Power Sequencing........................................................................................................................................................................... 56

5.15.1 On-board Sequencing................................................................................................................................................................................56
5.15.2 Inter-board Sequencing............................................................................................................................................................................56
5.16 Resets and Interrupts..................................................................................................................................................................... 57
5.16.1 Hard Reset.......................................................................................................................................................................................................57

5.16.2 External Interrupt.........................................................................................................................................................................................58
5.17 FPGA ....................................................................................................................................................................................................... 59
5 Functional Description (continued)

5.18 Control and Status Registers...................................................................................................................................................... 60
5.18.1 Board ID Register (Offset 0x0000) ........................................................................................................................................................61
5.18.2 Revision Register (Offset 0x0002) .........................................................................................................................................................61
5.18.3 Address Register (Offset 0x0006)..........................................................................................................................................................61
5.18.4 Power-On Configuration Register (Offset 0x0008) .......................................................................................................................61
5.18.5 Board Configuration Register 1 (Offset 0x000A)............................................................................................................................62
5.18.6 Board Configuration Register 2 (Offset 0x000C)............................................................................................................................62
5.18.7 RAM/Flash Configuration Register (Offset 0x000E) ......................................................................................................................63
5.18.8 Reset Cause Register (Offset 0x0010).................................................................................................................................................63
5.18.9 Link Status Register (Offset 0x0012)....................................................................................................................................................64
5.18.10 Control Register 1 (Offset 0x0014).....................................................................................................................................................64
5.18.11 Serial Control Register (Offset 0x0016)............................................................................................................................................65
5.18.12 Control Register 3 (Offset 0x001A).....................................................................................................................................................65
5.18.13 Test Pattern Registers 1 to 6 (Offsets 0x0020 to 0x002A) ......................................................................................................66
5.18.14 Scratchpad Registers (Offsets 0x0030 to 0x003E).....................................................................................................................66
5.18.15 Board Semaphore Registers (Offsets 0x0040 to 0x007C) ......................................................................................................67
5.18.16 Watchdog 0 Control Register 1 (Offset 0x2000) and Watchdog 1 Control Register 1 (Offset 0x2010).............67
5.18.17 Watchdog 0 Control Register 2 (Offset 0x2002) and Watchdog 1 Control Register 2 (Offset 0x2012).............67
5.18.18 Watchdog 0 Interrupt Value Register 1 (Offset 0x2004) and
Watchdog 1 Interrupt Value Register 1 (Offset 0x2014)........................................................................................................68
Watchdog 1 Interrupt Value Register 2 (Offset 0x2016)........................................................................................................68
5.18.20 Board Interrupt Status Register (Offset 0x4002).........................................................................................................................68
5.18.21 P4080 Interrupt INT0 Mask Register (Offset 0x4012)................................................................................................................69
5.18.23 P4080 Interrupt INT5 Mask Register (Offset 0x401A)................................................................................................................69
5.18.24 P4080 Interrupt INT6 Mask Register (Offset 0x401E)................................................................................................................69
5.18.27 REFCLK Counter High, Mid and Low Value Registers (Offsets 0x6000 to 0x6006)......................................................70
5.18.28 Counter Control Register (Offset 0x6008) ......................................................................................................................................70
5.18.29 REFCLK/AUXCLK Control Register (Offset 0x600A).....................................................................................................................70
5.18.30 AUXCLK Counter High and Low Value Registers (Offsets 0x600C & 0x600E)................................................................71
5.18.31 AXIS Semaphore Registers (Offsets 0x6020 to 0x603C)..........................................................................................................71
5.18.32 FIFO Data Registers (Offsets 0x6040 to 0x604C .........................................................................................................................71
5.18.33 FIFO Status Registers (Offsets 0x6050 to 0x605C).....................................................................................................................72
5.18.34 GPIO Registers ............................................................................................................................................................................................72
5.19 JTAG........................................................................................................................................................................................................ 73
5.19.1 Boundary Scan..............................................................................................................................................................................................73
5.19.2 Processor Debug Header .........................................................................................................................................................................74
5.19.3 FPGA Programming Header....................................................................................................................................................................74
5.20 LEDs ........................................................................................................................................................................................................ 75

5.20.1 Power Good LED (DS200)..........................................................................................................................................................................75
5.20.2 BIT LEDs (DS201 to DS204).......................................................................................................................................................................76
5.20.3 SATA Activity LEDs (DS205 and DS206)..............................................................................................................................................76
5.20.4 Reset Status LED (DS207) .........................................................................................................................................................................76
5.20.5 Ethernet PHY 1 Link Status LEDs (DS208 to DS211) .....................................................................................................................77
5.20.6 PCI Express Switch Link Status LEDs (DS212 to DS215) .............................................................................................................77
5.21 Front Panel .......................................................................................................................................................................................... 78
5.21.1 Air-cooled Versions (Build Levels 1 to 3)............................................................................................................................................78

5.21.2 Conduction-cooled Versions (Build Levels 4 and 5) .....................................................................................................................78
Contents 9
6 Connectors ................................................................................................................................................ 79
6.1 Backplane Connectors ..................................................................................................................................................................... 81
6.1.1 P0 ..........................................................................................................................................................................................................................81
6.1.2 Backplane J0.....................................................................................................................................................................................................81
6.1.3 P1 ..........................................................................................................................................................................................................................82
6.1.4 Backplane J1.....................................................................................................................................................................................................82
6.1.5 P2 ..........................................................................................................................................................................................................................83
6.1.6 Backplane J2.....................................................................................................................................................................................................84
6.1.7 Signal Definitions ............................................................................................................................................................................................85
6.2 PMC Connectors.................................................................................................................................................................................. 87

6.2.1 J11 and J12 .......................................................................................................................................................................................................87
6.2.2 J13 and J14 .......................................................................................................................................................................................................88
6.2.3 Signal Descriptions.........................................................................................................................................................................................89
6.3 XMC Connectors.................................................................................................................................................................................. 90

6.3.1 J15 .........................................................................................................................................................................................................................90
6.3.2 J16 .........................................................................................................................................................................................................................91
6.3.3 Signal Descriptions.........................................................................................................................................................................................92
6.4 JTAG Pass Thru Header (P7)........................................................................................................................................................... 92

6.5 Aurora Debug Header (J3).............................................................................................................................................................. 93
6.6 Test Access Card Connector (P4)................................................................................................................................................. 94
A Specifications........................................................................................................................................... 95
A.1 Mechanical Specification................................................................................................................................................................ 95
A.2 Technical Specification .................................................................................................................................................................... 95
A.3 Environmental Specifications ....................................................................................................................................................... 96
A.4 Electrical Specification..................................................................................................................................................................... 97
A.5 Reliability (MTBF).................................................................................................................................................................................. 98
A.6 Product Codes...................................................................................................................................................................................... 99
A.7 Software Support..............................................................................................................................................................................100
A.7.1 Boot Firmware .............................................................................................................................................................................................. 100
A.7.2 Built In Test ..................................................................................................................................................................................................... 100
A.7.3 Background Condition Screening........................................................................................................................................................ 101
A.8 I/O Modules .........................................................................................................................................................................................101
Glossary........................................................................................................................................................... 102
Index ................................................................................................................................................................. 103
List of Tables
Table 3-1 P8 Jumper Functions ................................................................................................................................................................ 20
Table 3-2 P9 Pins 1 to 4 Jumper Functions......................................................................................................................................... 20
Table 3-3 P9 Pins 5 and 6 Jumper Function ....................................................................................................................................... 21
Table 3-4 P9 Pins 7 and 8 Jumper Function ....................................................................................................................................... 21
Table 3-5 P9 Pins 9 and 10 Jumper Function..................................................................................................................................... 21
Table 5-1 Processor Specifications ......................................................................................................................................................... 29
Table 5-2 Local Bus Chip Select Targets............................................................................................................................................... 31
Table 5-3 SDRAM Configurations ............................................................................................................................................................. 32
Table 5-4 Flash Options ................................................................................................................................................................................ 33
Table 5-5 Boot Image Selection by Link................................................................................................................................................ 34
Table 5-6 Backplane PCI Express Port Configurations (Lanes 16 to 23)................................................................................ 37
Table 5-7 COM1/COM2 Signal Availability ........................................................................................................................................... 39
Table 5-8 SBC310-compatible COM2 Signal Availability .............................................................................................................. 40
Table 5-9 Baud Rates..................................................................................................................................................................................... 40
Table 5-10 COM3/COM4 Signal Availability......................................................................................................................................... 41
Table 5-11 P4080 Network Interface Mapping ................................................................................................................................. 41
Table 5-12 ETH0/ETH1 Pin Mapping....................................................................................................................................................... 41
Table 5-13 USB0/USB1 Signal Availability ........................................................................................................................................... 42
Table 5-14 SATA Signal Availability ......................................................................................................................................................... 42
Table 5-15 GPIO Line Routing .................................................................................................................................................................... 42
Table 5-16 PMC/XMC Site Signal Availability (X20d24s XMC I/O).............................................................................................. 45
Table 5-17 PMC/XMC Site Signal Availability (Full PMC I/O) ......................................................................................................... 46
Table 5-18 PCI Bus........................................................................................................................................................................................... 47
Table 5-19 PCI Express Switch Connections....................................................................................................................................... 48
Table 5-20 I2C Bus Addresses .................................................................................................................................................................... 49
Table 5-21 PCA9560 Pin Allocation ......................................................................................................................................................... 51
Table 5-22 Power Manager Monitor Points......................................................................................................................................... 52
Table 5-23 BMM Address Allocation ....................................................................................................................................................... 53
Table 5-24 SMB Address Allocation ........................................................................................................................................................ 53
Table 5-25 External Interrupt Inputs to P4080 .................................................................................................................................. 57
Table 5-26 P4080 PCI INTx and External IRQ sharing .................................................................................................................... 58
Table 5-27 Control and Status Registers.............................................................................................................................................. 60
Table 5-28 Board ID Register ..................................................................................................................................................................... 61
Table 5-29 Revision Register ...................................................................................................................................................................... 61
Table 5-30 Address Register....................................................................................................................................................................... 61
Table 5-31 Power-On Configuration Register .................................................................................................................................... 61
Table 5-32 Board Configuration Register 1......................................................................................................................................... 62
Table 5-33 Board Configuration Register 2......................................................................................................................................... 62
Table 5-34 RAM/Flash Configuration Register................................................................................................................................... 63
Table 5-35 Reset Cause Register.............................................................................................................................................................. 63
Table 5-36 Link Status Register................................................................................................................................................................. 64
Table 5-37 Control Register 1 .................................................................................................................................................................... 64
List of Tables 11
Table 5-38 Serial Control Register ........................................................................................................................................................... 65

Table 5-39 Control Register 3 .................................................................................................................................................................... 65
Table 5-40 Test Pattern Registers............................................................................................................................................................ 66
Table 5-41 Board Semaphore Register Offsets................................................................................................................................. 67
Table 5-42 Watchdog Control Register 1............................................................................................................................................. 67
Table 5-43 Watchdog Interrupt Value Register 1 ............................................................................................................................ 68
Table 5-44 Watchdog Interrupt Value Register 2 ............................................................................................................................ 68
Table 5-45 Board Interrupt Status Register ........................................................................................................................................ 68
Table 5-46 P4080 Interrupt INT0 Mask Register ............................................................................................................................... 69
Table 5-47 Counter Control Register...................................................................................................................................................... 70
Table 5-48 REFCLK Control Register ....................................................................................................................................................... 70
Table 5-49 AXIS Semaphore Register Offsets .................................................................................................................................... 71
Table 5-50 FIFO Data Register Offsets................................................................................................................................................... 71
Table 5-51 FIFO Status Register Offsets ............................................................................................................................................... 72
Table 5-52 FIFO Status Register................................................................................................................................................................ 72
Table 5-53 JTAG Chains................................................................................................................................................................................ 74
Table 5-54 USR_STATUS_BYTE Register Format............................................................................................................................... 74
Table 5-55 BIT LEDs ........................................................................................................................................................................................ 76
Table 5-56 BIT Status LED Meanings...................................................................................................................................................... 76
Table 5-57 SATA Activity LEDs ................................................................................................................................................................... 76
Table 5-58 Ethernet Link Status LEDs .................................................................................................................................................... 77
Table 5-59 PCI Express Switch Link Status LEDs .............................................................................................................................. 77
Table 6-1 Connector Functions................................................................................................................................................................. 79
Table 6-2 P0 Pin Assignments.................................................................................................................................................................... 81
Table 6-3 J0 Pin Assignments.................................................................................................................................................................... 81
Table 6-8 Backplane Connector Signal Definitions ......................................................................................................................... 85
Table 6-9 J11 Pin Assignments ................................................................................................................................................................. 87
Table 6-10 J12 Pin Assignments............................................................................................................................................................... 87
Table 6-13 PMC Signal Descriptions ....................................................................................................................................................... 89
Table 6-16 XMC Signal Descriptions ....................................................................................................................................................... 92
Table 6-17 J3 Pin Assignments ................................................................................................................................................................. 93
Table 6-18 J3 Signal Descriptions............................................................................................................................................................ 93
Table 6-19 P4 Pin Assignments................................................................................................................................................................. 94
Table A-1 Mechanical Construction........................................................................................................................................................ 95
Table A-2 Technical Data ............................................................................................................................................................................. 95
Table A-3 Convection-cooled Environmental Specifications...................................................................................................... 96
Table A-4 Conduction-cooled Environmental Specifications ..................................................................................................... 96
Table A-5 Voltage Supply Requirements .............................................................................................................................................. 97
Table A-6 Current Consumption ............................................................................................................................................................... 97
Table A-7 Reliability (MTBF).......................................................................................................................................................................... 98

Table A-8 Product Options........................................................................................................................................................................... 99
List of Figures
Figure 1-1 SBC312 (Conduction-cooled) General View ................................................................................................................. 14
Figure 1-2 ESD Label (Present on Board Packaging) ...................................................................................................................... 16
Figure 2-1 Box Contents ............................................................................................................................................................................... 17
Figure 2-2 Product Label (Packaging) .................................................................................................................................................... 18
Figure 2-3 Product Label (Product).......................................................................................................................................................... 18
Figure 2-4 Product Label (Conduction-cooled Product)................................................................................................................ 18
Figure 3-1 Link Positions............................................................................................................................................................................... 19
Figure 3-2 PMC/XMC Site Location.......................................................................................................................................................... 23
Figure 5-1 Block Diagram ............................................................................................................................................................................ 27
Figure 5-2 Flash Memory Structure ........................................................................................................................................................ 33
Figure 5-3 User Flash Page Numbering................................................................................................................................................ 34
Figure 5-4 I2C Bus Structure ....................................................................................................................................................................... 49
Figure 5-5 JTAG Chains................................................................................................................................................................................. 73
Figure 5-6 LED Positions............................................................................................................................................................................... 75
Figure 5-7 Air-cooled Front Panel............................................................................................................................................................ 78
Figure 5-8 Conduction-cooled Front Panel ......................................................................................................................................... 78
Figure 6-1 Connector Positions (Top)...................................................................................................................................................... 79
Figure 6-2 Connector Positions (Back)................................................................................................................................................... 80
List of Tables 13
1 Introduction
TheGEIntelligentPlatformsSBC312isamemberoftheVPXtreme3familyof3U
VPXSingleBoardComputers.ItusestheFreescaleP4080QorIQprocessor,which
containseighte500mcPowerPCprocessingcoresrunningatupto1.5GHz,with
dualmemorycontrollersandI/Ointerfaces.TheSBC312offersupto8GBytesof
DDR3SDRAMwithECCandupto512MBytesofNORFlashmemory,alongwith
twoGigabitEthernetchannels,serial,USB2.0andSerialATAinterfaces.Flexible
configurationofserialfabricsisprovidedtosuitavarietyofsysteminterconnect
requirements,withuptoeightlanesofPCIExpressavailableonthebackplane.
TheP4080processorisconnectedtoallonboardPCIdevicesandthemezzaninesite
usingPCIExpressthroughanonblockingswitcharchitecture.One64bitPMCsite
isprovided,supportingPCIXoperationatupto133MHz,allowingforofftheshelf
orcustommezzaninestobefittedtoaddfurtherfunctionalitytotheboard.Thesite
alsosupportsXMCmezzaninecards,supportingax8PCIExpresslinktothesite,for
higherbandwidthconnectivitytothehostandhighspeedrearI/O.
TheSBC312couplesfamiliarsoftwareinterfacesandreliabilitywithhighspeed
fabricinterfaces,offeringsignificantincreasesininterboardbandwidth.
Figure 1-1 SBC312 (Conduction-cooled) General View
1.1 Safety Notices

Thefollowinggeneralsafetyprecautionsrepresentwarningsofcertaindangersof
whichGEIntelligentPlatforms(GEIP)isaware.Failuretocomplywiththeseorwith
specificWarningsand/orCautionselsewhereinthismanualviolatessafety
standardsofdesign,manufactureandintendeduseoftheequipment.GEIPassumes
noliabilityfortheusersfailuretocomplywiththeserequirements.
Alsofollowallwarninginstructionscontainedinassociatedsystemequipment
manuals.
WARNINGS
Use extreme caution when handling, testing and adjusting this equipment. This device may operate in
an environment containing potentially dangerous voltages.
Ensure that all power to the system is removed before installing any device.
To minimize shock hazard, connect the equipment chassis and rack/enclosure to an electrical ground.
If AC power is supplied to the rack/enclosure, the power jack and mating plug of the power cable must
meet IEC safety standards.
1.1.1 Flammability
TheSBC312circuitboardismadebyaULrecognizedmanufacturerandhasa
flammabilityratingofUL94V1.
1.1.2 EMI/EMC Regulatory Compliance

CAUTION
This equipment generates, uses and can radiate electromagnetic energy. It may cause or be
susceptible to EMI if not installed and used in a cabinet with adequate EMI protection
TheSBC312isdesignedusinggoodEMCpracticesand,whenusedinasuitably
EMCcompliantchassis,shouldmaintainthecomplianceofthetotalsystem.The
SBC312alsocomplieswithEN60950(productsafety),whichisessentiallythe
requirementfortheLowVoltageDirective(73/23/EEC).
AircooledbuildlevelsoftheSBC312aredesignedforuseinsystemsmeetingVDE
classB,ENandFCCregulationsforEMCemissionsandsusceptibility.
ConductioncooledbuildlevelsoftheSBC312aredesignedforintegrationintoEMC
hardenedcabinets/boxes.
Introduction 15
1.1.3 Cooling
CAUTION
The SBC312 requires air-flow of at least 300 feet/minute for build levels 1 and 2, and at least
600 feet/minute for build level 3. If a conduction-cooled (level 4 or 5) SBC312 is operating on an
extender card, it requires air-flow of at least 300 feet/minute across it.
1.1.4 Handling
CAUTION
Only handle the SBC312 by the edges or front panel.
Figure 1-2 ESD Label (Present on Board Packaging)
1.1.5 Heatsink
CAUTIONS
Do not remove the heatsink. There are no user-alterable components underneath the heatsink, so
users should have no reason to remove it.
Users should not attempt reattachment of the heatsink, as this requires precise torque on the screws
attaching the heatsink to the PCB. Over-tightening the screws may cause the heatsink to damage
components beneath it. Removal and re-attachment of the heatsink should only be carried out by the
factory.
2 Unpacking
Onreceiptoftheshippingcontainer,ifthereisanyevidenceofphysicaldamage,the
TermsandConditionsofSale(suppliedwithyourdelivery)provideinformationon
whattodo.Ifyouneedtoreturntheproduct,pleasecontactyourlocalGEIPsales
officeoragent.
TheSBC312issealedintoanantistaticbagandhousedinapaddedcardboardbox.
Failuretousethecorrectpackagingwhenstoringorshippingtheboardmay
invalidatethewarranty.
2.1 Box Contents Checklist

1. SBC312inantistaticpackaging.
2. ManualCDROM(designmayvary).
3. EmbeddedSoftwareLicenseAgreement(GFJ353).
Figure 2-1 Box Contents
Unpacking 17
2.2 Identifying Your Board

TheSBC312isidentifiedbylabelsatstrategicpositions.Thesecanbecrosschecked
againsttheAdviceNoteprovidedwithyourdelivery.
Identificationlabels,similartotheexampleshowninFigure22,attachedtothe
shippingboxandtheantistaticbaggiveidenticalinformation:productcode,product
description,equipmentnumberandboardrevision.
Figure 2-2 Product Label (Packaging)
Ontheboardwithintheantistaticbag,thereisanidentifyinglabelsimilartothe
exampleshowninFigure23,attachedtothePCB.
Figure 2-3 Product Label (Product)
Onconductioncooledversionsoftheboard(buildlevels4and5),thereisalsoa
labelsimilartotheexampleshowninFigure24,attachedtothefrontpanel.
Figure 2-4 Product Label (Conduction-cooled Product)
SeetheProductCodeInformationsectioninAppendixAformoredetailsonthe
productcode(SBC312xxxxxxxx).
3 Configuration
3.1 Link Configuration
TheSBC312haspushonjumpersincludedinthestandardkitofparts;additional
jumpersmaybeobtainedonrequest.Thesearesuitableforlevel1to3lowvibration
applications.
TIP
For Level 4 and 5 products, make links by wire-wrapping between the pin posts and then cover these
wire wrapped links with the same conformal coating as that used on the board. This will provide a
reliable connection under heavy shock and vibration conditions and further prevent oxidation of the
connection due to moisture ingress.
Figure 3-1 Link Positions
Figure31showsstandard2.54mmpitchheadersforgeneraluse.
ThismanualreferstojumpersettingsasInorOut.Meaningsareasfollows:
In=jumperfitted
Out=jumpernotfitted
Configuration 19
3.2 Inspection
TheSBC312isshippedfromthefactorywithnojumpersfitted.
3.3 Link Descriptions

NOTES
1.
Ordinary operation requires no jumpers to be fitted.
2.
The states of most of the links can be read from the Link Status Register (register offset 0x0012).
TIP
If you are about to install your board and power-up for the first time, leaving your board in the default
configuration will enable board operation to be proven before tackling any further configuration
issues.
3.3.1 PMC 5V VIO Selection Link (P8)

PMCsmayuse+5Vor+3.3VfortheVIOsignalingvoltage.Thislinkcontrolsthe
VIOsignalingvoltageprovidedbytheSBC312atthePMCsite.Thislinkshouldonly
befittedwhenaPMCthatuses5Vsignalingisinstalled,andshouldbeleftnotfitted
otherwise.
ThestateofthislinkisreflectedintheBoardConfigurationRegister1(registeroffset
0x000A).
Table 3-1 P8 Jumper Functions
Setting
Pin 4 to pin 3
Pin 2 to pin 4
Meaning
VIO signaling voltage is 3.3 V
VIO signaling voltage is 5V
CAUTION
Selection of the wrong VIO signaling voltage may cause damage to the PMC.
3.3.2 Boot Area Selection (P9 Pins 1 to 4)

TheBootFlash(forallprocessingcores)isdividedintofoursections,allowingfor
threedifferentbootimagestobeloadedintotheFlash.Thereisalsoafactory
programmedRecoverybootimage.Theselinksareusedtoselectwhichimageis
usedatboottime.ThestateoftheselinksisreflectedintheLinkStatusRegister
(registeroffset0x0012).
Table 3-2 P9 Pins 1 to 4 Jumper Functions
Pins 1 & 2
Pins 3 & 4
Active Boot Image
Out
Out
Main boot image
In
Out
Alternate boot image
Out
In
Recovery boot image
In
In
Second Alternate boot image
Innormaloperation,theselinksarenotfittedandtheSBC312bootsfromtheMain
bootimage.
3.3.3 MRAM Write Enable Link (P9 Pins 5 and 6)

ThislinkcontrolsthewriteprotectionforthenonvolatileMRAMdeviceonthe
SBC312.Thisdeviceholdsfirmwarebootparametersaswellasuserdata.
ThestateofthislinkisreflectedintheLinkStatusRegister(registeroffset0x0012).
Table 3-3 P9 Pins 5 and 6 Jumper Function
Setting
Out
In
Meaning
The MRAM is write protected
The MRAM is write enabled
NOTE
The VPX backplane Non-Volatile Memory Read Only (NVMRO) signal (on connector P0 pin A4) must also
be set inactive low before the MRAM can be written.
3.3.4 Flash Protection Unlock Link (P9 Pins 7 and 8)

ThislinkmustbefittedtoallowsoftwaretoaltertheFlashpersistentsector
protection,whichremainsunchangedfollowingaresetorapowercycle.Seethe
FlashSectorProtectionsectionforfurtherdetails.
Ifthelinkisnotfitted,thesoftwareispreventedfromalteringanypreviously
configuredsectorprotection.ThestateofthislinkisreflectedintheLinkStatus
Register(registeroffset0x0012).
Setting
Out
In
Meaning
Persistent sector protection cannot be altered
Persistent sector protection can be altered
NOTE
The VPX backplane Non-Volatile Memory Read Only (NVMRO) signal (on connector P0 pin A4) must also
be set inactive low before the persistent sector protection can be altered.
3.3.5 JTAG Scanbridge Output Enable Link (P9 Pins 9 and 10)
TheSBC312usesaJTAGScanbridgedevicetoconnectalloftheJTAGcompliant
devicesontheboard.ThislinkisprovidedtoenabletheScanbridgeduring
boundaryscan.Itshouldnotnormallybefittedindeployedsystemsandmustnot
befittedwhentheProcessorDebugHeader(J3)isinuse.
Setting
Out
In
Meaning
Scanbridge disabled
Scanbridge enabled
Configuration 21
3.4 Software Board Configuration

TheSBC312containsanI2CEEPROMDIPSwitchdevice(seetheI2CBusessection),
whichmaybeusedtoconfigureadditionalboardoptionsundersoftwarecontrol.
TheVPXbackplaneNonVolatileMemoryReadOnly(NVMRO)signal(on
connectorP0pinA4)pulledlowbeforethesesettingscanbemodified.Fordetailson
howtomonitororchangethesesettings,refertotheappropriateSoftwareReference
Manual.
3.4.1 P4080 Cores 4 to 7 Disable

ThisconfigurationoptiondisablesfourcoresoftheP4080processorandtheir
associatedpowersupply,causingtheprocessortoappeartosoftwareasaP4040
quadcoredevice.Thismaybeusedtoachievelowerpoweroperationwhenthe
applicationdoesnotrequiremorethanfourprocessingcores.
ThissettingonlytakeseffectfollowingapowercycleoftheSBC612.Theactivestate
ofthissettingisreflectedinBoardConfigurationRegister1(registeroffset0x000A).
Thedefaultsettingofthisoptionisinactive,suchthatalleightprocessingcoresare
enabled.
3.4.2 P4080 UART Configuration

TheSBC312supportsoperatingtheUARTswithintheP4080inthefollowingmodes,
whichmaybeselectedusingthisconfigurationoption:
COM1andCOM2withflowcontrol
COM1,COM2,COM3andCOM4withoutflowcontrol
SeetheSerialCommunicationPortssectionforcorrespondingpinoutchanges.
ThissettingonlytakeseffectfollowingaresetoftheSBC312.
ThedefaultsettingofthisoptionistousetwoUARTs(COM1andCOM2)withflow
control.
3.5 Mezzanine Installation

Asshowninthediagrambelow,theSBC312hasonemezzaninesitethatsupports
bothIEEEP1386.1compliantPMCsandANSI/VITA42.3compliantXMCs(including
supportforfrontpanelI/O).Thesiteallowsforthefittingofonesinglewidth
PMC/XMC.
3.5.1 PMC Installation

CAUTION
Ensure that the PMC 5V VIO Selection Links (P8) is set according to the requirements of the
corresponding PMC. Damage to the PMC may otherwise result.
PMCssuppliedbyGEIParedeliveredwithafullkitofpartsformountingthem,
fittinginstructionsandamanual(onCDROM).APMCorderedwithanSBC312can
besuppliedfactoryfitted,ifrequired.
LINK
PMC Installation Note, publication number HN4/3-99.
CAUTION
Observe handling and anti-static precautions when fitting the PMC.
Itwillusuallybenecessarytoinstalldriversoftwareorimplementotherfirmware
configurationtoachievefullfunctionalityofaPMC(seethespecificPMCmanualfor
theexactprocedure).
TIP
Where a PMC is not pre-installed, prove operation of the SBC312 before installing the PMC.
Figure 3-2 PMC/XMC Site Location
Configuration 23
3.5.2 XMC Installation

XMCssuppliedbyGEIParedeliveredwithafullkitofpartsformountingthemand
amanual(onCDROM).FittingissimilartoaPMC.AnXMCorderedwithan
SBC312canbesuppliedfactoryfitted,ifrequired.
CAUTION
Observe handling and anti-static precautions when fitting the XMC.
Itwillusuallybenecessarytoinstalldriversoftwareorimplementotherfirmware
configurationtoachievefullfunctionalityofaXMC(seethespecificXMCmanual
fortheexactprocedure).
TIP
Where an XMC is not pre-installed, prove operation of the SBC312 before installing the XMC.
4 Installation and Power Up/Reset

ReviewtheSafetyNoticessectionbeforeinstallingtheSBC312.Thefollowingnotices
alsoapply:
CAUTION
Consult the enclosure documentation to ensure that the SBC312s power requirements are
compatible with those supplied by the backplane.
4.1 Power Supply Requirements

TheSBC312sestimatedpowerrequirementis30Wmaximumwhenoperatingwith
eightprocessingcoresat1.5GHz.NovoltageisrequiredtobesuppliedontheVs1
supplyastheSBC312doesnotconnecttothesepins.
4.2 Board Keying

TheVPXSpecificationrequiresallbackplaneslotstohavetwoguidepins:oneabove
theJ0connectorandonebelowtheJ2connector.Aswellasprovidingcorrect
alignment,thesepinsarekeyedtopreventcardsbeinginsertedintoincorrect
backplaneslot(s)toavoidelectricalincompatibility.
TheSBC320hasreceptaclesfortheseguidepins.Bydefault,thesearenotkeyed.
Contactthefactorytodiscussanykeyingrequirements.
4.3 Board Installation Notes

1. Keyingmaydictatethebackplaneslot(s)intowhichtheSBC312canbeinserted.
2. AircooledversionsoftheSBC312haveinjector/ejectorhandlestoensurethatthe
backplaneconnectorsmateproperlywiththebackplane.Thecaptivescrewsat
thetopandbottomofthefrontpanelallowtheboardtobetightlysecuredin
position,whichprovidescontinuitywiththechassisgroundofthesystem.
3. ConductioncooledversionsoftheSBC312havescrewdrivenwedgelocksatthe
topandbottomoftheboardtoprovidethenecessarymechanical/thermal
interface.Correctadjustmentrequiresacalibratedtorquewrenchwitha
hexagonalheadofsize3/32(2.38mm),settobetween0.6and0.8Nm.
4. Inanaircooleddevelopmentenclosure,whentakingI/Oconnectionsfromthe
backplaneconnectors,useofGEIPI/Omodules(orsomeequivalentsystem)
ensuresoptimumoperationoftheSBC312withregardtoEMI.SeetheVPXI/O
Modulesmanualformoredetails.
LINK
Installation and Power Up/Reset 25
4.4 Connecting to SBC312

TointeractwithonboardfirmwarerequirestheSBC312tohave,asaminimum,a
terminalconnectionpresentontheserialCOM1port.AnEthernetconnectionmay
alsoberequiredforHost/Targetinteraction.Theseportsmaybeaccessedthrough
thebackplanepins,usingareartransitionmodule.
COM1isconfiguredbydefaultasDTEwithsettingsof115200baud,8bits/character,
1stopbit,paritydisabledandnoflowcontrol.
4.4.1 Rear Transition Module

Fordevelopmentsystems,connectiontotheSerialandEthernetI/Ocanbeachieved
usingaRearTransitionModule(RTM).Thisconvertsthecondensedpinoutofthe
backplaneconnectorstopinoutssuitableforusebyindustrystandardconnectors.
Thefollowingitemsarerequired:
TheSBC312
TheappropriateRTM(VPX3UX600rev3orlater)
Anullmodem9wayDtypecableforconnectingCOM1toacontrolterminalor
PCrunningterminalemulationsoftware
FortheEthernetports,aCAT5(orbetter)straightthroughpatchcablefor
10/100/1000BaseTX
TheVPXI/OModulesmanualcontainsmoredetailsonfittingRTMs.Similar
antistaticandsafetyprecautionsapplywhenhandlingand/orinstallingRTMsasfor
theSBC312.
LINK
4.5 Reset & Power-up Sequence

Apowersequencermonitorsthebackplanesupplyvoltagesandwillholdthe
SBC312inresetorshutdowntheonboardpowersuppliesifthebackplanesupplies
arenotwithinspecifiedlimits.
ThegreenPowerGoodLEDislitwhenthebackplaneandallonboardsuppliesare
withinspecification.
The+5Vsupplytothemezzaninecardsisswitched,underthecontrolofthepower
managerdevice,sothatthe5Vand3.3Vsuppliesareappliedtothemezzaninesat
approximatelythesametime.
5 Functional Description
Figure 5-1 Block Diagram
NOTES
Due to the increasingly short lifetimes of system components, the I/O devices used on the SBC312 are not
guaranteed to remain fixed in the future.
Hardware should be accessed only through mechanisms provided by the Operating Systems Board Support
Package, and not directly by application software.
If a standard operating system is not being used, then it is recommended that applications are written in such a
way as to minimize direct access to hardware resources, bearing in mind that changes may be necessary to
support future iterations of the hardware.
GEIP-supported Operating Systems guarantee compatibility at the application level through hardware
independent mechanisms.
Functional Description 27
5.1 Features
FreescaleP4080QorIQIntegratedHostProcessorwitheighte500mcprocessing
coresatupto1.5GHz
Upto4GBytesdualchannelDDR3SDRAMwithECC(2GBytespercontroller)
Upto256MBytesofNORFlashmemorywithenhancedwriteprotection
features
512KBytesNonVolatileRAM
OnemezzaninesitesupportingPMCorXMCmodules.ThePMCinterfacehasa
64bitPCI/PCIXinterfaceandcanoperateatupto133MHz.TheXMCinterface
hasax8PCIExpresslink
PCIExpressboardinterconnectwithnonblockingswitcharchitecture
Upto8lanesofPCIExpresstothebackplane,operatingat2.5or5GHz
Two10/100/1000BaseTEthernetports
UptofourserialCOMports
TwoUSB2.0ports
UptotwoSATAports
Upto8bitsofGeneralPurposeI/Owithinterruptcapability
Realtimeclock
Elapsedtimeindicator
Watchdogtimers
Ambienttemperaturesensors
CompatiblewithrequirementsofVITA65OpenVPXspecification
Capableofbeingusedasapayloadboardwithinsystemsdesignedaroundit
I/OConfigurationsthatarepincompatiblewiththeSBC310
Fiveenvironmentalbuildlevels
5.2 Integrated Host Processor

TheSBC312isbasedaroundtheFreescaleQorIQP4080Eoctalcoreintegratedhost
processor.Thisprovides:
Eighte500mcPowerPCprocessingcoreswithprivateL1andL2caches
Shared2MByteL3PlatformCache
CoreNetfabricbasedinterconnectatupto800MHz
DualDDR3SDRAMcontrollers
16bitlocalbusinterface
TwoGigabitEthernetMACs
PCIExpressinterfaces
DMAcontrollers
SecurityandPatternMatchingEngines
Interruptcontroller
SerialI/Ointerfaces
I2Ccontrollers
Timers
TheSBC312alsosupportstheP4040quadcoreversionoftheprocessororcanrun
theP4080processorasaP4040,tominimizepowerconsumption,byremoving
powertotheupperfourcores.TheBoardConfigurationRegister1(registeroffset
0x000A)showsthephysicalCPUtypefitted.
5.2.1 PowerPC Processing Cores

TheP4080containseighte500mchighperformance,32bit,superscalardualissue
BookEcompliantPowerPCprocessingcores,clockedatupto1.5GHz.Eachcore
includes:
32KByteLevel1instructionanddatacaches
128KByteLevel2backsidecachewithECC
36bitphysicaladdressing
DoublePrecisionFloatingPointUnit
MMUwithembeddedHypervisorprivilegelevel
Table 5-1 Processor Specifications

Processor Type
Core Frequency (MHz)
Platform Frequency (MHz)
Memory Bus Frequency (MHz)
P4080E
1500
800
650
P4080E
1200
600
600
Dependingontheapplication,itispossibleforsoftwaretodynamicallyconfigure
processorstorunatlowerclockfrequenciestominimizepower.
5.2.2 Trust Architecture

TheP4080containsasetofhardwarefeaturesthatsupportatrustedboot
environmentwhereonlytrustedcodemaybeexecutedandhardwarefeaturesthat
couldbeusedtocompromisesecurityaredisabled.Theimplementationofthis
architectureisfullydescribedintheFreescalewhitepaperAnIntroductiontothe
QorIQPlatformsTrustArchitecture.
TheSBC312providestheabilitytoprogramfuseswithintheP4080toconfigure
securitykeys,accesstowhichiscontrolledbythesecuritystateoftheprocessor.
Ifyouwishtousethisfeatureoftheplatform,contactyourlocalGEIPsalesofficeor
agentformoreinformation.
5.2.3 Memory Map

TheP4080supportsafullyprogrammablememorymap,sharedbetweeneachofthe
processingcores.Memorywindowsaresoftwareconfiguredandthehardwaredoes
notcarryoutanyconfigurationofthememorymap.Forthisreason,nomemory
mapsareprovidedinthismanual.
Whereaddressesareprovidedinthismanual,theyarestatedasafixedoffsetfroma
softwareprogrammablebaseaddress.
Refertoapplicablesoftwaremanualsformoreinformation.
5.2.4 Reset Configuration Word

TheP4080processorisconfigured,duringreset,byloadingadatastructurecalled
theResetConfigurationWord(RCW)fromnonvolatilememory.Thisspecifiesthe
operatingfrequencyandnumerousconfigurationoptionsoftheprocessor.
NormallytheRCWisloadedfromfactoryconfiguredsettingswithintheFPGAand
nouserinteractionisrequired.Ifmoresophisticatedconfigurationisrequired,itis
possibletoloadthedatastructurefromanI2CEEPROMinstead,bysettingthe
relevantsoftwareconfigurationoptionintheI2CEEPROMDIPSwitch.
CAUTION
Do not change the source of the RCW unless advised to do so by the factory. Incorrect or invalid
settings may damage the processor or prevent the SBC612 from booting
WhenbootingfromtheRecoverybootarea,thefactoryconfiguredRCWsettingsare
alwaysused.ThisallowstheboardtoberecoveredifthedataintheI2CEEPROMis
invalidorbecomescorrupted.
5.2.5 Local Bus

TheP4080localbusisa16bitmultiplexedaddress/databus,whichisusedtoaccess
thefollowingdevicesontheSBC312:
FPGA
Flash
MRAM
Toreducetheloadingonthelocalbus,theFlashandMRAMdevicesareconnected
toseparatedataandaddressbusescreatedbytheFPGA.
5.2.6 Local Bus Memory Map

Alleightdevicechipselectsforthelocalbusaremadeavailable,sharedbetweenthe
devicesasdefinedinthetablebelow.Theminimumpossiblewindowsizeis
32KBytes.
Table 5-2 Local Bus Chip Select Targets
Chip Select
CS0
Target
Boot Flash
Device Width
16-bit
CS1
User Flash
16-bit
CS2
CS3
Unused
MRAM
Control/Status Registers,
Interrupt Controller
Watchdogs
AXIS registers
Unused
FPGA
- UARTs
- External SRAM
FPGA
- DMA engines
- Internal dual-port SRAM
- GPIO controller
CS4
CS5
CS6
CS7
Required Window Size

8 MBytes
128 MBytes in Paged mode
up to 1 GByte otherwise
8-bit
512 KBytes
32-bit
32 KBytes
8-bit
4 MBytes
16-bit
4 MBytes
5.2.7 Processor Power Management

TheP4080deviceimplementsthefollowingpowermanagementfeatures:
IndependentcontrolofDoze/Napmodesforeachprocessingcore
Devicesleepstate
5.3 RAM
TheP4080containsdual64bitDDR3memorycontrollersandhastheabilityto
interleaveaccessesbetweenthetwocontrollerstofurtherincreasetheavailableRAM
bandwidth.ThecontrollershavefullECCerrorcorrectionsupport,withtheability
todetectmultibiterrorsandcorrectsinglebiterrorswithinanibble.
TheSBC312providesuptoatotalof4GBytesofSDRAMintwobanks,each
connectedtoaseparatememorycontroller.TheRAMconfigurationsaredefined
below.
Table 5-3 SDRAM Configurations
Total RAM
(GBytes)
Number of
Devices
Device Type
Die
Density
Number of Banks/
Controllers
10
1 Gbit monolithic
1 Gbit
10
2 Gbit monolithic
2 Gbit
10
4 Gbit die stack
2 Gbit
10
4 Gbit monolithic
4 Gbit
TheRAM/FlashConfigurationRegister(registeroffset0x000E)showsthe
configurationofRAMfittedtotheboard.
TheP4080processorcontrolsthefrequencyoftheRAMinterface.Table51shows
thepossibleconfigurations.
5.4 NOR Flash

TheSBC312provides256MBytesofFlashmemory,connectedtotheFPGA.The
Flashuses16bitwideSpansionSG29GLfamilydevices,arrangedin128KByte
sectors.TheFlashhasanerasecapacityof100,000cyclespersectorandtypicaldata
retentionof20years.FlashdetailsareavailabletosoftwareviatheRAM/Flash
ConfigurationRegister(registeroffset0x000E).
TheFlashsupportspagemodeaccesses,whichallowstheFlasharraytobeaccessed
in128MBytepagesformaximumbusbandwidth.
CAUTION
Integrity of Flash data cannot be guaranteed if a hard reset occurs during a Flash write cycle.
ThefollowingtableshowstheFlashoptionsavailablefortheSBC312:
Table 5-4 Flash Options
Flash Size (MBytes)
256
Banks
2
Flash Bank Organization

2 x 1 Gbit
Figure52showstheFlashmemorystructure.Thebootimagesmaybeselected
usinghardwarelinks.
Figure 5-2 Flash Memory Structure
5.4.1 Boot Flash

Thetop8MBytesofFlashmemoryonthefirstFlashbankisusedasBootFlash,and
holdsinitializationandoperatingsystembootroutines.TheBootFlashregion
containsfourindependent2MBytebootareas(Main,Alternate,SecondAlternate
andRecovery).
TheactivebootimagecanbeselectedusinglinkP9pins1to4duringdevelopment.
Table 5-5 Boot Image Selection by Link
Pins 1 & 2
Pins 3 & 4
Active Boot Image
Out
Out
Main
In
Out
Alternate
Out
In
Recovery
In
In
Second Alternate
TheRecoverybootareacontainsa128KBytefactoryprogrammedbootimage,
allowingtheFlashtobereprogrammedifotherbootimagesbecomecorrupted.The
Recoveryareaisprotectedbyhardwareandisnotwriteablebytheuser.The
remainderofthis2MByteareacanbeusedtostoreBITresults.
NOTE
This small recovery image may be used to boot a fully-featured firmware image stored in the SPI
Flash, which is also not writeable by the user. See the SPI Serial Flash section.
5.4.2 User Flash

AnyFlashthatisnotusedasBootFlashisdesignatedasUserFlashandisintended
toholduserapplicationcodeordata.
TheP4080sLocalBusControllerusesChipSelect1(CS1)toaccessUserFlash.CS1
alsoprovidesaccesstotheareasaccessedbyCS0(atthetopoftheFlasharray),butis
notaffectedbythestateoftheBootImageSelectlinks(P8andP9).
5.4.3 Paged Flash Mode

Duetolimitationsonthesizeoftheprocessormemorymap,apagedmodeis
providedwheretheUserFlashareaisdividedinto128MBytepages.Pagingis
disabledbydefault.
Figure 5-3 User Flash Page Numbering
5.4.4 Flash Sector Protection

TheSBC312usesSpansionS29GLFlashdevices,whichprovideadvancedmethods
ofsectorprotectiontoensuretheintegrityofcodedatacontainedintheFlasharray.
Protectionisdefinedonapersectorbasis,whereasectoris128KBytesinsize.
Lockedsectorscannotbeerasedorprogrammed,theymayonlyberead.
NowriteprotectionofFlashisprovidedbyhardware.Softwaremustbeusedto
configuretheFlashdevicestoprotectagainstcorruptionofFlashdata.Thefollowing
typesofprotectionareprovided:
1. Persistentsectorprotectionprovidesnonvolatileprotectionthatremainsinplace
whenaboardispowercycledorreset.EachFlashsectormaybesetaslocked
(writeprotected)orunlocked(writeenabled)bywritingtoconfiguration
registerswithintheFlash.Theconfigurationofthisprotectionisonlypossible
whenthebackplaneNVMROsignalisinactivelow.Iftheseconditionsarenot
met,thesoftwareisunabletochangethesectorprotectionandthosesectorsthat
arelockedmaynotbeerasedorreprogrammedunderanycircumstances.
2. Nonpersistentprotectionmayalsobeused.Inthiscase,sectorslockedusing
Persistentmodemaynotbeerasedorreprogrammed,butpreviouslyunlocked
maynowbelocked.However,thisprotectionisonlypresentuntilapowercycle
orhardwareresetoccurs.
NOTE
Do not rely on non-persistent protection, as it may be subsequently altered by software. If further
protection is required, use the Persistent protection method.
Forfurtherdetailsoftheseprotectionmechanisms,seetheS29GLFlashFamilydata
sheet.
Softwarecandetectthesetting(fittedornotfitted)oftheFlashProtectionUnlock
Link(P10)fromtheLinkStatusRegister(registeroffset0x0012).
TheFlashdevicestopsectorhardwareprotectionmechanismisusedtoprovidethe
128KBytenoncorruptiblerecoverybootareainthefirstFlashbank.Thissectoris
protectedbydefaultandcannotbeunprotectedbytheuser.
5.5 SPI Serial Flash

A2MByteSSTS25VF106BSPIserialFlashdeviceisconnectedontheSPIinterfaceof
theP4080.Thisprovidesadditionalstorageforrecoveryboot,asthehardware
protectedareaoftheNORFlashdeviceusedtostoretherecoveryimageisonly
128Kbytes,whichmaynotbesufficienttoprovideallofthefunctionalityrequired
torecoveracorruptedboard.TheimageintheRecoveryBootareamaybeusedto
executethelargerimagestoredinSPIFlash.
TheSPIserialFlashisalsoprotectedbydefaultandcannotbeunprotectedbythe
user.
5.6 NAND Flash Solid State Drive

TBA
5.7 MRAM
TheSBC312has512KBytesofnonvolatileRAMforconfigurationdatastorageand
generalpurposeuse.Thisfunctionalityisimplementedusingan8bitwideEverspin
MR2A08ACMA35MRAMdevice.ChipselectCS3ontheP4080sLocalBus
ControllerisusedtoaccesstheMRAM,whichcanbereadfromandwrittentointhe
samewayasstandardRAM.
TheMRAMiswriteprotectedwhentheMRAMWriteEnableLink(P9pins5&6)is
notfittedoriftheNVMRObackplanesignal(onP0pinA4)isactivehigh.Thestatus
ofthislinkandbackplanesignalmaybereadfromtheLinkStatusRegister(register
offset0x0012).
Thedevicehasunlimitedread/writeenduranceandstateddataretentionisgreater
than20years.
5.8 VPX Interface

TheinterfacetotheVPXbackplaneiscompatiblewiththefollowingspecifications:
VITA46.0
VITA46.4(forPCIExpressI/O)
VITA46.9(forPMC/XMCI/O)
VITA65
5.8.1 OpenVPX Compatibility

TheSBC312iscompatiblewiththefollowingmoduleprofile,asdefinedbythe
VITA65OpenVPXSpecification:
SLT3PAY2F2T14.2.5
5.8.2 PCI Express

TheSBC312provideseightlanesofPCIExpresstotheP1connector.Theselanesare
Gen2capable,operatingateither2.5or5Gbps,andmaybeconfiguredinuptofour
portsasshownbelow.
Table 5-6 Backplane PCI Express Port Configurations (Lanes 16 to 23)
STK1CFG Value
0x0
0x1
0x2
0x3
23
x1
x1
PCI Express Lane Number

21 20 19 18 17
x4
x4
x1 x1 x1
x4
x1 x1 x1 x1 x1 x1
x4
x1 x1 x1
22
16
x1
x1
Uptotwonontransparentportsaresupported,forconnectingtootherintelligent
hosts,toprovideaddresstranslationandmailboxes.Theseareavailableonlyonthe
portsstartingatlanenumbers16and20.
TheconfigurationoftheseportsisalteredbywritingtothePCISwitch1
ConfigurationEEPROMundersoftwarecontrol.Thedefaultconfigurationofthe
switchiswithtwox4linkswithnonontransparentports.
5.8.3 REF_CLK
TheVPXREF_CLKsignal,whichisbusedbetweenallboardsinthebackplane,is
drivenwitha25MHzdifferentialoutputwhentheSBC312isconfiguredasthe
SystemController.Thiscanbesubsequentlyalteredbysoftwareusingthe
REFCLK/AUXCLKControlRegister(registeroffset0x600A).
TheREFCLKsignalisusedtoclocka48bitcounter,whichisreadfromthree
registers.Thisvaluecouldbeusedtoprovideacommontimestamptodatapassed
aroundthesystem.ThecounterisnormallyresetonlybytheVPXSYSRESET~signal
andsowillmaintainthecommoncountvalueevenifasingleboardinthesystemis
reset.
TheREFCLKcounterisusedtoreplacetheproprietaryAXIStimer.Seethe
AxisTimersectionfordetails.
5.8.4 AUX_CLK
OpenVPXalsosupportsabussedAUX_CLKsignalontheVPXRES_BUS+/pins
(P0pinsB8andC8).Thisisintendedtosupporta1pulsepersecondperiodic
referencetimingpulse,butcouldbeusedforanyothersystemtimingfunctionas
required.
OntheSBC312theAUX_CLKinputisusedtoincrementa32bitcounter,whichis
readfromtworegisters.
TheSBC312isalsoabletodrivetheAUXCLKsignaltotestthefunctionalityofthe
timerortoimplementthetimingfunction,undersoftwarecontrol.
5.8.5 Module Maskable Reset

OpenVPXsupportsasecondresetinputfromthebackplane(P1pinG15),which
maybemaskedundersoftwarecontrol.
TheSBC312ishardresetwhentheMaskableResetbackplanesignalisassertedfor
morethan10S,unlessthemaskbitinControlRegister3(registeroffset0x001A)is
setbysoftware.Theresetismaskedbydefault.
TheSBC312isalsoabletodrivetheMaskableResetundersoftwarecontrol,for
exampletoresetasubsetofotherboardsinthesystem,bysettingabitin
ControlRegister3(registeroffset0x001A).
TheMaskableResetsignalreplacestheproprietaryAXISTimerResetsignal,which
usedtooccupythesamepin,butfunctionalityisprovidedtoperformthisfunctionif
required.SeetheAxisTimersectionfordetails.
5.8.6 Global Discrete

OpenVPXsupportsasingleopendrainGPIOsignal,GDISC1(P1pinG1),whichis
busedtoallmoduleslotsinthebackplane.Itsfunctionisnotdefinedbythe
specification,butitcouldbeusedtoprovideacommoncontrolorstatusfunctionto
allboardsinthesystem.
TheSBC312providesregisterstodrivetheGDISC1pinlowundersoftwarecontrol,
toreaditsstatusandtogenerateaninterrupt(withprogrammablepolarityand
edge/levelselection).SeeControlRegister3(registeroffset0x001A)formore
information.
5.9 I/O
TheSBC312hasthefollowingI/Oconnectivity:
SerialPorts
Ethernet
USB
SerialATA
GeneralPurposeI/O
Duetopinoutrestrictions,someI/Osharespinsonthevariousconnectors.
5.9.1 Serial Communication Ports

TheSBC612providesuptofourexternalserialports.
COM1 and TheDUART1interfaceoftheP4080providestwodebugportswithhardwareflow
COM2 control.ThesignalsfortheseportsareconnectedtoISL41334serialtransceivers
capableofgeneratingRS232orRS422signallevels.
Table 5-7 COM1/COM2 Signal Availability
RS232 Signal
RS422 Signal
Pin
Signal
RS422 Signal
Pin
COM1_TXD
COM1_TXD_A
P1 G9
COM2_TXD
COM2_TXD_A
P1 G13
COM1_RXD
COM1_RXD_A
P1 G11
COM2_RXD
COM2_RXD_A
P2 G11
COM1_RTS
COM1_TXD_B
P2 G3
COM2_RTS
COM2_TXD_B
P2 G7
COM1_CTS
COM1_RXD_B
P2 G5
COM2_CTS
COM2_RXD_B
P2 G9
TheoptiontooperatetheportsinRS422modeortodisableorloopbackthe
transceivers,undersoftwarecontrol,isprovidedbytheSerialControlRegister
(registeroffset0x0016).Thetransceiversaredisabledbydefaultandmustbeenabled
beforeanyserialtransferscantakeplace.
IftheboardisconfiguredforSBC310compatibleI/O,COM2isrelocatedasshown
below.ThisisindicatedinBoardConfigurationRegister2(registeroffset0x000C).
Table 5-8 SBC310-compatible COM2 Signal Availability
Signal
Pin
COM2_TXD
P1 G13
COM2_RXD
P1 G15
COM2_RTS
P2 G7
COM2_CTS
P2 G9
Thebaudrateissoftwareprogrammable,derivedfromtheplatformfrequencyusing
thefollowingequation:
BaudRate=(1/16)*(PlatformFrequency/(2*DivisorValue))
Thetablebelowshowsthedivisorsusedforsomecommonlyusedbaudratesand
thepercentageerrorassociatedwiththeuseofanintegerdivider.
NOTE
The percentage error will increase significantly at higher baud rates. Different divisors will be required
if a different Platform Frequency is used.
Table 5-9 Baud Rates

Target Baud
Rate
Platform Frequency
(MHz)
Divisor
(Decimal)
Divisor
(Hex)
Actual Baud
Rate
Error
(%)
9600
800
2604
0A2C
9600.61
0.0064
19200
800
1302
0516
19201.23
0.0064
38400
800
651
028B
38402.46
0.0064
56000
800
446
01BE
56053.81
0.0961
128000
800
195
00C3
128205.13
0.1603
256000
800
98
0062
255102.04
-0.3508
Theactualperformanceoftheseportswillbelimitedbythethroughputcapabilityof
thesoftwaredriverandprocessorloading.
SoftwaredebugportsareconfiguredbydefaultasDTEwithsettingsof115200baud,
8bits/character,1stopbit,paritydisabledandnoflowcontrol.
Theseportsalsohavetheabilitytooperateasfourseparatetwowire(TXandRX)
UARTs,asdescribedbelow.
COM3 and TheP4080hastheabilitytoconfigureitsDUARTsasfourseparatetwowireUARTs,
COM4 withoutflowcontrol.Thisfeatureisasoftwareconfigurationoption,controlledby
theI2CEEPROMDIPswitch.Ifenabled,theextraportsarelabeledCOM3and
COM4.
Whenallfourserialportsareused,COM1andCOM2aredrivenbyDUART1within
theP4080,andCOM3andCOM4byDUART2.
InthismodeCOM1,COM2,COM3andCOM4mustallbeoperatedasRS232ports;
RS422operationisnotsupported.
NOTE
The transceiver and loopback enable controls for COM3 are linked to those of COM1, and the
transceiver and loopback enable controls for COM4 are linked to those of COM2.
Table 5-10 COM3/COM4 Signal Availability

Signal
P2 Pin
COM1 Equivalence
Signal
P2 Pin
COM2 Equivalence
COM3_TXD
G3
COM1_RTS
COM4_TXD
G7
COM2_RTS
COM3_RXD
G5
COM1_CTS
COM4_RXD
G9
COM2_CTS
Host-to-BMM TheFPGAcontainsanIPcorefora16550compatibleUART,whichmaybeusedby
Serial Port softwarerunningonthehostprocessortocommunicatewiththeonboardBMMif
required.
5.9.2 Ethernet
TheP4080providestwoEthernetports,connectedviaSGMIIlinkstoaMarvell
88E1322dualPHY.ThePHYisisolatedfromthebackplaneusingtransformer
coupledmagnetics.
TheEthernetportsaremappedtoP4080DatapathTriSpeedEthernetController
(dTSEC)interfaceswithinFrameManager1asshownbelow:
Table 5-11 P4080 Network Interface Mapping
P4080 Module
Ethernet Port
PHY Address
FM1_dTSEC1
ETH0
FM1_dTSEC2
ETH1
Twoportsof10/100/1000BaseTEthernet,ETH0andETH1,areprovidedontheVPX
P1connector,asfollows:
Table 5-12 ETH0/ETH1 Pin Mapping
Signal
P1 Pin
Signal
P1 Pin
ETH0_0P
A15
ETH1_0P
A13
ETH0_0N
B15
ETH1_0N
B13
ETH0_1P
D15
ETH1_1P
D13
ETH0_1N
E15
ETH1_1N
E13
ETH0_2P
B16
ETH1_2P
B14
ETH0_2N
C16
ETH1_2N
C14
ETH0_3P
E16
ETH1_3P
E14
ETH0_3N
F16
ETH1_3N
F14
Thenetwork(MAC)addressesoftheEthernetportsarefactoryconfiguredandmay
bedisplayedbysoftware.
LEDsareprovidedontherearoftheboardtoallowthestatusofeachEthernet
interfacetobemonitored.SeetheLEDssectionformoredetails.
5.9.3 USB
TheP4080providestwoUSB2.0portstotheP1connectorviaUSB3300ULPIPHY
devices.PowerfortheseportsisprovidedbyanLM3526device,controlledbythe
USBController.
Table 5-13 USB0/USB1 Signal Availability
Signal
P1 Pin
Signal
P1 Pin
USB1_P
B10
USB2_P
E10
USB1_N
C10
USB2_N
F10
USB1_PWR
A11
USB2_PWR
B11
5.9.4 SATA
ASiliconImageSil3132PCIetoSATAcontroller,capableofoperationat3GHz,
providestwoSATAportsontheSBC312.TheSil3132isconnectedtoPCIExpress
switch2viaax1Gen1PCIExpresslink.
ThefirstSATAport(SATA0)isconnecteddirectlytotheP1connector.Thesecond
SATAportisconnectedtotheonboardSolidStateDrive(formoredetailsseethe
NANDFlashSolidStateDrivesection).
AsecondbackplaneSATAport(SATA1)ontheP1connectorisabuildoptionatthe
expenseoffouroftheGPIOpins.ThisisprovidedbytheFPGA.
Table 5-14 SATA Signal Availability
Signal
P1 Pin
Signal
P1 Pin
SATA0_TXP
D9
SATA1_TXP
D11
SATA0_TXN
E9
SATA1_TXN
E11
SATA0_RXP
A9
SATA1_RXP
B12
SATA0_RXN
B9
SATA1_RXN
C12
LEDsontherearoftheboardindicateactivityonthecorrespondingSATAchannel.
5.9.5 GPIO
TheSBC312supportsupto8GPIOlines,eachwithinterruptgenerationcapabilities.
Theseare3.3VSingleEndedsignalswith5Vtolerance.Thesesignalsarecontrolled
bytheFPGAandcanbeconfiguredasinputs,withtheabilitytogeneratelevelor
edgetriggeredinterrupts,oroutputs,withtotempoleoropendraindrivers.
TheGPIOareintendedonlytobeusedbyGEIPsoftwaredrivers.Seetherelevant
softwaremanualfordetails.
TheGPIOsignalsareroutedtotheP1connectorandP2connectorasfollows:
Table 5-15 GPIO Line Routing
GPIO Line
0
1
2
3
Pin
P1 D11
P1 E11
P1 B12
P1 C12
GPIO Line
4
5
6
7
Pin
P1 E12
P1 F12
P2 G13
P2 G15
GPIO[3:0]shareI/OpinswiththeSATAport1(theSATAportisabuildoption).
GPIOline5canalsobeusedtocontrolthebehaviorofBITfollowingreset.This
signalisreadablebysoftwareasBIT_MODE0intheLinkStatusRegister(register
offset0x0012)and,ifusedforthispurpose,shouldnotbedrivenbytheGPIO
controller.
GPIOlines6and7shareI/OpinswiththeGEIPproprietarySEQ_INandSEQ_OUT
powersequencingsignals.Thesequencingsignalsareonlyusedatpowerup,sothe
GPIOlinesareavailableafterthis.
5.10 Mezzanines
5.10.1 PMC/XMC Site
TheSBC312hasonemezzaninesitethatsupportsbothIEEEP1386.1compliant
PMCsandANSI/VITA42.3compliantXMCs(includingsupportforfrontpanelI/O).
5.10.2 PCI Mezzanine Cards (PMCs)

ThesiteprovidesJ11,J12,J13andJ14connectorstoprovidea64bitPCIbuscapable
ofPCIXoperationatfrequenciesofupto133MHz.Theinterfaceisalso5Vtolerant
andsupportstheuseof5VPMCsat33MHzsignalingrateonly.
CAUTION
Ensure that the 5 V VIO Selection Link (P8) is set according to the requirements of the fitted PMC.
Damage to the PMC may otherwise result.
ThePCIbusisconnectedtoaPericomPI7C9X130PCIExpresstoPCIBridge,which
providesfrequencynegotiation,clocksandarbitrationforthebus.Thespeedofthe
busisbasedonthecapabilityofthePMC,andisdeterminedbythebridgeduring
reset.Thecurrentoperatingfrequencyofthebusmaybeascertainedbyreading
registerswithinthebridge.
ThePMCsitesupportsProcessorPMCs(asdefinedbyVITA322002)operatingin
nonMonarchmodeonly.ThisincludessupportforPMCswithtwoPCImasters.
ThePMCsitehasadedicatedPCIbus,sofittingaPMCthatrunsatalower
frequencydoesnotlimittheperformanceofotherfunctionsoftheSBC312.
ThepresenceofaPMCinthesiteisshownintheBoardConfigurationRegister2
(registeroffset0x000C).
5.10.3 PCI Express Mezzanine Cards (XMCs)

ThesitealsoprovidesJ15andJ16connectors.J15providesax8PCIExpresslinkto
thePCIExpressswitch,andJ16isusedtorouteXMCI/Otothebackplane.
AboardconfigurationoptionallowsXMCpowertobeprovidedeitherfromthe
backplane12Vsupplyorfromanonboardgenerated5Vsupply,whentheboard
itselfispoweredfrom12V,asbotharesupportedbytheVITA42.0specification.
TheselectedconfigurationisshownintheBoardConfigurationRegister1(register
offset0x000A).
TheSystemManagementpinsoftheXMCsiteareconnectedtoadedicatedI2C
interfaceontheBMM.ThegeographicaddressoftheXMCsiteisconfiguredto000b.
ThepresenceofanXMCinthesiteisshownintheBoardConfigurationRegister2
(registeroffset0x000C).
5.10.4 I/O Routing

RearI/OtrackingisprovidedfromtheJ14andJ16connectorsofthePMC/XMCsite
totherearVPXconnectorsinaccordancewithVITA46.9.TheI/Ofromthe
PMC/XMCsiteisroutedtotheP2connectorandsupportsthefollowing
configurations:
20differentialpairsand24singleendedXMCI/OfromJ16(X20d24s)
FullPMCI/OfromJ14(P64s)
TheselectedconfigurationisshownintheBoardConfigurationRegister2(register
offset0x000C).
TheI/OfromPMCconnectorsJn4pinsistrackedas50SingleEndedsignalsbut
matchedinlengthingroupsoffoursignals(14,58,etc.)suchthatitmaysupport
differentialsignaling(forEthernet,etc.)
TheI/OfromXMCconnectorsJn6columnsA,B,DandEistrackedas100
differentialpairs(A01andB01,D01andE01,etc.)andthatfrompinsC119andF1
19istrackedas50SingleEndedsignalsbutpairsarematchedinlength(C2toC3,
F2toF3,C4toC5,F4toF5,etc.)suchthattheymaysupportdifferentialsignaling.
Table 5-16 PMC/XMC Site Signal Availability (X20d24s XMC I/O)
XMC I/O
P2 Pin
XMC I/O
P2 Pin
XMC I/O
P2 Pin
J16_IO_C08
E1
J16_IO_A01
E7
J16_IO_A09
E13
J16_IO_C09
D1
J16_IO_B01
D7
J16_IO_B09
D13
J16_IO_F08
B1
J16_IO_D01
B7
J16_IO_D09
B13
J16_IO_F09
A1
J16_IO_E01
A7
J16_IO_E09
A13
J16_IO_C10
F2
J16_IO_A03
F8
J16_IO_A15
F14
J16_IO_C11
E2
J16_IO_B03
E8
J16_IO_B15
E14
J16_IO_F10
C2
J16_IO_D03
C8
J16_IO_D15
C14
J16_IO_F11
B2
J16_IO_E03
B8
J16_IO_E15
B14
J16_IO_C12
E3
J16_IO_A11
E9
J16_IO_A17
E15
J16_IO_C13
D3
J16_IO_B11
D9
J16_IO_B17
D15
J16_IO_F12
B3
J16_IO_D11
B9
J16_IO_D17
B15
J16_IO_F13
A3
J16_IO_E11
A9
J16_IO_E17
A15
J16_IO_C14
F4
J16_IO_A13
F10
J16_IO_A19
F16
J16_IO_C15
E4
J16_IO_B13
E10
J16_IO_B19
E16
J16_IO_F14
C4
J16_IO_D13
C10
J16_IO_D19
C16
J16_IO_F15
B4
J16_IO_E13
B10
J16_IO_E19
B16
J16_IO_C16
E5
J16_IO_A05
E11
J16_IO_C17
D5
J16_IO_B05
D11
J16_IO_F16
B5
J16_IO_D05
B11
J16_IO_F17
A5
J16_IO_E05
A11
J16_IO_C18
F6
J16_IO_A07
F12
J16_IO_C19
E6
J16_IO_B07
E12
J16_IO_F18
C6
J16_IO_D07
C12
J16_IO_F19
B6
J16_IO_E07
B12
Differentialpairsareshadedabove.
Table 5-17 PMC/XMC Site Signal Availability (Full PMC I/O)

PMC I/O
P1 Pin
PMC I/O
P1 Pin
J14_IO_1
E1
J14_IO_2
B1
J14_IO_3
D1
J14_IO_4
A1
J14_IO_5
F2
J14_IO_6
C2
J14_IO_7
E2
J14_IO_8
B2
J14_IO_9
E3
J14_IO_10
B3
J14_IO_11
D3
J14_IO_12
A3
J14_IO_13
F4
J14_IO_14
C4
J14_IO_15
E4
J14_IO_16
B4
J14_IO_17
E5
J14_IO_18
B5
J14_IO_19
D5
J14_IO_20
A5
J14_IO_21
F6
J14_IO_22
C6
J14_IO_23
E6
J14_IO_24
B6
J14_IO_25
E7
J14_IO_26
B7
J14_IO_27
D7
J14_IO_28
A7
J14_IO_29
F8
J14_IO_30
C8
J14_IO_31
E8
J14_IO_32
B8
J14_IO_33
E9
J14_IO_34
B9
J14_IO_35
D9
J14_IO_36
A9
J14_IO_37
F10
J14_IO_38
C10
J14_IO_39
E10
J14_IO_40
B10
J14_IO_41
E11
J14_IO_42
B11
J14_IO_43
D11
J14_IO_44
A11
J14_IO_45
F12
J14_IO_46
C12
J14_IO_47
E12
J14_IO_48
B12
J14_IO_49
E13
J14_IO_50
B13
J14_IO_51
D13
J14_IO_52
A13
J14_IO_53
F14
J14_IO_54
C14
J14_IO_55
E14
J14_IO_56
B14
J14_IO_57
E15
J14_IO_58
B15
J14_IO_59
D15
J14_IO_60
A15
J14_IO_61
F16
J14_IO_62
C16
J14_IO_63
E16
J14_IO_64
B16
5.11 PCI Express Infrastructure

OnboardPCIdevices,themezzaninesiteandoffboardlinksareconnectedtothe
P4080usingPCIExpress.ThePCIExpressandPCIstructureoftheSBC312isshown
inFigure51.
PCIExpressisahighspeedserial,pointtopointinterconnectrunningat2.5Gbits/s
ineachdirection.PCIExpresslinksarescalable,meaningthatmultiplelanescanbe
usedbetweendevicestoincreasetheaggregatebandwidth.Acomparisonofthe
bandwidthofPCIExpresslinkswithPCIimplementationsareshowninthetable
below.
Table 5-18 PCI Bus
Bus Type
Bus Width
Frequency
Bandwidth (MBytes/s)
Notes
PCI
32-bit
33 MHz
133
PCI
32-bit
66 MHz
266
PCI
64-bit
66 MHz
533
PCI-X
64-bit
133 MHz
1066
PCIe
x1
2.5 Gbps
250
Per direction
PCIe
X4
2.5 Gbps
1000
Per direction
PCIe
X8
2.5 Gbps
2000
Per direction
PCIe Bandwidths shown include 8b/10b encoding overheads
PCIExpressisapacketbasedprotocol,butusesthesameaddressspacesasstandard
PCI,meaningthatthesoftwareinterfacesarebackwardscompatible.PCIetoPCI
BridgesareusedtoconverttoPCIXorstandardPCIwhereconnectiontothese
devicesisrequired.
ThemaximumpacketpayloadsizeforthePCIExpresssubsystemis256bytes.
CRCerrorcheckingisperformedoneachpackettransmittedbetweendevicesinthe
system,andanycorruptedpacketsareretransmitted.Thetargetdevicecanalso
performendtoenderrorchecking,toensureintegrityofthereceiveddata.
5.11.1 P4080
TheSBC312connectstoP4080PCIExpresscontrollerSERDES03usingax4Gen2
PCIExpresslinkandalsoto45usingax2Gen2PCIExpresslink.TheonboardPCI
ExpressdevicesandoffboardlinksareconnectedtotheP4080usinganIDT
89H32NT24AG2multihostPCIExpressswitchwithnontransparentsupport,as
showninFigure51.
Theswitchprovidesnontransparentcapability,forconnectiontootherintelligent
endpointswithinthesystem,andDMAengines.
Themultihostcapabilitiesoftheswitchallowforflexiblesystemconfigurations.An
examplewouldbeasanintelligentcarrierwherethemezzaninesitecouldbe
accesseddirectlyfrombackplaneportsandhiddenfromsoftwareontheP4080
5.11.2 PCI Express Switch

Thisswitchprovidestwox4Gen2capablePCIExpresslinkstotheVPXP1connector
andalsoconnectstotheP4080asshowninFigure51.Thedefaultswitchport
configurationisshownbelow.
Table 5-19 PCI Express Switch Connections
Port
0&1
2
4 to 7
8 to 11
12 to 15
16 to 19
20 to 23
Port Width
x4
x4a
x8
x4
x4
x4
x4
Link To
P4080 SERDES 0 to 3
SATA
XMC site
P4080 SERDES 4 and 5
PCIe-PCI-X bridgeb
Backplane Port A
Backplane Port B
Speed (Gbps)
5
2.5
2.5/5
5
2.5
2.5/5
2.5/5
a. Configured as x4 but operate as x1.

b. Present only when the PMC/XMC is fitted.
NOTE
Ports 0 to 7 are each dual lane.
TheswitchisconnectedtoI2CBus3toallowconfigurationbytheprocessorand
outofbandlinkstatusmonitoring.
EachPCIExpressportoftheswitchappearstosoftwareasaPCItoPCIbridge,with
itsownPCIcompatibleconfigurationregisters.Eachportisaccessedontheinternal
virtualPCIbususingadevicenumberequaltoitsportnumber.
Port0alsocontainsaDMAfunction,containingtwoDMAchannels,fortransferring
databetweenaPCIExpressdeviceandprocessorRAMoranotherPCIExpress
device,withminimaloverheadonthehostprocessor.
Theswitchalsosupportsmulticastaddressing,asdefinedbyPCIExpressBase
Specification2.1,allowingPCIExpresswritestobeforwardedtomultiple
destinations.
Theportconfigurationoftheswitchisinitiallysetupbyhardwarestrapping.Each
portisabletonegotiatedowntosmallerlinkwidthsifrequired(suchasifafault
occursonanyparticularlane).Portwidthsofx1,x2andx4aresupported.
A32KByteserialEEPROMisconnectedtotheswitchsprivateI2Cbusforpowerup
configuration.ThisEEPROMiswriteenabledwhenthebackplaneNVMROsignal
(onP0pinA4)islow.TheswitchispreventedfromaccessingtheEEPROMwhenin
recoverymodesothatthedatamayberecoveredifitbecomescorrupted.
LEDsontherearoftheboardshowthestatusofthePCIelinks.Furtherstatus
information(numberofactivelanes,linkspeedetc.)canbeascertainedfrom
registerswithintheswitch.
5.12 I2C Buses

TheP4080hasfourseparateI2Cinterfaces,withdevicesallocatedtothemasshown
below.
Figure 5-4 I2C Bus Structure
WhereI2Caddressesarequotedinthefollowingsections,the8bitaddressisthe
valuethatwouldbeusedtowritetothedeviceonthebus(i.e.the7bitdevice
addressandtheLSBsetto0).
5.12.1 Addressing
Table 5-20 I2C Bus Addresses
Device
P4080
Bus 1
P4080 Config EEPROM
PCA9650 DIP Switch
Bus 2
RTC
ETI
Core Temp Sensor
Ambient Temp Sensor
BMM
Power Manager
Bus 3
PCIe Switch
PCIe Switchs Private I2C Bus
PCIe Switch Config EEPROM
7-Bit Address (Hex)

00 (programmable)
8-Bit Write Address (Hex)

00 (programmable)
50
4D
A0
9A
51
6B
4C
48
N/A (Master only)
40 (programmable)
A2
D6
98
90
N/A (Master only)
(programmable)
75
EA
50
A0
5.12.2 I2C Bus 1

ThisisconnectedtoanEEPROMdevice,usedforinitializationoftheP4080,andan
EEPROMDIPswitch,alsousedforboardconfiguration.
5.12.3 I2C Bus 2

Thisispartitionedintotwosegments.ThefirstsegmentcontainstheRTC,ETIand
temperaturesensordevices,whichareavailabletosoftwarerunningonthehost
processor.Thesecondsegmentcontainsthepowermanager,andisonlyaccessible
bytheBMM.Ifsoftwareonthehostrequiresaccesstothissensor,itshouldrequest
thedataviatheBMM.
ThetwosegmentsareseparatedbyaPCA9511I2Cbuffer,whichisnormally
disabled.ItmaybeenabledwhenthefunctionalityoftheBMMisnotusedorfor
testingofthesensor.Thebufferalsoprovidesisolationforthosedeviceswhichare
poweredfromthebackplaneP3V3_AUXpowerrail.
5.12.4 I2C Bus 3

ThisisconnectedtotheslaveI2CinterfaceofthePCIExpressswitchdeviceforout
ofbandmonitoringorconfiguration.TheconfigurationEEPROMusedbytheswitch
isconnectedtoanisolatedI2Cbusandisnotdirectlyaddressablefromthisbus.
Softwaremustuseregisterswithintheswitchtocommunicatewiththisdevice.For
moredetails,seethePCIExpressSwitchsection.
5.12.5 I2C Bus 4

Thisisnotused.
5.12.6 I2C Reset

AnI2Cbusmaypotentiallylockupiftheresetisapplied(stoppingtheI2Cclock)
whenaslavedevice(withoutaresetpin)isdrivingoutdata.
TheP4080providesasoftwaremechanismtorecoverfromthisstate,sonohardware
recoverymechanismisprovided.TheP4080andPCIeswitchapplyaresetpatternto
theappropriateI2CbusesbeforeconfiguringfromtheirEEPROMs.
5.12.7 P4080 Config EEPROM

A32KByte24LC256EEPROMisattachedtoI2CBus1.ThiscanstoretheReset
ConfigurationWordfortheP4080ifselectedbythesoftwareconfigurationoption.
ThedeviceiswriteenabledonlywhenthebackplaneNVMROsignal(onP0pinA4)
islow.
5.12.8 DIP Switch

APCA9560deviceisusedtoconfigurecertainaspectsofboardoperationasshown
below:
Table 5-21 PCA9560 Pin Allocation
Output
A
B
Ca
Da
Ea
Non-multiplexed
Function
Controls the Power Supply for Core Group B (4 to 7)
0 = Enabled
1 = Disabled
This only takes effect after a power-cycle
Sets the Reset Configuration Word source
0 = RCW read from FPGA (factory-configured)
1 = RCW read from I2C EEPROM on I2C Bus 1
(When booting from the Recovery Area, the factory-configured RCW is always used)
XMC_GA0
XMC_GA1
XMC_GA2
Controls the UART configuration of the P4080
0 = COM1/COM2 with flow control
1 = COM1/COM2/COM3/COM4 without flow control
This only takes effect following a reset
a. These outputs configure the geographic address of the XMC site, as the number of available I2C addresses is small and
the number and location of XMCs is system-dependant. Also see the BMM section
Thedefaultstateoftheoutputsislow.
ThisdeviceiswriteenabledwhenthebackplaneNVMROsignal(onP0pinA4)is
low.
5.12.9 Real Time Clock

TheSBC312providesanEpsonRX8581RTC,whichhasaminimumof1second
resolution.ThisdevicecanbepoweredfromtheP3V3_AUXsupply,ortheVBAT
signal(P1pinG3)whenthemainpowersupplyisremoved.Theinterruptoutputof
theRTCcangenerateaninterrupttotheprocessorviatheFPGAinterruptcontroller.
5.12.10 Elapsed-Time Indicator

ADallasDS1682ETIlogstheamountoftimetheSBC312ispoweredandthenumber
ofpowercycles.
5.12.11 Temperature Sensors

TheSBC312hastwotemperatesensors:anADT7461monitorsthetemperatureinthe
vicinityoftheP4080(givinganindicationofthecoretemperature)andanLM92
monitorstheambienttemperatureonthePCB.
TheinterruptoutputsofthesedevicescangenerateinterruptstotheP4080,viathe
FPGAinterruptcontroller,attwosoftwaredefinedthresholds.
5.12.12 Power Manager

TheSBC312usesaLatticeispPOWR1014Aprogrammablepowermanagerto
controlalloftheonboardpowersuppliestomeetsupplysequencingrequirements.
Inadditiontocontrollingtheonboardsupplies,thepowermanageralsomonitors
eachrail,anditsvoltagecanbereadfromregistersinternaltothedevice,acrossthe
I2Cinterface.
Thefollowingtableliststhesoftwaremonitorpoints:
Table 5-22 Power Manager Monitor Points
Monitor Point
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
Supply Name
VCOREB
VCOREA
P1V0
P1V8
P2V5
P3V3
P5V
P3V3_BP
P3V3_AUX
VCC
Nominal Voltage
+1.0 V
+1.0 V
+1.0 V
+1.8 V
+2.5 V
+3.3 V
+5.0 V
+3.3 V
+3.3 V
+5 V
ThepowermanagerdrivesagreenPowerGoodLED(DS200)whenallonboard
powersuppliesarewithintolerance.SeetheLEDssection.
5.12.13 Board Management Microcontroller

TheSBC312hasaBMM,whichprovidesaproprietarymechanismtoenablesharing
ofBITresultsbetweenboardsinasystemandremotemonitoringofboardstatus.
TheBMMisconnectedtoabackplaneI2CSerialManagementbus(usingtheSM0
andSM1connectionsontheP0connector)whichisbusedbetweenallslotsinthe
system.TheBMMoneachboardisaddressedbasedonitsGeographicAddressas
showninthefollowingtable.Thesearethebyteaddressesthatwouldbeusedto
writetothedeviceonthebus(i.e.the7bitdeviceaddressandtheleastsignificant
bitsetto0).
Table 5-23 BMM Address Allocation
Slot
1
2
3
4
5
6
7
GA[4:0]
11110
11101
11100
11011
11010
11001
11000
I2C Address
0xB0
0xB2
0xB4
0xB6
0xB8
0xBA
0xBC
Slot
8
9
10
11
12
13
14
GA[4:0]
10111
10110
10101
10100
10011
10010
10001
I2C Address
0xBE
0xC0
0xC4
0xC6
0xC8
0xCA
0xCC
Slot
15
16
17
18
19
20
21
GA[4:0]
10000
01111
01110
01101
01100
01011
01010
I2C Address
0xCE
0xD0
0xD2
0xD4
0xD6
0xD8
0xDA
TheSystemManagementpinsoftheXMCsitearealsoconnectedtothebackplane
SerialManagementBus.Thelower3bitsofitsaddressaredeterminedbythe
GeographicAddresspinsgeneratedbytheDIPSwitch,asshowninthetablebelow.
Again,thesearethebyteaddressesthatwouldbeusedtowritetothedeviceonthe
bus(i.e.the7bitdeviceaddressandleastsignificantbitsetto0).
Table 5-24 SMB Address Allocation
VPX_GA[2:0]
000
001
010
011
100
101
110
111
I2C Address
0xA0
0xA2
0xA4
0xA6
0xA8
0xAA
0xAC
N/A
TheBMMisalsoconnectedtotheCOMportfromtheFPGA.TheBMMserial
interfaceenablingiscurrentlyTBA.
TheBMMisalsoconnectedtoonboardI2CBus2,providingaccessforoutofband
monitoringofboardstatusinformationsuchasonboardvoltagerailstatusorboard
temperaturesbyanyotherboardinthesystem.
TheBMMprogrammingiscurrentlyTBA.Consultthefactoryonuse.
TheBMMispoweredfromtheP3V3_AUXsupply,meaningthatboard
configurationinformationorBITstatuscanbereadoutofthedevicewithout
enablingthemainpowerrail.AnI2CbufferissitedontheonboardI2CBus2to
allowtheBMMtoaccessthePowerManagerdevicewhentheonboardsuppliesare
notpoweredup.
5.13 Timers
TheP4080provideseight31bitgeneralpurposetimers,eachcapableofgenerating
interruptstotheprocessor.
Eachgroupof4timerscanbesettooperatefromadivideroftheplatformsclock
(dividedby8,16,32or64).
Eachgroupoftimerscanbecascadedtoformtwo63bittimers,one95bittimeror
one127bittimer,ifrequired.
AswellasthewatchdogtimersprovidedbytheFPGA(seebelow),eache500mccore
alsoprovidesaninternalwatchdogtimerthatcanbeconfiguredtogeneratean
internalinterrupt,coreresetorsystemreset.
5.13.1 Watchdog Timers

TheFPGAprovidestwoidenticalbutindependentwatchdogtimers.Theseare
capableofgeneratinginterruptstotheprocessorandresettingtheSBC312onexpiry.
Eachwatchdogisa32bitcountdowntimer,theperiodofwhichisprogrammable.
Thecounterisclockedbythelocalbusclock,givingaresolutionof20nsanda
maximumtimeoutperiodof85.9seconds(assuminga50MHzbusspeed).
Followingreset,thewatchdogtimersareinitiallydisabled.Theycanbeenabledby
writinga01followedby10patterntotherelevantcontrolregister.When
enabled,thecounterisreloadedtothepresetvalue,andtheresetandinterruptbits
arecleared(assumingthatthepresetcountervalueishigherthantheinterrupt
value).
Onceenabled,awatchdogmustbeservicedperiodically.Ifthecounterreacheszero
beforethewatchdogisserviced,thenahardresetisgenerated.Thewatchdogcanbe
servicedbywritinga01followedby10patterntotherelevantcontrolregister.
Thisoperationclearstheinterruptandresetflags,ifset,andreloadsthecounterto
thepresetvalue.
Aprogrammableinterruptthresholdcanbeset.Ifthecounterreachesthisthreshold,
thenaninterruptisgeneratedtotheinterruptcontroller,whichmayberoutedtothe
processorifrequired.
Awatchdogcountercanbedisabledbywritinga01followedby10patternto
therelevantcontrolregister.Thecurrentstatusofthewatchdogcanalsoberead
fromthisregister.
FurtherdetailsontheoperationofthewatchdogcanbefoundintheWatchdog
Registerssection.
5.14 AXIS Support

AXISisaproprietaryGEIPmultiprocessingsoftwareenvironment,whichrequires
hardwaresupporttoprovideacommontimestamp,messagepassingmechanism
andsemaphoresforcommonresourcelocking.TheSBC312providestherequired
hardwaresupport.
Formoredetails,seetheREFCLKregisters,theAXISSemaphoreregistersandthe
FIFOregistersinsection518.
5.14.1 AXIS Timer

TheSBC312isabletousethe48bitREF_CLKcounter,inplaceoftheproprietary
AXISTimer,toprovideatimestampfordatathatiscommontoallboardsinthe
system.Amasterboard(usuallytheVPXSystemController)drivestheREF_CLK
signalatafixedfrequencyof25MHzandeachboardincrementsa48bittimeron
therisingedgeoftheclock.
ThelegacyAXIS_TIMER_RST~signalisnowreplacedbytheOpenVPXMSKRST~,
althoughitispossibletoemulatethisfunctionbysettingabitinthe
REFCLK/AUXCLKControlRegister(registeroffset0x600A).Thiscausesthe
MaskableResettoresetthetimerandallowstheclockmastertodrivetheresetto
clearthetimeracrossthesystem.ItshouldbeensuredthattheMaskableResetMask
bitinControlRegister3(registeroffset0x001A)issetbeforeenablingthismode.
5.14.2 Mailboxes
TheSBC312providesamailboxmechanismformessagepassingfromotherboards
totasksontheprocessor.TheFPGAcontainsfour16bitwideFIFOs,eachcapableof
holdingupto128messages.TheseFIFOsaregeneralpurposeandsomaybe
allocatedasrequiredbysoftware.
ThestatusofaFIFO(Full,Empty,AlmostFull,AlmostEmpty)maybedetermined
fromacorrespondingstatusregister.EachFIFOmayalsoberesetusingthisregister.
AfullFIFOwillnotacceptanyfurtherwritedataandanemptyFIFOwillnotreturn
validdataifread.
Aninterruptcanbegeneratedtotheprocessorwhenamessageisreceivedinany
queueandremainsasserteduntilthequeueisemptied.
EachFIFOisaccessibleattwoconsecutive16bitaddressestoallowcompatibility
withexisting32bitimplementations.
5.14.3 Semaphores
TheFPGAprovideseightsemaphoresforuseinlockingcommonresources.
5.15 Power Sequencing

5.15.1 On-board Sequencing
TheSBC312usesaLatticeispPACPowerManagerdevicetosequencethepower
suppliesintherequiredorderforonboarddevices.ThePowerManageralso
monitorsthebackplanesupplyvoltagesandshutsdowntheonboardsuppliesif
thesefallbelowtheirspecifiedlevels.
ThePowerManagerwillshutdownallonboardsupplies(exceptP3V3_AUX)when
theBMMassertstheBMM_POWER_OFFsignalorSHUT_DOWN~fromthe
TestAccessCardConnector(P4)isasserted.
ThePowerManagerisconnectedtoI2CBus2,allowingsoftwarereadoutofthe
voltagesofallonandoffboardsupplies.
5.15.2 Inter-board Sequencing

TheSBC312supportsaproprietaryinterboardpowersequencingmechanism.This
allowsforthesequencingofpowerbetweenseveralboardsinasystemtobe
controlled(limitingoverallinrushcurrent),andisachievedviatheSEQ_OUTand
SEQ_INsignalsontheP2connector,whichcanbedaisychainedbetweenboards.
TheSBC312drivestheSEQ_OUTsignallowwhenthebackplanesuppliesareoutof
specificationandholdsitlowuntilallonboardsuppliesarewithinspecification.
TheSEQ_OUTsignalisnotdrivenlowwhenthepowerisremovedasaresultofthe
BMM_POWER_OFFsignalbeingasserted.
TheSBC312holdsoffallonboardsupplies(exceptP3V3_AUX)whiletheSEQ_IN
signalisheldlow.ThepoweronsequenceisinitiatediftheSEQ_INsignalremains
low500msaftertheoffboardsuppliesarewithinspecification,whichmayoccurif
thepreviousboardinthechainfails.
5.16 Resets and Interrupts

TheProgrammableInterruptControllerwithintheP4080controlsresetsand
interruptstotheprocessingcores.
ThefollowingtableshowsthevariousexternalinterruptsourcestotheInterrupt
Controllerandtheirrelativepriorities.Italsoshowswhetherthepreviousstateof
theprocessorisrecoverable.
Table 5-25 External Interrupt Inputs to P4080
Priority
Interrupt
Cause
Recoverability
Power-on reset
PORESET~ input
Non-recoverable
Hard Reset Input
HRESET~ input
Non-recoverable
External Interrupt
IRQ~ inputs
Recoverable
TheFPGAcontainsalloftherequiredlogicforresetsandinterrupts.
5.16.1 Hard Reset

Ahardreset,generatedbytheFPGA,isusedtoresettheP4080(includingthe
processingcores)andallotherdevicesontheSBC312thatrequireresetting.
Ahardresetisassertedwhenanyofthefollowingeventsoccur:
Anyofthepowersuppliesfalloutsidespecification
TheVPXSYSRESET~signalisasserted
TheprocessorHRESET_REQ~outputisasserted
ThefrontpanelResetswitchistoggled(whenenabledinsoftware)
TheHRESET~signalontheBDMheaderisasserted
TheresetoutputoftheBMMisasserted
TheEXT_RESET~backplanepinisasserted
TheRESET_OUT~signalfromthePMC/XMCsiteisasserted
Awatchdogtimerexpires
MSKRST~isassertedfor10s(andisnotmaskedbysoftware)
AresetisgeneratedviathePowerOnConfigurationRegister(registeroffset
0x0008)
Thedurationoftheinternalhardresetsignalisatleast10ms.
TheFPGAlatchesthecauseofahardresetanddisplaysitinthe
ResetCauseRegister(registeroffset0x0010)forsoftwareinterrogation.
WhenoperatingastheVPXSystemController,theSBC312assertstheVPX
SYSRESET~signalwhenahardresetoccurs.
5.16.2 External Interrupt

PCI Interrupts LegacyPCIdevices,connectedviaPCIExpresstotheP4080,havetheirinterrupts
connectedtotheirrespectivePCIePCIbridges,whichconverttheinterruptsintoPCI
Expressmessages.ThesearethenpassedtotheinterruptcontrollerintheP4080.The
internalinterruptsignalsthatareusedforthispurposeintheP4080aresharedwith
externalinterruptsignalsasshowninthefollowingtable.Forthisreason,these
externalinterruptsarenotusedandarepulledhigh.
Table 5-26 P4080 PCI INTx and External IRQ sharing
PCI Interrupt
External Interrupt Pin
PCI Interrupt
External Interrupt Pin
Port 1 INT B
IRQ[1]
Port 3 INT B
IRQ[9]
Port 1 INT C
IRQ[2]
Port 3 INT C
IRQ[10]
Port 1 INT D
IRQ[3]
Port 3 INT D
IRQ[11]
TheINTAsignalsfromthePCIeportsareroutedasdedicatedinputstotheInterrupt
Controllerandarenotsharedwithexternalpins.
FPGA TheFPGAconnectstotheIRQ[0]andIRQ[4:8]interruptinputstotheP4080.These
Interrupts inputsareconfiguredasactivelow,levelsensitive.TheFPGAregistersprovidethe
optiontoroutetheinternalandexternalinterruptsourcesshownbelowtoanyof
theseinterruptinputsundersoftwarecontrolviatheP4080InterruptINTxMask
Registers(x=0or4:8),offsets0x4012to0x4026.
WatchdogTimerinterrupts
AXISmessagingFIFOinterrupts
EthernetPHYinterrupts
RTCinterrupt
Temperatureinterrupts
BackplaneGDISC1inputinterrupt
BMMinterrupts
GPIOinterrupts
UARTinterrupts
DMAengineinterrupts
TheFPGAallowstheprocessortodeterminethecauseoftheinterruptbyreading
theBoardInterruptStatusRegister(registeroffset0x4002).
5.17 FPGA
ALatticeMachXO2280CdeviceconnectedtotheP4080LocalBusprovidesthe
followingfunctions:
P4080processorconfiguration
Address,dataandchipselectgenerationforFlash/MRAMdevices
Ancillaryboardfunctions
Resetlogic
ControlandStatusregisters
AXISMessagePassinginterface
Secondaryinterruptcontroller
UARTfortheBMM
GeneralPurposeI/OController(accessedusingChipSelectCS7)
DMAEnginesfortransferofdatabetweenserialportsandinternal/external
SRAM(accessedusingChipSelectCS7)
ExternalSRAMinterface(accessedusingChipSelectCS6)
AnexternalSRAMdeviceisconnectedtotheFPGAforlocalbufferingofdataas
requiredbytheapplication.Thedevicefittedis16bitswideandhasacapacityof
2MBytes.
5.18 Control and Status Registers

TheSBC312providesseveralregistersforsoftwaretocontrolorreadthestatusofthe
board.AllregistersareaccessedusingLocalBuschipselectCS4andareconfigured
as16bitwide.
Thefollowingtablegivesthelocationsoftheregisters,offsetfromtheCS4base
address(whichisconfiguredbysoftware),andaccesstotheregister:
Table 5-27 Control and Status Registers
Register
Offset
R/W
Register
Offset
R/W
Register
Offset
R/W
Board ID
0x0000
RO
Board Semaphore 1
0x0040
R/W
P4080 Interrupt INT5 Mask
0x401A
R/W
Revision
0x0002
RO
Board Semaphore 2
0x0044
R/W
0x401E
R/W
Address
0x0006
RO
Board Semaphore 3
0x0048
R/W
0x4022
R/W
Power-On Configuration
0x0008
RO
Board Semaphore 4
0x004C
R/W
0x4026
R/W
Board Configuration 1
0x000A
RO
Board Semaphore 5
0x0050
R/W
REFCLK Counter Mid Value
0x6000
RO
Board Configuration 2
0x000C
RO
Board Semaphore 6
0x0054
R/W
REFCLK Counter Low Value
0x6002
RO
RAM/Flash Configuration
0x000E
RO
Board Semaphore 7
0x0058
R/W
REFCLK Counter High Value
0x6006
RO
Reset Cause
0x0010
RO
Board Semaphore 8
0x005C
R/W
Counter Control
0x6008
R/W
Link Status
0x0012
RO
Board Semaphore 9
0x0060
R/W
REFCLK/AUXCLK Control
0x600A
R/W
Control 1
0x0014
R/W
Board Semaphore 10
0x0064
R/W
AUXCLK Counter High Value
0x600C
RO
Serial Control
0x0016
R/W
Board Semaphore 11
0x0068
R/W
AUXCLK Counter Low Value
0x600E
RO
Control 3
0x001A
R/W
Board Semaphore 12
0x006C
R/W
AXIS Semaphore 1
0x6020
R/W
Test Pattern 1
0x0020
RO
Board Semaphore 13
0x0070
R/W
AXIS Semaphore 2
0x6024
R/W
Test Pattern 2
0x0022
RO
Board Semaphore 14
0x0074
R/W
AXIS Semaphore 3
0x6028
R/W
Test Pattern 3
0x0024
RO
Board Semaphore 15
0x0078
R/W
AXIS Semaphore 4
0x602C
R/W
Test Pattern 4
0x0026
RO
Board Semaphore 16
0x007C
R/W
AXIS Semaphore 5
0x6030
R/W
Test Pattern 5
0x0028
RO
Watchdog 0 Control 1
0x2000
R/W
AXIS Semaphore 6
0x6034
R/W
Test Pattern 6
0x002A
RO
0x2002
R/W
AXIS Semaphore 7
0x6038
R/W
Scratch 1
0x0030
R/W
Watchdog 0 Interrupt Value 1
0x2004
R/W
AXIS Semaphore 8
0x603C
R/W
Scratch 2
0x0032
R/W
0x2006
R/W
FIFO Data A
0x6040/42
R/W
Scratch 3
0x0034
R/W
0x2010
R/W
FIFO Data B
0x6044/46
R/W
Scratch 4
0x0036
R/W
0x2012
R/W
FIFO Data C
0x6048/4A
R/W
Scratch 5
0x0038
R/W
0x2014
R/W
FIFO Data D
0x604C/4E
R/W
Scratch 6
0x003A
R/W
0x2016
R/W
FIFO Status A
0x6050/52
R/W
Scratch 7
0x003C
R/W
Board Interrupt Status
0x4002
RO
FIFO Status B
0x6054/56
R/W
Scratch 8
0x003E
R/W
0x4012
R/W
FIFO Status C
0x6058/5A
R/W
0x4016
R/W
FIFO Status D
0x605C/5E
R/W
Where:
R/W = Read/Write
RO = Read Only
Thefollowingsectionsprovidethedefinitionsforthefunctionofeachbitwithina
register.Allregistersareconfiguredsuchthatbit0isthemostsignificantbitandbit
15istheleastsignificantbit.
5.18.1 Board ID Register (Offset 0x0000)

ThisallowssoftwaretoidentifythespecificboardtypeandPCBrevision.
Table 5-28 Board ID Register
Bits
0:7
8:15
Description
Board ID
PCB revision
Notes
SBC312 = 0x52
1, 2, 3 etc.
5.18.2 Revision Register (Offset 0x0002)

ThisallowssoftwaretoidentifythespecificboardconfigurationandFPGAversion.
Table 5-29 Revision Register
Bits
0:7
8:15
Description
Minor board revision
FPGA revision
Notes
1 = A, 2 = B, 3 = C etc.
1, 2, 3 etc.
5.18.3 Address Register (Offset 0x0006)

ThiscontainstheSBC312sgeographicaddress,asdeterminedfromthebackplane.
Table 5-30 Address Register
Bits
0:6
Description
Reserved
VPX System Controller
8:9
Reserved
10
Geographic Address Odd Paritya
11:15
VPX Geographic Address
Notes
0x00
0 = Board is not VPX System Controller
1 = Board is VPX System Controller
00
0 = Odd number of bits set
1 = Even number of bits set
From the backplane signals.
All bits are inverted to present the actual address
a. Inverted from the backplane signal.
5.18.4 Power-On Configuration Register (Offset 0x0008)

ThisregisterprovidesawayforsoftwaresuchasBITtoexitcleanlytoanotherpiece
ofsoftware,suchasVxWorks.Astatusvaluethatispassedbetweenthesoftware
domainsmaybewrittentothisregister,andafullboardresetthatplacesallthe
hardwareintoaknownstatemaybegenerated.ThestatusofthefrontpanelBIT
LEDsisalsomaintainedifaresetisgeneratedinthismanner.
Thisregistercontainsfourstickybitsthatmakeuppartofthepoweronreset
configurationvaluethattheP4080takesinonthelocaladdress/databusandstores
initsGeneralPurposePORConfigurationRegister1(GPPORCR1).Ifthesebitsin
theGPPORCR1arezero,thensoftwareknowsthattheSBC312hasjustbeenresetby
hardware.
Table 5-31 Power-On Configuration Register
Bits
0:6
Description
Reserved
Software Hard Reset Request
8:11
12:15
Reserved
General purpose software configuration value
Notes
0x00
1 = Generate a hard reset to the SBC312
(all hardware except sticky bits in the FPGA will be reseta
0x0
Sticky bits (default to 0x0)
a. This bit will self-clear to 0 during the reset event and so should never be read as 1.
5.18.5 Board Configuration Register 1 (Offset 0x000A)

ThiscontainsinformationonthenumberofcoresinuseandtheSYSCLKfrequency.
Table 5-32 Board Configuration Register 1
Bits
0:10
Description
Reserved
11
Reduced cores mode
12 to 14
Reserved
15
SYSCLK Frequency
Notes
000
0 = 8-core mode
1 = 4-core mode
000
0 = Reserved
1 = 100 MHz (default)
5.18.6 Board Configuration Register 2 (Offset 0x000C)

ThiscontainsinformationontheconfigurationoftheSBC312includinginformation
onwhetheramezzanineisfittedandhowtherearI/Ofromtheboardisconfigured.
Table 5-33 Board Configuration Register 2
Bits
0:7
Description
Reserved
SBC310-compatible pinout
9:12
Reserved
13
XMC fitted in site
14
Reserved
15
PMC fitted in site
Notes
0x00
0 = OpenVPX compatible (COM2_RX on P2 G11)
1 = SBC310-compatible (COM2_RX on P1 G15)
0x0
0 = No XMC fitted
1 = XMC fitted
0
0 = No PMC fitted
1 = PMC fitted
5.18.7 RAM/Flash Configuration Register (Offset 0x000E)

ThiscontainsinformationontheconfigurationoftheSBC312includinginformation
ontheRAMandFlashdevicesfitted.
Table 5-34 RAM/Flash Configuration Register
Bits
0
1:2
3
Description
Flash type
Reserved
Flash bank width
4:5
Flash banks
6:7
Flash device size
8:10
Reserved
11
Stacked DRAM devices
12
RAM Device width
13:14
DRAM device size
15
Reserved
Notes
1 = Spansion Flash fitted
00
1 = 16-bit Flash
00 = 1 bank of Flash
01 = 2 banks of Flash
00 = Reserved
01 = 512 Mbit Flash devices
10 = 1 Gbit Flash devices
11 = 2 Gbit Flash devices
000
0 = Single die devices fitted (1 rank/controller)
1 = Stacked die devices fitted (2 ranks/controller)
1 = 16-bit
00 = 1 Gbit
01 = 2 Gbit
10 = 4 Gbit
11 = Reserved
0
5.18.8 Reset Cause Register (Offset 0x0010)

Forbits0to12,asetbitshowsthatthelastresetwascausedbythecorresponding
device/source.Ifnobitisset,itmaybeassumedthattheresetwascausedbya
powersupplybeingoutofspecification.
Table 5-35 Reset Cause Register
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Device
Backplane reset
P4080 Hard Reset Request reset
Watchdog 1 reset
Watchdog 0 reset
Backplane EXT_RESET~ reset
Reserved
BMM reset
BDM reset
Reserved
PMC/XMC reset
Reserved
Backplane MSKRST~ reset
Software Hard Reset Request reset
Reserved
14
XMC Built-In Self-Test (BIST)
15
EREADY
Notes
0
0
In Power-On Configuration Register
0
0 = XMC BIST complete
1 = XMC BIST in progress
0 = PMC ready for enumeration
1 = PMC not ready for enumeration
5.18.9 Link Status Register (Offset 0x0012)

Thiscontainsinformationonthelinks.
Table 5-36 Link Status Register
Bits
0:2
Description
Reserved
BIT Mode 0
Non-Volatile Memory Read Only
5:6
Reserved
MRAM Write Enable linka
Recovery Area Write Enablea
Flash Protection Unlock linka
10:12
Reserved
13
Boot Recovery Flash Area link
14
Reserved
15
Boot Alternate Flash Area link
Notes
000
0 = BIT_MODE0 signal high
1 = BIT_MODE0 signal low
0 = NVMRO signal high memory protected
1 = NVMRO signal low memory writeable
00
0 = Jumper not fitted
1 = Jumper fitted
0 = Recovery area not writeable
1 = Recovery area writeable
1 = Jumper fitted
000
1 = Jumper fitted
0
1 = Jumper fitted
a. Register bit is interlinked with backplane NVMRO signal.
5.18.10 Control Register 1 (Offset 0x0014)

SoftwarecanusethisregistertocontrolaspectsoftheSBC312sfunctionality,suchas
BITLEDs.
Table 5-37 Control Register 1
Bits
0:6
Description
Reserved
BIT Flag
Reserved
NVMRO overridea
10:11
Reserved
12
BIT Pass (green) LED status
13
BIT LED 2 (yellow) LED status
14
BIT LED 1 (yellow) LED status
15
BIT Fail (red) LED status
Notes
0x00
0 = BIT not run (default)
1 = BIT run
0
0 = NVMRO backplane signal not driven
1 = NVMRO backplane signal driven low (write enable)
00
0 = BIT Pass LED unlit (default)
1 = BIT Pass LED lit
0 = BIT LED 2 unlit (default)
1 = BIT LED 2 lit
0 = BIT LED 1 unlit (default)
1 = BIT LED 1 lit
0 = BIT Fail LED unlit
1 = BIT Fail LED lit (default)
a. This bit is only writeable when the SBC312 is VPX System Controller.
5.18.11 Serial Control Register (Offset 0x0016)

Softwarecanusethisregistertocontrolthedebugserialporttransceivers.
Table 5-38 Serial Control Register
Bits
0 to 9
Description
Reserved
10
COM2 RS232 mode
11 and 12
Reserved
13
COM1/COM2 loopback enable
14
COM1 RS232 mode
15
COM1/COM2 transceiver enable
Notes
0x00
0 = COM2 RS422
1 = COM2 RS232 (default)
00
0 = COM1/COM2 loopback disabled (default)
1 = COM1/COM2 loopback enabled
0 = COM1 RS422
1 = COM1 RS232 (default)
0 = COM1/COM2 transceiver disabled (default)
1 = COM1/COM2 transceiver enabled
5.18.12 Control Register 3 (Offset 0x001A)

SoftwarecanusethisregistertocontrolotheraspectsoftheSBC312sfunctionality
suchasoverridesforcontrolforthebackplaneGDISC1signalandresetmasks.
Table 5-39 Control Register 3
Bits
0:1
2:3
Description
Reserved
Reserved
Drive GDISC1 low
GDISC1 interrupt polarity
GDISC1 interrupt triggering
GDISC1 interrupt statusa
9:11
GDISC1 backplane input value

(read only)
Reserved
12
Backplane Maskable Reset mask
13
Backplane Maskable Reset drive
14:15
Reserved
Notes
00
00
0 = GDISC1 not driven low (default)
1 = GDISC1 driven low
0 = GDISC1 interrupt active low or high-to-low (default)
1 = GDISC1 Interrupt active high or low-to-high
0 = GDISC1 interrupt level triggered (default)
1 = GDISC1 interrupt edge triggered
0 = GDISC1 interrupt inactive (default)
1 = GDISC1 interrupt active
0 = GDISC1 input low
1 = GDISC1 input high
000
0 = Reset input active
1 = Reset input masked (default)
0 = Reset not driven active (default)
1 = Reset driven active
00
a. In edge-triggered mode, writing a value of 1 to this bit will clear the latched interrupt.
5.18.13 Test Pattern Registers 1 to 6 (Offsets 0x0020 to 0x002A)

Registers1to4normallycontainanalternatingsetbittestpatterntoverifybit
orderingandcheckforstuckbits.WhenthebackplaneNVMROsignalisinactive
low,thevalueoftheseregisterschangestoallowsoftwaretoaltertheFlashsector
protection.
Registers5and6containatestpatterntocheckforbyteorderingfromtheFPGA.
Table 5-40 Test Pattern Registers
Register
1
2
3
4
5
6
Test Pattern
0xAAAA
0xAAAA
0x5555
0x5555
0x5342 (SB)
0x4333 (C3)
5.18.14 Scratchpad Registers (Offsets 0x0030 to 0x003E)

Theseeight16bitregistershavenoeffectonthesystemandareprovidedfor
softwaretostorestatusinformationordata.Theirvalueonresetis0x0000.
5.18.15 Board Semaphore Registers (Offsets 0x0040 to 0x007C)

Eachregistercontrolsoneofsixteensemaphores.
Table 5-41 Board Semaphore Register Offsets
Offset
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
Semaphore
1
2
3
4
5
6
7
8
Offset
0x0060
0x0064
0x0068
0x006C
0x0070
0x0074
0x0078
0x007C
Semaphore
9
10
11
12
13
14
15
16
Asemaphoreistakenbyreadingthecorrespondingregister:
Ifthevaluereturnediszero,thensemaphoreiscurrentlyinuse
Ifthevaluereturnedisnonzero,thenthesemaphoretakeissuccessful
Thesemaphoreisreleasedbywritingtothecorrespondingregister(thevalue
writtenisnotsignificant).
Theresetvalueforallsemaphoreregistersis0x0001.
5.18.16 Watchdog 0 Control Register 1 (Offset 0x2000) and

Watchdog 1 Control Register 1 (Offset 0x2010)
Theseregisterscontroltheoperationofwatchdogtimers0and1respectively.
Table 5-42 Watchdog Control Register 1
Bits
Description
Watchdog statusa
Watchdog expireda
Watchdog interrupta
3
4:5
6:7
Reserved
Service watchdog
Enable watchdog
8:15
Counter preset value
Notes
0 = Watchdog enabled
1 = Watchdog disabled
0 = Watchdog not expired
1 = Watchdog counter expired (reset)
0 = Watchdog interrupt inactive
1 = Watchdog interrupt active
0
A write of 01 followed by 10 to these bits services the watchdog
A write of 01 followed by 10 to these bits enables/disables the watchdog
Bits 0 to 7 of the value loaded by the watchdog counter whenever it is enabled
or serviced. 0xFF by default.
a. Read only.
5.18.17 Watchdog 0 Control Register 2 (Offset 0x2002) and

Watchdog 1 Control Register 2 (Offset 0x2012)
Theseregisterssetbits8to23ofthevalueloadedbythecorrespondingWatchdog
counterwheneveritisenabledorserviced.Bits24to31arealways0xFF.Thedefault
valueoftheseregistersis0xFFFF.

Watchdog 1 Interrupt Value Register 1 (Offset 0x2014)
Theseregisterssetbits8to15oftheinterruptthresholdvalueforWatchdogtimers0
and1respectively.Onexpiryofthecount,aninterruptisgeneratedtotheinterrupt
controller.Thedefaultvalueoftheseregistersis0x0000.
Table 5-43 Watchdog Interrupt Value Register 1
Bits
0:7
8:15
Description
Bits 0 to 7 of the interrupt threshold value
Notes
Always 0x00

Watchdog 1 Interrupt Value Register 2 (Offset 0x2016)
Theseregisterssetbits16to31oftheinterruptthresholdvalueforWatchdogtimers
0and1respectively.Thedefaultvalueoftheseregistersis0x0000.
Table 5-44 Watchdog Interrupt Value Register 2
Bits
0:7
8:15
Description
Notes
Always 0x00
5.18.20 Board Interrupt Status Register (Offset 0x4002)

AsetbitindicatesanactiveinterruptfromthecorrespondingdevicetotheFPGA.
Table 5-45 Board Interrupt Status Register
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Device
GDISC1
Core temperature sensor (caution)
Core temperature sensor (critical)
Real Time Clock
Board temperature sensor (caution)
Board temperature sensor (critical)
Ethernet PHY1
Reserved
BMM UART
Reserved
Watchdog 0
Watchdog 1
AXIS Message FIFO A
AXIS Message FIFO B
AXIS Message FIFO C
AXIS Message FIFO D
5.18.21 P4080 Interrupt INT0 Mask Register (Offset 0x4012)

Asetbitenablesanactiveinterruptfromthecorrespondingdevicetodriveoutthe
P4080_INT0_Ninterrupt.
Table 5-46 P4080 Interrupt INT0 Mask Register
Bit
Device
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GDISC1
Core temperature sensor (caution)
Core temperature sensor (critical)
Real Time Clock
Board temperature sensor (caution)
Board temperature sensor (critical)
Ethernet PHY1
Reserved
BMM UART
Reserved
Watchdog 0
Watchdog 1
AXIS Message Queue 0

ThebitallocationisasfortheP4080InterruptINT0MaskRegister.
5.18.23 P4080 Interrupt INT5 Mask Register (Offset 0x401A)

5.18.24 P4080 Interrupt INT6 Mask Register (Offset 0x401E)



5.18.27 REFCLK Counter High, Mid and Low Value Registers

(Offsets 0x6000 to 0x6006)
Theseregistersholdbits0:15,16:31and32:47oftheREFCLKcountervalue
respectively.Thedefaultvalueoftheseregistersis0x0000.
NOTE
Reading the REFCLK Mid Value register causes the value of the whole timestamp (including the low
and high value registers) to be latched to prevent rollover during the read. The REFCLK Mid Value
register should therefore be read before the low/high value registers to prevent the reading of stale
data.
5.18.28 Counter Control Register (Offset 0x6008)

ThisregistercontainscontrolbitsfortheREFCLKandAUXCLKcounters.
Table 5-47 Counter Control Register
Bits
Description
Test mode
1:15
Reserved
Notes
0 = Normal operation (default)
1 = Counters split into separate 16-bit counters (three for REFCLK and two for AUXCLK)
0x0000
5.18.29 REFCLK/AUXCLK Control Register (Offset 0x600A)

ThisregistercontainscontrolbitsfortheREFCLKandAUXCLKcounters.
Table 5-48 REFCLK Control Register
Bits
Description
Use Maskable Reset for countersa
1:11
Reserved
12
AUXCLK Out
13
AUXCLK Master
14
Counter resetb
15
REFCLK masterc
Notes
0 = Maskable Reset not used for counters (default)
1 = Maskable Reset used for counters
0x000
The value of this bit is driven onto the backplane AUXCLK
when the AUXCLK Master bit is set to 1
0 = Backplane AUXCLK not driven (default)
1 = Backplane AUXCLK driven with value of AUXCLK Out bit
0 = Maskable Reset output inactive (default)
1 = Maskable Reset output active
0 = REFCLK slave - uses backplane REFCLK and reset for counter
1 = REFCLK master - generates backplane REFCLK and reset for counter
a. When 1, the VPX Maskable Reset is driven by the REFCLK master, using the value of bit 14, and is used to clear the
REFCLK and AUXCLK counters when active. Ensure that the Backplane Maskable Reset Mask bit in Control Register 3 is set
before enabling this mode. This mode is intended to emulate and be compatible with the legacy AXIS_TIMER_RESET signal.
b. This determines the state of the backplane Maskable Reset signal when in master mode and bit 0 is set.
c. This bit is set to 1 when VPX_SYSCON is 0. The REFCLK master may be subsequently reassigned by software if required.
5.18.30 AUXCLK Counter High and Low Value Registers

(Offsets 0x600C & 0x600E)
Theseregistersholdbits0:15and16:31oftheAUXCLKcountervaluerespectively.
Thedefaultvalueoftheseregistersis0x0000.
NOTE
Reading the AUXCLK Counter High Value register causes the value of the whole counter (including the
low value register) to be latched to prevent rollover during the read. The AUXCLK Counter High Value
register should therefore always be read before the low value register to prevent the reading of stale
data.
5.18.31 AXIS Semaphore Registers (Offsets 0x6020 to 0x603C)

Eachregistercontrolsoneofeightsemaphores.
Table 5-49 AXIS Semaphore Register Offsets
Offset
0x6020
0x6024
0x6028
0x602C
Semaphore
1
2
3
4
Offset
0x6030
0x6034
0x6038
0x603C
Semaphore
5
6
7
8
Asemaphoreistakenbyreadingthecorrespondingregister:
Ifthevaluereturnediszero,thensemaphoreiscurrentlyinuse
Ifthevaluereturnedisnonzero,thenthesemaphoretakeissuccessful
Thesemaphoreisreleasedbywritingtothecorrespondingregister(thevalue
writtenisnotsignificant).
Theresetvalueforallsemaphoreregistersis0x0001.
5.18.32 FIFO Data Registers (Offsets 0x6040 to 0x604C

TheseregistersformthedatapathtoeachFIFO.Awriteaccessaddsthe32bit
messageontothebackofthequeueandareadaccessremovesthefirstmessage
fromthefrontofthequeue.
Theseregistersareduplicatedwithina32bitword(e.g.awriteto0x6040or0x6042
willbothenterdataintoFIFOA)toallowcompatibilitywithexistingsoftware,
whichperforms32bitread/writeaccessestotheseregisters.TheLocalBuscontroller
ontheSBC312splitstheseintotwo16bitaccesses.
Table 5-50 FIFO Data Register Offsets
Offset
0x6040/42
0x6044/46
0x6048/4A
0x604C/4E
FIFO
A
B
C
D
Thedefaultvalueoftheseregistersis0x0000.
5.18.33 FIFO Status Registers (Offsets 0x6050 to 0x605C)

TheseregisterscontainstatusinformationoneachFIFO.
Theseregistersareduplicatedwithina32bitword(e.g.areadfrom0x6050or
0x6052willbothreadthestatusofFIFOA)toallowcompatibilitywithexisting
software,whichperforms32bitread/writeaccessestotheseregisters.TheLocalBus
controllerontheSBC312splitstheseintotwo16bitaccesses.
Table 5-51 FIFO Status Register Offsets
Offset
0x6050/52
0x6054/56
0x6058/5A
0x605C/5E
FIFO
A
B
C
D
Table 5-52 FIFO Status Register

Bits
0:10
Description
Reserved
11
FIFO reset
12
FIFO fulla
13
FIFO almost fulla
14
FIFO almost emptya
15
FIFO emptya
Notes
0x000
0 = FIFO normal operation (default)
1 = FIFO reset
0 = FIFO not full
1 = FIFO full
0 = FIFO has more than 1 space
1 = FIFO has only 1 space
0 = FIFO has more than 1 entry
1 = FIFO has only 1 entry
0 = FIFO not empty
1 = FIFO empty (default on reset)
a. Read-only.
5.18.34 GPIO Registers

TheregisterdefinitionsfortheregistersconcernedwithGeneralPurposeI/Oand
controlofCOM3toCOM5ontheSBC312arenotdocumentedinthismanualasthey
areintendedonlytobeaccessedbyGEIPsoftwaredrivers.
5.19 JTAG
5.19.1 Boundary Scan
TheSBC312providesJTAGboundaryscanfacilitiesforallIEEE1149.1and
IEEE1149.6compliantdevices.AFirecronJTS06BuScanbridgedevicepartitionsthe
JTAGchainforeasierfaultdiagnosisandfasterJTAGFlashprogramming.The
primaryinterfacetotheScanbridgechainisfromthestandardVPXpinsonthe
backplaneP0connector.
TheJTAGstructureisasfollows:
Figure 5-5 JTAG Chains
Mezzaninecards(XMCorPMC)areontheirownJTAGchainandthesiteis
automaticallybypassed(usingonboardbuffers)whennomezzaninecardisfitted.
TheJTAGarchitecturesupportstheuseoftheJTAGTechnologiesAutowritesignal
toaccelerateFlashprogrammingviaJTAG.ThissignalisconnectedtotheVPX
reservedP1G7pinandcouldbedisconnectedifrequired.
TheScanbridgecanbesetintopassthroughmodeusingsignalsavailableontheP7
connector(notnormallyfitted).Thisfunctionalitymaybeused,forexample,for
accessingJTAGchainstoFPGAmezzanineboardsfromthebackplanewithout
havingtocommunicatewiththeScanbridgedevice.Thebypassmodeisenabledby
settingtheJTAG_PASS_THRU_EN~signallow.
TheScanbridgesupportssixTestAccessPorts(TAPs).TherequiredTAPisselected
usingthePASS_THRU[2:0]signals,asshowninthefollowingtable.
Table 5-53 JTAG Chains
PASS_THRU2
PASS_THRU1
PASS_THRU0
TAP
Devices in Chain
P4080 processor
Ethernet PHY 1, Ethernet PHY 2
PCIe switch 1
PMC1 bridge
XMC site, PMC site
FPGA
ThebackplaneaddressoftheJTAGScanbridgeisderivedfromtheVPXgeographic
address(visibleintheAddressRegister[registeroffset0x0006]).Thisisusedwhen
operatingabusedJTAGsystemwithmultipleboards.
TheUSRSTATUS_BYTEregisterintheScanbridge(accessiblethroughtheprimary
TAP)hasthefollowingformat:
Table 5-54 USR_STATUS_BYTE Register Format
7
PMC2
PMC1
AFIX
4
1
3
1
2
0
ID
1
1
0
0
TheGEIPcardIDis26(0x1A).
Bits7to5areusedtodeterminewhatmezzaninecardsarefittedtotheSBC312as
follows:
Bit7=Always1(nomezzanine2site).
Bit6=Mezzanine1(0whenPMCorXMCfitted,1otherwise).
Bit5=Always1(noAFIXsite).
5.19.2 Aurora Debug Header

TheSBC312providesa22pinconnector(J3)forinterfacingtotheAurorahighspeed
debuginterfaceoftheP4080.ThisconnectoralsocontainsthelegacyJTAGsignals
forcontrollingtheprocessor.
Seesection6.5forthepinoutofthisheader.
CAUTION
When using this header, ensure that the Scanbridge is disabled (P9 pins 9 and 10 are not linked).
TheTestAccesscardalsohasastandardBDMheaderforJTAGaccesstotheP4080
BDM.
5.19.3 FPGA Programming Header

TheSBC312TestAccessCardprovidesaprogrammingheader,compatiblewiththe
Latticedownloadcable,toallowJTAGprogrammingaccesstothePowerManager
andFPGA.
CAUTION
When using this header, ensure that the Scanbridge is disabled (P9 pins 9 and 10 are not linked).
5.20 LEDs
LEDsaremountedonthebackoftheSBC312toreflectthestatusofthefollowing
functions:
PowerSupplies
BIT
Resetstatus
Ethernetlinks
PCIExpresslinks
SATAactivity
ThefollowingdiagramshowsthepositionsoftheLEDs.
Figure 5-6 LED Positions
5.20.1 Power Good LED (DS200)

ThisgreenLEDisdrivenbythePowerManager.Whenon,itindicatesthatallon
boardandoffboardpowersuppliesarewithintheirspecifiedlimits.
5.20.2 BIT LEDs (DS201 to DS204)

Table 5-55 BIT LEDs
LED
DS201
DS202
Color
Red
Yellow
Default Function
BIT Fail
BIT LED 1
DS203
DS204
Yellow
Green
BIT LED 2
BIT Pass
Description
Softwarecontrolled LEDs used to show
the status of BIT or other boot software
DS201maybeliteitherbytheBMMorundersoftwarecontrolviaControlRegister1
(registeroffset0x0014).Itislitbydefaultafterresetandmustbeturnedoffbyboth
theBMMandhostcard.DS201ispoweredfromtheauxiliarypowersupply,andso
canbelitevenwhenthemainpowersuppliesarenotactiveorhavefailed.DS202to
DS204areunlitafterresetandaredrivenundersoftwarecontrolfromControl
Register1.
WhenusedbyBIT,DS201eithershowsthatBIThasnotyetrun(straightaftera
reset)orhasrunbutfailed.DS202andDS203showprogressthroughBIT,andso
mayprovideinformationfordebuggingpurposesintheeventoffailure.DS204
showsthatBIThaspassed.
Table 5-56 BIT Status LED Meanings
BIT Fail LED
(DS202)
BIT Passed
LED (DS204)
Status
On
Off
BIT not yet run (Reset state) or BIT failed
Off
On
BIT complete and passed
TheBITFAIL~signalontheP2connectorisdrivenactivelowusinganopendrain
driverwhentheredBITLEDislit.
5.20.3 SATA Activity LEDs (DS205 and DS206)

Whenlit,theseyellowLEDsshowSATAactivityonthecorrespondingchannel.
Table 5-57 SATA Activity LEDs
LED ID
DS205
DS206
Function
SATA Channel 1 activity
SATA Channel 0 activity
5.20.4 Reset Status LED (DS207)

ThemainBoardResetsignaldrivesthisredLEDtoshowthattheboardisinreset.
5.20.5 Ethernet PHY 1 Link Status LEDs (DS208 to DS211)

TheseyellowLEDsarecontrolledbyPHY1.
Table 5-58 Ethernet Link Status LEDs
LED ID
DS208
DS209
DS210
DS211
Function
ETH0 Activity
ETH1 Activity
ETH1 Gigabit
ETH0 Gigabit
Description
Ethernet port 0 activity (off = no link, on = link active, flashing = activity)
Ethernet port 1 activity (off = no link, on = link active, flashing = activity)
Ethernet port 1 operating in 1000BaseT mode
Ethernet port 0 operating in 1000BaseT mode
5.20.6 PCI Express Switch Link Status LEDs (DS212 to DS215)

OnandoffboardPCIExpresslinkshaveassociatedgreenLEDs,whicharelitto
indicatethatthelinkisactive.
Table 5-59 PCI Express Switch Link Status LEDs
LED
DS212
DS213
DS214
DS215
Switch Port
0
4
8
16
Link
x4 to the P4080
XMC
x2 to the P4080
External port A
FurtherinformationonthelinkstatusmaybeobtainedbysoftwarereadingthePCI
Expressdeviceregisters.
5.21 Front Panel

5.21.1 Air-cooled Versions (Build Levels 1 to 3)
Figure 5-7 Air-cooled Front Panel
PMC Slot TheSBC312frontpanelhasprovisionforfrontI/OfromthePMC/XMCsite.Ifno

PMChasbeenorderedaspartofanassemblywiththeSBC312,thenGEIPwillfita
blankingplateintheslotforEMCprotection.
IfyouarefittinganonGEIPPMC,itmustcomplywiththeP1386.1standardforair
cooledmezzaninestoensurethatitmatescorrectlywiththeSBC312mechanics.GEIP
PMCscomplywiththisstandard.
IfyouarefittingaPMCyourself,beforefittingthemodule,removethe
correspondingblankingplatefromthedesiredPMCslot.ThePMCsbezelshouldfill
theslotandmayprovidefrontpanelconnectiontothemodule.GEIPPMCsare
deliveredwithafullkitofpartsformounting,plusfittinginstructions.
5.21.2 Conduction-cooled Versions (Build Levels 4 and 5)

Figure 5-8 Conduction-cooled Front Panel
PMC Slot ThereisnoaccesstofrontI/OfromPMCsinaconductioncooledenvironment.

IfyouarefittinganonGEIPPMC,itmustcomplywiththestandardforrugged,
conductioncooledPMCs(VITA202001)toensurethatitmatescorrectlywiththe
SBC312mechanics.GEIPPMCscomplywiththisstandard.
6 Connectors
Thissectiongivesthepinassignmentsandsignaldescriptionsfortheconnectorson
theSBC312.ThefollowingtableshowsthefunctionoftheconnectorsontheSBC312:
Table 6-1 Connector Functions
Connector
Function
Connector
Function
P0, P1, P2
VPX interface
P7
JTAG Pass Thru
J11, J12, J13, J14
PMC Site 1
P8
See Configuration section
J15, J16
XMC Site 1
P9
See Configuration section
J3
Aurora debug
P4 (rear of PCB)
Test Access Card
Figure 6-1 Connector Positions (Top)
Connectors 79
Figure 6-2 Connector Positions (Back)
6.1 Backplane Connectors

ThefollowingsectionsshowthepinassignmentsoftheSBC312VPXbackplane
connectors(P0toP2).Theseareshowninthe7rowformatasusedintheVPX
specifications.
AlsoprovidedarethecorrespondingpinoutsfortheJ0toJ2backplaneconnectors.
Theseareshowninthe9rowformat.
NOTE
Direction of fabrics is shown such that TX is an output from the SBC312 and RX is an input to the SBC312.
6.1.1 P0
Table 6-2 P0 Pin Assignments
A
VS2
VS2
VS2
N/C
VS1 (N/C)
VS1 (N/C)
VS1 (N/C)
VS2
VS2
VS2
N/C
VS1 (N/C)
VS1 (N/C)
VS1 (N/C)
VS3
VS3
VS3
N/C
VS3
VS3
VS3
NVMRO
SYSRESET~
GND
N12V_AUX
GND
N/C
N/C
SM_DATA
SM_CLK
GND
P3V3_AUX
GND
GA4~
GAP~
GA0~
GA1~
GND
P12V_AUX
GND
GA2~
GA3~
JTAG_TRST~
JTAG_TMS
GND
JTAG_TDI
JTAG_TDO
GND
JTAG_TCK
GND
AUXCLK_P
AUXCLK_N
GND
REFCLK_P
REFCLK_N
GND
6.1.2 Backplane J0
Table 6-3 J0 Pin Assignments
A
VS2
VS2
VS2
VS2
None
VS1 (N/C)
VS1 (N/C)
VS1 (N/C)
VS1 (N/C)
VS2
VS2
VS2
VS2
None
VS1 (N/C)
VS1 (N/C)
VS1 (N/C)
VS1 (N/C)
VS3
VS3
VS3
VS3
None
VS3
VS3
VS3
VS3
GND
NVMRO
SYSRESET~
GND
N12V_AUX
GND
N/C
N/C
GND
GND
SM_DATA
SM_CLK
GND
P3V3_AUX
GND
GA4~
GAP~
GND
GND
GA0~
GA1~
GND
P12V_AUX
GND
GA2~
GA3~
GND
JTAG_TRST~
JTAG_TMS
GND
GND
JTAG_TDI
JTAG_TDO
GND
GND
JTAG_TCK
GND
GND
AUXCLK_P
AUXCLK_N
GND
GND
REFCLK_P
REFCLK_N
GND
Connectors 81
6.1.3 P1
A
PCIE_A_L0_RXP
PCIE_A_L0_RXN
GND
PCIE_A_L0_TXP
PCIE_A_L0_TXN
GND
GDISC1
GND
PCIE_A_L1_RXP
PCIE_A_L1_RXN
GND
PCIE_A_L1_TXP
PCIE_A_L1_TXN
GND
PCIE_A_L2_RXP
PCIE_A_L2_RXN
GND
PCIE_A_L2_TXP
PCIE_A_L2_TXN
GND
VBAT
GND
PCIE_A_L3_RXP
PCIE_A_L3_RXN
GND
PCIE_A_L3_TXP
PCIE_A_L3_TXN
GND
PCIE_B_L0_RXP
PCIE_B_L0_RXN
GND
PCIE_B_L0_TXP
PCIE_B_L0_TXN
GND
SYSCON~
GND
PCIE_B_L1_RXP
PCIE_B_L1_RXN
GND
PCIE_B_L1_TXP
PCIE_B_L1_TXN
GND
PCIE_B_L2_RXP
PCIE_B_L2_RXN
GND
PCIE_B_L2_TXP
PCIE_B_L2_TXN
GND
JTAG_AUTOWR~a
GND
PCIE_B_L3_RXP
PCIE_B_L3_RXN
GND
PCIE_B_L3_TXP
PCIE_B_L3_TXN
GND
SATA0_RXP
SATA0_RXN
GND
SATA0_TXP
SATA0_TXN
GND
COM1_TXD
10
GND
USB1_P
USB1_N
GND
USB2_P
USB2_N
GND
11
USB1_PWR
USB2_PWR
GND
GPIO_0/
SATA1_TXP
GPIO_1/
SATA1_TXN
GND
COM1_RXD
12
GND
GPIO_2/
SATA1_RXP
GPIO_3/
SATA1_RXN
GND
GPIO_4
GPIO_5/
FAST_START
GND
13
ETH1_0P
ETH1_0N
GND
ETH1_1P
ETH1_1N
GND
COM2_TXD
14
GND
ETH1_2P
ETH1_2N
GND
ETH1_3P
ETH1_3N
GND
15
ETH0_0P
ETH0_0N
GND
ETH0_1P
ETH0_1N
GND
MSKRST~/
COM2_RXD
16
GND
ETH0_2P
ETH0_2N
GND
ETH0_3P
ETH0_3N
GND
a This pin is reserved in VITA46.0. It may be isolated from the backplane if required for other purposes in the future.
6.1.4 Backplane J1
A
PCIE_A_L0_RXP
PCIE_A_L0_RXN
GND
GND
PCIE_A_L0_TXP
PCIE_A_L0_TXN
GND
GND
GDISC1
GND
GND
PCIE_A_L1_RXP
PCIE_A_L1_RXN
GND
GND
PCIE_A_L1_TXP
PCIE_A_L1_TXN
GND
PCIE_A_L2_RXP
PCIE_A_L2_RXN
GND
GND
PCIE_A_L2_TXP
PCIE_A_L2_TXN
GND
GND
VBAT
GND
GND
PCIE_A_L3_RXP
PCIE_A_L3_RXN
GND
GND
PCIE_A_L3_TXP
PCIE_A_L3_TXN
GND
PCIE_B_L0_RXP
PCIE_B_L0_RXN
GND
GND
PCIE_B_L0_TXP
PCIE_B_L0_TXN
GND
GND
SYSCON~
GND
GND
PCIE_B_L1_RXP
PCIE_B_L1_RXN
GND
GND
PCIE_B_L1_TXP
PCIE_B_L1_TXN
GND
PCIE_B_L2_RXP
PCIE_B_L2_RXN
GND
GND
PCIE_B_L2_TXP
PCIE_B_L2_TXN
GND
GND
JTAG_AUTOWR~
GND
GND
PCIE_B_L3_RXP
PCIE_B_L3_RXN
GND
GND
PCIE_B_L3_TXP
PCIE_B_L3_TXN
GND
SATA0_RXP
SATA0_RXN
GND
GND
SATA0_TXP
SATA0_TXN
GND
GND
COM1_TXD
10
GND
GND
USB1_P
USB1_N
GND
GND
USB2_P
USB2_N
GND
GPIO_1
SATA1_TXN
GND
GND
COM1_RXD
GND
GPIO_4
GPIO_5/
FAST_START
GND
11
USB1_PWR
USB2_PWR
GND
GND
GPIO_0/
SATA1_TXP
12
GND
GND
GPIO_2/
SATA1_RXP
GPIO_3/
SATA1_RXN
GND
13
ETH1_0P
ETH1_0N
GND
GND
ETH1_1P
ETH1_1N
GND
GND
COM2_TXD
14
GND
GND
ETH1_2P
ETH1_2N
GND
GND
ETH1_3P
ETH1_3N
GND
15
ETH0_0P
ETH0_0N
GND
GND
ETH0_1P
ETH0_1N
GND
GND
MSKRST~/
COM2_RXD
16
GND
GND
ETH0_2P
ETH0_2N
GND
GND
ETH0_3P
ETH0_3N
GND
6.1.5 P2
A
PMC_IO_04/
XMC_IO_F09
PMC_IO_02/
XMC_IO_F08
GND
PMC_IO_03/
XMC_IO_C09
PMC_IO_01/
XMC_IO_C08
GND
BITFAIL~
GND
PMC_IO_08/
XMC_IO_F11
PMC_IO_06/
XMC_IO_F10
GND
PMC_IO_07/
XMC_IO_C11
PMC_IO_05/
XMC_IO_C10
GND
PMC_IO_12/
XMC_IO_F13
PMC_IO_10/
XMC_IO_F12
GND
PMC_IO_11
XMC_IO_C13
PMC_IO_09/
XMC_IO_C12
GND
COM1_RTS
GND
PMC_IO_16/
XMC_IO_F15
PMC_IO_14/
XMC_IO_F14
GND
PMC_IO_15/
XMC_IO_C15
PMC_IO_13/
XMC_IO_C14
GND
PMC_IO_20/
XMC_IO_F17
PMC_IO_18/
XMC_IO_F16
GND
PMC_IO_19/
XMC_IO_C17
PMC_IO_17/
XMC_IO_C16
GND
COM1_CTS
GND
PMC_IO_24/
XMC_IO_F19
PMC_IO_22/
XMC_IO_F18
GND
PMC_IO_23/
XMC_IO_C19
PMC_IO_21/
XMC_IO_C18
GND
PMC_IO_28/
XMC_IO_E01
PMC_IO_26/
XMC_IO_D01
GND
PMC_IO_27/
XMC_IO_B01
PMC_IO_25/
XMC_IO_A01
GND
COM2_RTS
GND
PMC_IO_32/
XMC_IO_E03
PMC_IO_30/
XMC_IO_D03
GND
PMC_IO_31/
XMC_IO_B03
PMC_IO_29/
XMC_IO_A03
GND
PMC_IO_36/
XMC_IO_E11
PMC_IO_34/
XMC_IO_D11
GND
PMC_IO_35/
XMC_IO_B11
PMC_IO_33/
XMC_IO_A11
GND
COM2_CTS
10
GND
PMC_IO_40/
XMC_IO_E13
PMC_IO_38/
XMC_IO_D13
GND
PMC_IO_39/
XMC_IO_B13
PMC_IO_37/
XMC_IO_A13
GND
11
PMC_IO_44/
XMC_IO_E05
PMC_IO_42/
XMC_IO_D05
GND
PMC_IO_43/
XMC_IO_B05
PMC_IO_41/
XMC_IO_A05
GND
N/C
COM2_RX
12
GND
PMC_IO_48/
XMC_IO_E07
PMC_IO_46/
XMC_IO_D07
GND
PMC_IO_47/
XMC_IO_B07
PMC_IO_45/
XMC_IO_A07
GND
13
PMC_IO_52/
XMC_IO_E09
PMC_IO_50/
XMC_IO_D09
GND
PMC_IO_51/
XMC_IO_B09
PMC_IO_49/
XMC_IO_A09
GND
SEQ_IN/
GPIO_6
14
GND
PMC_IO_56/
XMC_IO_E15
PMC_IO_54/
XMC_IO_D15
GND
PMC_IO_55/
XMC_IO_B15
PMC_IO_53/
XMC_IO_A15
GND
15
PMC_IO_60/
XMC_IO_E17
PMC_IO_58/
XMC_IO_D17
GND
PMC_IO_59/
XMC_IO_B17
PMC_IO_57/
XMC_IO_A17
GND
SEQ_OUT/
GPIO_7
16
GND
PMC_IO_64/
XMC_IO_E19
PMC_IO_62/
XMC_IO_D19
GND
PMC_IO_63/
XMC_IO_B19
PMC_IO_61/
XMC_IO_A19
GND
PMCorXMCI/Oisabuildoption.SeethePMC/XMCI/Osectionformoredetails.
Connectors 83
6.1.6 Backplane J2
A
PMC_IO_04/
XMC_IO_F09
PMC_IO_02/
XMC_IO_F08
GND
GND
PMC_IO_03/
XMC_IO_C09
PMC_IO_01/
XMC_IO_C08
GND
GND
BITFAIL~
GND
GND
PMC_IO_08/
XMC_IO_F11
PMC_IO_06/
XMC_IO_F10
GND
GND
PMC_IO_07/
XMC_IO_C11
PMC_IO_05/
XMC_IO_C10
GND
PMC_IO_12/
XMC_IO_F13
PMC_IO_10/
XMC_IO_F12
GND
GND
PMC_IO_11
XMC_IO_C13
PMC_IO_09/
XMC_IO_C12
GND
GND
COM1_RTS
GND
GND
PMC_IO_16/
XMC_IO_F15
PMC_IO_14/
XMC_IO_F14
GND
GND
PMC_IO_15/
XMC_IO_C15
PMC_IO_13/
XMC_IO_C14
GND
PMC_IO_20/
XMC_IO_F17
PMC_IO_18/
XMC_IO_F16
GND
GND
PMC_IO_19/
XMC_IO_C17
PMC_IO_17/
XMC_IO_C16
GND
GND
COM1_CTS
GND
GND
PMC_IO_24/
XMC_IO_F19
PMC_IO_22/
XMC_IO_F18
GND
GND
PMC_IO_23/
XMC_IO_C19
PMC_IO_21/
XMC_IO_C18
GND
PMC_IO_28/
XMC_IO_E01
PMC_IO_26/
XMC_IO_D01
GND
GND
PMC_IO_27/
XMC_IO_B01
PMC_IO_25/
XMC_IO_A01
GND
GND
COM2_RTS
GND
GND
PMC_IO_32/
XMC_IO_E03
PMC_IO_30/
XMC_IO_D03
GND
GND
PMC_IO_31/
XMC_IO_B03
PMC_IO_29/
XMC_IO_A03
GND
PMC_IO_36/
XMC_IO_E11
PMC_IO_34/
XMC_IO_D11
GND
GND
PMC_IO_35/
XMC_IO_B11
PMC_IO_33/
XMC_IO_A11
GND
GND
COM2_CTS
10
GND
GND
PMC_IO_40/
XMC_IO_E13
PMC_IO_38/
XMC_IO_D13
GND
GND
PMC_IO_39/
XMC_IO_B13
PMC_IO_37/
XMC_IO_A13
GND
11
PMC_IO_44/
XMC_IO_E05
PMC_IO_42/
XMC_IO_D05
GND
GND
PMC_IO_43/
XMC_IO_B05
PMC_IO_41/
XMC_IO_A05
GND
GND
N/C
COM2_RX
12
GND
GND
PMC_IO_48/
XMC_IO_E07
PMC_IO_46/
XMC_IO_D07
GND
GND
PMC_IO_47/
XMC_IO_B07
PMC_IO_45/
XMC_IO_A07
GND
13
PMC_IO_52/
XMC_IO_E09
PMC_IO_50/
XMC_IO_D09
GND
GND
PMC_IO_51/
XMC_IO_B09
PMC_IO_49/
XMC_IO_A09
GND
GND
SEQ_IN/
GPIO_6
14
GND
GND
PMC_IO_56/
XMC_IO_E15
PMC_IO_54/
XMC_IO_D15
GND
GND
PMC_IO_55/
XMC_IO_B15
PMC_IO_53/
XMC_IO_A15
GND
15
PMC_IO_60/
XMC_IO_E17
PMC_IO_58/
XMC_IO_D17
GND
GND
PMC_IO_59/
XMC_IO_B17
PMC_IO_57/
XMC_IO_A17
GND
GND
SEQ_OUT/
GPIO_7
16
GND
GND
PMC_IO_64/
XMC_IO_E19
PMC_IO_62/
XMC_IO_D19
GND
GND
PMC_IO_63/
XMC_IO_B19
PMC_IO_61/
XMC_IO_A19
GND
6.1.7 Signal Definitions

Table 6-8 Backplane Connector Signal Definitions
Mnemonic
Description
VS1
VPX VS1 power input. Not used
VS2
VPX VS2 (+3.3 V DC) power input. See the Electrical Specifications section for more details
VS3
VPX VS3 (+5 V DC) power input. See the Electrical Specifications section for more details
N12V_AUX
VPX -12 V DC auxiliary power input. Connected to the PMC/XMC site, otherwise unused by the SBC312
P12V_AUX
VPX +12 V DC auxiliary power input. Connected to the PMC/XMC site, otherwise unused by the SBC312
P3V3_AUX
VPX +3.3 V DC auxiliary power input. See the Electrical Specifications section for more details
NVMRO
Non-Volatile Memory Read Only. When this signal is high, all on-board Non-volatile memory is write-protected. This signal
can be externally pulled low (using a link on the backplane or RTM) or driven low by the SBC312 if configured as System
Controller. The state is reflected in the Link Status Register (register offset 0x0012)
SM_CLK, SM_DATA
System Management bus clock and data. Connected to the BMM via an I2C buffer. Allows access to certain on-board
resources from an external I2C master
GAP~
Geographical addressing parity bit input. The sum of all GA bits, including the parity bit, should be an odd number
GA[4:0]~
Geographical Addressing bits. Reflected in the Address Register (register offset 0x0006)
JTAG_TCK
JTAG TCK input. AC terminated and connects directly to the JTS06 Scan bridge device
JTAG_TDI
JTAG TDI input. Connects to the JTS06 Scanbridge device
JTAG_TDO
JTAG TDO output. Driven by the JTS06 Scanbridge device when selected by the JTAG master
JTAG_TMS
JTAG TMS input. Connects to the JTS06 Scanbridge device
JTAG_TRST~
JTAG TCK input. Connects to the JTS06 Scanbridge device
REFCLK_P/N
VPX Reference Clock positive/negative. See the VPX Interface section
AUXCLK_P/N
VPX Auxiliary Clock positive/negative. See the VPX Interface section
SYSRESET~
System-wide reset. May be driven low by the SBC312 if configured as System Controller
GDISC1
Global Discrete. See the VPX Interface section
VBAT
Battery supply. Can be used to power the real-time clock on the SBC312 (maximum current approximately 1A)
SYSCON~
Pulled low by the backplane to indicate that the module is the VPX system controller. Reflected in the Address Register
(register offset 0x0006)
JTAG_AUTOWR~
JTAG Autowrite signal. Connects to the JTS06 Scanbridge device
SEQ_IN/OUT
PSU sequencing input/output. See the Inter-board Sequencing section for more details.
PSU_SEQ_IN may be left unconnected if inter-board power sequencing is not required
MSKRST~
OpenVPX Module Maskable Reset. May be used to reset the SBC312 or is masked by software
PCIE_x_Ln_RXN/P
PCI Express backplane fabric receive negative/positive inputs. Link (x) = A or B. Lane (n) = 1 to 4. These should be connected
to the transmit outputs of another board to create a link. See the VPX Interface/PCI Express section for how these lanes
may be configured
PCIE_x_Ln_TXN/P
PCI Express backplane fabric transmit negative/positive outputs. Link (x) = A or B. Lane (n) = 1 to 4. These should be
connected to the receive inputs of another board to create a link. See the VPX Interface/PCI Express section for how these
lanes may be configured
PMC_IO_[01:64]
Rear I/O signals from PMC site 1 (J14 connector). Signal names reflect the pin numbers of this connector
XMC_IO_x[01:19]
Rear I/O signals from XMC site 1 (J16 connector). Signal names reflect the pin numbers of this connector
ETH0_nN/P
Gigabit Ethernet Channel 0 differential pairs
ETH1_nN/P
Gigabit Ethernet Channel 1 differential pairs
SATA0_RXN/P,
SATA0_TXN/P
Serial ATA Channel 0 Receive input and Transmit output differential pairs
SATA1_RXN/P,
SATA1_TXN/P
Serial ATA Channel 1 Receive input and Transmit output differential pairs
Connectors 85
Mnemonic
Description
USBn_N/P
Universal Serial Bus differential pairs
USBn_Power
Universal Serial Bus switched power outputs (5V)
COMn_RXD
Serial port n (n = 1 or 2) Receive Data input (RS232 mode)
COMn_TXD
Serial port n (n = 1 or 2) Transmit Data output (RS232 mode)
COMn_CTS
Serial port n (n = 1 or 2) Clear to Send input (RS232 mode). This signal may become COMn_RXD (n = 3 or 4) when selected
via the DIP Switch and Reset Configuration Word
COMn_RTS
Serial port n (n = 1 or 2) Ready to Send output (RS232 mode). This signal may become COMn_TXD (n = 3 or 4) when selected
via the DIP Switch and Reset Configuration Word
BITFAIL~
BIT Fail Output. Reflects the status of the BIT Fail LED. This output is open-drain and so may be used to wire-OR signals
from a number of cards. The output also has a series current limiting resistor and so may be used to drive an LED directly
GND
Signal ground
N/C
No connection
6.2 PMC Connectors

6.2.1 J11 and J12
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
TCK
N12V_AUX
P12V_AUX
TRST~
GND
INTA~
TMS
TDO
INTB~
INTC~
TDI
GND
BUSMODE1~
P5V
GND
N/C
INTD~
10
N/C
N/C
10
N/C
11
GND
12
N/C
11
BUSMODE2
12
P3V3
13
CLK
14
GND
13
RESET_IN
14
BUSMODE3
15
GND
16
GNT_A~
15
P3V3
16
BUSMODE4
17
REQ_A~
18
P5V
17
N/C
18
GND
19
VIO
20
AD31
19
AD30
20
AD29
21
AD28
22
AD27
21
GND
22
AD26
23
AD25
24
GND
23
AD24
24
P3V3
25
GND
26
C/BE3~
25
IDSELA
26
AD23
27
AD22
28
AD21
27
P3V3
28
AD20
29
AD19
30
P5V
29
AD18
30
GND
31
VIO
32
AD17
31
AD16
32
C/BE2~
33
FRAME~
34
GND
33
GND
34
IDSELB
35
GND
36
IRDY~
35
TRDY~
36
P3V3
37
DEVSEL~
38
P5V
37
GND
38
STOP~
39
XCAP
40
LOCK~
39
PERR~
40
GND
41
N/C
42
N/C
41
P3V3
42
SERR~
43
PAR
44
GND
43
C/BE1~
44
GND
45
VIO
46
AD15
45
AD14
46
AD13
47
AD12
48
AD11
47
M66EN
48
AD10
49
AD09
50
P5V
49
AD8
50
P3V3
51
GND
52
C/BE0~
51
AD7
52
REQ_B~
53
AD06
54
AD05
53
P3V3
54
GNT_B~
55
AD04
56
GND
55
N/C
56
GND
57
VIO
58
AD03
57
N/C
58
EREADY
59
AD02
60
AD01
59
GND
60
RESET_OUT~
61
AD00
62
P5V
61
ACK64~
62
P3V3
63
GND
64
REQ64~
63
GND
64
MONARCH~
Connectors 87
6.2.2 J13 and J14

Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
N/C
GND
PMC_IO_01
PMC_IO_02
GND
C/BE7~
PMC_IO_03
PMC_IO_04
C/BE6~
C/BE5~
PMC_IO_05
PMC_IO_06
C/BE4~
GND
PMC_IO_07
PMC_IO_08
VIO
10
PAR64
PMC_IO_09
10
PMC_IO_10
11
AD63
12
AD62
11
PMC_IO_11
12
PMC_IO_12
13
AD61
14
GND
13
PMC_IO_13
14
PMC_IO_14
15
GND
16
AD60
15
PMC_IO_15
16
PMC_IO_16
17
AD59
18
AD58
17
PMC_IO_17
18
PMC_IO_18
19
AD57
20
GND
19
PMC_IO_19
20
PMC_IO_20
21
VIO
22
AD56
21
PMC_IO_21
22
PMC_IO_22
23
AD55
24
AD54
23
PMC_IO_23
24
PMC_IO_24
25
AD53
26
GND
25
PMC_IO_25
26
PMC_IO_26
27
GND
28
AD52
27
PMC_IO_27
28
PMC_IO_28
29
AD51
30
AD50
29
PMC_IO_29
30
PMC_IO_30
31
AD49
32
GND
31
PMC_IO_31
32
PMC_IO_32
33
GND
34
AD48
33
PMC_IO_33
34
PMC_IO_34
35
AD47
36
AD46
35
PMC_IO_35
36
PMC_IO_36
37
AD45
38
GND
37
PMC_IO_37
38
PMC_IO_38
39
VIO
40
AD44
39
PMC_IO_39
40
PMC_IO_40
41
AD43
42
AD42
41
PMC_IO_41
42
PMC_IO_42
43
AD41
44
GND
43
PMC_IO_43
44
PMC_IO_44
45
GND
46
AD40
45
PMC_IO_45
46
PMC_IO_46
47
AD39
48
AD38
47
PMC_IO_47
48
PMC_IO_48
49
AD37
50
GND
49
PMC_IO_49
50
PMC_IO_50
51
GND
52
AD36
51
PMC_IO_51
52
PMC_IO_52
53
AD35
54
AD34
53
PMC_IO_53
54
PMC_IO_54
55
AD33
56
GND
55
PMC_IO_55
56
PMC_IO_56
57
VIO
58
AD32
57
PMC_IO_57
58
PMC_IO_58
59
N/C
60
N/C
59
PMC_IO_59
60
PMC_IO_60
61
N/C
62
GND
61
PMC_IO_61
62
PMC_IO_62
63
GND
64
N/C
63
PMC_IO_63
64
PMC_IO_64
6.2.3 Signal Descriptions

Table 6-13 PMC Signal Descriptions
Mnemonic
Description
AD[63:0]
Address/Data bits. Multiplexed address and data bus
CBE[7:0]~
Command/Byte Enables. During the address phase, these signals specify the type of cycle to carry out on the PCI bus. During the
data phase the signals are byte enables that specify the active bytes on the bus
FRAME~
FRAME. Driven low by the current master to signal the start and duration of an access
DEVSEL~
Device Select. Driven low by a PCI agent to signal that it has decoded its address as the target of the current access
PAR
Parity. Parity protection bit for AD31 to AD0 and BE3 to BE0
PAR64
Parity. Parity protection bit for AD63 to AD32
IRDY~
Initiator Ready. Driven low by the initiator to signal its ability to complete the current data phase
LOCK~
LOCK. Driven low to indicate an atomic operation that may require multiple transactions to complete
BUSMODE1~
Bus Mode 1. Driven low by a PMC if it supports the current bus mode. Used to detect the presence of a PMC on the site
BUSMODE[4:2]
Bus mode. Driven by the host to indicate the bus mode. On the SBC312 this is always PCI. BUSMODE2 is pulled-up. BUSMODE3 and
BUSMODE4 are pulled down to GND
RESET_IN
Reset. Driven low to reset the PCI bus
TRDY~
Target Ready. Driven low by the current target to signal its ability to complete the current data phase
PERR~
Parity Error. Driven low by a PCI agent to signal a parity error
SERR~
System Error. Driven low by a PCI agent to signal a system error
STOP~
STOP. Driven low by a PCI target to signal a disconnect or target-abort
INT[A:D]~
Interrupt lines. Level-sensitive, active-low interrupt requests
CLK
Clock. All PCI bus signals except RST~ are synchronous to this clock
REQ_A/B~
Request. Driven low by a PCI agent to request ownership of the PCI bus
GNT_A/B~
Grant. Driven low by the arbiter to grant PCI bus ownership to a PCI agent
IDSELA/B
Initialization Device Select. Device chip select during configuration cycles
REQ64~
Request 64 Bit. Driven low by PCI master to request 64 bit transfer
ACK64~
Acknowledge 64 Bit. Driven low by PCI agent in response to REQ64
EREADY
The PMC uses this signal to indicate when it is ready to be enumerated by the PCI software. Reflected in the Reset Cause Register
(register offset 0x0010)
RESET_OUT~
Reset output. This signal can be driven by a Monarch PMC to reset the SBC312
MONARCH~
Monarch mode is not supported on the SBC312. This signal is pulled high
TCK
Test Clock. Clock for the PMC JTAG
TMS
Test Mode Select. Select Test Mode for PMC JTAG
TRST~
Test Reset. Reset any PMC JTAG devices
TDI
Test Data In. Input data for PMC JTAG chain
TDO
Test Data Out. Data from a PMC JTAG chain
P5V
+5 V DC power
P3V3
+3.3 V supply pins
VIO
PCI V(I/O) pins
N/C
No connection
XCAP
PCI-X Capability detect. Used to determine whether a PMC is PCI-X capable
N12V_AUX
-12 V DC auxiliary supply pins
P12V_AUX
+12 V DC auxiliary supply pins
GND
Signal Ground
M66EN
Used to determine whether a PMC is 66 MHz PCI capable
Connectors 89
6.3 XMC Connectors

6.3.1 J15
J15suppliesthePCIExpressinterfacesignalsfortheXMC.
Pin
PCIE_TX0P
PCIE_TX0N
GND
GND
P3V3
PCIE_TX1P
PCIE_TX1N
VPWR
JTAG_TRST~
GND
GND
RESET_IN~
PCIE_TX2P
PCIE_TX2N
P3V3
PCIE_TX3P
PCIE_TX3N
VPWR
GND
GND
JTAG_TCK
GND
GND
RESET_OUT~
PCIE_TX4P
PCIE_TX4N
P3V3
PCIE_TX5P
PCIE_TX5N
VPWR
GND
GND
JTAG_TMS
GND
GND
P12V_AUX
PCIE_TX6P
PCIE_TX6N
P3V3
PCIE_TX7P
PCIE_TX7N
VPWR
GND
GND
JTAG_TDI
GND
GND
N12V_AUX
N/C
N/C
N/C
N/C
N/C
VPWR
10
GND
GND
JTAG_TDO
GND
GND
GA0
11
PCIE_RX0P
PCIE_RX0N
MBIST~
PCIE_RX1P
PCIE_RX1N
VPWR
12
GND
GND
GA1
GND
GND
PRESENT~
13
PCIE_RX2P
PCIE_RX2N
P3V3_AUX
PCIE_RX3P
PCIE_RX3N
VPWR
14
GND
GND
GA2
GND
GND
I2C_DATA
15
PCIE_RX4P
PCIE_RX4N
N/C
PCIE_RX5P
PCIE_RX5N
VPWR
16
GND
GND
NVMRO
GND
GND
I2C CLK
17
PCIE_RX6P
PCIE_RX6N
N/C
PCIE_RX7P
PCIE_RX7N
N/C
18
GND
GND
N/C
GND
GND
N/C
19
REFCLK_P
REFCLK_N
N/C
WAKE~
ROOT~
N/C
6.3.2 J16
J16providestherearI/OconnectivityfortheXMC.
Pin
XMC_IO_A01
XMC_IO_B01
N/C
XMC_IO_D01
XMC_IO_E01
N/C
GND
GND
N/C
GND
GND
N/C
XMC_IO_A03
XMC_IO_B03
N/C
XMC_IO_D03
XMC_IO_E03
N/C
GND
GND
N/C
GND
GND
N/C
XMC_IO_A05
XMC_IO_B05
N/C
XMC_IO_D05
XMC_IO_E05
N/C
GND
GND
N/C
GND
GND
N/C
XMC_IO_A07
XMC_IO_B07
N/C
XMC_IO_D07
XMC_IO_E07
N/C
GND
GND
XMC_IO_C08
GND
GND
XMC_IO_F08
XMC_IO_A09
XMC_IO_B09
XMC_IO_C09
XMC_IO_D09
XMC_IO_E09
XMC_IO_F09
10
GND
GND
XMC_IO_C10
GND
GND
XMC_IO_F10
11
XMC_IO_A11
XMC_IO_B11
XMC_IO_C11
XMC_IO_D11
XMC_IO_E11
XMC_IO_F11
12
GND
GND
XMC_IO_C12
GND
GND
XMC_IO_F12
13
XMC_IO_A13
XMC_IO_B13
XMC_IO_C13
XMC_IO_D13
XMC_IO_E13
XMC_IO_F13
14
GND
GND
XMC_IO_C14
GND
GND
XMC_IO_F14
15
XMC_IO_A15
XMC_IO_B15
XMC_IO_C15
XMC_IO_D15
XMC_IO_E15
XMC_IO_F15
16
GND
GND
XMC_IO_C16
GND
GND
XMC_IO_F16
17
XMC_IO_A17
XMC_IO_B17
XMC_IO_C17
XMC_IO_D17
XMC_IO_E17
XMC_IO_F17
18
GND
GND
XMC_IO_C18
GND
GND
XMC_IO_F18
19
XMC_IO_A19
XMC_IO_B19
XMC_IO_C19
XMC_IO_D19
XMC_IO_E19
XMC_IO_F19
Connectors 91
6.3.3 Signal Descriptions

Table 6-16 XMC Signal Descriptions
Mnemonic
Description
PCIE_TX[7:0]P/N
PCI Express Transmit Differential Pairs (from XMC to switch)
PCIE_RX[7:0]P/N
PCI Express Receive Differential Pairs (from switch to XMC)
REFCLK_P/N
PCI Express Reference Clock. 100 MHz Differential clock to XMC
PRESENT~
XMC Present. Pulled low by the XMC to allow the SBC312 to detect if an XMC is fitted
RESET_IN~
XMC Reset In. Reset driven from the SBC312 to the XMC
RESET_OUT~
XMC Reset Out. Reset signal driven by the XMC to the SBC312 (from a front-panel switch for example)
I2C_DATA
Data line for a two-wire I2C system management bus
I2C_CLK
Clock line for a two-wire I2C system management bus
MBIST~
XMC Built-in Self-Test. This signal can be held low by the XMC to indicate that it is not yet ready to be enumerated by the root
complex. The state is reflected in the Reset Cause Register (register offset 0x0010)
GA[2:0]~
Geographic Address. Used to identify the address of the XMC on a shared I2C bus (GA = 000b for the XMC site)
NVMRO
Non-Volatile Memory Read Only. Used to write protect any non-volatile memory on the XMC. This signal is driven from the VPX
backplane NVMRO signal
JTAG_TCK
JTAG Test Clock. Clock for the XMC JTAG
JTAG_TMS
JTAG Test Mode Select. Select Test Mode for XMC JTAG
JTAG_TRST~
JTAG Test Reset. Reset any XMC JTAG devices
JTAG_TDI
JTAG Test Data In. Input data for XMC JTAG chain
JTAG_TDO
JTAG Test Data Out. Data from an XMC JTAG chain
XMC_IO_*
Rear I/O Connection from XMC site
P12V_AUX
+12 V auxiliary supply pins
N12V_AUX
-12 V auxiliary supply pins
P3V3
+3.3 V supply pins
P3V3_AUX
+3.3 V auxiliary supply pins
VPWR
+5 V supply pins
GND
Signal Ground
N/C
No connection
6.4 JTAG Pass Thru Header (P7)

AfootprintisprovidedinthePMCkeepoutareatoallowfittingofa2x40.1
surfacemountheader(SamtecTSM10401SDVTRPLForsimilar)toprovide
accesstotheJTAGPassThrusignals.
Thisconnectorisnotnormallyfittedandisintendedforfactoryuseonly.
6.5 Aurora Debug Header (J3)

Thisusesanindustrystandardpinout,definedbyPower.orginthedocument
StandardforPhysicalConnectionforHighSpeedSerialTraceandtheP4080
HardwareSpecification.
TheconnectorisaSamtecASP13796901andisamodifiedversionoftheirERF8
seriesforthisapplication.
Pin
Signal
Pin
Signal
Latch
GND
Latch
GND
TX0P
BDM_VSENSE
TX0N
CPU_TCK
GND
CPU_TMS
TX1P
CPU_TDI
TX1N
10
CPU_TDO
11
GND
12
CPU_TRST~
13
RX0P
14
HALT
15
RX0N
16
EVENT_IN
17
GND
18
EVENT_OUT
19
RX1P
20
N/C
21
RX1N
22
BDM_HRESET~
Latch
GND
Latch
GND
Table 6-18 J3 Signal Descriptions

Signal
Description
TX*P
Transmit data positive
TX*N
Transmit data negative
RX*P
Receive data positive
RX*N
Receive data negative
CPU_TCK
JTAG Test Clock
CPU_TMS
JTAG Test Mode Select
CPU_TDI
JTAG Test Data In
CPU_TDO
JTAG Test Data Out
CPU_TRST
JTAG Test Reset
HALT
Connected to P4080 EVT[4] pin
EVENT_IN
EVENT_OUT
BDM_HRESET~
Hard reset
BDM_VSENSE
Voltage sense
GND
Signal Ground
Connectors 93
6.6 Test Access Card Connector (P4)

Pin
Signal
Pin
Signal
79
VCC
80
VCC
77
BOOT_ALTERNATE~
78
SPARE_0
75
CONFIG_WE_LINK~
76
SPARE_1
73
BOOT_RECOVERY~
74
SPARE_2
71
FLASH_PW_UNLOCK~
72
CLK_I2C_BUS_DATA
69
No connection
70
CLK_I2C_BUS_CLK
67
SPARE0~
68
No connection
65
No connection
66
No connection
63
BOOTSEQ_DIS_LINK~
64
No connection
61
No connection
62
No connection
59
MRAM_WE_LINK~
60
P4080_SPI_MISO
57
GND
58
GND
55
No connection
56
P4080_SPI_MOSI
53
JTAG_BP_JTAG_TCK
54
P4080_SPI_CS1~
51
JTAG_BP_JTAG_TDO
52
P4080_SPI_CLK
49
JTAG_BP_JTAG_TRST~
50
I2C_BUS1_CLK
47
JTAG_BP_JTAG_TMS
48
I2C_BUS1_DATA
45
JTAG_BP_JTAG_TDI
46
I2C_BUS2_CLK
43
HARD_RESET~
44
I2C_BUS2_DATA
41
+3.3V_BP
42
+3.3V_BP
39
POWER_GOOD~
40
No connection
37
BANC_WE_LINK~
38
SHUT_DOWN~
35
SPI_BOOT_LINK~
36
PROG_MODE_LINK~
33
JTAG_SB1_PASS_THRU_EN~
34
No connection
31
GND
32
GND
29
No connection
30
JTAG_PSU_MGR_TCK
27
JTAG_SB1_PASS_THRU2
28
JTAG_PSU_MGR_TMS
25
JTAG_SB1_PASS_THRU1
26
JTAG_PSU_MGR_TDO
23
JTAG_SB1_PASS_THRU0
24
JTAG_PSU_MGR_TDI
21
+3.3V
22
+3.3V
19
RESET_EXT~
20
JTAG_FPGA_TCK
17
No connection
18
JTAG_FPGA_TMS
15
No connection
16
JTAG_FPGA_TDO
13
No connection
14
JTAG_FPGA_TDI
11
No connection
12
No connection
No connection
10
SCANBR_EN_LINK~
No connection
No connection
No connection
No connection
No connection
No connection
GND
GND
A Specifications
A.1 Mechanical Specification
Table A-1 Mechanical Construction
Form Factor
Weight
Dimensions
The SBC312 occupies a single 3U VPX slot

SBC312 Level 4-5 = TBA
SBC312 Level 1-3 = TBA
The air-cooled SBC312 is constructed on a multi-layer 3U Eurocard and conforms to the dimensions specified in IEEE1101.1.
The conduction-cooled SBC312 is constructed on a multi-layer 3U Eurocard and conforms to the dimensions specified in IEEE
1101.2.
A.2 Technical Specification

Table A-2 Technical Data
Features
Processor
RAM
Details
Freescale P4080
Up to 8 GBytes DDR3 SDRAM with ECC
ROM
Up to 512 MBytes Flash memory
NOVRAM
Solid State Drive
Infrastructure
Ethernet ports
USB2.0
SATA
Discrete Digital I/O
PCI Express
PMC/XMC sites
512 KBytes
TBA
PCI Express
2 x 10/100/1000BaseT
Up to 4 x RS232 debug
2 x RS232/422/485 Sync/Async
2 backplane ports
2 backplane channels
Up to 8-bits, TTL-compatible
8 lanes on VPX P1
One PMC/XMC site
DMA controllers
10
Timers
8 x 31-bit timers
Watchdog timer
Two 32-bit timers
Real-Time Clock
Time Of Day/Calendar
ETI
Quarter second resolution
JTAG Interface
On-card connector
Serial ports
Comments
Contains eight e500mc PowerPC processing cores @ up to 1.5 GHz
Dual memory controllers running at up to 650 MHz
8 MBytes allocated to Boot Flash and the rest to User Flash. Advanced sector
protection features
Non-volatile storage for data that must not be lost when power is removed
High bandwidth serial-interconnect. Non-blocking switch architecture
P4080 provides COM1 & COM2 debug ports. Optional 2-wire COM3/COM4
Able to generate edge- or level-triggered interrupts

2.5 or 5 GHz. Configurable in up to 5 ports with 2 non-transparent ports
64-bit PCI-X interface at up to 133 MHz. x8 PCI Express interface
Eight engines available in the P4080 for efficiently moving large blocks of data.
Two further engines available in the PCI Express switch
Provided by the P4080. Programmable frequency with up to 15 ns resolution. Ability
to cascade to form larger timers
Programmable interrupt and reset thresholds
1 second resolution. Standby power may be connected from the VBAT pin to
maintain data during power down
Logs the total accumulated time the board has been powered, and the number of
power cycles
JTAG header provided for factory test and software debug purposes
Specifications 95
A.3 Environmental Specifications

A.3.1 Convection-cooled Boards
Table A-3 Convection-cooled Environmental Specifications
Build Style
Standard
(Level 1)
Temperature (C)
Operating: 0 to +55
with airflow of 300
feet/minute.
Storage: -50 to +100
Extended
Temperature
(Level 2)
Operating: -20 to +65

with airflow of 300
feet/minute
Rugged Aircooled
(Level 3)
Operating: -40 to +75

with airflow of 600
feet/minute
Vibration
Random:
0.002g2/Hz from 10
to 2000 Hz
Sine: 2g from 5
to 500 Hz
Random:
0.002g2/Hz from 10
to 2000 Hz
Sine: 2g from 5
to 500 Hz
Random:
0.04g2/Hz from 20
to 2000 Hz, with a
flat response to
1000 Hz. 6db/Octave
roll-off from 1000 to
2000 Hz.
Shock
20g peak
sawtooth,
11 ms
duration
Humidity
Up to 95% RH
Comments
Commercial grade cooled by forced air, for
use in benign environments and software
development applications. Optional conformal
coating
20g peak
sawtooth,
11 ms
duration
Up to 95% RH with
varying
temperature.
10 cycles,
240 hours
As Standard but conformally coated and

temperature characterized
20g peak
sawtooth,
11 ms
duration
Up to 95% RH with
varying
temperature.
10 cycles,
240 hours
Wide temperature rugged, cooled by forced

air. Conformally coated for additional
protection
A.3.2 Conduction-cooled Boards

Table A-4 Conduction-cooled Environmental Specifications
Build Style
Rugged
Conductioncooled (Level 4)
Temperature (C)
Operating: -40 to
+75 at the thermal
interface
Storage: -50 to
+100
Rugged
Conductioncooled (Level 5)
Operating: -40 to
+85 at the thermal
interface
Storage: -50 to
+100
Vibration
Random: 0.1g2/Hz
from 15 to 2000 Hz
per MIL-STD-810E
Fig 514.4 8 for high
performance aircraft.
12g RMS
Random: 0.1g2/Hz
from 15 to 2000 Hz
per MIL-STD-810E
Fig 514.4 8 for high
performance aircraft.
12g RMS
Shock
40g peak
sawtooth, 11
ms duration
Humidity
Up to 95% RH with
varying
temperature.
10 cycles,
240 hours
Comments
Designed for severe environment applications
with high levels of shock and vibration, small
space envelope and restricted cooling supplies.
Conformally-coated as standard. Optional ESS.
40g peak
sawtooth, 11
ms duration
Up to 95% RH with
varying
temperature.
10 cycles,
240 hours
Designed for severe environment applications

with high levels of shock and vibration, small
space envelope and restricted cooling supplies.
Conformally-coated as standard. Optional ESS.
A.4 Electrical Specification

A.4.1 Voltage Supply Requirements
TheVPXVs2(+3.3V),Vs3(+5V)and+3.3VAuxiliarysuppliesarerequiredand
mustremainwithinthespecifiedlimitsasdefinedbelow.Ifanyofthesesuppliesis
outsideofthesespecificationsatpowerup,thentheSBC312willfailtostart.If
duringapoweredstatethesesuppliesfalloutsideoftheselimitsthentheSBC312
willbeheldinresetandallonboardsupplieswillbeshutdown.
TheVPX12VAuxiliarysuppliesarenotusedontheSBC312butareconnectedto
thePMC/XMCsite.
TheVBATbackplanesignalmayoptionallybeusedtopowertheRealTimeClock
whenothersuppliesareremoved.
Table A-5 Voltage Supply Requirements
Supply
VS1
VS2
VS3
P3V3_AUX
P12V_AUX
N12V_AUX
VBAT
Minimum
+3.14 V
+4.88 V
+3.14 V
+11.4 V
-11.4 V
1.8 V
Nominal
Not used
+3.3 V
+5.0 V
+3.3 V
+12.0 V
-12.0 V
3.3 V
Maximum
+3.46 V
+5.25 V
+3.46 V
+12.6 V
-12.6 V
5.5 V
WARNING
Do not exceed the maximum rated input voltages or apply reversed bias to the assembly. If such
conditions occur, toxic fumes may be produced due to the destruction of components.
A.4.2 Current Consumption

CurrentconsumptionfiguresforSBC312areshownbelow.Thesearegivenatcold
walltemperaturesof+25Cand+85Cinaconductioncooledenvironment
Allfiguresweremeasuredonaboardwith2GBytesofDDR3SDRAMand
512MBytesofFlash.AllGigabitEthernetlinkswereactivebutidle.
Table A-6 Current Consumption
Temperature (C)
+25
+85
Operation
Current (A)
P4080 @ 1.2 GHz
P4080 @ 1.5 GHz
Typical
TBD
TBD
Maximum
TBD
TBD
Typical
TBD
TBD
Maximum
TBD
TBD
NOTE
Ensure that any PMC used does not cause the specified maximum supply current to be exceeded. It
may not be possible to support all PMCs within this limit.
Specifications 97
A.5 Reliability (MTBF)

TableA7showsthepredictedvaluesforreliabilityasMeanTimeBetweenFailures
(MTBF)andfailurespermillionhours(fpmh)fortheSBC312xxxxxxxx(seethe
ProductCodessectionforvariantdetails).
Table A-7 Reliability (MTBF)
Environment
Fail Rate
(Failures Per Million Hours)
Ground benign 30c
2.3194
431 146
Ground fixed 40c
12.0074
83 282
Ground mobile 45c
28.9396
34 555
Naval sheltered 40c
15.9100
62 854
MTBF (Hours)
Naval unsheltered 45c
38.2867
26 119
Airborne inhabited cargo 55c
30.3275
32 973
Airborne inhabited fighter 55c
43.1994
23 148
Airborne uninhabited cargo 70c
78.0740
12 808
Airborne uninhabited fighter 70c
107.3936
9312
Airborne rotary wing 55c
83.5022
11 976
Space flight 30c
1.7175
582 230
Missile flight 45c
37.56704
26 619
Missile launch 55c
112.54
8886
ThepredictionsarecarriedoutusingMILHDBK217FNotice2,partscountmethod.
Tocomplementthe217failurerates,somemanufacturersdataisincludedwhere
appropriate;QvalueshavebeenmodifiedaccordingtoANSI/VITA51.1.
Thesefailureratesarebasedonlyonthecomponentsandconnectorsfittedtothe
boardatdeliveryandtakenoaccountofuserfittedmezzanines.
A.6 Product Codes

Table A-8 Product Options
-
1 = 0.8" pitch, VITA 46

2 = 0.85" pitch, VITA 46
3 = 1" pitch, VITA 46
A = 0.8" pitch, VITA 48 (2LM)
B = 0.85" pitch, VITA 48 (2LM)
C = 1" pitch, VITA 48 (2LM)
3 = VxWorks
4 = BIT/VxWorks
5 = U-Boot
6 = BIT/U-Boot
0 = OpenVPX, 2xPCIe
1 = OpenVPX, PCIe + 10Gig
2 = SBC310 compatible, 2xPCIe
3 = SBC310 compatible, PCIe + 10Gig
0 = Not fitted
1 = 8 GBytes
2 = 16 GBytes
3 = 32 GBytes
1 = 256 Mbytes
2 = 512 MBytes
3 = 2 GBytes
4 = 4 GBytes
1 = P4080 @ 1.2 GHz
2 = P4080 @ 1.5 GHz
1 = Build level 1
2 = Build level 2
3 = Build level 3
4 = Build level 4
5 = Build level 5
NAND Flash
NOR Flash
SDRAM
Processor and Frequency
Ruggedization Level
I/O Options
Software
Mechanics
SBC312
ThedefaultproductcodeisSBC31211310011.
Specifications 99
A.7 Software Support

GEIPssoftwarestrategyallowsfullyintegratedsystemlevelsolutionstoberealized
easilyandwithconfidence.Offtheshelf,layeredsoftwaremodulesdeliverthemost
fromlowlevelhardwarefeatureswhileexploitingthebesthighleveldebugand
runtimefunctionalityofpopularCOTSoperatingsystemsandcommunications
modules.
Thesoftwareproductsdescribedbelowbuildonthoseavailableforprevious
generationsofproducts,soprovidingacommoninterfacefortechnologyinserts.
TheGEIPsoftwarestrategyensuresthatcustomerscandevelopmarketleading
productsusingtheO/Sanddevelopmentenvironmentbestsuitedtotheirlongterm
programrequirements.
A.7.1 Boot Firmware

TheBootfirmwareprovidesafoundationlayertointerfacebetweentherawboard
hardware,withitshighlyprogrammabledevicesetupsandflexibility,andthe
supportedOperatingSystems,whichrequireastraightforwardbootinganddevice
interfacemodel.
TheUBootFirmwareincludescomprehensiveconfigurationfacilities,interactiveor
autobootsequencingfromarangeofdevicetypes,automaticPCIresource
allocationatinitialization,PCIdisplay/interrogationutilitiesandothervaluable
featuresforsystemintegrators.
Memoryorotherspeedandfeatureenhancementsareseamlesslyabsorbedbythe
Bootfirmware,givingthesamelookandfeeltotheO/Sandtheuserapplicationas
theGEIPhardwaremodelsadvance.Thisallowstheconstantuseoflatest
technologyinrequiredareaswithoutsystemimpact.Whereparticularoperating
systemsdefinetheuseofalternatebootmethods(e.g.VxWorksbootroms),theBoot
firmwaretechnologyisabsorbedintosuchbootmethodology.
A.7.2 Built In Test

BITprobesfromthelowestlevelofdiscreteonboardhardwareuptoLine
ReplaceableUnitlevelwithinasystem,ensuringthehighestdegreeofconfidencein
systemintegrity.BITincludescomprehensiveconfigurationfacilities,allowing
automaticinitializationteststobedefinedforthedesiredmixofsystemfunctionality
andoptions.Furthertestscanbeinvokedinteractively,givingBITavaluableroleas
afieldservicetool.Bothobjectandsourcecodeproductsareavailable.
A.7.3 Background Condition Screening

BCSsupplementstheBITinitializationtestcoveragewithfurtherhealthscreening
thatcancoexistwithastandardCOTSOperatingSystem.
IncontrasttoatraditionalBITstyletest,theintensityandcoverageofwhichmakes
itdestructivetooperatingsystems,theconfigurableBCSpackageallowsfunctions
suchasperiodicchecksumming,memoryscrubbing,andotherstobetailoredfor
operationalongsidetheapplicationinonlineconditions.ResultsarestoredinFlash
inthesameformatasBITresults.CodeisavailableforreadingoutBIT/BCSresults
underLynxOSandVxWorks.
A.8 I/O Modules

TheRearTransitionModule(RTM)fortheSBC312istheVPX3UX600rev3orlater.
MoreinformationaboutRTMscanbefoundintheVPXI/OModulesmanual.
LINK
Specifications 101
Glossary
NOTE
The connector signals are explained in Section 6.
LINK
This glossary only features terms special to this manual. Explanations of more general terms can be
found in the Glossary, publication number GLOS1.
BMM BoardManagementMicrocontroller.
GEIP GEIntelligentPlatforms.
MRAM MagnetoresistiveRandomAccessMemory.
NVMRO NonVolatileMemoryReadOnly.
RCW ResetConfigurationWord.
Index
A
Airflow ..........................................................................16
AUX_CLK .....................................................................38
AXISSupport................................................................55
B
BCS...............................................................................101
BIT................................................................................100
LEDs..........................................................................76
BlockDiagram..............................................................27
BMM ..............................................................................53
BoardIdentification .....................................................18
BoardInstallation.........................................................25
BootFirmware............................................................100
BootFlash......................................................................34
C
Cautions ........................................................................15
ChassisGround............................................................25
Configuration
Board.........................................................................23
Links .........................................................................19
BootAreaSelection ............................................20
Descriptions.........................................................20
FlashProtectionUnlock.....................................21
PMCVIOSelection.............................................20
Positions...............................................................19
ScanbridgeOutputEnable ................................21
StatusRegister.....................................................64
P4080Cores4to7Disable .....................................22
P4080UART.............................................................22
Software....................................................................22
ConnectingtoSBC312 .................................................26
Connectors ....................................................................79
AuroraDebug..........................................................93
Backplane .................................................................81
J0 ...........................................................................81
J1 ...........................................................................82
J2 ...........................................................................84
P0 ..........................................................................81
P1 ..........................................................................82
P2 ..........................................................................83
J11 ..............................................................................87
J12 ..............................................................................87
J13 ..............................................................................88
Connectors(continued)
J14..............................................................................88
J15..............................................................................90
J16..............................................................................91
J3................................................................................93
P7...............................................................................92
PMC ..........................................................................87
Positions .............................................................79,80
SignalDescriptions
Backplane ............................................................85
PMC......................................................................89
XMC .....................................................................92
XMC..........................................................................90
Cooling ....................................................................16,96
CurrentConsumption .................................................97
D
Dimensions ...................................................................95
DIPSwitch ....................................................................51
DocumentationConventions .......................................3
E
ElectricalSpecification ................................................97
EMI/EMC ......................................................................25
RegulatoryCompliance .........................................15
EnvironmentalSpecifications ....................................96
EquipmentNumber.....................................................18
Ethernet .........................................................................41
LinkStatusLEDs.....................................................77
ETI..................................................................................51
F
Features .........................................................................28
Flammability ................................................................15
Flash...............................................................................33
Boot ...........................................................................34
NOR ..........................................................................33
Paging.......................................................................34
ProtectionUnlockLink ..........................................21
SectorProtection .....................................................35
SPISerial ..................................................................36
User...........................................................................34
FPGA .............................................................................59
FrontPanel....................................................................78
SeeAlso ..................................................ChassisGround
FunctionalDescription................................................27
Index 103
GlobalDiscrete .............................................................39
GPIO ..............................................................................42
Handling .......................................................................16
Heatsink ........................................................................16
HostProcessor..............................................................29
Cores4to7Disable.................................................22
PCIExpressConnection.........................................47
PowerManagement................................................31
Humidity.......................................................................96
MaskableReset.............................................................38
MechanicalSpecification ............................................95
Memory
Flash..........................................................................33
Maps .........................................................................30
MRAM......................................................................36
P4080ConfigEEPROM ..........................................50
RAM..........................................................................32
MRAM...........................................................................36
WriteEnable ............................................................21
MTBF .............................................................................98
I/OCapabilities.............................................................39
I/OModules................................................................101
I2CBuses........................................................................49
Reset..........................................................................50
IdentifyingProduct .....................................................18
Inspection......................................................................20
Interrupts ......................................................................57
External.....................................................................58
StatusRegister .........................................................68
Introduction..................................................................14
OpenVPXCompatibility.............................................37
OperatingEnvironment..............................................96
Options..........................................................................99
J
JTAG ..............................................................................73
ScanbridgeOutputEnable.....................................21
Jumpers ................................ SeeConfiguration(Links)
K
Keying ...........................................................................25
L
Label ..............................................................................18
LEDs ..............................................................................75
BIT .............................................................................76
EthernetLinkStatus ...............................................77
PCIExpressLinkStatus .........................................77
PowerGood .............................................................75
ResetStatus ..............................................................76
SATAActivity .........................................................76
Links .................................................. SeeConfiguration
LocalBus .......................................................................31
P
PCIExpress
HostProcessorConnection....................................47
I/O .............................................................................37
Infrastructure...........................................................47
Switch .......................................................................48
Photograph ...................................................................14
PMC ...............................................................................44
Connectors ...............................................................87
Installation ...............................................................23
Routing.....................................................................45
SignalDescriptions .................................................89
Site.............................................................................44
PowerManager............................................................52
PowerSequencing .......................................................56
PowerSupplyRequirements......................................25
Problems .........................................................................6
ProductCodes ........................................................18,99
ProductIdentification .................................................18
Profile ............................................................................95
RAM...............................................................................32
REF_CLK.......................................................................38
Registers
Address ....................................................................61
AUXCLKCounter...................................................71
AXISSemaphore .....................................................71
BoardConfiguration...............................................62
BoardConfigurationRegister1.............................62
BoardID ...................................................................61
BoardInterruptStatus............................................68
BoardSemaphore....................................................67
Control1...................................................................64
Control3...................................................................65
ControlandStatus ..................................................60
CounterControl ......................................................70
FIFOData .................................................................71
FIFOStatus...............................................................72
LinkStatus ...............................................................64
P4080InterruptINT0Mask ...................................69
PowerOnConfiguration .......................................61
RAM/FlashConfiguration .....................................63
REFCLKControl .....................................................70
REFCLKCounter ....................................................70
ResetCause ..............................................................63
Revision ....................................................................61
Scratchpad................................................................66
SerialControl...........................................................65
TestPattern ..............................................................66
WatchdogControl...................................................67
WatchdogInterruptValue.....................................68
RelatedDocuments........................................................4
Reliability ......................................................................98
Resets .............................................................................57
CausesRegister .......................................................63
Maskable ..................................................................38
ResetConfigurationWord.....................................30
SequenceandTiming .............................................26
StatusLEDs..............................................................76
RevisionState ...............................................................18
RTC ................................................................................51
RTM .............................................................................101
SafetyNotices...............................................................15
SATA .............................................................................42
ActivityLEDs ..........................................................76
SerialPorts ....................................................................39
COM3&COM4.......................................................40
Configuration ..........................................................22
HosttoBMM ...........................................................41
Shock .............................................................................96
Size.................................................................................95
SoftwareSupport .......................................................100
Specifications................................................................95
Electrical...................................................................97
Environmental.........................................................96
Mechanical ...............................................................95
Technical ..................................................................95
SPISerialFlash .............................................................36
StorageEnvironment...................................................96
SystemROM.................................................................33
T
TechnicalHelpContactDetails....................................6
TechnicalSpecification................................................95
TemperatureSensors...................................................52
Timers............................................................................54
U
USB ................................................................................42
UserFlash .....................................................................34
V
Vibration .......................................................................96
VoltageSupplyRequirements ...................................97
VPXInterface................................................................37
W
Warnings.......................................................................15
WatchdogTimers.........................................................54
WebSites.........................................................................5
Weight ...........................................................................95
X
XMC...............................................................................44
Connectors ...............................................................90
Installation ...............................................................24
Routing.....................................................................45
SignalDescriptions .................................................92
Site.............................................................................44
Index 105
2010 GE Intelligent Platforms Embedded

Systems, Inc. All rights reserved.
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contains Confidential/Proprietary Information
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Hardware Reference Manual

Board Artwork Revision

Waste Electrical and Electronic Equipment (WEEE) Returns

2 SBC312 3U VPX Single Board Computer

Publication No. SBC312-HRM/1

About this Manual

Warnings alert you to the risk of severe personal injury.

Cautions alert you to system danger or loss of data.

Tips give guidance on procedures that may be tackled in a number of ways.

About this Manual 3

Third Party Documents

4 SBC312 3U VPX Single Board Computer

Publication No. SBC312-HRM/1

Registration may be required for access to these specifications.

Third Party Web Sites

Registration may be required for access to standards.

Publication No. SBC312-HRM/1

About this Manual 5

Technical Support Contact Information

FollowtheDownloadRMA Request Form (Word Doc)hyperlinkunderDSP,SBCs,

6 SBC312 3U VPX Single Board Computer

Publication No. SBC312-HRM/1

3.4 Software Board Configuration ..................................................................................................................................................... 22

3.5 Mezzanine Installation...................................................................................................................................................................... 23

4 Installation and Power Up/Reset.................................................................................................... 25

5 Functional Description (continued)

5.11 PCI Express Infrastructure ........................................................................................................................................................... 47

5.12 I2C Buses............................................................................................................................................................................................... 49

5.13 Timers .................................................................................................................................................................................................... 54

5.14 AXIS Support....................................................................................................................................................................................... 55

5.14.1 AXIS Timer........................................................................................................................................................................................................55

5.15 Power Sequencing........................................................................................................................................................................... 56

5.16 Resets and Interrupts..................................................................................................................................................................... 57

5.16.1 Hard Reset.......................................................................................................................................................................................................57

5.17 FPGA ....................................................................................................................................................................................................... 59

8 SBC312 3U VPX Single Board Computer

Publication No. SBC312-HRM/1

5 Functional Description (continued)

5.20 LEDs ........................................................................................................................................................................................................ 75

5.21 Front Panel .......................................................................................................................................................................................... 78

5.21.1 Air-cooled Versions (Build Levels 1 to 3)............................................................................................................................................78

Publication No. SBC312-HRM/1

6.2 PMC Connectors.................................................................................................................................................................................. 87

6.3 XMC Connectors.................................................................................................................................................................................. 90

6.4 JTAG Pass Thru Header (P7)........................................................................................................................................................... 92

A.8 I/O Modules .........................................................................................................................................................................................101

10 SBC312 3U VPX Single Board Computer

Publication No. SBC312-HRM/1

Table 5-38 Serial Control Register ........................................................................................................................................................... 65

Publication No. SBC312-HRM/1

Table A-7 Reliability (MTBF).......................................................................................................................................................................... 98

Publication No. SBC312-HRM/1

14 SBC312 3U VPX Single Board Computer

Publication No. SBC312-HRM/1

1.1 Safety Notices

1.1.2 EMI/EMC Regulatory Compliance

Publication No. SBC312-HRM/1

Only handle the SBC312 by the edges or front panel.

Figure 1-2 ESD Label (Present on Board Packaging)

16 SBC312 3U VPX Single Board Computer

Publication No. SBC312-HRM/1

2.1 Box Contents Checklist

Publication No. SBC312-HRM/1