Embedded Systems

I Objective / Relevance
Embedded systems are specialized computers used in larger systems or machines to control equipments
such as automobiles, home appliances, communication, control and office machines. Embedded system is
a combination of software and hardware system, in which s/w drives the hardware. The fact that such
systems are everywhere and in our everyday life. Such pervasively is particularly evident in immersive
realities, i.e., scenarios in which invisible embedded systems need to continuously interact with human
users, in order to provide continuous sensed information and to react to service requests from the users
themselves. Examples of such scenarios are digital libraries and eTourism, automotive, next generation
buildings and infrastructures, eealth, domestics. aving the users at the centre poses many new
challenges to the current middleware and service technologies for embedded systems, in terms of
!ynamicity, Scalability, !ependability, Security and privacy. These considerations require, in the
"onsortium opinion, novel techniques and middleware technologies targeted to person#centric embedded
systems $i.e., usable in immersive scenarios%. The main ob&ective' # $(% less power consumption $)%
memory constraint $*% less area requirement.
+fter going through this lesson the student would be able to
, -now what an embedded system is
, distinguish a .eal Time Embedded System from other systems
, tell the difference between real and non#real time
, /earn more about a mobile phone
, -now the architecture
, Tell the ma&or components of an Embedded system
II Syllabus
III Session Plan
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( 0verview
1ntroduction to the sub&ect in unit wise
as per 23T4 syllabus
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+pplications 5
its
extensio
n
+pplications of embedded systems /)
*
3ecessary
bac6gro
und
1nformation .egarding 7icrocontrollers /*
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UNIT ' ( Embedded )omputin"
8 1ntroduction 1ntroduction of Embedded Systems /8 T(#"h( $(%
9
"omplex
Systems
and
7icropr
ocessor
Embedded "omputing
/9 T(#"h($)#:%
"haracteristics
"hallenges
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;
Embedded
System
!esign
<rocess
.equirements
/; T(#"h($(=#(:%
Specifications
+rchitecture !esign
>
?ormalisms for
System
!esign
Structural description
/> T(#"h($)(#)@%
Aehavioral description
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!esign
Exampl
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/: T(#"h($*)#*@%
Specifications
UNIT * II ( +,-' .rc/itecture
@
1ntroduction Introduction /@ T)#"h*$;=%
(=
:=9(
+rchitecture /(= T)#"h*$;=#>)%
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7icroco
ntroller
ardwa
re
/(( <ins
((
Timers and
"ounter
s
T=,T( /() T)#"h*$:=#:8%
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()
1/0 <orts and
"ircuits
<=,<(,<),<* /(* T)#"h*$>*#>>%
(*
Serial !ata
"ommu
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S"03 /(8 T)#"h*$:9#@=%
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External
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/(9
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(9 1nterrupts <riorities T)#"h*$@(#@;%
UNIT * III ( +,-' Pro"rammin"
(;
+ssembly
/anguage
<rogramming
<rocess
/(; T)#"h8$((=#(((%
(> <rogramming <rogramming Tools and Techniques /(> T)#"h8$((;#()8%
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!ec
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Tools and
Techniques
(: <rogramming Syntax for programming :=9( /(: T)#"h8$()9#():%
(@ !ata Transfer !ata Transfer 1nstructions /(@ T)#"h9$(*(#(88%
)=
/ogical
1nstructions
/ogical 1nstructions /)= T)#"h;$(9(#(;(%
)( +rithmetic +rithmetic 1nstructions /)(
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0perations
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)8
1nterrupt
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UNIT * I0 ( PSo) arc/itecture and Pro"rammin"
)9 <So" as a
single chip
solution for
embedded
!ifferences between microcontroller and
<So"
/)9
T*#"h($(#9=%
+dvantages /);
S.
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system design
); Aloc6s in <So" +nalog ,!igital and controller bloc6s
/)>
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T*#"h($(#9=%
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through <So"
/*= T*#"h($(#9=%
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creator
):
1/0 <in
configurability
/*(
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UNIT * 0 ( .pplications
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/E!
<ro&ect overview ,bac6ground
information, pro&ect steps and
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*= "apsense
<ro&ect overview ,bac6ground
information, pro&ect steps and
conclusion
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<ro&ect overview ,bac6ground
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analog logic
information, pro&ect steps and
conclusion
**
serial
communication
<ro&ect overview ,bac6ground
information, pro&ect steps and
conclusion
/*;
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UNIT *0I Introduction to RTOS
*8 -ernel 0b&ects of -ernel /*> .;#"h; $(9>#(>)%
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Tas6 and Tas6 States
Tas6 and !ata
SBmaphores and Shared data /*: .;#"h; $(>*#(:>%
7ail Aoxes
7essage Cueues
/*@ .;#"h>$(@*#)=*%
*9 Timers Timer ?unctions
Events
/8= .;#"h> $)=8#)(8%
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<ipes
*; 1S.
7emory 7anagement
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UNIT *0I #asic desi"n usin" a RTOS
*> <rinciples <rinciples /8) .;#"h:$)*>%
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*:
Semaphores
and Cueues
Semaphores and Cueues /8* .;#"h:$);8#)>)%
*@
ard .eal#
Time
Scheduling
"onsiderations
ard .eal#Time Scheduling
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/88 .;#"h:$)>*#)>8%
8= Saving Saving 7emory and <ower /89 .;#"h:$)>8#)>:%
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7emory and
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8( +n example
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8)
ost and Target
7achines
ost and Target 7achines /8> .;#"h@$):(#):)%
8* /in6er//ocators
for Embedded
Software
/in6er//ocators for Embedded Software /8:
/8@
.;#"h@$):*#)@9%
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88
Detting
Embedded
Software into
the Target
System
Detting Embedded Software into the
Target System
/9=
/9(
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89 Testing on ost
7achine
Testing on ost 7achine /9) .;#"h(=$*=8#*)(%
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8;
4sing
/aboratory
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/9*
/98
.;#"h(=$*)>#*89%
8>
+n Example
System
+n Example System
/99
/9;
.;#"h(($*8@#8)(%
UNIT * 0III ( Introduction to advanced arc/itectures
S.
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8:
+.7 and
S+."
+.7 and S+."
/9>
/9:
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8@ <rocessor and
memory
organization
and 1nstruction
<rocessor and memory organization and
1nstruction level parallelism
/9@
/;=
T(#"h)$;)#@:%
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SubTopics
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ture
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level
parallelism
9= 3etwor6ed
embedded
systems
Aus protocols /;( T(#"h:$89:%
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9(
()" bus and
"+3 bus
()" bus and "+3 bus
/;)
/;*
T(#"h:$89@#8;;%
9)
1nternet#
Enabled
Systems
1nternet#Enabled Systems
/;8
/;9
T(#"h:$8:8#8:9%
9* !esign
Example#
!esign Example#Elevator "ontroller /;; T(#"h:$8:;#8@)%
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Su""ested #oo$s
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Elevator
"ontroller
I0 .SSI1N2ENT 3UESTIONS
Unit '
(. Ehat is an embedded computer systemF Dive an example.
). Ehat are the ma&or components of embedded system hardwareF
*. Explain the characteristics of embedded computing applications.
8. Ehat are the reasons for using microprocessor in digital systemsF
9. Explain the challenges in embedded computing system design.
;. Ariefly describe about requirements in the design process. Explain with an example.
>. Ehat is specificationF !istinguish between requirements and specification.
:. Erite Short notes on,
$a% +rchitecture design
$b% "omponents
$c% System integration
). Ehat are the levels of abstraction in an embedded system design processF
*. "ompare and contrast top#down and bottom#up design methodologies.
8. Explain with an example the structural description of the system components. +lso discuss the
types of relationship between the ob&ects and classes.
9. ow the behavioral description of a system is different from its structural description. Explain.
;. Explain with a suitable illustration. ow 47/ is used for system modelingF
Unit 4
(. !raw and explain the bloc6 diagram of :=9( microcontroller.
). ow is !<T. register is used in :=9( microcontrollerF Explain.
*. Explain the programming model of :=9( microcontroller.
8. !iscuss the significance of cloc6 and oscillator circuit in :=9( microcontroller. +lso discuss the
role of stac6 in storing memory addresses.
9. !raw the pin diagram of :=9( microcontroller. Explain in detail about the various registers and
memory used by it.
;. !istinguish between a counter and timers.
>. Ehat are the different modes of operation associated with a timer in :=9( microcontrollerF
Explain.
:. Explain the significance of each field in T70! and T"03 registers.
@. !iscuss in detail about the input/output pins, ports and circuits of :=9( microcontroller.
(=. !iscuss in detail about the serial data communication circuit in:=9( microcontroller.
((. !raw S"03 and <"03 special function registers and explain the functioning of each field.
(). !iscuss the four modes of serial data transmission.
(*. !raw the memory organization of :=9( microcontroller and explain in detail.
(8. !efine interrupt. Ehat are the ) ways of generating an interruptF ow to control an interruptF
(9. !iscuss about the different types of interrupts in :=9( microcontroller.
(;. Explain 1E and 1< special function registers.
Unit 5
(. Ehat is an assembly#level languageF Dive the reasons for writing computer instructions in
assembly language.
). /ist the four types of utility programs.
*. Erite about the assembly language programming process, programming tools and techniques.
8. Erite short notes on addressing modes of :=9(.
9. Explain briefly about the external addressing using 70GH and 70G" instructions. +lso discuss
code memory read#only data moves.
;. Explain the significance of <4S and <0< instructions in direct data addressing.
>. Signify the role played by exchange and swap instructions in moving data in ) directions.
:. Erite about arithmetic operations and explain with examples.
@. !iscuss the role of flags in performing arithmetic operations and what instructions affect the flags.
(=. "ompare and contrast byte#level and bit#level logical operations.
((. Explain all the Aoolean bit#level operations.
(). !iscuss rotate and swap operations.
(*. Erite a brief note on shift and rotate operations in :=9(.
(8. Explain different +/4 instructions in :=9( with an example.
(9. Explain Ait &umps, Ayte &umps and unconditional &umps.
(;. Erite short notes on calls and sub routines.
(>. Explain the types of &ump and call instructions of :=9( with examples.
(:. Erite a brief note on S27<, /27< and +27< instruction in :=9(.
(@. !iscuss about decimal arithmetic with example.
)=. Explain interrupt handling capacity of :=9(.
Unit 6
(. Ehat is <S0"F ow it is different from microcontrollerF
). Explain about the features provided by <S0" architecture.
*. Eith a neat diagram explain the architecture of <S0" microcontroller.
8. /ist out the various advantages and limitations of <S0" microcontroller.
9. Explain the need of low power consumption in microcontroller based system.
;. Eith neat diagram explain the analog bloc6 employed in the <S0" microcontroller.
>. Erite short notes on digital <S0" bloc6s.
:. !iscuss about the internal register organizations of "<4 bloc6 in <S0".
@. State and explain in brief about the 8 embedded design steps involved in hardware configuration
through <S0" creator.
(=. Explain in detail about the three types of pins available in <S0" architecture.
UNIT -
(. /ist the steps performed while starting a new pro&ect of blin6ing an /E!.
). Erite the steps of adding the following components.
a. "loc6 component
b. <E7 component
c. !igital pin component
). Explain the procedure for establishing connection between components and chips resources.
*. Explain how pins are assigned to <S0" creator.
8. !iscuss in brief about cap sense and its operation.
9. Erite the five steps involved in adding and configuring a cap sense I "S! component.
;. Erite the steps for setting of the pro&ect of digital logic.
>. Explain the procedure for adding and configuring a control register.
:. Explain how sheet connectors are used.
@. /ist the steps involved in a% adding a loo6 up table b% adding more registers c%adding hardware
delays.
UNIT 7
(. Ehat is a tas6F Ehat are the different states of a tas6F
). Ehat is a Shared !ata problem in embedded systemF Explain with an example.
*. Explain the characteristics of a JreentrantK function. Ehat are the rules that help you to decide
whether a function is reentrant or notF
8. Ehat is a semaphoreF Explain the wor6ing of semaphores in an .T0S with an example. +lso
discuss the process of initializing semaphores.
9. Ehat are the problems that are to be addressed using semaphoresF
;. "ompare and contrast the * methods of protecting shared data.
>. Ehat are 6inds of SemaphoresF
:. Erite short notes on the following in the context of an .T0S,
a. <riority inversion
b. !eadly embrace
c. 7utex
d. "ounting Semaphores.
). "ompare binary semaphores, mutex and counter semaphores.
*. Explain the features of the following methods of inter#tas6 communication,
a. Semaphores
b. Cueues
c. 7ailboxes
d. <ipes
8. "ompare semaphores, events and queues for implanting inter tas6 communication with an
example.
9. Explain the inter#tas6 communications through message queues, pipes and mailboxes.
;. Ehy do we need timer functions in .T0SF Ariefly discuss how they are provided.
>. Ehat are eventsF Explain the role of events in .T0S.
:. "ompare events with semaphores and queues.
@. ow memory management is done by an .T0SF Ehy is memory management not used in
embedded systemsF
(=. Ehat are the rules to be followed by the interrupt routines in .T0SF EhyF
Unit 8
(. Explain the basic design principles when using an .T0S and differentiate between operating
system and .T0S.
). Explain with an example the basic design of an embedded system using a real time operating
system.
*. Explain the need for encapsulating semaphores and queues with an example.
8. Explain the hard real time scheduling considerations.
9. !iscuss various methods adopted to reduce memory space in embedded applications.
;. Ehat are the techniques of energy and power management in an embedded systemF
>. !escribe the function relevant to L"#0S operating systems.
:. Explain the difference between a Jost computer systemK and a JTarget systemK in terms of their
hardware and software.
@. Explain in detail about cross#compilers and cross#assemblers.
(=. Erite about embedded software development tools and any one debugging technique.
((. Explain the following software development models,
a. "ross#compilers
b. "ross#assemblers.
c. /in6er//ocators
d. /oader.
). Erite short notes on,
a. +ddress resolution
b. 1nitialized data and constant strings.
c. /ocator maps
*. Explain different methods of getting software into the target system.
8. Explain in detail about the functioning of the following devices,
a. .07 Emulators
b. ?lash 7emory and
c. 7onitors
9. !iscuss about the goals for testing process.
;. Dive the basic technique for testing embedded software on the host system.
>. !iscuss the limitations of testing an embedded code on the host system.
Unit +
(. Explain about the processor and memory organization in +.7 processor.
). !iscuss all the data, comparison, move and load#store instructions supported by the +.7
processor.
*. Explain in details about the flow of control in +.7 processor.
8. Explain about the memory organization in S+." processor.
9. !iscuss the data operations performed in S+." processor.
;. Explain the flow of control in S+." processor is different from that of +.7 processor.
>. !iscuss the procedure calls in S+." processor.
:. Explain the instruction#level parallelism in S+." processor.
@. Erite a note on architectural features of +.7.
(=. Erite about +.7 architecture and compare with :=9( microcontroller architecture.
((. Erite a brief note on,
a. 7emory organization of +.7 processor
b. ?ixed point +/4 in S+.".
). Erite a brief notes on 1
)
" bus.
*. Erite a brief notes on "+3 bus architecture.
8. "ompare the data frame format of 1
)
" bus and "+3 bus.
9. !iscuss in detail about 1nternet I Enabled systems along with an example application.
;. Erite a brief note on,
a. !istributed embedded architecture
b. 1< <ac6et structure.
>. !iscuss the operation of an elevator controller.

0 Unit 9ise * 3uestion #an$
UNIT '
(. Explain in detail the embedded system design process. %Nov/:ec * 4,'5&
). Explain the various levels of abstraction in the design of D<S moving map with a neat s6etch.
$2ay/June * 4,'5&
*. a% Explain the characteristics of embedded computing applications.
b% Explain the important problems or challenges that must be considered while designing an
embedded system. $2ay/June * 4,'5&
8. a% Explain all the ma&or steps involved in the embedded system design process and
also explain about the requirements analysis of a D<S moving map.
b% Explain how 47/ is used to model systems, by ta6ing model train controller as
an example. $2ay/June * 4,'5&
9. !raw and explain an embedded system design flow. +lso discuss the design challenges to
optimize the design metrics in an embedded system design. %2ay;4,'4&
;. $a% 3ame and describe the four development models which most embedded pro&ects are based
upon.
$b% Explain in brief about Mve challenges commonly faced when designing an embedded system.
%2.< 4,''&
>. a% "lassify the embedded systems into small scale, medium scale and sophisticated systems.
b% /ist the software tools needed in designing an embedded system. !iscuss about any one of
them. %2.< * 4,',&
:. a% Explain the formalisms for embedded system design.
b% /ist the various complex systems available and explain their performance characteristics.
%2.< * 4,',&
@. a% 3ame and describe the four development models which most embedded pro&ects are based
upon.
b% Explain in brief about five challenges commonly faced when designing an embedded system.
%2.< * 4,',&
(=. a% Explain why is the architecture of an embedded system importantF
b% !raw the layered embedded system model and explain about each layer.
%2.<*4,',&
((. Explain in detail about Embedded system design process with examples. $2ay/June * 4,,=&
(). Ehat is an Embedded system and write about the design process. . $2ay/June * 4,,=&
(*. Erite about formalisms for embedded system design in detail. $2ay/June * 4,,=&
(8. Explain about Embedded "omputing in detail. $2ay/June * 4,,=&
UNIT 4
(. !iscuss about the interrupts and serial 1/0 ports of :=9(. %Nov/:ec * 4,'5&
). a% !raw the flowchart for assembly language programming process and explain.
b% Explain when 0G flag is raised.
c% Ehat is the function of <SE.* and <SE.8F $2ay/June * 4,'5&
*. a% Explain the different modes of operation of timer/counter in :=9( microcontroller
b% Erite an :=9( assembly language program for serial port programming and also explain the
steps involved. $2ay/June * 4,'5&
8. Explain the basic architecture of a microcontroller with a neat diagram and how is it different from
a microprocessor. %2ay;4,'4&
9. Explain the following instructions'
$a%70G, 70GH, 70G"
$b%<4S, <0<
$c%H", H"!. %2.< 4,''&
;. !escribe the features of serial port of the :=9( in detail. %2.< 4,''&
>. a% Explain the operation of the :=9( microcontroller stac6 and the stac6 pointer with relevant
diagram.
b% !iscuss about special function registers and an internal .07 organization of the :=9(
microcontroller. %2.< * 4,',&
:. a% Explain the timer modes of operation in :=9( microcontroller.
b% !iscuss about S"03 and <"03 function registers relevant to serial data input/output in :=9(
microcontroller. %2.< * 4,',&
@. Explain about External and 1nternal <rogram memory. ow does :=9( differentiate between the
external and internal program memory F $2ay/June * 4,,=&
(=. !raw the memory organization in :=9( and explain in detail. $2ay/June * 4,,=&
((. !raw the bloc6 diagram of the :=9( microcontroller and describe in detail about its hardware
features. %2.< * 4,',&
UNIT 5
(. +% Erite a program to chec6 the status of 03N0?? condition of : machines using :=9(.
b% Explain any two programming tools used for +ssembly /anguage <rogramming. %Nov/:ec *
4,'5&
). a% Explain the siginificance of the following pins $i% +/E $ii% $iii% $iv%
b% /ist the addressing modes of :=9( with an example for each. $2ay/June * 4,'5&
*. a% Erite an :=9( assembly language program for multiplying the unsigned number in register .*
by the unsigned number on port) and storing the result in external .+7 locations (=h and ((h.
b% Erite a program to read data from <= and echo it to <(continuously while giving a copy of it to
the serial "07 port to be transmitted out serially. $2ay/June * 4,'5&
8. a% Explain the learning process for assembly language programming. %2.< * 4,',&
b% !ifferentiate manual assembly process 5 automated assembly process. %2.< 4,',&
9. a% Explain how to perform testing programs using a personal computer.
b% Explain how to perform testing programs on a single#board computer.
c% Ehat is importance of testing programsF %2.< * 4,',&
;. Explain the various addressing modes and logical operations of :=9( with examples. $2ay/June
* 4,,=&
>. Explain about +ssembly /anguage <rogramming tools and techniques. $2ay/June * 4,,=&
:. Erite about +rithmetic operations and explain with examples. $2ay/June * 4,,=&
@. a% Explain the interfacing of +/! converter with :=9( microcontroller.
b% Erite an assembly language program for the same. $2ay/June * 4,,=&
(=. Explain about data transfer and logical instructions with examples.$2ay/June* 4,,=&
((. Erite about the assembly language programming process, programming tools and Techniques.
$2ay/June * 4,,=&
(). $a%Eith a diagram, show the memory mapping of the :=9( microcontroller.
$b%?ind the baud rate for the serial port in mode= for a ;7z crystal.
$c%?ind the largest possible time delay for a timer in mode( if a ()7z crystal is used. %2.<
4,''&
(*. a% Explain how to understand the assembler program. !iscuss about assembler directives. %2.< *
4,',&
b% Ehat are the diamond decision elementsF !iscuss about them with simple :=9( decision
instructions. %2.< * 4,',&
(8. a% Explain the commands that get data from .07 addresses.
b% Explain the commands that exchange data. %2.< * 4,',&
(9 a% Explain the organization of .+7 and .07 in :=9( with a neat structure.
b% Erite the difference between the operation of timers and counters.$2ay/June*4,'5&
(;.Explain the types of 247< and "+// instructions of :=9( with examples. $2ay/June * 4,,=&
(>.Explain the timer modes of operation of :=9( in detail. $2ay/June * 4,,=&
)(.Explain about the arithmetic operations and interrupts. $2ay/June * 4,,=&
UNIT 6
(. !escribe the function of various bloc6s of psoc %Nov/:ec 4,'4&
). Explain the operation of psoc based capacitive sensor used for robust detection
of the human finger with a light touch.%may/june4,'5&
UNIT-
(. Explain how serial communication from one i/o device to another i/o device is done using psoc
%Nov/:ec 4,'4&
). Explain any one of the application of psoc %Nov/:ec 4,'4&
*. Explain the features of the psoc* and psoc9 architectures with neat diagrams%may/june4,'5&
UNIT 7
(. Ariefly discuss the various software development tools used in the design of embedded systems.
$2ay/June * 4,'5&
). a% Explain how semaphores are useful as a signaling device.
b% Explain about events and compare different methods for inter tas6 communication. $2ay/June
* 4,'5&
*. a% Ehat is a tas6F Ehat are the various tas6 states explain for an example.
b% Ehat is a semaphoreF ow is it used for a critical section of a designF %2ay;4,'4&
8. Erite the pros and cons of restricting the use of .T0S functions and features in developing
embedded software using .T0S with a suitable example application. %2.< 4,''&
9. !iscuss the commonly as6ed questions on using timer functions as .T0S services. %2.< * 4,',&
;. Explain in detail the process of building software for embedded system.%2.<*4,',&
>. a% Explain how semaphores ma6e a function reentrant with an example code using nucleus .T0S
function prototypes.
:. b% Erite the merits and demerits of using multiple semaphores in an application. %2.< * 4,',&
UNIT 8
(. Explain the various inter process communication mechanisms used in .T0S. $2ay/June * 4,'5&
). a% "ompare various techniques of loading software in to the target system for testing
b% Explain the operation of logic analyzer both in timing mode and state mode. $2ay/June *
4,'5&
*. Ehat is a queue and a pipeF ow do they help in inter tas6 communicationF Explain each with an
example. %2ay;4,'4&
8. $a%Ehat are .eentrant functionsF Explain how to decide if a given piece of function code is
reentrant.
$b%Gerify whether the following function is reentrant with &ustiMcationF 1f not, modify the code to
ma6e it reentrant using semaphores or any other mechanism Static int iGalueO
int i?ixGalue$int i<arm%
P int iTempO iTemp Q ivalueO iTemp RQi<arm S (>O
1f $iTemp 8@)) %
iTemp Q i<armO
iGalue Q iTempO
i<arm Q itempR(>@O
if $i<arm T )===%
return (O
else
return =O
U %2.< 4,''&
9. !escribe memory management function prototypes in 7ulti Tas6 .T0S with an example.
+ssume suitable data wherever necessary. %2.< * 4,',&
;. !iscuss in detail how interrupt routines are tested in the test environment of testing on host
machine. Dive an example code of your choice. %2.< * 4,',&
>. Erite about Embedded software !evelopment tools and any one !ebugging Technique.
$2ay/June * 4,,=&
:. Explain the basic design principles when using an .T0S and differential between operating
system and .T0S. $2ay/June * 4,,=&
@. Erite notes on
a. Semaphores and queues in .T0S
b. ard .eal#Time Scheduling "onsiderations $2ay/June * 4,,=&
(=. Erite in detail about !ebugging techniques in Embedded software.$2ay/June*4,,=&
((. Explain the basic design principles when using an .T0S and differentiate between 0perating
system and .T0S. $2ay/June * 4,,=&
(). Explain in detail about an Embedded software development tools.$2ay/June * 4,,=&
(*. !iscuss in detail the goals of typical testing process for testing the target system. $2ay/June *
4,,=&
(8. a% !escribe different types of data in an .T0S#based .eal#Time System with their characteristics.
b% Ehat do you understand by shared data problemF Explain with an example. $2ay/June *
4,,=&
UNIT +
(. Eith a neat diagram explain the processor and memory organization of +.7 processor.
$2ay/June * 4,'5&
). a% Explain about physical and electrical organization of a "+3 bus along with its
data frame format.
b% Explain the theory of operation and requirements of an elevator controller with neat diagram.
$2ay/June * 4,'5&
*. Explain in detail "+3 Aus protocol. %2ay;4,'4&
8. Explain the memory organization and 1nstruction <arallelism in +.7 processors. %2ay;4,'4&
9. a% ow does a networ6ed embedded system design process differ from standalone systemF
b% !raw a neat bloc6 diagram of S+." architecture and describe the same. %2ay;4,'4&
;. !raw a neat bloc6 diagram of data path model of +.7 processor. %2ay;4,'4&
>. a% !escribe the S+." processor with the help of its functional bloc6 diagram.
b% Erite short notes on S+." /in6 ports. %2.< 4,''&
:. !escribe the various architectural features of one of the S+." processors of your choice with its
functional bloc6 diagram. %2.< * 4,',&
@. a% Ehat is 1)" busF !escribe its functional features and applications.
b% Ehat is a "+3 busF !escribe its functional features 5 applications.%2.<*4,',&
(=. Explain how memory organization of +.7 processor is different from conventional general
purpose processors memory organization. %2.< * 4,',&
((. Erite two applications of S+." processor#based systems with functional bloc6 diagram for
each application and explain its wor6ing. %2.< * 4,',&
(). !raw +.7> +rchitecture and explain its features in detail. $2ay/June * 4,,=&
(*. Erite about +.7 architecture and compare with :=9( micro controller architecture. $2ay/June *
4,,=&
(8. !escribe about +.7 architecture, organization and specifications in detail. $2ay/June * 4,,=&
(9. Erite about <rocessor and memory organization and instruction level parallelism in any one
advanced architecture. $2ay/June * 4,,=&
0I Unit 9ise * Objective 3uestions
UNIT * '
(. +bsolute ob&ect file VVVVVVVV.
$a% has fixed non#relocatable addresses and is used by a device programmer
$b% has fixed non#relocatable addresses and is used by an emulator
$c% has fixed addresses and is used by a simulator
$d% is from an .T0S
). 7acro +ssembler VVVVVVVV.
$a% assembles macros only
$b% assembles macros as well as subroutines only
$c% assembles macros as well as subroutines and 1S.s
$d% generates software building bloc6s
*. Area6pointVVVVVVVV.
$a% removed before testing the codes
$b% removed before burning in the codes in <.07
$c% added before burning in the codes in <.07
$d% need not be removed
8. +ssembler is a tool toVVVVVVVV.
$a% develop and editing source file in assembly language and create list and ob&ect files, and ob&ect
file is executable after lin6ing/location
$b% develop and editing compiled file in assembly language and create ob&ect file, which is
executable after lin6ing/locating
$c% assemble file in assembly language and create ob&ect file, which is executable after
lin6ing/locating
$d% assemble macros
9. Aurning the codes actually meansVVVVVVVV.
$a% erasing the select cells as per the source program hex#file
$b% writing the =s at select cells as per the source ob&ect file
$c% converting the =s at select cells into (s as per the source program hex#file
$d% converting the (s at select cells into =s as per the source program hex#file
;. "ode Aan6VVVVVVVV.
$a% is a code in the register ban6 of internal memory space in :=9(
$b% code ban6 is used only in 1!E generated ob&ect files for :=9( architecture
$c% memory ban6 of ;8 6A size each in a program of code size greater than ;8 6A and is used in
extended :=9( as well as hardware ban6 switched :=9( classic architecture
$d% code ban6 is used only in extended :=9( architecture microcontrollers
>. "ode optimization is to reduceVVVVVVVV.
$a% the code size
$b% the code size and increase the code execution speed
$c% the code size or increase the code execution speed or both as per the option chosen
$d% the code size or decrease the code execution speed or both as per the option chosen
:. "ompiler is a tool to develop and editing source file in high# level language and create VVVVVVVVV.
$a% absolute ob&ect file
$b% assembled source file and absolute ob&ect file
$c% assembled source file, list file and absolute ob&ect file
$d% assembled source file, list file and ob&ect file
@. "9( compiler can haveVVVVVVVV.
$a% fourteen data types to specifically handle :=9( specific features
$b% only standard data bit, char, short, int, float and long data types
$c% only standard data unsigned and signed char, unsigned and signed short, unsigned and signed,
int, float and long data types
$d% +3S1 " standard data types
(=. 1n an embedded system device meansVVVVVVVV.
$a% + microcontroller or peripheral 10 or memory or memory system for a particular purpose or
part of the application or application and the actions of which are controlled by the program sent
or put into it
$b% + peripheral 10 or memory or memory system interfaced to the microcontroller for a particular
purpose or part of the application or application and the actions of which are controlled by the
program sent or put into it
$c% + non#programmable peripheral 10 or memory or memory system interfaced to the
microcontroller
$d% +!", timer, serial port and 10 ports with the control, status and data registers
((. EmulatorVVVVVVVV.
$a% emulates the microcontroller
$b% emulates the microcontroller 10s, serial ports and timers and internal devices
$c% is a software embedded into a microcontroller
$d% is a simulator
(). ex#file is 1ntel hex#formattedVVVVVVVV.
$a% file of hexadecimal codes at different addresses
$b% file of binary codes at different addresses
$c% +S"11 text file of hexadecimal codes at different absolute addresses
$d% binary file of hexadecimal codes at different addresses
(*. /ibrary is for ready made ob&ect codes forVVVVVVVV.
$a% standard function
$b% standard function and common application functions, which can be lin6ed when required
$c% common application functions, which can be lin6ed when required
$d% for ready made ob&ect codes for standard function and common application functions, which
can be exported when required
(8. 7onitorVVVVVVVV.
$a% is in target board, runs application, and gets command during debugging
$b% is in a debugger at target board
$c% is in emulator board
$d% runs application at target board
(9. .eentrant function is a function, whichVVVVVVVV.
$a% returns from the interrupt or diversion
$b% after return from the interrupt or diversion reenters into the same state of "<4, registers and
variables as before leaving
$c% after return from the interrupt or diversion reenters into the same state of registers and stac6s as
before leaving
$d% after return from the interrupt or diversion reenters into the same state of "<4 and stac6 as
before leaving
>ill in t/e blan$s
(. + tool to develop and edit source file in high# level language and create assembled source file, list
file and ob&ect file is calledVVVVVVVV. The ob&ect file is executable after lin6ing/location.
). + cross#assemblerVVVVVVVVrunning on theVVVVVVVVforVVVVVVVVthe machine codes for the target
"<4.
*. + compiler is called cross#compiler whenVVVVVVVVcompiling machine codes for "<4 at the
VVVVVVVV
8. !ata types Aoolean and sfr are specific toVVVVVVVV7"4. !efining data types help a
VVVVVVVVperforming data type chec6ing duringVVVVVVVVandVVVVVVVVthe assignments and
expressions in a program corrected.
9. + bug means an errorVVVVVVVVat theVVVVVVVVThe bug$s% isVVVVVVVVafter the testing
andVVVVVVVVthe actions of the codes.
;. !evelopment cycle consists ofVVVVVVVVin software development phase.
>. Example of devices areVVVVVVVV, andVVVVVVVV+ctions of device are controlled by the VVVVVVVV
:. !evice#database helps inVVVVVVVVfor an application or pro&ect.
@. !evice <rogrammer is a laboratory tool toVVVVVVVVand has theVVVVVVVVin the input.
(=. "onversion of ob&ect file machine codes is done byVVVVVVVVto assembly mnemonics or high#level
language statements.
((. Editor facilitatesVVVVVVVV.
(). 1n#circuit Emulator emulates theVVVVVVVVfunctions of the target "<4 andVVVVVVVV
(*. Expression in " use VVVVVVVV,VVVVVVVV andVVVVVVVV operators on the variables or functions.
(8. ex#?ile is a VVVVVVVV file, which saves VVVVVVVV for VVVVVVVVat each address in VVVVVVVV.
(9. The device isVVVVVVVVaccording to the developed software byVVVVVVVVthe codes and data in the
hex#file.
(;. 1!E is VVVVVVVV tool for selecting VVVVVVVV VVVVVVVV, VVVVVVVV, VVVVVVVV,
VVVVVVVVandVVVVVVVV1t uses menus, tools,VVVVVVVVandVVVVVVVVduring development.
(>. 2T+D isVVVVVVVVstandard testVVVVVVVVandVVVVVVVVarchitecture, used for testing
VVVVVVVVthrough theVVVVVVVVport.
(:. + file of routines or macros having large number of the ob&ect code files, and that gives an ob&ect
code file$s% is calledVVVVVVVV
(@. /in6er is a toolVVVVVVVVinto an absolute ob&ect code file. The file isVVVVVVVVafter lin6ing.
)=. + tool to develop a file is calledVVVVVVVVwhen the file has the machine codes, which are located
at the addresses after they are burned in by the device programmer into the device$s%.
UNIT * 4
"onsider :=9( family microcontroller in the following questions
(. $a% +, A and <SE
$b% + is accumulator, only A and <SE
$c% <SE is not among ones, which
$d% 3one of the +, A and <SE are the special functions registers
). 3umber of ports used in an expanded mode are'
$a% two
$b% three
$c% four in case of additional devices present in a family member
$d% depends according to the use of external program memory or on use of external as well as data
memory
*. .S= and .S('
$a% are not in the <SE as these are not the flags
$b% are in the register sets $ban6s%
$c% are the bits#8 and 9, respectively, for selecting the register ban6 in the <SE
$d% are the bits#* and 8, respectively, for selecting the register ban6 in the <SE. 3ote' Ait > is "
$carry or borrow% flag
8. .eset pin is'
$a% active when connected to (
$b% active for a few cycles only
$c% active when connected to =
$d% active only on watchdog timer reset
9. Ait address =x== and byte address =x== are for the'
$a% Ait = at =x)= and the byte at =x== in the internal .+7
$b% Ait = at =x== and the byte at =x== in the internal .+7
$c% Ait Q = in a S?. and the byte Q =x==
$d% Ait = at =x)= and byte at =x==, respectively
;. T(, T/(, T= and T/= S?.s are at the addresses'
$a% =x:!, =x:", =x:A and =x:+
$b% =x+!, =x+A, =x+" and =x++
$c% =x:!, =x:A, =x:" and =x:+
$d% not between =x:= and =x?? as these are not the S?.s
>. 7ode bits 7( and 7= can'
$a% be set as (( at T70!.9 and T70!.8 and get assigned to T= as an :#bit timer
$b% be set as == only
$c% can be set as == and (= only
$d% not be set as (( at T70!.9 and T70!.8 because timer ( does not function in mode *
:. Timer ( runs and timer = stops'
$a% when T"03.; Q ( and T"03.8 Q =
$b% when T"03.8 Q = and T"03.9 Q (
$c% when T"03.> Q ( and T"03.9 Q =
$d% when T"03 all bits are (s
@. $a% Synchronous mode of operation of serial interface can either be to transmit or receive at a
given instant
$b% asynchronous mode of operation of serial interface can only either be transmit or receive at a
given instant
$c% synchronous and asynchronous mode of operation of serial interface can be transmit and
receive at a given instant
$d% only asynchronous (=T period and ((T periods exist in the serial interface using TA: and
.A:, bits
(=. Ehen S7) is set to'
$a% (, it facilitates the multiprocessor communication in case of mode ( and * $variable baud rate
serial 4+.T mode%
$b% (, it facilitates sending the address for the multiprocessor communication in case of mode )
and * $total (( bit serial 4+.T mode%
$c% =, it facilitates the multiprocessor communication in case of mode ) and * $total (( bit serial
4+.T mode%
$d% =, it facilitates the multiprocessor communication in case of mode = only $synchronous
communication mode%
((. 1f a period is =.** ms between the serial bits, we can transfer in one second when S"03 sets for
mode )'
$a% *== characters
$b% )>9 only
$c% *= characters
$d% )>) characters
(). +t the .S)*)" because of the need to provide a margin for the attenuation and noise pic6ups'
$a% = means R *G down to R )9G
$b% = means R 9G down to R )9G
$c% ( means R *G down to R )9G
$d% ( means R 9 G down to R ()G
(*. 1<.8 is set to ( in the interrupt priority register'
$a% synchronous serial communication mode priority becomes highest
$b% timer T( priority becomes highest
$c% interface serial communication mode priority becomes highest
$d% synchronous serial communication mode priority becomes lowest
(8. 1f 1< register has been set as =x== then'
$a% 13T( has the highest priority
$b% 13T= has the highest and serial interface as the lowest priority
$c% timer overflows have the highest priorities
$d% there is no priority, interrupt processes in the order of its occurrence
>ill in t/e #lan$s
(. 70G +, .= is an instruction of length Q VVVVVVV, fetched between the states S( and VVVVVVV and
executes between states VVVVVVV and VVVVVVV and ta6es VVVVVVV instruction cycle, and the time
ta6en to execute is VVVVVVV Ws when the oscillator frequency Q VVVVVVV.
). 70G +, direct means VVVVVVV and the addressing mode is VVVVVVV 70G +, X.
i
means
VVVVVVV and the addressing mode is VVVVVVV 70G +, Ydata: means VVVVVVV and the addressing
mode is VVVVVVV.
*. 7achine codes for 70G +, X.(, 70G +, .( and H./ +, .( are VVVVVVV.
8. 70G ", ): transfer bit from VVVVVVV at the address of the byte Q VVVVVVV to VVVVVVV.
9. 70G !<, >! will VVVVVVV and has VVVVVVV addressing mode.
;. S< VVVVVVV by ( VVVVVVV when a <4S instruction executes. <" changes by VVVVVVV when
70GH X.
i
, + executes.
>. 0./ ", is VVVVVVV operation between " and complement of VVVVVVV +!!" instruction
affects VVVVVVV flags and 74/ affects VVVVVVV
:. ?or subtracting in :=9(, we must ma6e " Q VVVVVVV because VVVVVVV.
@. /et + Q 9( and A Q )>. +fter 74/ +A instruction + Q VVVVVVV and A Q VVVVVVV, and the
flag VVVVVVV changes and is VVVVVVV.
(=. !+ + after adding A"! numbers 9> and >9 will give result VVVVVVV and " Q VVVVVVV.
((. VVVVVVV instructions change the 0G flag.
(). !23Z direct, .el VVVVVVV and .el can be between RVVVVVVV and #VVVVVVV.
(*. The following instructions complement VVVVVVV bits of VVVVVVV after VVVVVVV Ws. $i% 70G +,
Y??O $ii% 70G .=, =*O $iii% 70G .(, Y?+O 30<O 30<O !23Z .(, ?"O $iv% !23Z .=,
?@O $v% H./ +, <( and $vi% 70G <(, +. +ssume HT+/ frequency Q () 7Z.
(8. +27< is used when VVVVVVV and VVVVVVV affect the S<.
(9. /"+// is used when VVVVVVV and VVVVVVV affect the S<.
(;. The last instruction in a routine is VVVVVVV.
(>. The last instruction in an interrupt service routine is VVVVVVV
UNIT * 5
(. 1n the 7"4 :=9( family, which one of the following options is trueF
$a% +n opcode is of ( byte length in each instruction
$b% +n opcode has variable number of bits in an instruction
$c% +n opcode must have the operands also specified in each instruction
$d% 0pcode bits cannot coexist with the bits for the program counter
). There are distinct 70G instructions to transfer into an S?..
$a% Three
$b% ?our
$c% ?ive
$d% Six
*. 70G" instructions uses as a pointer for transferring a byte of the code or constant into the
accumulator.
$a% <"
$b% .
i
, !<T., + R !<T., + R<", .
i
$c% .
i
R <", !<T., + R<"
$d% 3o !<T.
8. S?. at address :* has )= and at :) has ?E. 13" !<T.
$a% Eill not affect the S?.s
$b% Eill effect the !< of !<T.
$c% Eill effect !</ of !<T.
$d% Eill affect both !< and !</
9. +ll logic operations on a byte
$a% <lace the result into + or direct and ta6es the same time
$b% <lace the result into + or direct and ta6es the same time except for the operations on
immediate data
$c% <lace the result into + and ta6es the same time except for the direct and data operations
$d% <lace the result into + or direct and ta6es the same time except for the direct and data
operations
;. 1f + Q =9 and A Q ;8, then after 74/ +A the S?.s at ?= and E=
$a% !o not change
$b% Equal =( and ?8
$c% Equal ?8 and =(
$d% 3one of these equal ?8
>. 0G flag affects in
$a% 7ultiply and divide
$b% +ddition, subtract, multiply and divide
$c% +ddition and subtraction
$d% +ddition, subtraction and multiply operations
:. +" flag affects in
$a% +ddition, subtraction, multiply and divide
$b% 7ultiply and divide
$c% +ddition and subtraction
$d% +ddition, subtraction and multiply operations
@. + bit address using an instruction can change a bit at
$a% Ait addressable valid S?.s or select internal .+7 area
$b% Ait addressable valid S?.s only
$c% "arry and bit addressable valid S?.s and select internal .+7 area
$d% "arry and bit addressable valid S?.s only
(=. The carry flag affects in
$a% +dd, subtract, multiply and divide
$b% +dd, subtract, increment and decrement
$c% +dd, subtract, ..", ./" and Aoolean processing instructions
$d% +dd, subtract, ..", ./", "23E and Aoolean processing instructions
((. 30< instruction
$a% 1s a &ump to the next instruction within &ust one cycle
$b% !oes no operation and does not change the program counter
$c% Stops the cloc6 of the "<4 and does not do any operations
$d% 1ncrements the <" by (, stops the cloc6 of the "<4 and does not do any operation
(). 1f " Q ( and bit at <).( Q =, the +3/ ", += execution is such that
$a% " can be either ( or =
$b% " Q =
$c% <).( Q (
$d% " and <).( are both (
(*. There is !23Z (:, =?! instruction at the address (===. +fter the execution of this
instruction, the new instruction address is
$a% (=== if the accumulator is == after decrementing
$b% (==) if .= is == after decrementing
$c% (==* if the accumulator is == after decrementing
$d% (==) if .= is not == after decrementing
(8. + programmer should, wherever possible for temporary data or pointer address storage
$a% 4se registers
$b% 4se registers and internal memory
$c% 4se registers and also use the stac6 if the register space is insufficient
$d% 4se the stac6
(9. .egisters are used in the instructions
$a% ?or the temporary variables
$b% ?or the temporary variables or pointers
$c% +s an internal .+7 as well as S?.s
$d% ?or the temporary variables or pointers or specific purposes li6e an accumulator
>ill in t/e #lan$s
( 70G +, .= is an instruction of length Q VVVVVVV, fetched between the states S( and VVVVVVV and
executes between states VVVVVVV and VVVVVVV and ta6es VVVVVVV instruction cycle, and the time ta6en to
execute is VVVVVVV Ws when the oscillator frequency Q VVVVVVV.
) 70G +, direct means VVVVVVV and the addressing mode is VVVVVVV 70G +, X.
i
means VVVVVVV and
the addressing mode is VVVVVVV 70G +, Ydata: means VVVVVVV and the addressing mode is VVVVVVV.
* 7achine codes for 70G +, X.(, 70G +, .( and H./ +, .( are VVVVVVV.
8 70G ", ): transfer bit from VVVVVVV at the address of the byte Q VVVVVVV to VVVVVVV.
9 70G !<, >! will VVVVVVV and has VVVVVVV addressing mode.
; S< VVVVVVV by ( VVVVVVV when a <4S instruction executes. <" changes by VVVVVVV when 70GH
X.
i
, + executes.
> 0./ ", is VVVVVVV operation between " and complement of VVVVVVV +!!" instruction affects
VVVVVVV flags and 74/ affects VVVVVVV
: ?or subtracting in :=9(, we must ma6e " Q VVVVVVV because VVVVVVV.
@ /et + Q 9( and A Q )>. +fter 74/ +A instruction + Q VVVVVVV and A Q VVVVVVV, and the flag
VVVVVVV changes and is VVVVVVV.
(= !+ + after adding A"! numbers 9> and >9 will give result VVVVVVV and " Q VVVVVVV.
(( VVVVVVV instructions change the 0G flag.
() !23Z direct, .el VVVVVVV and .el can be between RVVVVVVV and #VVVVVVV.
(* The following instructions complement VVVVVVV bits of VVVVVVV after VVVVVVV Ws. $i% 70G +, Y??O
$ii% 70G .=, =*O $iii% 70G .(, Y?+O 30<O 30<O !23Z .(, ?"O $iv% !23Z .=, ?@O $v% H./ +,
<( and $vi% 70G <(, +. +ssume HT+/ frequency Q () 7Z.
(8 +27< is used when VVVVVVV and VVVVVVV affect the S<.
(9 /"+// is used when VVVVVVV and VVVVVVV affect the S<.
UNIT * 6
( + System#on#"hip $S0"%#based embedded system is one which uses configurable hardware
surrounding a soft or hard processor core
)."onventional ?<D+#based So" architecture consists of configurable logic bloc6s
$"/AKs%, configurable 1/0 bloc6s, programmable interconnect, and a soft or hard processor core
*The "/A is the basic building bloc6 in an ?<D+.
8The basic building bloc6 in a <So" is the !igital Aloc6
9+ !igital Aloc6 consists of the data path, input multiplexers, output de#multiplexers,configuration
registers, and chaining signals
;. The programmable interconnect enables routing of signals from any !igital Aloc6 to anyof the on#chip
1/0 pins.
UNIT * -
( The <So" * and <So" 9 architectures provide you with a programmable system#on#chip that excels
in precision analog processing and digital flexibility.
) The <So" platform offers :#bit and *)#bit "<4s.
*. The <So" * and <So" 9 architectures include uncommitted operational amplifiers, switched cap/
continuous time $S"/"T% bloc6s, and comparators.
8. The digital to analog converter $!+"% of the <So" * and <So" 9 architectures operates as either a
voltage !+" or a current !+".
9. The 4!A contains two programmable logic devices $</!s%, a datapath module, and some control
and timing logic
;. The first tas6 to be completed upon entering main$% is to call the start functions for the different
components that we have added.
>.The start functions route power to those components and enable theirfunctionality.
>. 4+.T universal asynchronous receiver transmitter
:. 4+.T serial communications port has been a basic lin6 to communicate between the personal
computer and external devices.
@."ypress uses the term "apSense to describe capacitive sensing.
(=."apSense allows a robust detection of the humanfinger with a light touch and without any moving
parts.
((The basic process in capacitive sensing is to measure a change in capacitance that is caused by the
approach of a finger or other conductive ob&ect that can affect capacitance
((. The configurable digital functions available in the 4!As of the <So" device can be customized for
your design and routed to any D<10 pin.
().The digital functions can operate independently from the
"<4 or the "<4 can monitor and control the digital logic fabric through the use of control and status
registers.
UNIT * 7
(. .eal#time means VVVVVVVVVVVV.
$a% actual time
$b% time from start of a tas6
$c% a time that has a fixed and unalterable zero reference, which a cloc6 advances at constant
intervals and which cannot be reloaded
$d% time measured using the system cloc6 of a real#time operating system
). .eal#time operating system is one, which
$a% allows flexible scheduling of the system resources $"<4, memory, etc.% to several tas6s
$b% controls the tas6 synchronization using signals, semaphores and messages
$c% is an 0S for the microcontrollers
$d% is an 0S with preemptive scheduling
>ill in t/e #lan$s
(. + h+ system consists of VVVVVVVVVVVV and the system[s software supervises the running of the
tas6s.
). VVVVVVVVVVVV means information of the present program counter, stac6 pointer and other "<4
registers. Ehen the context of one tas6 VVVVVVVVVVVV and the context of other tas6
VVVVVVVVVVVV then that tas6 runs.
*. .T0S controls a tas6 which can be in one of the following states at any given instance
VVVVVVVVVVVV, VVVVVVVVVVVV, VVVVVVVVVVVV, VVVVVVVVVVVV, waiting for a specific period, and
waiting till some signal or message before some specific or undefined period.
8. .eal#time means VVVVVVVVVVVV from the system[s start and different actions ta6es place in the
system at different instances of this time.
9. .eal#time constraint means VVVVVVVVVVVV before which a tas6 should start after an event$s%.
.ealtime constraint also means the VVVVVVVVVVVV up to which it must respond to an event$s%, and
time limit within which it must finish.
;. .eal#time operating system $.T0S% is VVVVVVVVVVVV when the system requires VVVVVVVVVVVV to
be done at the VVVVVVVVVVVV and in VVVVVVVVVVVV space. .T0S is in between software layer
between VVVVVVVVVVVV and VVVVVVVVVVVV and, VVVVVVVVVVVV routines.
UNIT 8
(.Ehich of the following options is trueF
$a% + tas6 cannot call any other function
$b% + function can call a tas6
$c% + tas6 can call multiple tas6s in a multi#tas6ing system
$d% + tas6 can be assigned to an 1S.
)Ehich of the following options is trueF
$a% + deleted tas6 means a tas6 not present in the .+7
$b% + deleted tas6 means a tas6 detached from the .T0S control and a deleted tas6 cannot be
created again
$c% + deleted tas6 means a tas6 detached from .T0S control
$d% + deleted tas6 means a tas6 detached from .T0S control and the deleted tas6 can be created
again in the same tas6 or from another tas6
*. + tas6 control bloc6 VVVVVVVVVVVV.
$a% saves all the tas6s 1!, state, priority number, stac6 pointer, message pointer$s%, requested
action pointer$s% and return address
$b% can save the created tas6 1!, state, priority number and return address
$c% is for .T0S multi#tas6ing control
$d% is assigned to a tas6 where the tas6 1!, state, priority number, stac6 pointer, message
pointer$s%, requested action pointer$s% and return address save
8. Ehich of the following options is not rightF
$a% + signal is a boolean notification
$b% + signal and a semaphore are of one bit each
$c% + signal and a mutex are of one bit each
$d% + signal, a semaphore and a message are of one bit each
9. Ehich of the following options is rightF
$a% + signal is to notify to the .T0S to permit running of a waiting tas6 or section of a tas6
$b% + signal permits running of a waiting tas6 or a section of tas6
$c% + signal means start a waiting tas6 immediately on priority
$d% + signal is from a tas6 that it has finished its tas6
;. Ehich of the following options is rightF
$a% + timeout is used to let a waiting tas6 or a section of tas6 run after waiting for a signal
$b% + timeout is used to let a waiting tas6 or a section of tas6 run after waiting for a signal or
message or semaphore or timer timeout
$c% + timeout is a signal not received within the defined number of tic6s
$d% + timeout is a signal or semaphore or mailbox message not received within the defined
number of tic6s or a wait period over for a bloc6ed tas6
>. Ehich of the following options is rightF
$a% + tas6 is a program in infinite loop under the .T0S control
$b% + tas6 is a program thread that has no in#between branches, which lead to another end point
and thus has only one start point and one end point and tas6 program can be in infinite loop
$c% + tas6 is a program that also has an infinite loop and starts only on a signal or action from 0S
>ill in t/e blan$s
(VVVVVVVVVVVV controls the running of the tas6s and interrupt#service routines using the hardware.
)The tas6 of VVVVVVVVVVVV when ready, preempts $bloc6s% the low#priority tas6 in order to function
within the time constraints.
*Tas6 in VVVVVVVVVVVV state of ready when it gets a signal for which it is waiting or gets a message
for which it is waiting or time out when its waiting#period is over.
8VVVVVVVVVVVV are assigned to the tas6s in preemptive scheduling.
9 Ehen the tas6s run in cyclic schedule and when one completes then other is signalled to start, then
scheduling is called VVVVVVVVVVVV.
; The VVVVVVVVVVVV generates a timeout at regular $preset% intervals. 1t is called VVVVVVVVVVVV
The VVVVVVVVVVVV interrupts the .T0S at VVVVVVVVVVVV. System cloc6 tic6s are used for the
VVVVVVVVVVVV actions.
> + tas6 VVVVVVVVVVVV another tas6 but it can call the function$s% to implement certain action$s%.
: + tas6 i waits for VVVVVVVVVVVV when 0SVwait function executes for a period Q VVVVVVVVVVVV.
@ + tas6 i VVVVVVVVVVVV a signal at time t
(
. Then waiting tas6 & ta6es the VVVVVVVVVVVV and ta6es
over the resources $"<4, memory, 10s, etc.% and starts at time t
)
.
(= + tas6 i VVVVVVVVVVVV a semaphore $to6en% s
(
at time t
(
. Then waiting tas6 & ta6es the
VVVVVVVVVVVV and ta6es over the resources $"<4, memory, 10s, etc.% and starts at time t
)
.
(( + tas6 i VVVVVVVVVVVV a VVVVVVVVVVVV into mailbox 7
l
at time t
(
. Then waiting tas6 & the
VVVVVVVVVVVV the message and ta6es over the resources $"<4, memory, 10s, etc.% and starts at
time t
)
.
() + high priority tas6 must be waiting for VVVVVVVVVVVV, VVVVVVVVVVVV, VVVVVVVVVVVV, or
VVVVVVVVVVVV so that the lower priority tas6 can run in preemptive scheduling.
(* .TH9( Tiny 6ernel requires only VVVVVVVVVVVV bytes of program memory codes space. Ehen
we don[t need VVVVVVVVVVVV, VVVVVVVVVVVV, and VVVVVVVVVVVV functions we use it. 7aximum
number of defined tas6s can be VVVVVVVVVVVV. 7aximum number of tas6s which can be active
are VVVVVVVVVVVV at an instant. 1t requires maximum !+T+ space of VVVVVVVVVVVV. Aytes in
1nternal .+7. 1t requires ST+"- space of VVVVVVVVVVVV bytes per tas6.
(8 .TH9( ?ull has the functions for preemptive scheduling. .TH9( ?ull has the following features.
$a% Denerates the timer tic6s $for cyclic interrupts% using VVVVVVVVVVVV.
$b% <rovides for VVVVVVVVVVVV of a high priority tas6 by switching from a lower priority tas6.
$c% 1t has program codes of Q VVVVVVVVVVVV -bytes, data in internal .+7 !+T+ Q
VVVVVVVVVVVV bytes, stac6 in internal .+7 $1!+T+% Q VVVVVVVVVVVV bytes, and external
memory H!+T+ Q VVVVVVVVVVVV bytes $minimum%.
$d% 1t has the functions to enable preemptive scheduling. high#priority tas6 must have an infinite
loop
UNIT * +
(<hilips +.7 7"4 /<" )(xx has VVVVVVVVVVVVVVV.
$a% ;= 7z operation, =.(:#mm "70S, embedded fast flash
$b% 8: 7z operation, =.(:#mm "70S, embedded fast flash
$c% ;= 7z operation, =.(*#mm "70S, embedded fast flash
$d% ;= 7z operation, =.(*#mm "70S, but no embedded fast flash.
)+.7 VVVVVVVVVVVVVVV.
$a% instruction set and processor show .1S" features
$b% processor is .1S" but instruction set retaining the best of "1S" features and that gives a
simplicity of programming
$c% all arithmetic and logic operations are on registers
$d% all arithmetic and logic operations are on registers used as index register
*"<4 registers VVVVVVVVVVVVVVV.
$a% S<, /. and <" are separate registers from r=#r(9 D<. set
$b% S< and <" are separate registers from r=#r(9 D<. set
$c% /. and <" are registers within the r=#r(9 D<. set and a register can be assumed as S<
$d% "<S., S<, /. and <" are registers within the r=#r(9 D<. set
8?or un#nested calls, VVVVVVVVVVVVVVV.
$a% S< is not necessary
$b% S< is necessary
$c% Saving <" is necessary
$d% Saving <" and /. is necessary
9 ST7?! r(*\,Pr@#r(8U instruction means store VVVVVVVVVVVVVVV.
$a% registers r@ and r(8 at memory start address pointed by r(* and then increment r(* for next
time to next available memory address after the bloc6 transfer
$b% word after subtracting r@ and r(8 at memory start address pointed by r(* and then increment
r(* for next time to next available memory address after the bloc6 transfer
$c% registers r@ and r(8 at memory start address pointed by r(* and then pre#increment r(* for
memory address before the bloc6 transfer
$d% registers r@ to r(8 at memory start address pointed by r(* and then increment r(* for next time
to next available memory address after the bloc6 transfer
; !irectly an extended address VVVVVVVVVVVVVVV.
$a% is not used in +.7
$b% is not used in +.7 and a pseudo instruction is used for it by assembler
$c% 0nly register and immediate addressing modes are used in +.7
$d% 0nly register, indexed and immediate addressing modes are used in +.7
> "ondition test for VVVVVVVVVVVVVVV.
$a% DT $greater than% means 3 and Z Q=
$b% DT $greater than% means G and Z Q =
$c% DT $greater than% means 3 Q G and Z Q =
$d% DT $greater than% means Z Q =
: Exception priorities are in following descending order VVVVVVVVVVVVVVV.
$a% .eset, !ata +bort, ?1C, 1.C <re#fetch +bort, SE1 or 4ndef
$b% .eset, !ata +bort, ?1C, 1.C <re#fetch +bort, SE1 and 4ndef
$c% .eset, ?1C, 1.C, !ata +bort, <re#fetch +bort, SE1 or 4ndef
$d% not in fixed order, it is as per user#defined prioritization
>ill in t/e #lan$s
(. VVVVVVVVVVVVVVV does processing of multiple instructions and data by VVVVVVVVVVVVVVV and
pipeline# based processing.
). + VVVVVVVVVVVVVVV VVVVVVVVVVVVVVV has two or more pipelines for processing in which, at an
instance more than one instruction is at the fetching, decoding and executing stages.
*. <ipelining facilitates when each instruction fetch is in a single cycle, VVVVVVVVVVVVVVV in single
cycle and VVVVVVVVVVVVVVV in the single cycle. The performance becomes VVVVVVVVVVVVVVV#
times in n#stage pipeline in the pipelined processor. <ipelining gives about VVVVVVVVVVVVVVV#
times greater performance in 71<S $million instructions per second% for same cloc6 speed and
same architecture implementation.
8. VVVVVVVVVVVVVVV means a computer processor, which has ]] addressing modes,
VVVVVVVVVVVVVVV length instructions, VVVVVVVVVVVVVVV cycle times for executing an instruction
and instruction decoder implementing instructions using VVVVVVVVVVVVVVV
9. Smart card interface is an interface for VVVVVVVVVVVVVVV or VVVVVVVVVVVVVVV #less
communication with an 7"4# based card.
;. S<S. Saved program status register has the bits for VVVVVVVVVVVVVVV for the VVVVVVVVVVVVVVV
program.
>. Ayte, VVVVVVVVVVVVVVV and word are three data types in +.7.
:. SG" means VVVVVVVVVVVVVVV and SE1 instruction is used for VVVVVVVVVVVVVVV
@. Thumb means VVVVVVVVVVVVVVV instruction set for VVVVVVVVVVVVVVV #bit +.7. 1t gives
advantage of VVVVVVVVVVVVVVV density and instructions at which VVVVVVVVVVVVVVV at run#time
into VVVVVVVVVVVVVVV #bit +.7 instructions.
(=. Zero wait state means VVVVVVVVVVVVVVV
((. +.7 7"4s can run in VVVVVVVVVVVVVVV power modes^ VVVVVVVVVVVVVVV,
VVVVVVVVVVVVVVV, VVVVVVVVVVVVVVV and <ower#off%
(). +.7 has VVVVVVVVVVVVVVV architecture. VVVVVVVVVVVVVVV processors have VVVVVVVVVVVVVVV
addressing modes^ VVVVVVVVVVVVVVV and store architecture, VVVVVVVVVVVVVVV register set, and
]] implementation of the instructions, VVVVVVVVVVVVVVV cycle and VVVVVVVVVVVVVVV length
of instructions.
(*. .1S" gives VVVVVVVVVVVVVVV performance in 71<S. +.7 has VVVVVVVVVVVVVVV *)#bit
registers with VVVVVVVVVVVVVVV as <", VVVVVVVVVVVVVVV as lin6 register for return address and
conventionally VVVVVVVVVVVVVVV as stac6 pointer.
(8. +.7 architecture#based 7"4s give VVVVVVVVVVVVVVV performance at VVVVVVVVVVVVVVV ?our
7"4 examples are VVVVVVVVVVVVVVV, VVVVVVVVVVVVVVV, VVVVVVVVVVVVVVV and
VVVVVVVVVVVVVVV
(9. VVVVVVVVVVVVVVV is an exception thrown for data error. Exception means VVVVVVVVVVVVVVV
condition of an VVVVVVVVVVVVVVV interrupt or error, which VVVVVVVVVVVVVVV and lin6s to the
handler $1S.%.
(;. VVVVVVVVVVVVVVV is a memory in an 7"4, in which sectors can be VVVVVVVVVVVVVVV fast and
bytes can be written VVVVVVVVVVVVVVV
(>. VVVVVVVVVVVVVVV is a term used in " program for running a function $handler% when an
VVVVVVVVVVVVVVV is thrown. +.7 has SE1 handler, which runs on catching an exception.
(:. Exception handler means VVVVVVVVVVVVVVV, which address is specified by a vector address and
which runs to respond the exception.
(@. VVVVVVVVVVVVVVV is a term used in " program for activation of a run#time condition or error or
interrupt running a function $handler% or method when an exception is thrown. +.7 has
instruction VVVVVVVVVVVVVVV to throw an exception.
0II Sample ?uestion papers