EE 110 Lab Experiment #3 Fall 2009

NAME: _________________________________
EXPERIMENT 3: a!i" TTL L#$i" %ate! &1 'ee()
The purpose of this laboratory is to learn to use TTL logic gates and understand the basic logic functions
of AND, OR and NOT. *t+,ent! 'ill '#r( in,i-i,+all./
a"($r#+n,:
The following diagrams illustrate the pinouts of several TTL devices we have in stoc. These integrated
circuits are in Dual !n"line #acages $D!#%, consisting of a central case with two rows of pins. &een from
the top $i.e., the pins pointing away from you%, loo for the dent or notch at one end. This notch indicates
the origin for pin numbering. #ins are numbered consecutively, going counterclocwise from the notch.
!n all cases, pin ' must connect to (ND and pin )* to the +,- power supply. .ithout proper power and
ground connections, the device will not function. DO NOT wire these bacwards / you will destroy the part0
Remin,er: As you do this lab, please mae sure that you follow every step as specified, and that you fill in all
tables and 1uestions. #lease read each part of the lab carefully as you are about to begin that portion. This lab
re1uires a TA signature at the end, verifying that all your circuits wor as e2pected. As you finish each part of
the lab, be sure to leave that circuit and all its connections on your protoboard, so that you can show the TA
that it wors as e2pected at the end of the lab. This lab has ' pages / please be sure to chec the bac page of
the lab. This page includes verification of your lab results by the lab TA, and your conclusions and comments
about this lab.
PART 1 0 N1T $ate
Pr#"e,+re:
). !n the space below, labeled 3igure ), draw a logic diagram of the NOT gate. 4int5 Loo at the
inidividual NOT gates shown in the '*L&6* chip. !nclude input and output lines7 you can draw
them as straight lines.
8. Label the gate with the '*66 family part number you plan to use7 for the NOT gate, this would be
a '*L&6* device.
8")
EE 110 Lab Experiment #3 Fall 2009
9. Label the input and output of each gate with the pin numbers you wish to use for the chosen
device. The '*L&6* device includes : NOT gates, each with one input and one output7 you could
use input pin ) and output pin 8 for one gate, or input pin 9 and output pin *. Remember to use
input and output for the same gate.
Fi$+re 1: L#$i" ,ia$ram #2 N1T $ate
*. Now build this logic circuit on your proto board. ;se 88"gauge wire to mae all connections.
a. <ae sure power is turned off. #lug the chosen device into your proto board in the correct
places $use the area on the left side of the proto board%. .ire each part to power and
ground as re1uired. $=onnect to the power busses you configured in the first lab
e2periment. ;se R>D wires for your connections to the +,- supply and ?LA=@ wires
for the (ND connections.% Double"chec your pin numbers for the power and ground
wires7 you donAt want to wire these bacwards0 !t pays to tae the time to be careful. !f
you are not sure how to wire up either the power bus $it is probably already wired up, but
chec to be sure% or the chip, please as for help from the TA or lab instructor before
powering up your lab trainer. Bou can destroy either the chip if power and (ND are
reversed, or the trainer if there is a short $power connected to directly to (ND%.
b. =onnect the output to the leftmost of the C single L>Ds above your proto board. !t should
be labeled L>D '. ;se any wire color other than red or blac for your connection.
c. .ire the input to switch &.6. Again, use any wire color other than red or blac. !t helps
to use the same color wire for both input and output7 that way, you can eep trac of the
signal path.
,. =hec your wiring. <ae sure you have not connected a gate output directly to a switch. <ae
sure your power connections $R>D% and ground connections $?LA=@% are correct to the chip. ?e
sure that the power busses are wired correctly. <ae sure your chip is not in upside"down.
:. 3ill out the truth table in Table ) below with possible input values of A in column ), and the output
values you e2pect to see for a NOT gate, based on the input values for A, listed in column 8.
Remember, A is a binary variable. A will be controlled by switch &.6.
'. Now power on your lab trainer. &et switch &.6 to 6. !s L>D ' lighted or notD Decide whether a
lighted L>D means a 6 or ), and put the appropriate value into Table ) as observed output, in
column 9, in the appropriate row given that &.6 is set to 6.
C. Now move switch &.6 to ). !s L>D ' lighted or notD Again put the appropriate value for your
observed output, as indicated by L>D ', in column 9, again in the appropriate row for &.6 set to
). Do your observed outputs match your e2pected outputsD !f they donAt, consider the following
possibilities, and try to determine what the problem is and fi2 it5
a. !nput not connected properly7 chec input with logic probe to be certain that &.6 is set to
the value you e2pect. !tAs also possible the switch &.6 is not woring, and you can
determine that by checing &.6 output also.
b. Output not connected properly to L>D '7 chec output with logic probe. !f the output is
correct, perhaps your wire connection to the L>D ' terminal is not solid. Does the wire
end loo lie it might brea offD !f so, use another wire. !f not, try pushing the wire into
8"8
EE 110 Lab Experiment #3 Fall 2009
the L>D ' terminal a little further. Or switch the wire to another L>D. !f the L>D still
does not display the value you e2pect, consider whether you have made the correct
decision as to whether a lighted L>D means a 6 or a ).
c. =hip not powered correctly7 chec pin ' and pin )* with logic probe to be certain they are
at (ND and +, -, respectively. !f they are not, chec to see if you have5
i. =onnected (ND andEor +, - to the wrong pin location $they are switched, are off
by one pin, or chip is upside down%. !f so, change them 1uicly. 4aving the
power and ground switched will cause the chip to overheat and eventually destroy
the chip.
ii. .ired the power busses correctly7 chec both the +, - and (ND busses to be
certain they are at the correct voltage.
iii. <ae sure the lab trainer power switch is turned on.
d. >2pected output values are incorrect. The NOT gate output inverts the input, so the
output value should be the complement $or the opposite% of the input value.
e. Observed output values placed in the wrong row. Fuicly chec to be certain that your
input A value corresponds to the correct value for &.6, and that your observed output
value corresponds to the L>D ' result for that given value of &.6 $A%.
f. !f you chec everything on this list, and still cannot determine why the gate is not woring
as e2pected, as the lab TA or instructor for help.
G. Lea-e .#+r "3ip an, "#nne"tin$ 'ire! #n t3e b#ar,4 Bou will need to 1uicly display their
functioning to the TA at the end of this lab.

Inp+t A Expe"te, 1+tp+t 1b!er-e, 1+tp+t
Table 1: Tr+t3 Table 2#r N1T $ate
PART 2 0 AN5 $ate
Pr#"e,+re:
)% !n the space below, labeled 3igure 8, draw a logic diagram of the AND gate. 4int5 Loo at the
individual AND gates shown in the '*L&6C chip. !nclude input and output lines. !f there are not
enough '*L&6C gates, you can use a NAND gate $'*L&66% with an inverter $NOT gate, '*L&6*%
after the output. Tal with the TA or instructor if you have any 1uestions about this.
8% Label the gate with the '*66 family part number you plan to use7 for the AND gate, this would be
a '*L&6C device.
9% Label the inputs and output of each gate with the pin numbers you wish to use for the chosen
device. The '*L&6C device includes * AND gates7 you could use input pins ) and 8 and output
pin 9 for one gate, or input pins * and , and output pin :. Remember to use inputs and output for
the same gate.
*% The two inputs will be connected to &.) and &.8. !t helps to also label those on your logic
diagram, so that you can 1uicly tell which switch is controlling the voltage to which input pin.
8"9
EE 110 Lab Experiment #3 Fall 2009
Fi$+re 2: L#$i" ,ia$ram #2 AN5 $ate
,% Now build this logic circuit on your proto board. ;se 88"gauge wire to mae all connections.
a. <ae sure power is turned off. #lug the chosen device into your proto board in the correct
places $use the area on the left side of the proto board%. .ire each part to power and
ground as re1uired. $=onnect to the power busses you configured in the first lab
e2periment. ;se R>D wires for your connections to the +,- supply and ?LA=@ wires
for the (ND connections.% Double"chec your pin numbers for the power and ground
wires. #in ' is (ND, and pin )* is +, -.
b. =onnect the output to L>D : above your proto board. ;se any wire color other than red
or blac.
c. .ire the two inputs to switch &.) and &.8. Again, use any wire color other than red or
blac. !t helps to use the same color wire for both input and output7 that way, you can
eep trac of the signal path. !f you use different color wires than for the NOT gate, you
can 1uicly tell which wires go to which chip7 this is helpful in trouble"shooting
$debugging% if your circuit does not wor as e2pected.
:% =hec your wiring. <ae sure you have not connected a gate output directly to a switch. <ae
sure your power connections $R>D% and ground connections $?LA=@% are correct to the chip. ?e
sure that the power busses are wired correctly. <ae sure your chip is not in upside"down.
'% 3ill out the truth table in Table 8 below with possible input values of A and ? in columns ) and 8
respectively, and the output values you e2pect to see for a AND gate, based on the input values for
A and ?, listed in column 9. Remember, both A and ? are binary variables, and they will be
controlled by &.) and &.8. Loo at your logic diagram to see which input pin is connected to
&.) and which to &.8. !ndicate on the truth table which switch is A and which is ?.
C% Now power on your lab trainer. &et both switch &.) and &.8 to 6. !s L>D : lighted or notD
Decide whether a lighted L>D means a 6 or ), and put the appropriate value into Table 8 as
observed output, in column *, in the appropriate row given that both &.) and &.8 are set to 6.
G% <ove your switches &.) and &.8 through all possible combinations of values $there should be
four total, counting the 66 setting in part C above%. !s L>D : lighted or notD Again put the
appropriate value for your observed output, as indicated by L>D :, in column * of Table 8, in the
appropriate row for your &.) and &.8 values. Do your observed outputs match your e2pected
outputs for every rowD !f they donAt, chec over the possibilities listed in #art ).C.a"e $now you
have 8 inputs to chec, instead of only )% and see if you can determine what the problem is and fi2
it. !f you chec everything in the list and still cannot determine what the problem is, as your TA
or lab instructor for help.
Inp+t A Inp+t Expe"te, 1+tp+t 6 1b!er-e, 1+tp+t 6
8"*
EE 110 Lab Experiment #3 Fall 2009
Table 2: Tr+t3 Table 2#r AN5 $ate/
)6. Lea-e .#+r "3ip an, "#nne"tin$ 'ire! 2r#m Part 2 #n t3e b#ar,4 Bou will need to 1uicly
display their functioning to the TA at the end of this lab.
PART 3 0 1R $ate
Pr#"e,+re:
)% !n the space below, labeled 3igure 9, draw a logic diagram of the OR gate. 4int5 Loo at the
individual OR gates shown in the '*L&98 chip. !nclude input and output lines. !f there are not
enough '*L&98 gates, you can use a NOR gate $'*L&68% with an inverter $NOT gate, '*L&6*%
after the output. Tal with the TA or instructor if you have any 1uestions about this.
8% Label the gate with the '*66 family part number you plan to use7 for the OR gate, this would be a
'*L&98 device.
9% Label the inputs and output of each gate with the pin numbers you wish to use for the chosen
device. The '*L&98 device includes * OR gates7 you could use input pins ) and 8 and output pin
9 for one gate, or input pins * and , and output pin :. Remember to use inputs and output for the
same gate. N#te: !f you use a NOR gate $'*L&68%, the gates are facing the opposite direction on
the chip from the OR gate $'*L&98%7 this means that for the NOR gate, pins 8 and 9 are inputs,
and pin ) is an output. ?e sure you now the correct input and output pins for the device you are
using. Always chec the pin diagrams at the beginning of the lab handout.
*% The two inputs will be connected to &.9 and &.*. !t helps to also label those on your logic
diagram, so that you can 1uicly tell which switch is controlling the voltage to which input pin.
Fi$+re 3: L#$i" ,ia$ram #2 1R $ate
,% Now build this logic circuit on your proto board. ;se 88"gauge wire to mae all connections.
a. <ae sure power is turned off. #lug the chosen device into your proto board in the correct
places $use the area on the left side of the proto board%. .ire each part to power and
ground as re1uired. $=onnect to the power busses you configured in the first lab
e2periment. ;se R>D wires for your connections to the +,- supply and ?LA=@ wires
for the (ND connections.% Double"chec your pin numbers for the power and ground
wires. #in ' is (ND, and pin )* is +, -.
b. =onnect the output to L>D , above your proto board. ;se any wire color other than red
or blac.
c. .ire the two inputs to switch &.9 and &.*. Again, use any wire color other than red or
blac. !t helps to use the same color wire for both input and output7 that way, you can
8",
EE 110 Lab Experiment #3 Fall 2009
eep trac of the signal path. !f you use different color wires than for the NOT and AND
gates, you can 1uicly tell which wires go to which chip7 this is helpful in trouble"shooting
$debugging% if your circuit does not wor as e2pected.
:% =hec your wiring. <ae sure you have not connected a gate output directly to a switch. <ae
sure your power connections $R>D% and ground connections $?LA=@% are correct to the chip. ?e
sure that the power busses are wired correctly. <ae sure your chip is not in upside"down.
'% 3ill out the truth table in Table 9 below with possible input values of A and ? in columns ) and 8
respectively, and the output values you e2pect to see for a AND gate, based on the input values for
A and ?, listed in column 9. Remember, both A and ? are binary variables, and they will be
controlled by &.9 and &.*. Loo at your logic diagram to see which input pin is connected to
&.9 and which to &.*. !ndicate on the truth table which switch is A and which is ?.
C% Now power on your lab trainer. &et both switch &.9 and &.* to 6. !s L>D , lighted or notD
Decide whether a lighted L>D means a 6 or ), and put the appropriate value into Table 9 as
observed output, in column *, in the appropriate row given that both &.9 and &.* are set to 6.
G% <ove your switches &.9 and &.* through all possible combinations of values $there should be
four total, counting the 66 setting in part C above%. !s L>D , lighted or notD Again put the
appropriate value for your observed output, as indicated by L>D ,, in column * of Table 9, in the
appropriate row for your &.9 and &.* values. Do your observed outputs match your e2pected
outputs for every rowD !f they donAt, chec over the possibilities listed in #art ).C.a"e $now you
have 8 inputs to chec, instead of only )% and see if you can determine what the problem is and fi2
it. !f you chec everything in the list and still cannot determine what the problem is, as your TA
or lab instructor for help.
Inp+t A Inp+t Expe"te, 1+tp+t 6 1b!er-e, 1+tp+t 6
Table 3: Tr+t3 Table 2#r 1R $ate/
)6% Lea-e .#+r "3ip an, "#nne"tin$ 'ire! 2r#m Part 3 #n t3e b#ar,4 Bou will need to 1uicly
display their functioning to the TA at the end of this lab.

PART 7 0 5em#n!trate 8#+r Re!+lt! an, 6#n"l+!i#n!
Pr#"e,+re:
)% Demonstrate the operation of your three logic circuits $NOT, AND and OR% to the teaching
assistant.
TA *i$nat+re: _______________________________________________________________
8":
EE 110 Lab Experiment #3 Fall 2009
8% Describe your results.
a. .hat results did you obtain in this e2perimentD
b. .hat difficulties did you haveD
c. .hat are your conclusionsD .hat did you learnD
9% Once your wor is complete, please dismantle your wiring and remove the chips you installed.
$Leave the power bus wiring in place.% Return your chips to the correct places in the parts bin.
8"'