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Priority Encoders

VHDL
Following is the VHDL code for a 3-bit 1-of-9 Priority
Encoder.
library ieee;
use ieee.std_logic_1164.all;
entity priority is
port ( sel : in std_logic_vector (7 downto 0);
code :out std_logic_vector (2 downto 0));
end priority;
arcitecture arci o! priority is
begin
code "# $000$ wen sel(0) # %1% else$001$ wen sel(1)
# %1% else$010$ wen sel(2) # %1% else$011$ wen
sel(&) # %1% else$100$ wen sel(4) # %1% else$101$
wen sel(') # %1% else$110$ wen sel(6) # %1%
else$111$ wen sel(7) # %1% else$((($;
end arci;
VHDL (ne-Hot!
Following is the VHDL code for a 3 to " line decoder.
library ieee#
use ieee.std_logic_1164.all;
entity dec is
port (sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0));
end dec;
arcitecture arci o! dec is
begin
res "#$00000001$ wen sel # $000$ else$00000010$ wen
sel # $001$ else$00000100$ wen sel # $010$
else$00001000$ wen sel # $011$ else$00010000$ wen
sel # $100$ else$00100000$ wen sel # $101$
else$01000000$ wen sel # $110$ else$10000000$;
end arci;
VHDL (ne-$old!
Following is the VHDL code for a 3 to " line decoder.
library ieee;
use ieee.std_logic_1164.all;
entity dec is
port (sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0));
end dec;
arcitecture arci o! dec is
begin
res "#$11111110$ wen sel # $000$ else$11111101$ wen
sel # $001$ else$11111011$ wen sel # $010$
else$11110111$ wen sel # $011$ else$11101111$ wen
sel # $100$ else$11011111$ wen sel # $101$
else$10111111$ wen sel # $110$ else$01111111$;
end arci;
% &ins Descri&tion
s'()*+ ,elector
res
Data -t&-t
VHDL
Following is the VHDL code.
library ieee;
use ieee.std_logic_1164.all;
entity dec is
port (sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0));
end dec;
arcitecture arci o! dec is
begin
res "#$00000001$ wen sel # $000$ else
(( unused decoder output
$))))))))$ wen sel # $001$ else
$00000100$ wen sel # $010$ else
$00001000$ wen sel # $011$ else
$00010000$ wen sel # $100$ else
$00100000$ wen sel # $101$ else
$01000000$ wen sel # $110$ else
$10000000$;
end arci;
% &ins Descri&tion
s'()*+ ,elector
res
Data -t&-t
VHDL
Following is the VHDL code.
library ieee;
use ieee.std_logic_1164.all;
entity dec is
port (sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0));
end dec;
arcitecture arci o! dec is
begin
res "#$00000001$ wen sel # $000$ else$00000010$ wen
sel # $001$ else$00000100$ wen sel # $010$
else$00001000$ wen sel # $011$ else$00010000$ wen
sel # $100$ else$00100000$ wen sel # $101$ else
(( 110 and 111 selector values are unused
$))))))))$;
end arci;
VHDL $ode
Following is the VHDL code for a .-to-1 1-bit /01 -sing
an %f state2ent.
library ieee;
use ieee.std_logic_1164.all;
entity *u+ is
port (a, b, c, d : in std_logic;
s : in std_logic_vector (1 downto 0);
o : out std_logic);
end *u+;
arcitecture arci o! *u+ is
begin
process (a, b, c, d, s)
begin
i!
(s # $00$) ten o "# a;
elsi! (s # $01$) ten o "# b;
elsi! (s # $10$) ten o "# c;
else o "# d;
end i!;
end process;
end arci;
.-to-1 /01 0sing $3,E ,tate2ent
4he following table shows &in definitions for a .-to-1 1-
bit /01 -sing a $ase state2ent.
% Pins
Descri&tion
a5 b5 c5 dData %n&-ts
s'1)*+
/01 selector
o
Data -t&-t
VHDL $ode
Following is the VHDL code for a .-to-1 1-bit /01 -sing
a $ase state2ent.
library ieee;
use ieee.std_logic_1164.all;
entity 2-6 is
port (a, b, c, d : in std_logic;
s : in std_logic_vector (1 downto 0);
o : out std_logic);
end *u+;
arcitecture arci o! *u+ is
begin
process (a, b, c, d, s)
begin
case s is
wen $00$ #- o "# a;
wen $01$ #- o "# b;
wen $10$ #- o "# c;
wen oters #- o "# d;
end case;
end process;
end arci;
.-to-1 /01 0sing 4ristate 7-ffers
4his section shows VHDL and Verilog e6a2&les for a .-
to-1 /-6 -sing tristate b-ffers
4he following table shows &in definitions for a .-to-1 1-
bit /01 -sing tristate b-ffers.
% Pins
Descri&tion
a5 b5 c5 dData %n&-ts
s'3)*+
/01 ,elector
o
Data -t&-t
VHDL $ode
Following is the VHDL code for a .-to-1 1-bit /01 -sing
tristate b-ffers.
library ieee;
use ieee.std_logic_1164.all;
entity *u+ is
port (a, b, c, d : in std_logic;
s : in std_logic_vector (& downto 0);
o : out std_logic);
end *u+;
arcitecture arci o! *u+ is
begin
o "# a wen (s(0)#%0%) else %.%;o "# b wen (s(1)#%0%)
else %.%;o "# c wen (s(2)#%0%) else %.%;o "# d wen
(s(&)#%0%) else %.%;
end arci;
8o .-to-1 /01
4he following e6a2&le does not generate a .-to-1 1-bit
/015 b-t 3-to-1 /01 with 1-bit
latch. 4he reason is that not all selector 9al-es were
described in the %f state2ent. %t is
s-&&osed that for the s:11 case5 ;; <ee&s its old 9al-e5
and therefore a 2e2ory ele2ent
is needed.
4he following table shows &in definitions for a 3-to-1 1-
bit /01 with a 1-bit latch.
% Pins
Descri&tion
a5 b5 c5 dData %n&-ts
s'1)*+
,elector
o
Data -t&-t
VHDL $ode
Following is the VHDL code for a 3-to-1 1-bit /01 with a
1-bit latch.
library ieee;
use ieee.std_logic_1164.all;
entity *u+ is
port (a, b, c, d : in std_logic;
s : in std_logic_vector (1 downto 0);
o : out std_logic);
end *u+;
arcitecture arci o! *u+ is
begin
process (a, b, c, d, s)
begin
i!
(s # $00$) ten o "# a;elsi! (s # $01$) ten o "#
b;elsi! (s # $10$) ten o "# c;end i!;
end process;
end arci;
Logical ,hifters
E6a2&le 1
4he following table shows &in descri&tions for a logical
shifter.
% &ins
Descri&tion
D'=)*+ Data %n&-t
,EL
shift distance selector
,'=)*+ Data -t&-t
VHDL
Following is the VHDL code for a logical shifter.
library ieee;
use ieee.std_logic_1164.all;
use ieee.nu*eric_std.all;
entity lsi!t is
port(/0 : in unsigned(7 downto 0);
123 : in unsigned(1 downto 0);
14 : out unsigned(7 downto 0));
end lsi!t;
arcitecture arci o! lsi!t is
begin
wit 123 select
14 "# /0 wen $00$,
/0 sll 1 wen $01$,
/0 sll 2 wen $10$,
/0 sll & wen oters;
end arci;
E6a2&le (
1,4 willnot infer a Logical ,hifter for this e6a2&le5 as
not all of the selector 9al-es are
&resented.
% &ins
Descri&tion
D'=)*+ Data %n&-t
,EL
shift distance selector
,'=)*+ Data -t&-t
VHDL
Following is the VHDL code.
library ieee;
use ieee.std_logic_1164.all;
use ieee.nu*eric_std.all;
entity lsi!t is
port(/0 : in unsigned(7 downto 0);
123 : in unsigned(1 downto 0);
14 : out unsigned(7 downto 0));
end lsi!t;
arcitecture arci o! lsi!t is
begin
wit 123 select
14 "# /0 wen $00$,
/0 sll 1 wen $01$,
/0 sll 2 wen oters;
end arci;
E6a2&le 3
1,4 willnot infer a Logical ,hifter for this e6a2&le5 as
the 9al-e is not incre2ented by 1
for each conse>-ent binary 9al-e of the selector.
% &ins
Descri&tion
D'=)*+ Data %n&-t
,EL
shift distance selector
,'=)*+ Data -t&-t
VHDL
Following is the VHDL code.
library ieee;
use ieee.std_logic_1164.all;
use ieee.nu*eric_std.all;
entity lsi!t is
port(/0 : in unsigned(7 downto 0);
123 : in unsigned(1 downto 0);
14 : out unsigned(7 downto 0));
end lsi!t;
arcitecture arci o! lsi!t is
begin
wit 123 select
14 "# /0 wen $00$,
/0 sll 1 wen $01$,
/0 sll & wen $10$,
/0 sll 2 wen oters;
end arci;
3rith2etic &erations
1,4 s-&&orts the following arith2etic o&erations)

3dders with)
o $arry %n
o $arry -t
o $arry %n?-t

,-btractors

3dders?s-btractors

$o2&arators (:5 ?:5@5 @:5 A5 A:!

/-lti&liers

Di9iders
3dders5 ,-btractors5 $o2&arators and /-lti&liers are
s-&&orted for signed and -nsigned
o&erations.
Please refer to the ;,igned?0nsigned ,-&&ort; section of
this cha&ter for 2ore
infor2ation on the signed?-nsigned o&erations s-&&ort
in VHDL.
/oreo9er5 1,4 &erfor2s reso-rce sharing for adders5
s-btractors5 adders?s-btractors and
2-lti&liers.
3dders5 ,-btractors5 3dders?,-btractors
4his section &ro9ides HDL e6a2&les of adders and
s-btractors
0nsigned "-bit 3dder
4his s-bsection contains a VHDL and Verilog descri&tion
of an -nsigned "-bit 3dder
4he following table shows &in descri&tions for an
-nsigned "-bit 3dder.
% &ins
Descri&tion
3'=)*+5 7'=)*+3dd &erands
,0/'=)*+
3dd Bes-lt
VHDL
Following is the VHDL code for an -nsigned "-bit 3dder.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(5,6 : in std_logic_vector(7 downto 0);
178 : out std_logic_vector(7 downto 0));
end adder;
arcitecture arci o! adder is
begin
178 "# 5 9 6;
end arci;
0nsigned "-bit 3dder with $arry %n
4his section contains VHDL and Verilog descri&tions of
an -nsigned "-bit adder with
$arry %n.
4he following table shows &in descri&tions for an
-nsigned "-bit adder with carry.
% &ins
Descri&tion
3'=)*+5 7'=)*+3dd &erands
$%
$arry %n
,0/'=)*+
3dd Bes-lt
VHDL
Following is the VHDL code for an -nsigned "-bit adder
with carry in.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(5,6 : in std_logic_vector(7 downto 0);
:0: in std_logic;
178 : out std_logic_vector(7 downto 0));
end adder;
arcitecture arci o! adder is
begin
178 "# 5 9 6 9 :0;
end arci;
0nsigned "-bit 3dder with $arry -t
4he following table shows &in descri&tions for an
-nsigned "-bit adder with carry
% &ins
Descri&tion
3'=)*+5 7'=)*+3dd &erands
,0/'=)*+
3dd Bes-lt
$
$arry -t
VHDL
Following is the VHDL code for an -nsigned "-bit adder
with carry o-t.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arit.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(5,6 : in std_logic_vector(7 downto 0);178 : out
std_logic_vector(7 downto 0);:4: out std_logic);
end adder;
arcitecture arci o! adder is
signal t*p: std_logic_vector(; downto 0);
begin
t*p "# conv_std_logic_vector(
(conv_integer(5) 9
conv_integer(6)),<);
178 "# t*p(7 downto 0);
:4"# t*p(;);
end arci;
%n the &receding e6a2&le5 two arith2etic &ac<ages are
-sed)

stdClogicCarith. 4his &ac<age contains the integer to


stdClogic con9ersion
f-nction5 that is5 con9CstdClogicC9ector.

stdClogicC-nsigned. 4his &ac<age contains the -nsigned


;D; o&eration.
0nsigned "-bit 3dder with $arry %n and $arry -t
4his section contains VHDL and Verilog code for an
-nsigned "-bit adder with $arry %n
and $arry -t.
4he following table shows &in descri&tions for an
-nsigned "-bit adder with carry.
% &ins
Descri&tion
3'=)*+5 7'=)*+3dd &erands
$%
$arry %n
,0/'=)*+
3dd Bes-lt
$
$arry -t
VHDL
Following is the VHDL code for an -nsigned "-bit adder
with carry in and carry o-t.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arit.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(5,6 : in std_logic_vector(7 downto 0);
:0: in std_logic;
178 : out std_logic_vector(7 downto 0);
:4: out std_logic);
end adder;
arcitecture arci o! adder is
signal t*p: std_logic_vector(; downto 0);
begin
t*p "# conv_std_logic_vector(
(conv_integer(5) 9
conv_integer(6) 9
conv_integer(:0)),<);
178 "# t*p(7 downto 0);
:4"# t*p(;);
end arci;
,i2&le ,igned "-bit 3dder
4he following table shows &in descri&tions for a si2&le
signed "-bit adder.
% &ins
Descri&tion
3'=)*+5 7'=)*+3dd &erands
,0/'=)*+
3dd Bes-lt
VHDL
Following is the VHDL code for a si2&le signed "-bit
adder.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity adder is
port(5,6 : in std_logic_vector(7 downto 0);
178 : out std_logic_vector(7 downto 0));
end adder;
arcitecture arci o! adder is
begin
178 "# 5 9 6;
end arci;
0nsigned "-bit ,-btractor
4he following table shows &in descri&tions for an
-nsigned "-bit s-btractor.
% &ins
Descri&tion
3'=)*+5 7'=)*+,-b &erands
BE,'=)*+
,-b Bes-lt
VHDL
Following is the VHDL code for an -nsigned "-bit
s-btractor.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity subtr is
port(5,6 : in std_logic_vector(7 downto 0);
=21 : out std_logic_vector(7 downto 0));
end subtr;
arcitecture arci o! subtr is
begin
=21 "# 5 ( 6;
end arci;
0nsigned "-bit 3dder?,-btractor
4he following table shows &in descri&tions for an
-nsigned "-bit adder?s-btractor.
% &ins
Descri&tion
3'=)*+5 7'=)*+3dd?,-b &erands
PEB
3dd?,-b ,elect
,0/'=)*+
3dd?,-b Bes-lt
VHDL
Following is the VHDL code for an -nsigned "-bit
adder?s-btractor.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addsub is
port(5,6 : in std_logic_vector(7 downto 0);
4>2=: in std_logic;
=21 : out std_logic_vector(7 downto 0));
end addsub;
arcitecture arci o! addsub is
begin
=21 "# 5 9 6 wen 4>2=#%0%
else 5 ( 6;
end arci;
end*odule
$o2&arators (:5 ?:5@5 @:5 A5 A:!
4his section contains a VHDL and Verilog descri&tion for
an -nsigned "-bit greater or
e>-al co2&arator.
0nsigned "-bit Ereater or E>-al $o2&arator
4he following table shows &in descri&tions for a
co2&arator.
% &ins
Descri&tion
3'=)*+5 7'=)*+3dd?,-b &erands
$/P
$o2&arison Bes-lt
VHDL
Following is the VHDL code for an -nsigned "-bit greater
or e>-al co2&arator.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity co*par is
port(5,6 : in std_logic_vector(7 downto 0);
:8> : out std_logic);
end co*par;
arcitecture arci o! co*par is
begin
:8> "# %1% wen 5 -# 6
else %0%;
end arci;
/-lti&liers
Fhen i2&le2enting a 2-lti&lier5 the siGe of the
res-lting signal is e>-al to the s-2 of (o&erand lengths.
%f yo- 2-lti&ly 3 ("-bit signal! by 7 (.-bit signal!5 then
the siGe of theres-lt 2-st be declared as a 1(-bit signal.
0nsigned "6.-bit /-lti&lier
4his section contains VHDL and Verilog descri&tions of
an -nsigned "6.-bit 2-lti&lier.
4he following table shows &in descri&tions for an
-nsigned "6.-bit 2-lti&lier.
% &ins
Descri&tion
3'=)*+5 7'3)*+/0L4 &erands
BE,'=)*+
/0L4 Bes-lt
VHDL
Following is the VHDL code for an -nsigned "6.-bit
2-lti&lier.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity *ult is
port(5 : in std_logic_vector(7 downto 0);
6 : in std_logic_vector(& downto 0);
=21 : out std_logic_vector(11 downto 0));
end *ult;
arcitecture arci o! *ult is
begin
=21 "# 5 ? 6;
end arci;
Di9iders
Di9isions are only s-&&orted5 when the di9isor is a constant and
is a &ower of (. %n thatcase5 the o&erator is i2&le2ented as a
shifter# otherwise5 an error 2essage will be iss-edby 1,4.
Di9ision 7y $onstant (
4his section contains VHDL and Verilog descri&tions of a
Di9ision 7y $onstant (
di9ider.
4he following table shows &in descri&tions for a Di9ision
7y $onstant ( di9ider.
% &ins
Descri&tion
D%'=)*+ D%V &erands
D'=)*+ D%V Bes-lt
VHDL
Following is the VHDL code for a Di9ision 7y $onstant (
di9ider.
library ieee;
use ieee.std_logic_1164.all;
use ieee.nu*eric_std.all;
entity divider is
port(/0 : in unsigned(7 downto 0);
/4 : out unsigned(7 downto 0));
end divider;
arcitecture arci o! divider is
begin
/4 "# /0 @ 2;
end arci;
Beso-rce ,haring
4he goal of reso-rce sharing (also <nown as folding! is
to 2ini2iGe the n-2ber of
o&erators and the s-bse>-ent logic in the synthesiGed
design. 4his o&ti2iGation is based
on the &rinci&le that two si2ilar arith2etic reso-rces
2ay be i2&le2ented as one singlearith2etic o&erator if
they are ne9er -sed at the sa2e ti2e. 1,4 &erfor2s
both reso-rcesharing and5 if re>-ired5 red-ces of the
n-2ber of 2-lti&le6ers that are created in the&rocess.
1,4 s-&&orts reso-rce sharing for adders5 s-btractors5
adders?s-btractors and 2-lti&liers.
Belated $onstraint
4he related constraint isreso-rceCsharing.
E6a2&le
For the following VHDL?Verilog e6a2&le5 1,4 will gi9e
the following sol-tion)
4he following table shows &in descri&tions for the
e6a2&le.
% &ins
Descri&tion
3'=)*+5 7'=)*+5 7'=)*+D%V &erands
PEB
&eration ,elector
BE,'=)*+
Data -t&-t
VHDL
Following is the VHDL e6a2&le for reso-rce sharing.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adds-b is
port(5,6,: : in std_logic_vector(7 downto 0);
4>2=: in std_logic;
=21 : out std_logic_vector(7 downto 0));
end addsub;
arcitecture arci o! addsub is
begin
=21 "# 5 9 6 wen 4>2=#%0%
else 5 ( :;
end arci;
adder
306=5=A ieee ;
712
ieee.std_logic_1164.all ;
712
ieee.std_logic_arit.all ;
2BC0CA adder 01
>4=C(in1:
0B
std_logic_vector(1' /4DBC4 0) ;
in2:
0B
std_logic_vector(1' /4DBC4 0) ;
c_out:
47C
std_logic ;
su*:
47C
std_logic_vector(1' /4DBC4 0)
) ;
2B/ adder ;
5=:E0C2:C7=2 syntesiFable 4G adder 01
62H0B>=4:211(in1, in2)
I5=05632
t*p_in1:
signed(16 /4DBC4 0) ;
I5=05632
t*p_in2:
signed(16 /4DBC4 0) ;
I5=05632
output:
signed(16 /4DBC4 0) ;
I5=05632
c:
std_logic ;
62H0Bt*p_in1 :# signed(%0% J in1) ;
t*p_in2 :# signed(%0% J in2) ;
output :# t*p_in1 9 t*p_in2 ;
0G (output(16) # %1%) CE2B
c :# %1% ;
2312 c :# %0% ;
2B/ 0G ;
su* "# std_logic_vector(output(1' /4DBC4 0)) ;
c_out "# c ;
2B/ >=4:211 ;
2B/ syntesiFable ;
((counter
306=5=A ieee ;
712
ieee.std_logic_1164.all ;
712
ieee.std_logic_arit.all ;
2BC0CA counter 01
>4=C(clK:
0B
std_logic ;
input:
0B
std_logic_vector(11 /4DBC4 0) ;
output: 47C
std_logic_vector(11 /4DBC4 0) ;
ld:
0B
std_logic ;
inc:
0B
std_logic ;
clr:
0B
std_logic
) ;
2B/ counter ;
5=:E0C2:C7=2 beavioral 4G counter 01
62H0Bgeneric_counter: >=4:211(clK, input, ld, inc,
clr)
I5=05632t*pvar:unsigned(11 /4DBC4 0) ;
62H0B 0G (rising_edge(clK)) CE2B
0G (clr # %1%) CE2B
t*pvar :# (4CE2=1 #- %0%) ;
2310G (ld # %1%) CE2B
t*pvar :# unsigned(input) ;
2310G (inc # %1%) CE2B
t*pvar :# t*pvar 9 $000000000001$ ;
2B/ 0G ;
output "# std_logic_vector(t*pvar) ;
2B/ 0G ;
2B/ >=4:211 ;
2B/ beavioral ;
((
(( /esign a 2(bit count(down counter
((
306=5=A ieee ;
712
ieee.std_logic_1164.all ;
712
ieee.std_logic_arit.all ;
712
ieee.std_logic_signed.all ;
712
ieee.std_logic_unsigned.all ;
2BC0CA down_counter 01
>4=C(10HB53 +:
0B
std_logic ;
10HB53count :47Cstd_logic_vector(1 /4DBC4 0) ;
10HB53 reset:
0B
std_logic ;
10HB53 clK:
0B
std_logic
) ;
2B/ down_counter ;
5=:E0C2:C7=2 arc1 4G down_counter 01
62H0B
>=4:211(clK, +, reset)
I5=05632t*p_cnt:unsigned(1 /4DBC4 0) ;
62H0B
0G (reset # %1%) CE2B
t*p_cnt :# $00$ ;
2310G rising_edge(clK) CE2B
0G (+ # %1%) CE2B
t*p_cnt :# t*p_cnt ( $01$ ;
2B/ 0G ;
2B/ 0G ;
count "# std_logic_vector(t*p_cnt) ;
2B/ >=4:211 ;
2B/ arc1 ;
((
(( ; to & priority encoder
((
306=5=A
ieee ;
712
ieee.std_logic_1164.all ;
2BC0CA enc;to& 01
>4=C(10HB53 input:
0B
std_logic_vector(7 /4DBC4 0) ;
10HB53 output:47Cstd_logic_vector(2 /4DBC4 0)
) ;
2B/ enc;to& ;
((
(( Eere is a case were we really need te DE2B ( 2312
(( 0 don%t tinK te D0CE select will worK because
(( we want a priority encoder
((
5=:E0C2:C7=2 arc1 4G enc;to& 01
62H0B
output "# $111$ DE2B (input(7) # %1%) 2312$110$ DE2B
(input(6) # %1%) 2312$101$ DE2B (input(') # %1%)
2312$100$ DE2B (input(4) # %1%) 2312$011$ DE2B
(input(&) # %1%) 2312$010$ DE2B (input(2) # %1%)
2312$001$ DE2B (input(1) # %1%) 2312$000$ ;
2B/ arc1 ;
(( !a.vd
((
(( 5 1(bit !ull(adder
((
(( Heorge 3. 2ngel, 1072
((
306=5=A ieee ;
712
ieee.std_logic_1164.all ;
2BC0CA !a 01
>4=C( a, b : in std_logic ;
cin: in std_logic ;
cout : out std_logic ;
su*: out std_logic
) ;
2B/ !a ;
5=:E0C2:C7=2 arc1 4G !a 01
62H0B
su*"# (a )4= b) )4= cin ;
cout "# (a 5B/ b) 4= ((a 4= b) 5B/ cin) ;
2B/ arc1 ;
((=2H01C2=
306=5=A ieee ;
712
ieee.std_logic_1164.all ;
2BC0CA reg 01
>4=C(clK:
0B
std_logic ;
input:
0B
std_logic_vector(1' /4DBC4 0) ;
output: 47C
std_logic_vector(1' /4DBC4 0) ;
ld:
0B
std_logic
) ;
2B/ reg ;
5=:E0C2:C7=2 beavioral 4G reg 01
62H0Bgeneric_register: >=4:211(clK, input, ld)
62H0B 0G (rising_edge(clK)) CE2B
0G (ld # %1%) CE2B
output "# input ;
2B/ 0G ;
2B/ 0G ;
2B/ >=4:211 ;
2B/ beavioral ;
(((((((((((((((((((((((((((((((((((((((((((((
(( / Glip(Glop (21/ booK :apter 2.&.1)
(( by DeiLun .ang, 04@2001
((
(( Glip(!lop is te basic co*ponent in
(( seMuential logic design
(( we assign input signal to te output
(( at te clocK rising edge
(((((((((((((((((((((((((((((((((((((((((((((
library ieee ;
use ieee.std_logic_1164.all;
use worK.all;
(((((((((((((((((((((((((((((((((((((((((((((
entity d!! is
port(
data_in:
in std_logic;
clocK:
in std_logic;
data_out:out std_logic
);
end d!!;
((((((((((((((((((((((((((((((((((((((((((((((
arcitecture bev o! d!! is
beginprocess(data_in, clocK)
begin(( clocK rising edge
i! (clocK#%1% and clocK%event) ten
data_out "# data_in;
end i!;
end process;
end bev;
((((((((((((((((((((((((((((((((((((((((((((((
((((((((((((((((((((((((((((((((((((((((((((((
(( NO Glip(Glop wit reset
(( (21/ booK :apter 2.&.1)
(( by DeiLun .ang, 04@2001
((
(( te description o! NO Glip(Glop is based
(( on !unctional trut table
(( concurrent state*ent and signal assign*ent
(( are using in tis e+a*ple
((((((((((((((((((((((((((((((((((((((((((((((
library ieee;
use ieee.std_logic_1164.all;
((((((((((((((((((((((((((((((((((((((((((((((
entity NO_GG is
port (clocK:
in std_logic;
N, O:
in std_logic;
reset:
in std_logic;
P, Pbar:
out std_logic
);
end NO_GG;
(((((((((((((((((((((((((((((((((((((((((((((((
arcitecture bev o! NO_GG is
(( de!ine te use!ul signals ere
signal state: std_logic;
signal input: std_logic_vector(1 downto 0);
begin(( co*bine inputs into vector
input "# N J O;
p: process(clocK, reset) is
begin
i! (reset#%1%) ten
state "# %0%;
elsi! (rising_edge(clocK)) ten
(( co*pare to te trut table
case (input) is
wen $11$ #-
state "# not state;
wen $10$ #-
state "# %1%;
wen $01$ #-
state "# %0%;
wen oters #-
null;
end case;
end i!;
end process;
(( concurrent state*ents
P "# state;
Pbar "# not state;
end bev;
(((((((((((((((((((((((((((((((((((((((((((((((((
(((((((((((((((((((((((((((((((((((((((((((((((((((
(( n(bit =egister (21/ booK !igure 2.6)
(( by DeiLun .ang, 04@2001
((
(( O2A D4=/: concurrent, generic and range
(((((((((((((((((((((((((((((((((((((((((((((((((((
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
(((((((((((((((((((((((((((((((((((((((((((((((((((
entity reg is
generic(n: natural :#2);
port(
0:
in std_logic_vector(n(1 downto 0);
clocK:in std_logic;
load:
in std_logic;clear:in std_logic;P:
out std_logic_vector(n(1 downto 0)
);
end reg;
((((((((((((((((((((((((((((((((((((((((((((((((((((
arcitecture bev o! reg is
signal P_t*p: std_logic_vector(n(1 downto 0);
beginprocess(0, clocK, load, clear)
begin
i! clear # %0% ten
(( use %range in signal assig*ent
P_t*p "# (P_t*p%range #- %0%);
elsi! (clocK#%1% and clocK%event) ten
i! load # %1% ten
P_t*p "# 0;
end i!;
end i!;
end process;
(( concurrent state*ent
P "# P_t*p;
end bev;
(((((((((((((((((((((((((((((((((((((((((((((((((((
(((((((((((((((((((((((((((((((((((((((((((((((((((
(( &(bit 1i!t(=egister@1i!ter
(( (21/ booK !igure 2.6)
(( by DeiLun .ang, 04@2001
((
(( reset is ignored according to te !igure
(((((((((((((((((((((((((((((((((((((((((((((((((((
library ieee ;
use ieee.std_logic_1164.all;
(((((((((((((((((((((((((((((((((((((((((((((((((((
entity si!t_reg is
port(
0:
in std_logic;
clocK:
in std_logic;
si!t:
in std_logic;
P:
out std_logic
);
end si!t_reg;
arcitecture bev o! si!t_reg is
(( initialiFe te declared signal
signal 1: std_logic_vector(2 downto 0):#$111$;
beginprocess(0, clocK, si!t, 1)
begin
(( everyting appens upon te clocK canging
i! clocK%event and clocK#%1% ten
i! si!t # %1% ten
1 "# 0 J 1(2 downto 1);
end i!;
end i!;
end process;
(( concurrent assign*ent
P "# 1(0);
end bev;
((((((((((((((((((((((((((((((((((((((((((((((((((((
((((((((((((((((((((((((((((((((((((((((((((((((((((
(( IE/3 code !or n(bit counter (21/ !igure 2.6)
(( by DeiLun .ang, 04@2001
((
(( tis is te beavior description o! n(bit counter
(( anoter way can be used is G18 *odel.
((((((((((((((((((((((((((((((((((((((((((((((((((((
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
((((((((((((((((((((((((((((((((((((((((((((((((((((
entity counter is
generic(n: natural :#2);
port(
clocK:in std_logic;clear:in std_logic;count:in
std_logic;P:
out std_logic_vector(n(1 downto 0)
);
end counter;
((((((((((((((((((((((((((((((((((((((((((((((((((((
arcitecture bev o! counter is
signal >re_P: std_logic_vector(n(1 downto 0);
begin(( beavior describe te counter
process(clocK, count, clear)
begin
i! clear # %1% ten
>re_P "# >re_P ( >re_P;
elsi! (clocK#%1% and clocK%event) ten
i! count # %1% ten
>re_P "# >re_P 9 1;
end i!;
end i!;
end process;
(( concurrent assign*ent state*ent
P "# >re_P;
end bev;
(((((((((((((((((((((((((((((((((((((((((((((((((((((
IE/3 :ode !or 1i!t registers
"-bit ,hift-Left Begister with Positi9e-Edge $loc<5 ,erial
%n5 and ,erial
-t
8ote For this e6a2&le5 1,4 will infer ,BL1H.
4he following table shows &in definitions for an "-bit
shift-left register with a &ositi9e-
edge cloc<5 serial in5 and serial o-t.
% Pins Descri&tion
$
Positi9e-Edge $loc<
,%
,erial %n
,
,erial -t&-t
VHDL $ode
Following is the VHDL code for an "-bit shift-left register
with a &ositi9e-edge cloc<5
serial in5 and serial o-t.
library ieee;
use ieee.std_logic_1164.all;
entity si!t is
port(:, 10 : instd_logic;
14 : out std_logic);
end si!t;
arcitecture arci o! si!t is
signal t*p: std_logic_vector(7 downto 0);
begin
process (:)
begin
i! (:%event and :#%1%) ten
!or i in 0 to 6 loop
t*p(i91) "# t*p(i);
end loop;
t*p(0) "# 10;
end i!;
end process;
14 "# t*p(7);
end arci;
"-bit ,hift-Left Begister with 8egati9e-Edge $loc<5 $loc<
Enable5 ,erial
%n5 and ,erial -t
8ote For this e6a2&le5 1,4 will infer ,BL1HEC1.
4he following table shows &in definitions for an "-bit
shift-left register with a negati9e-
edge cloc<5 cloc< enable5 serial in5 and serial o-t.
% Pins Descri&tion
$
8egati9e-Edge $loc<
,%
,erial %n
$E
$loc< Enable (acti9e High!
,
,erial -t&-t
VHDL $ode
Following is the VHDL code for an "-bit shift-left register
with a negati9e-edge cloc<5
cloc< enable5 serial in5 and serial o-t.
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(:, 10, :2 : instd_logic;
14 : out std_logic);
end si!t;
arcitecture arci o! si!t is
signal t*p: std_logic_vector(7 downto 0);
begin
process (:)
begin
i! (:%event and :#%0%) ten
i! (:2#%1%) ten
!or i in 0 to 6 loop
t*p(i91) "# t*p(i);
end loop;
t*p(0) "# 10;
end i!;
end i!;
end process;
14 "# t*p(7);
end arci;
"-bit ,hift-Left Begister with Positi9e-Edge $loc<5
3synchrono-s $lear5
,erial %n5 and ,erial -t
8ote 7eca-se this e6a2&le incl-des an asynchrono-s
clear5 1,4 will not infer ,BL1H.
4he following table shows &in definitions for an "-bit
shift-left register with a &ositi9e-
edge cloc<5 asynchrono-s clear5 serial in5 and serial o-t.
% Pins Descri&tion
$
Positi9e-Edge $loc<
,%
,erial %n
$LB
3synchrono-s $lear (acti9e High!
,
,erial -t&-t
VHDL $ode
Following is the VHDL code for an "-bit shift-left register
with a &ositi9e-edge cloc<5
asynchrono-s clear5 serial in5 and serial o-t.
library ieee;
use ieee.std_logic_1164.all;
entity si!t is
port(:, 10, :3= : in std_logic;
14 : out std_logic);
end si!t;
arcitecture arci o! si!t is
signal t*p: std_logic_vector(7 downto 0);
begin
process (:, :3=)
begin
i! (:3=#%1%) ten
t*p "# (oters #- %0%);
elsi! (:%event and :#%1%) ten
t*p "# t*p(6 downto 0) J 10;
end i!;
end process;
14 "# t*p(7);
end arci;
"-bit ,hift-Left Begister with Positi9e-Edge $loc<5
,ynchrono-s ,et5 ,erial
%n5 and ,erial -t
8ote 7eca-se this e6a2&le incl-des an asynchrono-s
clear 1,4 will not infer ,BL1H.
4he following table shows &in definitions for an "-bit
shift-left register with a &ositi9e-
edge cloc<5 synchrono-s set5 serial in5 and serial o-t.
% Pins Descri&tion
$
Positi9e-Edge $loc<
,%
,erial %n
,
synchrono-s ,et (acti9e High!
,
,erial -t&-t
VHDL $ode
Following is the VHDL code for an "-bit shift-left register
with a &ositi9e-edge cloc<5
synchrono-s set5 serial in5 and serial o-t.
library ieee;
use ieee.std_logic_1164.all;
entity si!t is
port(:, 10, 1 : instd_logic;
14 : out std_logic);
end si!t;
arcitecture arci o! si!t is
signal t*p: std_logic_vector(7 downto 0);
begin
process (:, 1)
begin
i! (:%event and :#%1%) ten
i! (1#%1%) ten
t*p "# (oters #- %1%);
else
t*p "# t*p(6 downto 0) J 10;
end i!;
end i!;
end process;
14 "# t*p(7);
end arci;
"-bit ,hift-Left Begister with Positi9e-Edge $loc<5 ,erial
%n5 and Parallel
-t
8ote For this e6a2&le 1,4 will infer ,BL1H.
4he following table shows &in definitions for an "-bit
shift-left register with a &ositi9e-
edge cloc<5 serial in5 and serial o-t.
% Pins
Descri&tion
$
Positi9e-Edge $loc<
,%
,erial %n
P'=)*+ Parallel -t&-t
VHDL $ode
Following is the VHDL code for an "-bit shift-left register
with a &ositi9e-edge cloc<5
serial in5 and serial o-t.
library ieee;
use ieee.std_logic_1164.all;
entity si!t is
port(:, 10 : instd_logic;
>4 : out std_logic_vector(7 downto 0));
end si!t;
arcitecture arci o! si!t is
signal t*p: std_logic_vector(7 downto 0);
begin
process (:)
begin
i! (:%event and :#%1%) ten
t*p "# t*p(6 downto 0)J 10;
end i!;
end process;
>4 "# t*p;
end arci;
"-bit ,hift-Left Begister with Positi9e-Edge $loc<5
3synchrono-s Parallel
Load5 ,erial %n5 and ,erial -t
8ote For this e6a2&le 1,4 will infer ,BL1H.
4he following table shows &in definitions for an "-bit
shift-left register with a &ositi9e-
edge cloc<5 asynchrono-s &arallel load5 serial in5 and
serial o-t.
% Pins
Descri&tion
$
Positi9e-Edge $loc<
,%
,erial %n
3L3D3synchrono-s Parallel Load (acti9e High!
D'=)*+
Data %n&-t
,
,erial -t&-t
VHDL $ode
Following is VHDL code for an "-bit shift-left register
with a &ositi9e-edge cloc<5
asynchrono-s &arallel load5 serial in5 and serial o-t.
library ieee;
use ieee.std_logic_1164.all;
entity si!t is
port(:, 10, 5345/ : in std_logic;
/
: in std_logic_vector(7 downto 0);
14: out std_logic);
end si!t;
arcitecture arci o! si!t is
signal t*p: std_logic_vector(7 downto 0);
begin
process (:, 5345/, /)
begin
i! (5345/#%1%) ten
t*p "# /;
elsi! (:%event and :#%1%) ten
t*p "# t*p(6 downto 0) J 10;
end i!;
end process;
14 "# t*p(7);
end arci;
"-bit ,hift-Left Begister with Positi9e-Edge $loc<5
,ynchrono-s Parallel
Load5 ,erial %n5 and ,erial -t
8ote For this e6a2&le 1,4 will not infer ,BL1H.
4he following table shows &in definitions for an "-bit
shift-left register with a &ositi9e-
edge cloc<5 synchrono-s &arallel load5 serial in5 and
serial o-t.
% Pins
Descri&tion
$
Positi9e-Edge $loc<
,%
,erial %n
,L3D,ynchrono-s Parallel Load (acti9e High!
D'=)*+
Data %n&-t
,
,erial -t&-t
VHDL $ode
Following is the VHDL code for an "-bit shift-left register
with a &ositi9e-edge cloc<5
synchrono-s &arallel load5 serial in5 and serial o-t.
library ieee;
use ieee.std_logic_1164.all;
entity si!t is
port(:, 10, 1345/ : in std_logic;
/: in std_logic_vector(7 downto 0);
14 : out std_logic);
end si!t;
arcitecture arci o! si!t is
signal t*p: std_logic_vector(7 downto 0);
begin
process (:)
begin
i! (:%event and :#%1%) ten
i! (1345/#%1%) ten
t*p "# /;
else
t*p "# t*p(6 downto 0) J 10;
end i!;
end i!;
end process;
14 "# t*p(7);
end arci;
"-bit ,hift-Left?,hift-Bight Begister with Positi9e-Edge
$loc<5 ,erial %n5
and Parallel -t
8ote For this e6a2&le 1,4 will not infer ,BL1H.
4he following table shows &in definitions for an "-bit
shift-left?shift-right register with a
&ositi9e-edge cloc<5 serial in5 and serial o-t.
% Pins
Descri&tion
$
Positi9e-Edge $loc<
,%
,erial %n
LEF4CB%EH4Left?right shift 2ode selector
P'=)*+
Parallel -t&-t
VHDL $ode
Following is the VHDL code for an "-bit shift-left?shift-
right register with a &ositi9e-edge
cloc<5 serial in5 and serial o-t.
library ieee;
use ieee.std_logic_1164.all;
entity si!t is
port(:, 10, 32GC_=0HEC : in std_logic;
>4 : out std_logic_vector(7 downto 0));
end si!t;
arcitecture arci o! si!t is
signal t*p: std_logic_vector(7 downto 0);
begin
process (:)
begin
i! (:%event and :#%1%) ten
i! (32GC_=0HEC#%0%) ten
t*p "# t*p(6 downto 0) J 10;
else
t*p "# 10 J t*p(7 downto 1);
end i!;
end i!;
end process;
>4 "# t*p;
end arci;
$o-nters
.-bit 0nsigned 0& $o-nter with 3synchrono-s $lear
4he following table shows &in definitions for a .-bit
-nsigned -& co-nter with
asynchrono-s clear.
% Pins Descri&tion
$
Positi9e-Edge $loc<
$LB
3synchrono-s $lear (acti9e High!
I'3)*+ Data -t&-t
VHDL $ode
Following is VHDL code for a .-bit -nsigned -& co-nter
with asynchrono-s clear.
library ieee#
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(:, :3= : instd_logic;
P : out std_logic_vector(& downto 0));
end counter;
arcitecture arci o! counter is
signal t*p: std_logic_vector(& downto 0);
beginprocess (:, :3=)
begin
i! (:3=#%1%) ten
t*p "# $0000$;
elsi! (:%event and :#%1%) ten
t*p "# t*p 9 1;
end i!;
end process;
P "# t*p;
end arci;
.-bit 0nsigned Down $o-nter with ,ynchrono-s ,et
4he following table shows &in definitions for a .-bit
-nsigned down co-nter with
synchrono-s set.
% Pins Descri&tion
$
Positi9e-Edge $loc<
,
,ynchrono-s ,et (acti9e High!
I'3)*+ Data -t&-t
VHDL $ode
Following is the VHDL code for a .-bit -nsigned down
co-nter with synchrono-s set.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(:, 1 : instd_logic;
P : out std_logic_vector(& downto 0));
end counter;
arcitecture arci o! counter is
signal t*p: std_logic_vector(& downto 0);
begin
process (:)
begin
i! (:%event and :#%1%) ten
i! (1#%1%) ten
t*p "# $1111$;
else
t*p "# t*p ( 1;
end i!;
end i!;
end process;
P "# t*p;
end arci;
.-bit 0nsigned 0& $o-nter with 3synchrono-s Load fro2
Pri2ary %n&-t
4he following table shows &in definitions for a .-bit
-nsigned -& co-nter with
asynchrono-s load fro2 &ri2ary in&-t.
% Pins
Descri&tion
$
Positi9e-Edge $loc<
3L3D3synchrono-s Load (acti9e High!
D'3)*+
Data %n&-t
I'3)*+
Data -t&-t
VHDL $ode
Following is the VHDL code for a .-bit -nsigned -&
co-nter with asynchrono-s load
fro2 &ri2ary in&-t.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(:, 5345/ : instd_logic;
/ : in std_logic_vector(& downto 0);
P : out std_logic_vector(& downto 0));
end counter;
arcitecture arci o! counter is
signal t*p: std_logic_vector(& downto 0);
begin
process (:, 5345/, /)
begin
i! (5345/#%1%) ten
t*p "# /;
elsi! (:%event and :#%1%) ten
t*p "# t*p 9 1;
end i!;
end process;
P "# t*p;
end arci;
.-bit 0nsigned 0& $o-nter with ,ynchrono-s Load with a
$onstant
4he following table shows &in definitions for a .-bit
-nsigned -& co-nter with
synchrono-s load with a constant.
% Pins
Descri&tion
$
Positi9e-Edge $loc<
,L3D,ynchrono-s Load (acti9e High!
I'3)*+
Data -t&-t
VHDL $ode
Following is the VHDL code for a .-bit -nsigned -&
co-nter with synchrono-s load with
a constant.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(:, 1345/ : instd_logic;
P : out std_logic_vector(& downto 0));
end counter;
arcitecture arci o! counter is
signal t*p: std_logic_vector(& downto 0);
begin
process (:)
begin
i! (:%event and :#%1%) ten
i! (1345/#%1%) ten
t*p "# $1010$;
else
t*p "# t*p 9 1;
end i!;
end i!;
end process;
P "# t*p;
end arci;
.-bit 0nsigned 0& $o-nter with 3synchrono-s $lear and
$loc< Enable
4he following table shows &in definitions for a .-bit
-nsigned -& co-nter with
asynchrono-s clear and cloc< enable.
% Pins Descri&tion
$
Positi9e-Edge $loc<
$LB
3synchrono-s $lear (acti9e High!
$E
$loc< Enable
I'3)*+ Data -t&-t
VHDL $ode
Following is the VHDL code for a .-bit -nsigned -&
co-nter with asynchrono-s clear and
cloc< enable.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(:, :3=, :2 : in std_logic;
P : out std_logic_vector(& downto 0));
end counter;
arcitecture arci o! counter is
signal t*p: std_logic_vector(& downto 0);
begin
process (:, :3=)
begin
i! (:3=#%1%) ten
t*p "# $0000$;
elsi! (:%event and :#%1%) ten
i! (:2#%1%) ten
t*p "# t*p 9 1;
end i!;
end i!;
end process;
P "# t*p;
end arci;
.-bit 0nsigned 0&?Down co-nter with 3synchrono-s
$lear
4he following table shows &in definitions for a .-bit
-nsigned -&?down co-nter with
asynchrono-s clear.
% Pins
Descri&tion
$
Positi9e-Edge $loc<
$LB
3synchrono-s $lear (acti9e High!
0PCDF8-&?down co-nt 2ode selector
I'3)*+
Data -t&-t
VHDL $ode
Following is the VHDL code for a .-bit -nsigned -&?down
co-nter with asynchrono-s
clear.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(:, :3=, 7>_/4DB : in std_logic;
P : out std_logic_vector(& downto 0));
end counter;
arcitecture arci o! counter is
signal t*p: std_logic_vector(& downto 0);
begin
process (:, :3=)
begin
i! (:3=#%1%) ten
t*p "# $0000$;
elsi! (:%event and :#%1%) ten
i! (7>_/4DB#%1%) ten
t*p "# t*p 9 1;
else
t*p "# t*p ( 1;
end i!;
end i!;
end process;
P "# t*p;
end arci;
.-bit ,igned 0& $o-nter with 3synchrono-s Beset
4he following table shows &in definitions for a .-bit
signed -& co-nter with
asynchrono-s reset.
% Pins Descri&tion
$
Positi9e-Edge $loc<
$LB
3synchrono-s $lear (acti9e High!
I'3)*+ Data -t&-t
VHDL $ode
Following is the VHDL code for a .-bit signed -& co-nter
with asynchrono-s reset.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity counter is
port(:, :3= : instd_logic;
P : out std_logic_vector(& downto 0));
end counter;
arcitecture arci o! counter is
signal t*p: std_logic_vector(& downto 0);
begin
process (:, :3=)
begin
i! (:3=#%1%) ten
t*p "# $0000$;
elsi! (:%event and :#%1%)
ten
t*p "# t*p 9 1;
end i!;
end process;
P "# t*p;
end arci;
Begisters
Fli&-flo& with Positi9e-Edge $loc<
4he following fig-re shows a fli&-flo& with &ositi9e-edge
cloc<.
4he following table shows &in definitions for a fli&-flo&
with &ositi9e edge cloc<.
% Pins Descri&tion
D
Data %n&-t
$
Positi9e Edge $loc<
I
Data -t&-t
VHDL $ode
Following is the e>-i9alent VHDL code sa2&le for the
fli&-flo& with a &ositi9e-edge
cloc<.
library ieee;
use ieee.std_logic_1164.all;
entity !lop is
port(:, / : in std_logic;
P : out std_logic);
end !lop;
arcitecture arci o! !lop is
begin
process (:)
begin
i! (:%event and :#%1%) ten
P "# /;
end i!;
end process;
end arci;
Bote Den using IE/3, !or a positive(edge clocK
instead o! using
i! (:%event and :#%1%) ten
yo- can also -se
i! (rising_edge(:)) ten
and for a negati9e-edge cloc< yo- can -se
i! (!alling_edge(:)) ten
Fli&-flo& with 8egati9e-Edge $loc< and 3synchrono-s
$lear
4he following fig-re shows a fli&-flo& with negati9e-edge
cloc< and asynchrono-s clear.
4he following table shows &in definitions for a fli&-flo&
with negati9e edge cloc< and
asynchrono-s clear.
% Pins Descri&tion
D
Data %n&-t
$
8egati9e-Edge $loc<
$LB
3synchrono-s $lear (acti9e High!
I
Data -t&-t
VHDL $ode
Following is the e>-i9alent VHDL code for a fli&-flo& with
a negati9e-edge cloc< and
asynchrono-s clear.
library ieee;
use ieee.std_logic_1164.all;
entity !lop is
port(:, /, :3=
: in std_logic;
P
: out std_logic);
end !lop;
arcitecture arci o! !lop is
begin
process (:, :3=)
begin
i! (:3= # %1%)ten
P "# %0%;
elsi! (:%event and :#%0%)ten
P "# /;
end i!;
end process;
end arci;
Fli&-flo& with Positi9e-Edge $loc< and ,ynchrono-s ,et
4he following fig-re shows a fli&-flo& with &ositi9e-edge
cloc< and synchrono-s set.
4he following table shows &in definitions for a fli&-flo&
with &ositi9e edge cloc< and
synchrono-s set.
% Pins Descri&tion
D
Data %n&-t
$
Positi9e-Edge $loc<
,
,ynchrono-s ,et (acti9e High!
I
Data -t&-t
VHDL $ode
Following is the e>-i9alent VHDL code for the fli&-flo&
with a &ositi9e-edge cloc< and
synchrono-s set.
library ieee;
use ieee.std_logic_1164.all;
entity !lop is
port(:, /, 1
: instd_logic;
P
: out std_logic);
end !lop;
arcitecture arci o! !lop is
begin
process (:)
begin
i! (:%event and :#%1%) ten
i! (1#%1%) ten
P "# %1%;
else
P "# /;
end i!;
end i!;
end process;
end arci;
Fli&-flo& with Positi9e-Edge $loc< and $loc< Enable
4he following fig-re shows a fli&-flo& with &ositi9e-edge
cloc< and cloc< enable.
4he following table shows &in definitions for a fli&-flo&
with &ositi9e edge cloc< and
cloc< enable.
% Pins Descri&tion
D
Data %n&-t
$
Positi9e-Edge $loc<
$E
$loc< Enable (acti9e High!
I
Data -t&-t
VHDL $ode
Following is the e>-i9alent VHDL code for the fli&-flo&
with a &ositi9e-edge cloc< and
cloc< Enable.
library ieee;
use ieee.std_logic_1164.all;
entity !lop is
port(:, /, :2: instd_logic;
P
: out std_logic);
end !lop;
arcitecture arci o! !lop is
begin
process (:)
begin
i! (:%event and :#%1%) ten
i! (:2#%1%) ten
P "# /;
end i!;
end i!;
end process;
end arci;
.-bit Begister with Positi9e-Edge $loc<5 3synchrono-s
,et and $loc<
Enable
4he following fig-re shows a .-bit register with &ositi9e-
edge cloc<5 asynchrono-s set
and cloc< enable.
4he following table shows &in definitions for a .-bit
register with &ositi9e-edge cloc<5
asynchrono-s set and cloc< enable.
% Pins Descri&tion
D'3)*+ Data %n&-t
$
Positi9e-Edge $loc<
PBE
3synchrono-s ,et (acti9e High!
$E
$loc< Enable (acti9e High!
I'3)*+ Data -t&-t
VHDL $ode
Following is the e>-i9alent VHDL code for a .-bit
register with a &ositi9e-edge cloc<5
asynchrono-s set and cloc< enable.
library ieee;
use ieee.std_logic_1164.all;
entity !lop is
port(:, :2, >=2 : in std_logic;
/ : instd_logic_vector (& downto 0);
P : out std_logic_vector (& downto 0));
end !lop;
arcitecture arci o! !lop is
begin
process (:, >=2)
begin
i! (>=2#%1%) ten
P "# $1111$;
elsi! (:%event and :#%1%)ten
i! (:2#%1%) ten
P "# /;
end i!;
end i!;
end process;
end arci;
Latch with Positi9e Eate
4he following fig-re shows a latch with &ositi9e gate.
4he following table shows &in definitions for a latch with
&ositi9e gate.
% Pins Descri&tion
D
Data %n&-t
E
Positi9e Eate
I
Data -t&-t
VHDL Code
Following is the e>-i9alent VHDL code for a latch with a
&ositi9e gate.
library ieee;
use ieee.std_logic_1164.all;
entity latc is
port(H, / : instd_logic;
P
: out std_logic);
end latc;
arcitecture arci o! latc is
begin
process (H, /)
begin
i! (H#%1%) ten
P "# /;
end i!;
end process;
end arci;
3-7it 1-of-9 Priority Encoder
8ote For this e6a2&le 1,4 2ay infer a &riority encoder.
Jo- 2-st -se the
&riorityCe6tract constraint with a 9al-e force to force its
inference.
Belated $onstraint
3 related constraint is&riorityCe6t ract.
VHDL
Following is the VHDL code for a 3-bit 1-of-9 Priority
Encoder.
library ieee;
use ieee.std_logic_1164.all;
entity priority is
port ( sel : in std_logic_vector (7 downto 0);
code :out std_logic_vector (2 downto 0));
end priority;
arcitecture arci o! priority is
begin
code "# $000$ wen sel(0) # %1% else$001$ wen sel(1)
# %1% else$010$ wen sel(2) # %1% else$011$ wen
sel(&) # %1% else$100$ wen sel(4) # %1% else$101$
wen sel(') # %1% else$110$ wen sel(6) # %1%
else$111$ wen sel(7) # %1% else$((($;
end arci;
0nsigned "-bit Ereater or E>-al $o2&arator
4he following table shows &in descri&tions for a
co2&arator.
% &ins
Descri&tion
3'=)*+5 7'=)*+3dd?,-b &erands
$/P
$o2&arison Bes-lt
VHDL
Following is the VHDL code for an -nsigned "-bit greater
or e>-al co2&arator.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity co*par is
port(5,6 : in std_logic_vector(7 downto 0);
:8> : out std_logic);
end co*par;
arcitecture arci o! co*par is
begin
:8> "# %1% wen 5 -# 6
else %0%;
end arci;