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CHAPTER 3
ASMD based Design
3-1 Introduction to Design Partition
Algorithmic State Machine Design (ASMD)focuses on dividing design into two parts:
1- Control Logic (Control Unit)
2- Components that actually execute the Logic (Data Path)
Its Just like a small organization may work without any organizational structure but in larger organization
there are administrative people (Control Unit) who govern policies for working bodies and people who
actually execute the policies and formulations (Data Path).
Control Unit undergoes different states, each state issue commands to Data path which are executed as
per direction of Control Unit in the Data Path. Control Unit just think what are the control sequences and
do not know how the design will operate on data, Data Path gets the signals from Control Unit and dont
think what next, and execute the current control signals.
Figure 3-1: ASMD based Design Partitioning
Figure 3-1 gives the simplified view of Design Partitioning; generally speaking Data Path has Data and the
entire armory to perform operation on the data. The control unit is master mind; operations in Data Path
are control and commanded by Control Unit.
Its important to know that Control Unit dont have artificial intelligence to command operations, it goes
through predefine sequence of operations called states. State is defined as collection of Control Signals
Control Unit
Generates Control Signals
and decides what to do
Data Path
Gets Control Signal from
Control Unit and Execute the
job
Control
Signal
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performing Similar Job/Operations. The Control Unit Performs predefined operations based on state
machine containing States and control signals grouped into states. Each State Machine Design require
following steps to realize a practice design.
1- Draw a Block diagram of the System with all inputs, Outputs and their widths indicated.
2- Break the main block Diagram into Two Blocks Control Unit and Data path. All inputs are applied to
the control Unit and Outputs are taken from Data Path.
3- Start thinking on possible components required in data path, make blocks for each element in Data
path.
4- Put all data components together, and guess about possible signals required from the control Unit.
Rules for ASMD designs are following.
1- All inputs are given to the control Unit. Clock is given to Control Unit, in certain designs it may be
routed to Data Path as well.
2- Control Unit has State Machine which takes different states. Each State contains some control
signals which are issued to the Data Path if State is acquired.
3- State Transition is decided by condition boxes, which take decisions on inputs and Status Signal.
4- Data Path take Control Signals execute on the basis of control signals and generates Outputs and
Status Signals. These Status signals are returned to Control Unit for decision making process.
Figure 3-2: ASMD based Design Partition in Detail
Control Unit Data Path
Control
Signal
Status
Signal
inputs
Output s
Storage
Elements
Data
Clk
Clk
Control
Signal
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5- Data Path may have storage elements, however data fetching is controlled by control unit. Data Path
can only perform date saving or storage operations.
6- Data Signals are routed directly to Data Path while Control Unit hold their control Signals.
Figure 3-3 explains basic Flow of ASMD; Square block is used for state and all control signals are issued
in a certain states. The triangular box show the decision box and arrows indicate flow of logic.
Figure 3-3: Example of State Diagram
3-1-1: Writing Code in ASMD
Writing code for ASMD is very simple, it only requires to follow certain steps.
1- Define Constants for all the states.
2- Make State Register of ceil(Log
2
n) bits where n are number of states.
3- Make always block for State Transition
4- Make Always block for Signal Assignment
State-1
State-2
Decision
Control
signal
Control
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module CU_DesignName(------);
parameter State_1=2b00,State_2=2b01, State_3=2b10;//constants for States
reg [1:0]State_Reg;//State Register
always@(posedge clk)
//State Transition
always@(State_Reg)
//Signal Assignement
endmodule
3-2 Traffic Light Controller, Example of ASMD Driven Designs
As a simpler example of ASMD based designs lets start with traffic light controller. The design has Four
Roads each containing three signals Red, Green and Orange. Each signal opens turn on turn bases for 5
seconds and remains close 15 seconds.
Figure 3-4: Traffic Light System Scenario
3-2-1 Design Partitioning of the design :
The design in partition according to the figure 3-1, the data Path has only one counter which sends
Count_Flag equals 1 on every count of 5. This value is used by the Control Unit to Transact the State
from one Signal to other signal.
Sig_East Sig_West
Sig_South
Sig_North
West Boulevard East Boulevard
North Boulevard
South Boulevard
Sig_West Sig_East
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Each States change make Sel_East to North in Clock wise direction, the Sel Signals are passed to data path which
select 2 or 1 using multiplier to the Sig_East to Sig_North respectively. Each Sig_East to Sig_North are 2 bit signals.
Two bit means to make Red active we need to pass 2b10 i.e. 2 and to make Green Signal Active 2b01 is passed i.e.
1.
3-2-2 Data Path of TLC
The Data Path Contains Multiplexer controller by the control sig Sel_XXX. If a certain signal Sig_XXX is desired to be
turned Red Sel_XXX must be zero so that 2 is selected to the output otherwise if Sel_XXX is 1 the output Sig_XXX is
turned green. Just as an example consider Mux_East, if Sel_East is 0 Sig_East becomes 2 and this indicates Red as 2
in Binary is 2b10 means Make Red as 1 and Green as 0. If Sel_East is 1 then Sig_East becomes 1 and this indicates
2b01 means make red as zero and Green as 1. Data Path contains Counter which count from 0-5 and generates
Count_Flag equals 1 for one Clock Cycle this is latter used by Control Unit for State Transaction.
Figure 3-5: Design Partitioning of Traffic Light Controller
Figure 3-6: Data Path of Traffic Light Controller
Control Unit Data Path
Sel_East
Count_Flag
RST
Clk
Sel_West
Sel_North
Sel_South
Sig_East
Sig_West
Sig_North
Sig_South
Clk
Sel_East
Count_Flag
Sel_West
Sel_North
Sel_South
Sig_East
Sig_West
Sig_North
Sig_South
Clk
2
1
1 2 Mux_East
Mux_North
Mux_South
Mux_West
Counter
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3-2-3 ASMD of Control Unit
The ASMD is given 3-7 below , on every RST button press S_Rst is acquired. After one Clock Cycle the
S_West State is attained. The Count_Flag returns 1 after every count , which equals Counter counting 5.
On each Count_Flag State is transacted unit it reaches S_South, after this point S_West is again
acquired.
Figure 3-7: ASMD based design
S_RST
Sel_East->0; Sel_North->0
Sel_South->0; Sel_West->0
S_West
S_West->1; S_South->0
Count_Flag
S_North
S_North->1; S_West->0
Count_Flag
S_East
S_East->1; S_North->0
S_South
S_South->1; S_East->0
Count_Flag
Count_Flag
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Seeing State Diagram we can easily write code of State Transition and Signal Assignment as given in
Figure 3-8. The rules discussed in 3-1-1 are followed in this section and every ASMD based design will
follow these rules.
The code in Figure 3-9a describes the State transition with unconditional and Conditional State
Transition. While Figure 3-9b Show the Signal Assignment to each State.
module CU_TLC(input Clk, input Rst, input Count_Flag, output reg Sel_East , output reg Sel_West, output reg
Sel_North, output reg Sel_South);
parameter S_Rst=3'b100,S_East=3'b011,E_West=3'b010,S_North=3'b001,S_South=3'b000;//States Definition
reg [2:0]State_Reg;///State Register
always@(posedge Clk or negedge Rst)/////////State Transition
if(Rst==0)
State_Reg<=S_Rst;
else
case(State_Reg)
//State Transition here
endcase
always@(State_Reg)
case(State_Reg)
//Signal Assignment here
endcase
endmodule
Figure 3-8: ASMD based Control Unit, Signal Assignment
always@(posedge Clk or negedge Rst)/////////State Transition
if(Rst==0)
State_Reg<=S_Rst;
else
case(State_Reg)
S_Rst: State_Reg<=E_West;
E_West: if(Count_Flag==1)
State_Reg<=S_North;
else
State_Reg<=E_West;
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Figure 3-10 Shows the Wave form of the design:
1- Initially RST signal is applied and S_RST State is acquired. On this State All Signals are red.
2- Then Starting from West till South the signals are send States are acquired in Clock wise
direction.
3- The States are repeated on Cyclic Basis.
S_North: if(Count_Flag==1)
State_Reg<=S_East;
else
State_Reg<=S_North;
S_East: if(Count_Flag==1)
State_Reg<=S_East;
else
State_Reg<=S_South;
S_South:
if(Count_Flag==1)
State_Reg<=E_West;
else
State_Reg<=S_South;
endcase
endmodule
Figure 3-9a: ASMD based Control Unit, State Transition
always@(State_Reg)
case(State_Reg)
S_Rst: begin
Sel_East<=0; Sel_North<=0;
Sel_South<=0; Sel_West<=0;
end
E_West: begin
Sel_South<=0; Sel_West<=1;
end
S_North: begin
Sel_North<=1;Sel_West<=0;
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The waveform of the design is given below here 4 represents Reset State and So one So Forth.
3-2-4 Data Path of The Traffic Light Controller
Figure 3-11 presents the code of Data Path containing Multiplexers and Counters.
end
S_East: begin
S_East<=1;S_North<=0;
end
S_South:begin
S_South<=1;S_East<=0;
end
endcase
Figure 3-9b: ASMD based Control Unit, Signal Assignment
Figure 3-10: ASMD based Control Unit, Signal Assignment
module DP_TLC(input Clk,input Rst,output Count_Flag,input Sel_East,input Sel_West,input Sel_North,input
Sel_South,output reg Sig_East,output reg Sig_West,output reg Sig_North,output reg Sig_South);
wire [1:0]A1,A2; assign A1=2'b10; assign A2=2'b01;
DP_Mux MWest(.Mux_Sel(Sel_West),.Mux_in1(A1),.Mux_in2(A2),.Mux_Out(Sig_West));
DP_Mux MEast(.Mux_Sel(Sel_East),.Mux_in1(A1),.Mux_in2(A2),.Mux_Out(Sig_East));
DP_Mux MNorth(.Mux_Sel(Sel_North),.Mux_in1(A1),.Mux_in2(A2),.Mux_Out(Sig_North));
DP_Mux MSouth(.Mux_Sel(Sel_South),.Mux_in1(A1),.Mux_in2(A2),.Mux_Out(Sig_South));
DP_Counter C1(.Clk(Clk),.Rst(Rst),.Count_Flag(Count_Flag));
endmodule
Figure 3-11: Data path design
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The counter is given below which generates Count_Flag at every count of 5. This is latter passed to the
control unit on which state transactions are done.
In the Top Level module TLC (Traffic Light Controller) the Clock and Reset are routed to Data Path and
Control Unit. The Wires SE, SW, SN and SS connect the Control Signal of Control Unit to the Data path.
These Control Signals can control the Data Path as shown in Figure 3-13.
module TLC(input Rst,input Clk,output [1:0] Sig_East,output [1:0] Sig_West,output[1:0]
module DP_Counter(input Clk,input Rst,output reg Count_Flag);
reg [3:0]CReg;
always@(posedge Clk or negedge Rst)
if(Rst==0)
CReg<=4'b0000;
else
if(CReg==4'd4 | | CReg==4'd9 | | CReg==4'd14)
begin
Count_Flag<=1'b1;
CReg<=CReg+1;
end
else if(CReg==4'd15)
CReg<=4'd0;
else
begin
Count_Flag<=1'b0;
CReg<=CReg+1;
end
endmodule
Figure 3-12: ASMD based Control Unit, Signal Assignment
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Sig_North,output[1:0] Sig_South);
wire CF;
wire SE,SW,SN,SS;
CU_TLC
C1(.Clk(Clk),.Rst(Rst),.Count_Flag(CF),.Sel_East(SE),.Sel_West(SW),.Sel_North(SN),.Sel_South(SS));
DP_TLC
D1(.Clk(Clk),.Rst(Rst),.Count_Flag(CF),.Sel_East(SE),.Sel_West(SW),.Sel_North(SN),.Sel_South(SS),
.Sig_East(Sig_East),.Sig_West(Sig_West),.Sig_North(Sig_North),.Sig_South(Sig_South));
endmodule
Figure 3-13: Top Level Module and Its Simulation
Figure 3-14 describes full wave form of the design with Different States and Signals generated in these
states.
3-3 Counter for Traffic Light Controller, Example of ASMD Driven Designs
Section 3-2 is about Traffic light controller; each signal is opened for 5 Seconds and remains close for 15
Seconds. This section will cover counters which can be used to display time on each signal counting
down from 5 to zero for opened signal and 15 to zero for Close Signals. Figure 3-15 gives the modified
design requirement. This section will address the design of such counter however they will not be
integrated with the Traffic Light controller of Section 3-2 and is left for Reader in the End Problems.
Figure 3-14: Top Level Module and Its Simulation
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Figure 3-15: Traffic Light System Scenario
3-3-1 Self Aligned and Force Aligned Counters
There are two Classes of Counters Self Aligned Counters and Forced Aligned Counter. Both Types can be
Up or Down and Can have any wide. Self-Aligned Counters move automatically on each tickle of Clock,
they can be Reset in Asynchronous manner. The counters discussed so far are Self-Aligned Counters.
Figure 3-16a: Self Aligned Counters Figure 3-16b: Forced Aligned Counters
Sig_East Sig_West
Sig_South
Sig_North
West Boulevard East Boulevard
North Boulevard
South Boulevard
Sig_West Sig_East
C_North
C_West
C_East
C_South
Self-Aligned
Counters
RST
Clk
Forced Aligned
Counters
RST
Clk
LE
Data_in
Count
Count
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Forced aligned counters are specialized class of counters which can work in two modes, data loading
mode allow N-Bit data to be loaded in N-Bit Counter. In second mode the counter counts up/down form
the Data loaded and come back to the same number. Assume that we have 4-Bit down counter, in self-
aligned mode it will go from 15 to 0 and back to 15. However in forced aligned counter a value will be
loaded into counter which is suppose 10. In this case the counter will go from 10 to 0 and back to 10.
Similar understanding can be developed regarding up counter. To summarize the Forced aligned counter
restrict N-Bit counter to a certain point.
3-3-2 Counter for Traffic Light Controller and its design Partitioning
This section will address the problem posed in the start of section-3 using forced aligned counters
discussed in 3-3-1. The Problem is left to design a counter which can count from 15-0 once and then 5-0.
It is controlling Forced aligned counter in two states Long State (15-0) and Short State (5-0). After each
count down is completed Counter will generate a Status Flag to the Control Unit to tell that count is
completed so transact to the next State. The counter for Traffic Light Controller will look like Simple
Counter which receives Clock and RST Generate a count of 4.
TLC Counter
RST
Clk
Count
CU_TLCCounter DP_TLCCounter
Count
RST
Clk
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As per methodology of ASMD based design we will partition the design into two parts control Unit and
Data Path with all inputs applied to the Control Unit and all outputs taken from data Path. At this point
the control and Status Signals are not worked out.
The data path will require a Counter which is Forced Aligned Counter and it can be loaded with 15 and 5
as required by the State of the Control Unit. It also requires control Signal which enables/disables
counter. The counter in Figure 3-16b will work well in this case if a Status Signal CFlag is added to it,
CFlag will be asserted each time counter completes cycle and reaches zero.
The Control Unit will Load 15 into Forced Aligned Counter and Starts it in Long State, the Counter counts
15 to 0 and Asserts CFlag. The control Unit waits for CFlag to be one, it turns to short state where it
loads 5 into Forced aligned counter and Start it, the similar process is repeated as for Long State. The
Control Unit, data Path and their interconnections are shown in Figure 3-18.
3-3-3 Control Unit Design for TLC Counter
In the last section the design partitioning of Counter was done. It is known that counter does into two
states Short and Long State, we also require a State for Reset Signal S_RST. After S_Longor S_Short is
acquired we need Waiting state S_Wait which make LE as zero and counter will Tick. The state
Transition from S_RST to the S_Long is unconditional. The Change of State from S_Wait to S_Short and
S_Long however requires CFlag Signal to be one. To avoid confusion of next state after S_Wait a Turn
Figure 3-17: Counter for Traffic Light Controller
Figure 3-18: Counter for Traffic Light Controller
CU_TLCCounter
DP_TLCCounter
Count
RST
Clk
Clk
RST_Counter
LE
Data_In(4)
CFlag
4-Bit Forced
Aligned
Counter
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Flag T_Flag will be used. It will be zero when control goes from S_Long to S_Wait and one when it is
from S_Short to S_wait, as shown in Figure 3-19.
3-4 UART Transmitter
3-4-1 UART Basics
UART (Universal Asynchronous Receiver Transmitter) Performs serial communication between UART
and other components. UART takes a Byte of Data in Parallel form converts it into serial form and
includes Stop, Start and Parity Bits with the data. This data is transmitted over serial link. UART perform
all the task of Correct Data Transmission, Timing and Flow control. Most UARTs have Buffer to store
large bit of data before it is transmitted. Mostly UART are used in modems and for Non Networked
Communication.
The UART transmission is controlled by the Clock specially controlled with accordance to the Baud Rate.
The Host Sends the Data to the UART Transmitted and Asserts a signal to tell UART that data is ready.
The data is acquired by the UART data Buffer, and then send serially out.
Figure 3-19: TopLevel Module and Its Simulation
S_RST
S_Long
S_Wait
S_Short
LE->1 RST_Counter->0
Data_In->15 T_Flag->1
CFlag==1
RST_Counter->1
T_Flag==1
LE->0
LE->1 RST_Counter->0
Data_In->5 T_Flag->0
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Host send one byte of data in parallel for using Data_in and assert Data_Ready, this tells UART that data
is ready. This data is loaded into UART Register, and remains their until Data_Send is not asserted by the
host. The host asserts Data_Send to tell UART to send the data to the Serial_Out channel. This output is
received and reassembled by the UART Receiver. This is shown in Figure 3-20, the details of UART
Transmitted will be discussed in the next Section. The Frame of UART contain Start bit which is generally
zero, as the idle Serial link has one on it. The communication starts with UART sending 0 on the line to
tell that the communication has been started. Parity bit is send followed by 8-bit data is send on each
positive edge of the clock, to complete the communication 1-bit stop bit zero is send. The UART
communication Frame is shown in Figure 3-20.
3-4-2 UART Transmitter, Design Partitioning
Initially we will divide the design into control unit and data path. At this point we will not think about
what is inside Control Unit or Data Path.
Figure 3-20:Serial Communication: UART Transmitter and Receiver
D[0]
Start
D[1] D[2] D[3] D[4] D[5] D[6] D[7] Stop
Parity
UART_RX
RST
Clk
Data_In(8)
Data_Send
Data_Ready
Serial_Out
UART_TX
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Figure 3-21:UART Transmitter Design Partitioning
The Status signals and control signals can be figured out, if Data Path is thought first. Following must be
well planned about Data Path.
1- What can be possible components/blocks of data path.
2- What are IOs of these Blocks. And what are the functionality of theses blocks.
3- Which Signals of Blocks are outputs and which are Generating Status Signals.
3-4-3 UART Transmitter, Data Path Design
The data path components are placed together as a system and their I/Os are connected. This gives idea
of what can be possible signals from the control unit. The model in Figure 3-2 gives a good bird eye view
of the system design. The data path may have following components:
1- A register needed to buffer the data, this register can be Stack or a simple 8 bit Register. We will
use 8-Bit Register to simply the design.
DP_UART
Serial_Out
H
O
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T
CU_UART
UBusy
RST
Data_Ready
Data_Send
Data_In(8)
RST
Clk
Data_In(8)
Data_Send
Data_Ready
Serial_Out
UART_TX
UBusy
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2- A Counter which can count from 0 to 9 when to count how many bits are transmitted. When the
counter will complete its counting cycle this will ensure that Serial data has been transmitted.
3- A shift register which can shift the bit out one by on each transact of the Clock.
4- A parity calculator which generates one bit parity when the 8-bit data is given to it.
Once we are familiar with the possible modules of the data path, now think what can be the possible
I/Os of each block. The best way to do it is to drawn a block diagram of each component individually
without thinking about their interconnection or the system itself.
Table3-1:BrainStormingPossible Data Path Components
Data Register
Data input which may depends upon size of the
register
In our case the data size will be 8-bit. So 8-bit input
is required.
A signal which enables/disables data loading
operation. The similar signals can be used as
thinking it in read or write logic way
LD_Dreg in Figure 3-21has the similar signal.
Counter
Counter will count from 0-9 and raise the signal
once the Timer completes.
A signal to Reset the Counter and to Enable or
starts its operation.
A signal to Tell control Unit that count from 0-9 is
completed.
RST_Counter-To Reset the counter
CFlag-To inform Control unit that count of 0-9 is
completed.
Enable-Start the counting process.
Transmitter Register
Load Data and Parity from Data Register. The
Register add Start, Stop, Parity and Data into
Transmitter Register
A signal to Reset the Transmitter Register.
A Signal to Load Data and Parity from Data
Register.
Shift Register Signal which starts Shifting of Data
bit by bit out. It also triggers the counter to Start
counting.
RST_TXReg-Resets TX_Reg
Shift_TxReg-Shift the TX_Reg on Serial_Out with 1
inserted on Left side.
LD_TxReg-Loads data from Data Register and
Parity from Parity Module.
Once we know about possible components and their I/Os, we will draw block diagram of each
component and suggest writing their Verilog Codes.
3-4-4: Data Path Components
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The First Component we will design in this section is Counter. As discussed in table 3-1 Counter will
count from 0-9 and Raise a Flagging Signal CFlag to Reflects that Counting is completed. Counter will
only work if Enable Signal is asserted. The Module of Counter and its waveform is shown in Figure 3-22.
The Verilog Code for the module is given in Figure 3-23. It can be seen that the counter will only work if
Enable is one, if Count completes count of 10 it raises the CFlag Signal and restarts the Counter.
Figure 3-22: Counter Design for Data Path of UART Transmitter
Counter
Enable
RST
CLK
CFlag
Counter
Enable
RST
CLK
CFlag
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The Second Component we will discuss is Data Register; it is very simple module which can load data
when the LD_Dreg is asserted. Figure 3-24 Show the Data Register and its Verilog HDL Implementation
since it is combination it does not require any Clock Signal. The Reset can make the data register to load
with all zeros. Data_In and Data_Out are 8-Bit inputs which can be stored and retrieved into Data
Register.
module Counter(output reg CFlag,input Enable,input Clk,input Rst);
reg[3:0]Count_Reg;
always@(posedge Clk or posedge Rst)
if(Rst==1)
begin
Count_Reg<=0;
CFlag<=1'b0;
end
else
if(Enable==1) //if Enable is one
if(Count_Reg==4'd9) //if Counter Completes Cycle of 10 Counts
begin
Count_Reg<=4'd0;
CFlag<=1'b1;
end
else //if Counter is Still Counting Cycle of 10 Counts
begin
CFlag<=1'b0;
Count_Reg<=Count_Reg+1;
end
else ////if Enable is zero
begin
Count_Reg<=0;
CFlag<=1'b0;
end
endmodule
Figure 3-23: Coding Counter for UART Tx
Data
Register
LD_DReg
RST
Data_in
Data_Out
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Writing a Parity Module is very simple it requires Xor of all 8-Bit. Parity Module is a combination circuit
which XOR all the 8-Bits given at Data_in and generates even Parity Signal Parity_Out. Parity will not be
generator until ParityEnable is not asserted. Parity will be appended with the serial data and is used for
data error detection. The logic given in figure 3-25 generates even parity, if the output is inverted it can
be converted to odd parity circuit. Alternatively the coding can also be done in Gate level.
module Data_Reg(input [7:0] Data_In,input Ld_DReg,output [7:0] Data_Out, input Rst);
reg [7:0]DReg;
assign Data_Out=DReg;
always@(Data_In or Ld_DReg or Rst)
if(Rst==1)
DReg<=8'b0000_0000;
else
if(Ld_DReg==1)
DReg<=Data_In;
else
DReg<=DReg;
endmodule
Figure 3-24: Data Register for Data Path of UART Transmitter
Parity
Generator
Parity Enable
Data_in(8)
Parity_Out(1)
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To conclude the discussing we will end this section with design of most important component of Data
Path Called Transmitter Register. Transmitter register is a Shift register, it takes data from Data Register,
Parity from parity module and generates start and stop bits. The output of Transmitter register is Serial
Data. It has two control signals, LD_TxReg will load data from data register, parity from parity module
and makes the first location zero which will act as start bit. Each time shift operation is performed 1 is
inserted from the left which eventually fill the whole transmitter register with ones. This one when
reaches the first location of Register will act as stop bit.
Figure 3-26 Show the design of Transmitter Register and Figure 3-27 given the code for the required
design.
module ParityGenerator(output POut,input PEnable,input [7:0] Pin);
assign POut=PEnable?(Pin[0]^Pin[1]^Pin[2]^Pin[3]^Pin[4]^Pin[5]^Pin[6]^Pin[7]):1'b0;
endmodule
Figure 3-25: Parity Modulefor Data Path of UART Transmitter
Figure 3-26: Transmitter Register Modulefor Data Path of UART Transmitter
Transmitter
Register
RST
LD_TxReg
Parity_Out(1)
Shift_TxReg
Data_in(8)
Pin(1)
Clk
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3-4-5 Connecting Data Path Components and Figuring out Control Unit
As given in the last section the data path components are thought their block diagrams are drawn and
they are placed together to give one unified data path. This also figures out possible Control and Status
signals required by the control unit.
module TX_Reg(output Serial_Out,input LD_TXReg,input Shift_TXReg,input [7:0] Data_In,input Clk,input
RST,input Pin);
reg [9:0]SReg;
assign Serial_Out=SReg[0];
always@(posedge Clk or posedge RST)
if(RST==1)//////Make all Bits 1 at Reset
SReg<=10'd1023;
else
if(LD_TXReg==1)///if Load TX is 1
SReg<={Pin,Data_In,1'b0};
else if(Shift_TXReg==1)//if Shifting is 1
begin
SReg<=SReg>>1;
SReg[9]<=1'b1;
end
else //Other wise retain Register Value
SReg<=SReg;
endmodule
Figure 3-27: Verilog Code for Transmitter Register
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Figure 3-28: UART Transmitter Design Partitioning
Figure 3-28 gives the complete Picture of the System, UART Transmitter has three major components.
Baud Clock , Control Unit and Data Path. We will discuss baud clock in the latter section. All the
components discussed in last section are instantiated in Figure 3-29.
Once the Data path is glued together it exactly gives idea what control and status signals are required
for Control Unit.
moduleDP_UART(input RST_Counter,input RST_TxReg,input RST_DReg,input UBusy_In,output UBusy_Out,
output CFlag,input [7:0] Data_In,input LD_TxReg,input Shift_TxReg,input LD_DReg,output Shift_Out,input Clk);
assign UBusy_Out=UBusy_In;
wire WParity;
wire [7:0] WData;
ParityGenerator P1(.POut(WParity),.PEnable(LD_TxReg),.Pin(WData));
CounterC1(.CFlag(CFlag),.Enable(Shift_TxReg),.Clk(Clk),.Rst(RST_Counter));
Data_RegD1(.Data_In(Data_In),.Ld_DReg(LD_DReg),.Data_Out(WData),.Rst(RST_DReg));
TX_RegT1(.Serial_Out(Shift_Out),.LD_TXReg(LD_TxReg),.Shift_TXReg(Shift_TxReg),.Data_In(WData)
,.Clk(Clk),.RST(RST_TxReg),.Pin(WParity));
Endmodule
Figure 3-29: Data pathVerilogCode
RST_DReg
DP_UART
CLK BaudClock
Generator
BaudClock
Data_Reg(8 Bits)
TX_Reg
P
E
n
a
b
l
e
Serial_Out
H
O
S
T
UBusy
RST_TXReg
Parity
Generator
P
I
n
POut
LD_DReg
Shift_TxReg
LD_TxReg
Counter
RST_Counter
CFlag
Enable
RST
CU_UART
RST
Data_Ready
Data_Send
Data_In(8)
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3-4-6 Control Unit Design
Control Unit take two control Signal Data_Send and Data_Ready from the Host. Data_Ready tells Control
Unit that data is ready on the data bus while Data_Send is asserted when host want to transmit the data
stored in the buffer. CFlag is input returned from the Data Path, when counter completes its counting
process after sending all the data it send one at CFlag. Output signals are already discussed in Data Path
design.
Figure 3-30: UART Transmitter Block Level Diagram
RST
Clk
Data_Send
Data_Ready
CU_UART
CFlag
RST_Counter
RST_TxReg
RST_DReg
UBusy
LD_DReg
LD_TxReg
Shift_TxReg
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The backbone of Control unit is its ASMD, in this design it contains 6- States given in Figure 3-31.
1- After Reset button is pressed the design comes in S_Rst is acquired which make all modules in data
path with RST.
2- After this point it enters S_Waiting, where it waits for Valid data which is determined by Data_Ready.
3- Once Host sends valid data on data bus and send Data_Ready High, the design enters data Loading
State. And then wait for Data_Send signals to asserted.
4- The Transmission is done in Two States, First in S_PreTx, loading of TX Register is done.
5- S_Tx Register Start sending Data out Serially , it also start the counter. The ASMD of the design is
given in Figure 3-31.
Coding involve Similar logic as for Any ASMD based design Figure 3-32 a and b represents the Verilog
Coding for the design given in Figure 3-31.
Figure 3-31: ASMD of Control Unit
S_Rst
Rst_Counter=1'b1
Rst_TxReg=1'b1
Rst_DReg=1'b1
S_Waiting
Rst_Counter=1'b0
Rst_TxReg=1'b0
Rst_DReg=1'b0
LD_DReg=1'b0
S_DataLd
LD_DReg=1'b1
S_PreTx
UBusy=1'b1
LD_TxReg=1'b1
S_Tx
LD_TxReg=1'b0
Shift_TxReg=1'b1
S_PostTx
Shift_TxReg=1'b0
UBusy=1'b0
Rst_Counter=1'b1
Rst_TxReg=1'b1
Data_Ready
Data_Send
CFlag
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always@(posedge Clk or negedge Rst)
if(Rst==0)
State_Reg<=S_Rst;
else
case(State_Reg)
S_Rst:
State_Reg<=S_Waiting;//Reset State
S_Waiting:///Wait State
if(Data_Ready==1)
State_Reg<=S_DataLd;
else
if(Data_Send==1)
State_Reg<=S_PreTx;
else
State_Reg<=S_Waiting;
S_DataLd: //Data Loading State
State_Reg<=S_Waiting;
S_PreTx: ///Pre Transmitt State
State_Reg<=S_Tx;
S_Tx:///Transmitt State
if(CFlag==1)
State_Reg<=S_PostTx;
else
State_Reg<=S_Tx;
S_PostTx: //Post Transmitt State
State_Reg<=S_Waiting;
default:
State_Reg<=S_Rst;
endcase
always@(State_Reg)
case(State_Reg)
S_Rst:
begin
Rst_Counter<=1'b1;
Rst_TxReg<=1'b1;
Rst_DReg<=1'b1;
end
S_Waiting:
begin
Rst_Counter<=1'b0;
Rst_TxReg<=1'b0;
Rst_DReg<=1'b0;
LD_DReg<=1'b0;
end
S_DataLd:
begin
LD_DReg<=1'b1;
end
S_PreTx:
begin
UBusy<=1'b1;
LD_TxReg<=1'b1;
end
S_Tx:
begin
LD_TxReg<=1'b0;
Shift_TxReg<=1'b1;
end
S_PostTx:
begin
Shift_TxReg<=1'b0;
UBusy<=1'b0;
Rst_Counter<=1'b1;
Rst_TxReg<=1'b1;
end
endcase
Figure 3-32a: StateTransitionBehavioral Block Figure 3-32b: Signal Assignment Behavioral Block
3-4-7 Writing Top Level Module
This section will address top level module for the Whole design but before we really get into the
Complete design lets first go through baud rate generator. To Synchronize Transmitter and Receiver
Clocks and to exchange proper data rate RS 232 works on a certain Baud Rate and accordingly the clock
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Draft 2011 INSIDE DIGITAL DESIGN
Page83
is required to be slow down. To get the exact clock count divide the Clock Crystal Frequency by the
required baud rate and then divide the Whole term by 2.
Clock Count=((FPGA Clock)/Desired Baud)/2
The effect of Clock Divider is shown in Figure 3-33.
To put everything together we will write a Top Level Module
module BaudClockController(input Clk,output reg BaudClk);
integer i;
always@(posedge Clk)
if(i==20834) //1200 Baud rate
begin
BaudClk<=~BaudClk;
i<=0;
end
else
i<=i+1;
endmodule
Figure 3-33: Baud Rate Generator
module UART_TX(input RST,input Clk,input Data_Send,input Data_Ready,output Serial_Out,output
UBusy);
wire WCFlag,WLd_DReg,WLd_TxReg,WShift_TxReg,WBussy;
wire WRST_Counter,WRST_TxReg,WRST_DReg,WBClk;
reg [7:0]Data_In;
initial
begin
Data_In<=8'b1111_1110;
end
BaudClockController B1(.Clk(Clk),.BaudClk(WBClk));
CU_UARTC1(.Data_Ready(Data_Ready),.Data_Send(Data_Send),.Clk(WBClk),.CFlag(WCFlag),.Rst(RST),
.Shift_TxReg(WShift_TxReg),.LD_TxReg(WLd_TxReg),.LD_DReg(WLd_DReg),.UBusy(WBussy),
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Draft 2011 INSIDE DIGITAL DESIGN
Page84
Figure 3-35 show Transmitter Top Level Diagram and Its simulation.
Figure 3-35: UARTTransmitter Block Level Diagram
.Rst_Counter(WRST_Counter),.Rst_TxReg(WRST_TxReg),.Rst_DReg(WRST_DReg));
DP_UARTD1(.RST_Counter(WRST_Counter),.RST_TxReg(WRST_TxReg),.RST_DReg(WRST_DReg),
.UBusy_In(WBussy),.UBusy_Out(UBusy),.CFlag(WCFlag),.Data_In(Data_In),.LD_TxReg(WLd_TxReg),
.Shift_TxReg(WShift_TxReg),.LD_DReg(WLd_DReg),.Shift_Out(Serial_Out),.Clk(WBClk));
endmodule
Figure 3-34:Top Level Module
RST
Clk
Data_In(8)
Data_Send
Data_Ready
Serial_Out
UART_TX
UBusy
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