IJRDE MEPED 2014 Special Issue

International Journal for Research and Development in Engineering (IJRDE)
www.ijrde.com ISSN: 2279-0500 Special Issue: pp- 001-005

Methods Enriching Power and Energy Development (MEPED) 2014 1 | P a g e
Power Generation from the Light Energy Emitted From
the Fluorescent Lamps

N.Lakshmanan
1
, Sumit Kumar
2
, A. Saravanan
3

1,2
Final Year EEE, Dhaanish Ahmed College of Engineering, Chennai, Tamilnadu
3
HOD EEE, Dhaanish Ahmed College of Engineering, Chennai, Tamilnadu

ABSTRACT
The project based on the concept of
conservation of light energy from the House
Hold lamps such as Fluorescent Lamp, CFL,
Incandescent etc .The lamps are the essential
things that we have been using day to day life
.The Solar cells act as the light absorber which
will convert the light energy into the electrical
energy. We have been using more number of
lamps during night .So from that we can
generate more energy by interconnecting n-
number of lamps with the solar cells and store
this in a battery. The overall system design,
Hardware implementation and the performance
have been discussed in this paper.
Keywords: Voltage, Current, Power,
Illumination level, Depreciation Factor,
Utilization Factor
I. INTRODUCTION
This concept have been already worked using the
Infrared leds. The Led will also act as the light
absorber so it is able to generate electricity but the
power generated from this Led arrays on the tube
light are very less it is 12V , 21 A . This paper
has been presented in an International Conference
on Green Computing, Green communication and
Conservation of energy ICGCE 2013 and this is yet
to be published in IEEE Xplore Digital Library [1].
From the proceeding of conference work this paper
has been made. Here we worked on the Fluorescent
lamp with the small solar panel cells and
interconnected with each other in the tube light to
generate the bulk power .
The use of the lamps becomes the essential thing
in our day to day life. In all the places they use the
lamps; the number of lamp used will vary
depending upon the environment. The environment
such as Railway station, Class rooms, saw mills,
Ware house, Food Industry, Companies etc.
So we would be able to install this system in
any of the above applications and power generated
can be stored in the battery and that can be used to
feed to the loads whenever a power shut down
occurs. The overall system design and the work
proceeded have been discussed in this paper.
II. PROPOSED SYSTEM
A. Power Generated from the Single Fluorescent
Lamp using the Solar Cells:
The project work is started with working on the
single tube light. The Block Diagram of the
arrangement of single Tube light with solar panel
has been give below

Fig: 1 Block Diagram of the Single Fluorescent Lamp
with Solar panel
The system contains the Fluorescent lamp, Solar
panel, Voltage Regulator and the Battery unit. The
block diagram depicts the power generation on the
individual lamp. The light energy from the Tube
Light fall on the Solar cells which converts it into
the useful electrical energy. And that will be
regulated by the voltage regulator IC 7805 and then
stored in the battery [4].

The overall system design has been given below
describes about the placing the solar panels on the
Tube light. The panel support has been made above
the tube light support stand.

Fig 2: Hardware setup of single Fluorescent Lamp with
solar cells with two output terminals
The specification of the system components have
been given below
Table: 1 Technical Specification of Hardware Set up
COMPONENTS
NAME
RATINGS
Solar panel

Fluorescent
Lamp
4V , 100mA , Power = 0.4
W , Size = 64 cm
2

Power = 18 W
Lumens = 1015
Length = 60 cm
Colour Temperature =
6500 K

Fig 3: Voltage and Current Characteristics of the Single
Fluorescent Lamp with Solar cells
From the above graph it shows the variation of the
voltage and current with respect to the time. The
voltage is gradually varying between 3.67 V and
3.69 V. And the current is gradually varying
between 22 mA and 23 mA. The paper is worked
on with Tube light having the length 60 cm
generating 85 milli Watts and that has been used
for the small application but most of the places
people use the Fluorescent Tube light with length
114 cm generally. So we have been mathematically
calculated the power that can be generated from the
114 cm Fluorescent tube light .The power
generated is 170 milli Watts [4].
B.Power Generation from the Multiple Numbers of
Fluorescent Lamps and its Interconnection:
The latter section is dealing about the power
generation from the single Lamp. We can install
this system where multiple numbers of lamps have
been used and it is interconnected to generate more
power and that can be stored in the Battery bank.
From this we can feed to the Loads whenever we
need .The block diagram of multiple Fluorescent
lamp with solar cells is the same process flow in
the power generation from the single lamp
employed with solar cells.
The main factor is the interconnection of these
multiple number of lamps with each other. The
below Figure deals about interconnection of
multiple lamps
3.65 3.68 3.67 3.67 3.69 3.68 3.67 3.67
20.8
22.5 22.8 22.9 23 23.2 22.8 22.9
5.52
PM
5.55
PM
5.57
PM
6.11
PM
6.13
PM
6.17
PM
7.10
PM
8.30
PM
V I
CHARACTERISTICS
VOLTAGE ( Volts) CURRENT ( mA)


Fig: 4 Multiple Fluorescent Lamp with solar cells
Interconnection Diagram
The fig contains the interconnection diagram which
consists of the Fluorescent lamp with solar cells
symbol, Blocking Diode and the Bypass Diode
.The Role of the Blocking Diode is to prevent the
solar cells which will act as the load for the battery
when the system is at off condition. And the bypass
diode will be used to Bypass the power flow from
one Fluorescent lamp to another because all the
lamps will not be operating continuously. In some
applications depend on the need it will be used and
in some it may be used 247. When it is not
operating continuously at that instant when one of
the Lamps among the network is Off since is at the
series condition , it will make the circuit open this
will reduce the overall output in order to avoid that
the Bypass Diode will bypass the flow of electric
current to the terminals which avoid the circuit
Open . The ratings of the diodes will vary depend
the power ratings of the system such as voltage,
current. This concept is similar to the concept of
interconnection of PV panel in the PV array [2].
III. CALCULATION ON THE POWER CAN
BE GENERATED FROM THE MULTIPLE
LAMPS
The calculations have been made based on the
application of the system where it has been
installed. The various applications are defined in
this paper and also the various parameters are
considered while making these calculations. The
Lux value has been standardized for the various
applications such as School, Library, Ware House,
Company, Show Room etc [5]. Based on this lux
value the calculations have been made on the
amount of power can be generated from these real
time applications.
The table deals with the recommended lux values
in various places and referring the calculations
have been made on the amount power can be
generated in these places and this is purely depends
on the number of lamps used in the particular place
and this count will depend on the lux value
required, Area of the place to be illuminated,
Depreciation Factor of lamps and working
duration. This has been referred from the IES
Standards [5].
The calculation have been made by taking the Data
Sheet of the Philips Fluorescent tube light datasheet
number 36791-2 F17T8/TL835/ALTO [3] [5] .
Example Calculation based on the Philips
Datasheet
Depreciation Factor: 1.05 Utilization Factor:
0.95 Area to be illuminated: 50 m
2

Required Lux value: 200 lux
Lumens required: 50 200 = 10000 lumens
Actual Lumens: 100001.05/0.95 = 11053 lumens
Number Of tube Lights needed = Actual Lumens /
Lumens of Lamp= 11053 / 1400 =7.895 = 8
(approx)
Power can be generated =Number of lamps
power generated in single lamp
Power = 8 170 10
-3
= 1.36 Watts

Table: 2 Recommended Lux Value given by the
IES Standards

S.No

LEVEL

LUX

APPLICATION
1 Very low
illumination
Below
50 lux
Tanks , Entrance ,
Conveyors
2 Low
illumination
100 lux Transformer ,
Switch Gear ,
Bathrooms ,Bed
room , Corridors

3 Moderate
illumination
150 lux Lecture Hall ,
Hospital ,
Restaurant
4 High
illumination
- I
200 lux Libraries ,Kitchen
sinks , Press
,Machine Works
5 High
illumination
- II
300 lux General Office
work, Cash
Counters
6 Very High
illumination
700 lux Testing Room of
instruments ,
Soldering

In similar way we have been worked out on the
above table recommended lux value by assuming
the depreciation factor, utilization factor and area
to be illuminated.
Table: 3 Calculated Power can be Generated from
Various Applications

APPLICATIO
N

RECO
MMEN
DED
LUX

ILLUMIN
ATED
AREA

CALCUL
ATED
POWER
Transformer ,
Switch Gear

100 lux
370 m
2
4.39
Watts
Hospitals
150 lux
370 m
2
7.44
Watts
Libraries
200 lux
370 m
2
9.93
Watts
General Office
Work

300 lux
370 m
2
14.90
Watts

The graph shown below denotes the variation of
the power generated with respect to the Lux value
.The Graph is Linear and as the Lux value
increases the number of lamp used will also
increase such that the power generated can also
been increased .The Calculation is made by
referring the Illumination Engineering Principles.
The Calculated Power will be varied while
changing Lamp parameters.

Fig: 5 Variation Power generated with respect to Lux
value of various application
The Area of the place is also an important
parameter that will determine amount of power can
be generated in that particular place. The power
generated will increases when area to be
illuminated increases since number of lamps to be
installed increases. More power can be generated
when we place solar cells throughout the lamp. The
place of fluorescent on the solar panel will may
affect the Lux value receiving on the surface to be
illuminated so we designed the system in such a
way in order avoid the effect on the lux level
receiving on the surface. So that we placed solar
cells at the back of the Fluorescent Tube in order to
avoid the affect on the Lux value.
IV. CONCLUSION
The project have been analyzed with the single
Fluorescent Tube light and the result obtained is
discussed and its generating 170 milli Watts , this
is far enough to power the electronic items such as
Electronic motor , Buzzer , Led Array and
Charging the Low rated batteries . Using the
illumination engineering calculation techniques we
calculated the amount of power can be generated
from the various applications such as Substation,
Industries, Colleges and General Office. Future
scope of this project is to find out the power can be
generated from the different kinds of the lamps.
REFERENCES
[1] N.Lakshmanan ,Sumit Kumar, Generating
Electricity from the Tube lights for Charging
Battery Operated Electronics Items using
0
5
10
15
20
25
30
35
40
100 150 200 300
P
O
W
E
R

I
N

W
A
T
T
S
LUX
Power(
Watts)


Leds 978-1-4673-6126-2 IEEE Digital
Xplore Library( yet to published )
[2] Chetan Singh Solanki, Solar Photovoltaics
book
[3] Philips Advantage T12 Fluorescent Lamp
data sheet on the featuring, ALTO Lamp
Technology
[4] Kulshreshtha, Alok K, Basic Electrical
Engineering: Principles and Applications
India: Tata McGraw-Hill Education.
p. 801. ISBN 0-07-014100-2.
[5] IES standards for the Lightning Design for
the various applications.

Wind Energy Based Mobile Battery Charging and Battery
Applications
Saikumar.P
1,
Thamaraikannan.D
2
, Yuvaraj.G
3
, Yuvaraj.C
4
1,2,3
Student, B.E.Electrical and Electronics Engineering, Ganadipathy Tulsis Jain Engineering College, Vellore,
India.
4
Assistant Professor, Electrical and Electronics Engineering, Ganadipathy Tulsis Jain Engineering College,
Vellore, India.

ABSTRACT
In recent days power generation using
renewable energy sources gained more
attraction. The most commonly available and
used energy resources are solar and wind. The
objective presented here is charging of low
power electronic gadgets using the wind energy
available during travelling. A DC generator
with a Sepic converter provides voltage required
for charging the gadgets when the vehicle speed
exceeds 40km/hr. Even though the speed fall is
observed, the gadgets will get continuously
charged by the external battery source which is
connected to the proposed circuit. This could be
used as emergency source for charging
electronic gadgets while travelling in a vehicle.

Keywords: Battery, Charging Controller, DC
Motor, Sepic Converter, Voltage Regulator, Wind
Energy
I. INTRODUCTION
With the rapid industrialization development and
exploitation of natural resources. Many times
condition occurs which result in non charging of
our daily use gadgets and mobile. But this problem
can be tackled by using renewable energy
resources[1-5]Technologies like solar charger,
charging pins powered through automobile battery
and gadgets through hand operated dynamo
through a combination of many gears are used for
charging mobile phones .But a problem occurs
when there is no sunlight or the light is not in a
proper amount or when the automobile battery is not
in a condition to charge the other one and also the
use of hand operated gadget is very laborious work
and also not effective for long. In order to
overcome these types of problem, exploration has
been carried out with mobile phone and at present
we have come with a solution of maintaining
sustainability of energy stored in the phone battery
by Wind Driven Mobile Battery Charger [6-7].
This concept utilises wind generated electrical
energy to charge the mobile phones battery.

Figure 1: Block diagram of whole setup

The model consists of four main components that
are propeller, generator, chip integrated on PCB,
and mobile set suitable charging pin.
II. MATERIALS AND METHODS
A. Propeller
A propeller is a t y p e o f fan that
t r a n s m i t s p o we r b y converting rotational
motion into thrust. A pressure difference is
produced between the forward and rear surfaces of
the airfoil -shaped blade, and a fluid (such as air
or water) is accelerated behind the blade.
Propeller dynamics can be modeled b y b o t h
Bernoulli and Newtons t h i r d l a w . A
propeller is often colloquially known as screw.
The number of blades decides the rotational speed
of the propeller and differs with the pitch angle
and the angle between the blades. If the number
of blades is more the speed output is more and
thus give more output voltage and vice versa.
Normally the propeller is chosen according to the
type of application.

B. 12 volt D.C Generator
A simple D.C generator is preferred over the
A.C generator so as to avoid the use of rectifier
circuit and to make the circuit cheap and compact
and also to avoid extra cost. The main difference
in the A.C and D.C generator lies in the manner in

which the rotating coil is connected to the external
circuit connecting the load. In an A.C generator
both end of the coil is connected to the external
circuit via brushes. In this manner, the e.m.f
E
ext. in the
external circuit is always the same as
the emf E generated around the rotating coil. In a
D.C generator the two ends of the coil are
attached to the different halves of a single split
ring which co-rotates with the coil. The split ring
is connected to the external circuit by means of
metal brushes

The combination of split rings and the stationary
metal brushes is called a commutator. The purpose
of the commutator is to ensure that the emf E
ext.
In t h e external circuit is equal to the emf E
generated around the rotating coil for half the
rotating period, but is equal and opposite of
polarity of this emf for the other half. In the
special case as theoretical, the emf seen in the
external circuit is simply.
E
ext.
= E =E
max.
sin(2ft)
If Eext
.
Plotted as a function of time according to
the Formula. The variation of the voltage with
respect to time is Very similar to that of an A.C
generator, except that when the negative polarity
of an A.C generator is reversed to the positive
one by the commutator. So, as to avoid the use of
diodes in the A.C generator D.C generator is
preferred. So, as a result a bumpy direct emf which
rises and fall but never changes the direction is
achieved at the output terminals.

C. Charging Regulator Circuit
This is a combination of a 6v/22f capacitor.
I.C 7805, charging pin
6V/22f capacitor: The bypass capacitor is
hooked up at the output terminal of the DC
generator .The capacitor is there to filter out any
noise coming from the voltage source (the
generator). The voltage regulator I.C will work
best if a clean D.C is fed to it. To avoid any
A.C noise (ripple) imposed on the D.C line
voltage, the capacitor in essence act as a bypass
capacitor. It shorts the A.C signal of the voltage
signal (which is noise on the voltage signal) to
ground and only the D.C portion of the signal goes
to the regulator.
I.C 7805: I.C. 7805 voltage regulator employ built
in current limiting, thermal shutdown, and safe area
protection which make them virtually immune to
damage from output overload. With adequate heat
sinking it can deliver in excess of 0.5 A of current.
Typical application will include local regulators
which can eliminate the noise and degrade
performance associated with single point
regulation. As the most prominent voltage for
charging the mobile phones is 5 Volts. So, I.C
7805 is used as a regulator.
Battery: In ordinary mobile a 3.7 volts Li
+
battery
is used 3.70 Wh rating the battery when fully
charged shows the voltage of about 3.95 volt and
when discharged it shows 1.75volts.

Table1:Module Parameters

III. DESIGN AND ANALYSIS OF
SEPIC CONVERTER
In a single ended primary inductance converter
(SEPIC) design, the output voltage can be higher or
lower than the input voltage. The SEPIC converter
shown in Figure 2 uses two inductors: L1 and L2.
The two inductors can be wound on the same core
since the same voltages are applied to them
throughout the switching cycle.
S.No Module Specifications
1. Wind Driven Generator
Gen. voltage
(12V max.)
2. Wind Speed Range 40 kmph (min.)
3. Bypass Capacitor 6V/22f
4. Voltage Controller Ic 7805
5. Battery 3.7V,970mAh


Figure 2:Basic Sepic Topologyy
The basic wave form of the sepic converter has
been shown in the figure3.

Figure 3: Sepic converter switching waveforms (V
Q1
:
Q1 Drain to Source Voltage)
A. Design Parameters:

I. Duty Cycle Consideration:

For a SEPIC converter operating in a
continuous conduction mode (CCM), the
duty cycle is given by:

V V
V V V
1
V
D
is the forward voltage drop of the
diode D1. The maximum duty cycle is

V V
V V V
2
II. Inductor Selection:
A good rule for determining the
inductance is to allow the peak-to-peak ripple
current to be approximately 40% of the maximum
input current at the minimum input voltage. The
ripple current flowing in equal value inductors L1
and L2 is given by:
I I 40% I
V
Vi
40%
3
The inductor value is calculated by:
L1 L2 L
Vinmin
I fsw
D 4
f
sw
is the switching frequency and D
max
is the duty cycle at the minimum V
in
.
The peak current in the inductor, to
ensure the inductor does not saturate, is
given by:

I1 I
V V
V
1
40%
2

5
If L1 and L2 are wound on the same core, the
value of inductance in the equation above is
replaced by 2L due to mutual inductance. The
inductor value is calculated by:

L1
L2

L
2

V
2 I F
D 6

III. Power Mosfet selection:
The parameters governing the selection
of the MOSFET are the minimum threshold
voltage V
th(min)
, the on- resistance R
DS(ON)
,
gate-drain charge Q
GD
, and the maximum drain
to source voltage, V
DS(max)
. Logic level or
sublogic-level threshold MOSFETs should be
used based on the gate drive voltage. The peak
switch voltage is equal to Vin + Vout. The peak
switch current is given by:

I1 I1 I2 7

The RMS current through the switch is given by:
I1
I
Vout V V Vout VD
Vin

8



The MOSFET power dissipation PQ1 is
approximately:

P1 I1
R
V I1
Q F
9

P
Q1
, the total power dissipation for MOSFETs
includes conduction loss (as shown in the first
term of the above equation) and switching loss
as shown in the second term. I
G
is the gate
drive current. The R
DS(ON)
value should be
selected at maximum operating junction
temperature and is typically given in the
MOSFET data sheet. Ensure that the
conduction losses plus the switching losses do
not exceed the package ratings or exceed the
overall thermal budget.

IV. Output Diode Selection:

The output diode must be selected to
handle the peak current and the reverse voltage.
In a SEPIC, the diode peak current is the same
as the switch peak current I
Q1(peak)
. The
minimum peak reverse voltage the diode must
withstand is:

V1 V V 10

Similar to the boost converter, the average
diode current is equal to the output current.
The power dissipation of the diode is equal to
the output current multiplied by the forward
voltage drop of the diode. Schottky diodes are
recommended in order to minimize the
efficiency loss.

V. Sepic Converter Selection:

The selection of SEPIC capacitor, Cs,
depends on the RMS current, which is given by:

I I
V V
V
11
The SEPIC capacitor must be rated for a large
RMS current relative to the output power. This
property makes the SEPIC much better suited to
lower power applications where the RMS current
through the capacitor is relatively small (relative
to capacitor technology). The voltage rating of
the SEPIC capacitor must be greater than the
maximum input voltage. Tantalum and ceramic
capacitors are the best choice for SMT, having
high RMS current ratings relative to size.
Electrolytic capacitors work well for through-
hole applications where the size is not limited and
they can accommodate the required RMS current
rating.
The peak-to-peak ripple voltage on Cs (assuming
no ESR):
V
I D
C F
12
A capacitor that meets the RMS current
requirement would mostly produce small ripple
voltage on Cs. Hence, the peak voltage is typically
close to the input voltage.
I. Output Capacitor Selection:
In a SEPIC converter, when the power
switch Q1 is turned on, the inductor is charging and
the output current is supplied by the output
capacitor. As a result, the output capacitor sees
large ripple currents. Thus the selected output
capacitor must be capable of handling the
maximum RMS current. The RMS current in the
output capacitor is:

I I
V V
V
13
The ESR, ESL, and the bulk capacitance of
the output capacitor directly control the
output ripple. Assume half of the ripple is
caused by the ESR and the other half is
caused by the amount of capacitance. Hence,

ESR
V 0.5
IL1 IL2
14

Cout
I
V 0.5 F
15

www.ijrde.com

Methods Enriching Power and Energy Development
The output cap must meet the RMS
ESR and capacitance requirements. In
mount applications, tantalum, polymer
electrolytic, and polymer tantalum, or
layer ceramic capacitors are recommended
the output.

II. Input Capacitor Selection

Similar to a boost converter,
has an inductor at the input. Hence,
current waveform is continuous and
The inductor ensures that the input capacitor
fairly low ripple currents. The RMS current
input capacitor is given by:

IC
I
12
16
The input capacitor should be capable
the RMS current. Although the input
not so critical in a SEPIC application,
higher value, good quality capacitor would
impedance interactions with the input supply.

IV. EXPERIMENTAL RESULTS
Proposed Block Diagram of Wind Energybased
mobile battery charging and battery applications
Figure 4: Block diagram for proposed converter
Proposed Circuit of Sepic Converter is shown in
figure 4. A fixed voltage is boosted to a voltage
level necessary to charge a battery. It is boosted
with the design parameters and simulated using the
matlab. The output voltage and the current
waveforms are shown in the figure 4.1 and 4.2
respectively.
ISSN: 2279-0500 Special Iss
Methods Enriching Power and Energy Development (MEPED) 2014
current,
surface
polymer
or multi-
are recommended at
the SEPIC
Hence, the input
triangular.
capacitor sees
current in the

capable of handling
capacitor is
application, a 10 F or
would prevent
supply.
EXPERIMENTAL RESULTS
Proposed Block Diagram of Wind Energybased
mobile battery charging and battery applications
diagram for proposed converter
Proposed Circuit of Sepic Converter is shown in
figure 4. A fixed voltage is boosted to a voltage
level necessary to charge a battery. It is boosted
with the design parameters and simulated using the
voltage and the current
waveforms are shown in the figure 4.1 and 4.2

Figure 4.1 Circuit diagram for proposed converter
Figure 4.2 Input Voltage Waveform
Figure 4.3 Switching Pulse for Mosfet
sue: pp- 006-011
10 | P a g e
Circuit diagram for proposed converter
Input Voltage Waveform
Switching Pulse for Mosfet

Figure 4.4 Output Voltage Waveform
Figure 4.5 Output Current Waveform
V. CONCLUSION
In this a wind battery charger has been investigated
to charge the mobile phone or battery while
travelling .This technology can help to meet the
emergency power requirement when grid electricity
is not available. The wind driven mobile charger is
also portable, cost-effective and energy efficient
.By further suitable modifications, the system could
be used to charge gadgets for daily use. In the
Future work charging of laptop and high power
gadgets will be accomplished.

REFERENCES
[1] S.N. Singh ,Sumit Kumar Jha, Sudhir Kumar
Sinha, 2011, Wind driven mobile charging of
automobile battery International Journal of
Engineering Science and Technology (IJEST) :
(3):1:68-74,
[2] Daniel S. A.and Gaunden,N.A. 2001, A stand
alone integrated array wind turbine gen and
photovoltaic-array in feed-forward controlled
PWM inverter, Proceedings of the
International Conference on energy, automation
and information Technology(EAIT 2001), Indian
Institute of Technology, Kharagpur, India, pp. 667-
670.
[3] Eltamaly, A. M. 2005 Modelling of wind
turbine driving permanent magnet generator with
maximum power point tracking system,
Proceeding of 2nd MInia International conference
for advance Trends in Engg (MICATE2005),
Elminia, Egypt.
[4] Muljadi, E., Piercek, K.and Migliore,P. 1998
Control strategy for variable speed Stall regulated
wind turbines , National Renewable Energy
Laboratory 1617 Cole Boulevard Golden,
Colorado 80401-3393.
[5] Rizk, J. and Nagriak, M.H..2010 Design of
permanent magnet generator for wind energy
application, Power Electronics, Machines and
Drives (PEMD2010) 5th IET International
Conference, Australia.
[6] AN-1484 Designing A SEPIC
Converter(SNVA168EMay 2006-Revised April
2013) by Dongbing Zhang from texas Instruments.
[7] A Novel Design of wind driven mobile battery
charger by K.Sudhakar & Priyanka Saxena,
International Journal of Science, Engineering and
Technology Research (IJSETR),March 2013.



Design and Implementation of Maximum Power Point Tracking
For Super Lift Converter

Indu V. R
1
; V. Chamundeeswari
2

1,2
Department of EEE, St. Josephs college of engineering, Chennai, India

ABSTRACT
Photovoltaic (PV) is a technical name in which radiant
(photon) energy from the sun is converted to direct
current (dc) Electrical Energy. PV power output is still
low, continuous efforts are taken to develop the PV
converter and controller for maximum power extracting
efficiency and reduced cost factor. The maximum power
point tracking (MPPT) is a process which tracks one
maximum power point from array input, varying the
ratio between the voltage and current delivered to get
the most power it can. A number of algorithms have
been developed for extracting maximum power. This
paper details the study of incremental conductance
MPPT algorithm with the help of a negative output luo
converter.

Keywords- PV Module, MPPT, Incremental
Conductance (IC) Algorithm, luo converter.

I. INTRODUCTION

Solar Energy is the ultimate source of energy, which is
naturally replenished in a short time period of time, for this
reason it is called Renewable Energy or Sustainable
Energy. Due to the severity of the global energy crisis and
environmental pollution, the photovoltaic (PV) system has
become one kind of important renewable energy source.
Solar energy has the advantages of maximum reserve,
inexhaustibleness, and is free from geographical
restrictions, thus making PV technology a popular research
topic. The efficiency of solar cells depends on many factors
such as temperature, insolation, spectral characteristics of
sunlight, dirt, shadow, and so on. Changes in insolation on
panels due to fast climatic changes such as cloudy weather
and increase in ambient temperature can reduce the
photovoltaic (PV) array output power. In
addressing the poor efficiency of PV systems, some
methods is proposed, among which is a new concept called
maximum power point tracking (MPPT). All MPPT
methods follow the same goal which is maximizing the PV
array output power by tracking the maximum power on
every operating condition. In this paper we use incremental
conductance algorithm for precise control under rapidly
changing atmospheric conditions.

II. PV CELL MODELING
A PV module consists of number of solar cells connected in
series and parallel to obtain desired voltage and current.
Each solar cell is basically a p-n diode. As sunlight strikes a
solar cell, the incident energy is converted directly into
electrical energy without any mechanical effort.
Transmitted light is absorbed within the semiconductor by
using its energy to excite free electrons from a low energy
status to an unoccupied higher energy level [6]. When a
solar cell is illuminated, excess electron hole pairs are
generated by light throughout the material, hence the p-n
junction is electrically shorted and current will flow. The
equivalent circuit of a PV cell is as shown in Figure1.

Figure1. PV cell modeled as diode circuit

The current source represents the cell photo current. Rsh
and Rs are the intrinsic shunt and series resistance of the
cell respectively. Usually the value of Rsh is very large and
that of Rs is very small.Equations of PV Module The


photovoltaic module can be modeled mathematically as
given in equations shown below.
Module photo current:
Iph = [Isc + Ki (Tk - Tref)] * / 1000. (1)
Module reverse saturation current:
Irs = Iscr/[exp( qV / N kAT ) .1] (2)
The module saturation current Io varies with the cell
temperature, which is given by
Io = Irs(T/Tr )^3 exp((qEg/KA)*(1/Tr-1/T)) (3)
The current output of PV module is :
Ipv=Iph- Is*[exp{q(V pv +IpvRs)/Ns AKT}-1] (4)
Where Vpv=Voc. Here we consider 36 series connected Pv
cells

Figure 2 Simulink model

PV system naturally exhibits a nonlinear I-V and P-V
characteristics which vary with the radiant intensity and cell
temperature. The typical I-V and P-V characteristics of
solar cell are shown in figure 3& figure4.

Figure 3 I-V characteristics of PV panel.

Figure 4 P-V characteristic

III. MPPT
MPPT algorithms are necessary in PV applications because
the MPP of a solar panel varies with the irradiation and
temperature, so the use of MPPT algorithms is required in
order to obtain the maximum power from a solar array.
Over the past decades many methods to find the MPP have
been developed and published. These techniques differ in
many aspects such as required sensors, complexity, cost,
range of effectiveness, convergence speed, correct tracking
when irradiation and or temperature change, hardware
needed for the implementation or popularity [1]. Among
these techniques, the P&O and the Incremental
Conductance algorithms are the most common. These
techniques have the advantage of an easy implementation.
Other techniques based on different principles are fuzzy
logic control, neural network, and fractional open circuit
voltage or short circuit current etc .Among different


algorithms, Incremental Conductance method is used here.
In this method, the array terminal voltage is always adjusted
according to the MPP voltage. It is based on the
incremental and instantaneous conductance of the PV
module figure given below shows that the slope of the PV
array power curve is zero at the MPP, increasing on the left
of the MPP and decreasing on the right-hand side of the
MPPT .The basic equations of this method are as follows
dI/dV= - I/V, at MPP (5)
dI/dV> I/V, left of MPP (6)
dI/dV< I/V, right of MPP (7)
Where, I and V are the PV array output current and voltage
respectively. The left-hand side of the equations represents
the Incremental conductance of the PV module, and the
right-hand side represents the instantaneous conductance.
From (5)(7), it is obvious that when the ratio of change in
the output conductance is equal to the negative output
conductance, the solar array will operate at the MPP. In
other words, by comparing the conductance at each
sampling time, the MPPT will track the maximum power of
the PV module. The accuracy of this method is proven,
where it mentions that the Incremental conductance method
can track the true MPPs independent of PV array
characteristics. The efficiency was observed to be as much
as 98.2%, but it is some modifications and reformations
were proposed on this method so far, but since this method
inherently has a good efficiency, the aforementioned
amendments increase the complexity and cost of the system
and there was no remarkable change in system efficiency.
In this paper, control action is done using a microcontroller.
It generates pulse width modulation (PWM) waveform to
control the duty cycle of the converter switch according to
the Incremental conductance algorithm. Flow chart for the
incremental conductance is given below.

Figure 5. Incremental conductance algorithms

IV. CONVERTER
Luo converters were developed from the prototypes using
VL technique. These converters perform DC-DC voltage
increasing conversion with high power density, high
efficiency, and cheap topology in simple structure. They are
different from any other DC-DC step up converters and
possess many advantages including a high output voltage
with small ripples. Therefore, these converters are widely
used in computer peripheral equipment and industrial
applications, especially for high output voltage projects.
This paper introduces negative output super lift technique
that implements the output voltage increasing in stage by
stage along the geometric progression. Equation (8) shows
the input output relationship of luo converter
Vo = Vin/(1-k) (8)
The NOESLLC provides high voltage transfer gain using
Super-lift technique Its topology differs from the
conventional circuit as it uses additional capacitor in
parallel with the load boosting the output voltage. The


linkage between input and output is alleviated which
degrades the output voltage. The above figure shows the
circuit diagram of NOESLLC. It consists of a power switch
MOSFET M1, Inductor L1, Resistor R1, Diodes D1, D2,
Capacitor C1, C2 and load resistance.

Figure 6 negative output luo converter
MODE1
When the switch is closed during the duty interval 0 to T,
the supply voltage increases the current through the
inductor L1 and the capacitor C1 gets charged. The load
current is maintained constant by the discharge of the
capacitor C2 during this period

Figure 7 mode 1 representation
MODE 2
During the duty interval T to T the switch is closed where
the stored charges in the inductor supplies the load current
and the capacitor C1 and C2 produces the boosted voltage
across the load

Figure 8 mode 2 representations
V. SIMULATION RESULTS
The simulation system consists of PV module; negative
output luo converter circuit and MPPT control block as
shown in the figure (9).

Figure 9 simulation system

Output power available at the output of the system without
MPPT is given in figure 10. By using incremental
conductance algorithm, PV panels working point is shifted
to the MPP and power output is increased.

Figure 10 PV output power without MPPT


Figure 11 Output power with MPPT.

VI. CONCLUSION
This paper presents the design and simulation for maximum
power point tracking (MPPT) for photovoltaic system,
which includes a high-efficiency luo converter with
incremental conductance algorithm. The converter can draw
maximum power from the PV panel for a given solar
insolation and temperature by adjusting the duty cycle of
the converter.

REFERENCES
[1] Azadeh Safari And Saadmekhilef, Member, IEEE, (2011)
Simulation And Hardware Implementation Of Incremental
Conductance Mppt With Direct Control Method Using Cuk
Converter IEEE Transactions On Industrial Electronics, Vol. 58,
No. 4, April 2011
[2] S. Nema, R.K.Nema, and G.Agnihotri, Matlab / simulink
based study of photovoltaic cells / modules / array and their
experimental verification, International Journal of Energy and
Environment, pp.487-500, Volume 1, Issue 3, 2010.
[3] N. Femia, D. Granozio, G. Petrone, G. Spagnuolo, andM.
Vitelli, Predictive & adaptive MPPT perturb and observe
method, IEEE Trans. Aerosp.Electron. Syst., vol. 43, no. 3, pp.
934950, Jul. 2007.
[4] E. Koutroulis, K. Kalaitzakis, and N. C. Voulgaris,
Development of a microcontroller-based, photovoltaic maximum
power point tracking controlsystem, IEEE Trans. Power
Electron., vol. 16, no. 1, pp. 4654,Jan. 2001.
[5] S. Jain and V. Agarwal, A new algorithm for rapid tracking of
approximate maximum power point in photovoltaic systems,
IEEE PowerElectron. Lett., vol. 2, no. 1, pp. 1619, Mar. 2004.
[6] S.Chowdhury, S.P.Chowdhury, G.A.Taylor, and Y.H.Song,
Mathematical Modeling and Performance Evaluation of a Stand-
Alone Polycrystalline PV Plant with MPPT Facility, IEEE Power
and Energy Society General Meeting -Conversion and Delivery of
Electrical Energy in the 21st Century, July 20-24, 2008, Pittsburg,
USA.
www.ijrde.com ISSN: 2279-0500 Special Issue: pp-017-019


Energy Harvesting Using Oscillating Pendulum
S.Nithiya
1
, K.Sadhuna
2
, A. Saravanan
3

1,2
Final Year EEE, Dhaanish Ahmed College of Engineering, Chennai, Tamilnadu

3
HOD EEE, Dhaanish Ahmed College of Engineering, Chennai, Tamilnadu

ABSTRACT
There is abundance of mechanical energy that can be
harvested and recycled from our living environment.
Here we developed a pendulum motion based power
generator that sustains its motion with low
maintenance providing voltage output peaks from a
reciprocating mechanical structure. The reciprocating
effect of our device is enhanced by using gear
mechanism that is composed of shaft with a dynamo.
We demonstrate lighting up a commercial LED light
bulb by harvesting mechanical energy of the
pendulum oscillation. This project is a platform of
developing a sustainable, low maintenance system to
harvest mechanical energy.
I. INTRODUCTION
The more power demand has been occurring now a day
in India. The main reason of the power demand is due to
the lack of improper energy utilization and conservation.
The paper deals with the power generation from the
mechanical energy that has been wasted in many day
today real time applications. The root of paper is the
Soccket ball concept invented in the Chicago in 2010.
The pendulum setup has been made inside the Soccket
ball, that is whenever it has been kicked Off the kinetic
energy of ball makes the pendulum to oscillate which cuts
the electromagnetic field, generates the electrical energy
.Thus the electrical energy obtained will power up t he
LED and stored in the battery for further usage. We can
implement the pendulum based power generation system
in real time application wherever the vibration produced
.The example is vehicles, the vibrations will be produced
due to movement when it passes through the speed
breakers. We can implement a pendulum based power
generation system in such dynamic application we can
generate power from it. The power is used to charge the
batteries .In this paper we have proposed the hardware
setup of the pendulum system, power regulatory circuit
and its battery unit [1].
II. PROPOSED SYSTEM
A. General Block diagram of the proposed system
The Block Diagram of the proposed system given below
deals with the overall system design and process flow
control.
Figure: 1 Proposed System Block Diagram
The pendulum model will be generating power from the
real time dynamic movements. Once when the pendulum
is disturbed from its equilibrium position it swings to and
fro. The oscillation movement is converted into the linear
motion with the help of the Reciprocating system. .The
RPM is coupled with the Dynamo. The Linear Charge
control circuit is the combination of the embedded system
design which will control the flow of power from the
pendulum model to the Battery storage unit and also from
the Battery to the Load.
B.Proposed System Circuit Diagram:
The latter part is dealing about the general block diagram
of the proposed system .The system design , components
and the process flow will be discussed here .The circuit
diagram will contain the following components such as
the given in the table.
Table: 1 Technical specification of the components used
COMPONENT SPECIFICATION
Microcontroller PIC 16F877A
Voltage Regulator IC7805
Inverter SG3525A


MOSFET RFZ44NTO
Step up Transformer 12/120 Volt
LCD display 4-Bit

Figure: 2 proposed system circuit diagram
The circuit given above will depict the process flow and
the power flow from the pendulum model to the battery
system. The PIC 16F877A microcontroller used in our
paper is basically used in controlling the process flow
among the various devices [4] .And this is cheaper cost
and easily available in market. The Voltage Regulator
IC7805 is used to regulate the voltage and provide the
fixed voltage to the various units in the circuit .The
Inverter SG3525A have been used in this circuit. The
main objective of using this inverter ,that in order to feed
to the AC loads from the battery unit .The inverter will
convert DC to AC and that will feed to the loads. The
inverter will use the PWM technique to provide this
operation with the help of the two MOSFET RFZ44NTO.
The Step Up transformer will act as a voltage doubler
circuit to double the voltage so that it will feed to the AC
Loads. The process flow is quite simple. The pendulum
will be subjected to the motion when it has been placed
on the real time dynamic movements. The power
generated from the pendulum model must be handled
properly to store in the battery unit. The PIC will sense
the battery storage limit once the limit exceeds the PIC
will remove the gate signal from the MOSFET so that
power given to the Inverter SG3525A which will convert
the dc into ac with the help of the PWM Technique[4].
The inverted AC power will feed to the step up
transformer which will step up the voltage to the required
voltage level needed for the load. The load will be such as
the Lamp, Fan and other ac loads depend on the power
stored in the battery.
C. Calculation on the Power Generated from the
Pendulum Model:
The calculation part will consists of the parameter that
have been discussed below
Calculation on Time Period
FORMULAE USED:
T = 2 (L/g)
L Length of Rope (meters)
G Acceleration due to Gravity (m/ s
2
)

Table 2: variation of Time period with length of string

Time period (T) of pendulum is significantly affected
only by its length and the acceleration of gravity.
Depending upon the length of the string the time period
will gets varied
D.Calculation on power generated with respect to the
Angle x (deg):
The power generated from the pendulum system can be
calculated from the formulae given below
Power = 2Mg (1-Cos(x))/ gL
M - Mass of bob
g- Acceleration due to gravity
L- Length of the string
Assuming of the variables:
M = 0.15 kg, G = 9.8 m/s
2
, l = 0.27m, x = 30 Deg
Power = 0.072 Watts
The same calculation has been made on the different
angles that have been made during the oscillation of the

Length
Acceleration due to
gravity
Time Period
(secs)
1.2 m 9.8 m/ s
2
2.2secs
1.5 m 9.8 m/s
2
2.5 secs


pendulum. And the below table has been made based on
the calculated datas of power generated [2],[3].
Table: 3 variation power with respect to the angle
S.No Angle x ( Deg) Power (Watts)
1. 30 0.072
2. 45 0.157
3. 60 0.268
4. 75 0.398
5. 90 0.5
6. 120 0.805
7. 150 1.02
8. 180 1.074
The calculation has been made and that is described in the
above table and for better understanding the below chart
deals about the variation of power with respect to the
angle x (deg)

Figure: 2 variation power with respect to the angle x (deg)
The graph is exactly defined that when the angle of the
pendulum oscillation increases the power generation also
increases. From this is it clear we can implement this
system in the application where the more dynamic
movements have been available
III. CONCLUSION
Energy harvesting is, in itself, an energy resource. At the
end of a research we have designed a power generator
with a pendulum that employs the concept of
reciprocating system .The ambient vibration can be used
in an effective way by converting them to electrical
energy. It proposes energy conversion system in terms of
generating electricity. The technique of implementing the
pendulum power generator is to reduce global warming.
The compact model not only provides the accurate result
but also gave the computational speed-ups of the
generation. In future, maximize version of our project can
be installed to produce power. Also some techniques need
to be developed to install our setup in the vehicles. A
large amount of vibrations are produced every time when
it passes through the speed breaker. With appropriate
development of technology, the electrical energy
generated from these vibrations can be used to power up
the batteries.
REFERENCES
[1] Weisstein, Eric W. (2007). "Simple Pendulum". Eric
Weisstein's world of science. Wolfram Research. Retrieved
2009-03-09.
[2] E. Roller, Duane, Leo Nedelsky
(2008). "Conservation of energy". Access Science. McGraw-
Hill Companies. Retrieved 2011-08-26.

[3] Tenenbaum (2004). Fundamentals of Applied
Dynamics. Springer. ISBN 0-387-00887-X.
[4] Heath, Steve (2003). Embedded systems design. EDN
series for design engineers, Newnes. pp. 11
12. ISBN 9780750655460
0
0.2
0.4
0.6
0.8
1
1.2
30 45 60 75 90 120 150 180
P
O
W
E
R

(
W
a
t
t
s
)
ANGLE X(Deg)


Comparison Analysis of PI and Fuzzy Control of LLC
Resonant Converter Incorporating ZVS Boost Converter
N.Madhanakkumar
1
, T. S. Sivakumaran
2
, D.Sujitha
3
1
Research Scholar, Department of Electrical and Electronics Engineering, Anna University, India
madhanakkumar_n@yahoo.co.in
2
Professor, Department of Electrical and Electronics Engineering, Arunai College of Engineering, India
3
PG Scholar in Power Electronics and Drives, Mailam Engineering College, India

ABSTRACT
The closed loop fuzzy control of LLC type of
series parallel resonant converter
configuration of load resonant converter and its
modeling analysis is presented in this paper. The
LLC resonant converter provides high
frequency operation, without affecting its high
efficiency, which leads to their applications
mostly in DC DC converters. The state space
modeling is analyzed to know the internal state
i.e. stability of the converter. The common
closed loop fuzzy controller is used on both the
side of the LLC resonant tank which eliminates
the steady-state error and decrease the rise time
of the output voltage. The input of 40V LLC
resonant converter is built to produce 220V
output with the help of ZVS boost converter
with 140 kHz resonant frequency. The
comparison of simulation result with the closed
loop fuzzy controller and closed loop PI
controller shows the output performance
characteristics and reliability of a fuzzy
controller.
Keywords: Nyquist Plot, LLC Resonant
Converter, Fuzzy controller, State Space
Modelling, Stability Analysis, ZVS Boost
Converter, PI controller.
I. INTRODUCTION
Though there are different categories of resonant
converters and with each having their abundant
benefits such as operating with high frequency
range of the power switches and low switching
losses, among those LLC resonant converter
(LLRC) which merge the merits of the series
resonant converter and parallel resonant converter
are gaining lots of attention in DC DC converter
applications. It is also analyzed that series
parallel resonant converter (SPRC) can operate
over a wide load range and large input range with
excellent efficiency, when compared with half-
bridge series resonant converter (SRC), parallel
resonant converter (PRC) and series parallel
resonant converters (SPRC) [2].
The optimization of LLC resonant converter is
provided with high accuracy and efficiency with
small size [3, 4, and 6] and used for application
such as over current protection [5] with frequency
in an acceptable value. The LLCRC is applicable to
various applications such as SMPS [9],
telecommunication [11] and for an adjustable wide
range regulated current source [9] with the help of
fundamental harmonic approximation method [10].
This FHA analysis with the parasitic components
are included with this converter and analyzed with
traditional FHA method [7]. The steady state
design is done with the help of state space
modeling method [14, 21] and the state plane
trajectories explains about the boundaries of
various operating modes [17] for the resonant tank
circuit.

II. RESONANT CONVERTER

A. LLC Resonant Converter

The LLC resonant converter operates at high
frequency and also the switching losses are
reduced and provide high efficient LLC converter
design [1]. Thus, the LLC resonant converter
provides high power packing density with high
frequency range up to several MHz [12] as it
combines the frequencies of series resonant
converter and parallel resonant converter. The
LLC resonant converter consists of a resonant tank
with a capacitor (C
r
) and an inductor (L
r
) in series
with the inverter side and an inductor (L
m
) in
parallel to the inverter side and rectifier side, to
provide high voltage gain [1]. The LLC resonant
converter is one of the type of series parallel load
resonant converter and it overcomes the
disadvantages of both series resonant
converter and parallel resonant converter, as it


provides lack in no load regulation and
circulating current independent of load [2]
respectively. The LLC resonant converter in this
work consists of four power MOSFET switches for
construction of single phase full bridge inverter, on
the input side of the converter or primary side of
the transformer which works under the control
operation of ZVS boost converter. The secondary
side of the transformer or the output side of the
converter consists of four IGBT power
semiconductor switches for the construction of 1
full bridge rectifier. The LLC resonant converter
circuit diagram is shown in fig.1.

Fig.1. LLC resonant converter circuit diagram.

B. Zero Voltage Switching Boost Converter

The zero voltage switching (ZVS) eliminates
capacitive turn on loss, but in zero current
switching (ZCS) it leads to capacitive turn on loss
with high current loss when operate in high
frequency so ZVS is more advantageous than ZCS.
Thus, ZVS is mostly suitable for high frequency
operation with constant off time control. So, in
this proposed design to control the input side
inverter circuit and primary side of the transformer,
the ZVS boost converter is applied. The ZVS boost
converter works with the principle operation of DC
DC boost converter under zero voltage switching
condition of MOSFET switches. Thus the input
voltage of 40Volt is boost up to 150Volt at the
output of ZVS boost converter and it acts as input
and control the inverter circuit on primary side of
the transformer.
III. MODELING ANALYSIS
The modeling is done with the help of state space
modeling. The modeling is used to measure the
data for the system model and to predict the system
behavior for different input situations. Though
there are various techniques for modeling of
converter, the state space modeling is more
advantageous than other. Since, they can be
applicable to non linear, time invariant and
MIMO (multiple inputs and multiple outputs)
systems it is preferred mostly for modeling of
resonant converters. But, the transfer function
modeling can be applicable to linear, time invariant
system under zero initial conditions. The state
space modeling is done for the LLC resonant
converter in this proposed work based on different
mode of operation and with the help of equivalent
circuit formation. The state space matrix is
formed only for three modes of operations in this
work. The state vector includes the state variables
which is the voltage or current of capacitor or
inductor element.

A. State space analysis:
Some of the assumptions are made before
forming the state space matrix for above
operating modes. The assumptions are:
a) All the components of ZVS boost converter
and the components before the inverter side are
considered as ideal.
b) The resonant frequency is higher than the
switching frequency.
c) The output capacitor is large enough to
produce constant output voltage Vo.
d) The circuit losses, including the resonant tank,
switch and filter losses are negligible.

1) For PP mode:
In PP mode, the switches M
1
and M
2
on the inverter
side and T
1
and T
2
on the rectifier side is turned on
in positive conduction mode. The state space
input matrix is given as:
di
t
dt
dv
t
dt

0
1
L
1
C
t
v

1
L
0
V

2) For PN mode:
In this mode of operation, there is a positive
conduction of inverter side with the switches M
1

and M
2
turned on and negative conduction on
rectifier side with the switches T
3
and T
4
turned on.
The state space input matrix is given as:


di
t
dt
dv
t
dt

0
1
L
1
C
t
v

1
L
0
V

3) PO mode:
The positive conduction of inverter side with
switches M
1
and M
2
turned on and turn off of all
the switches on rectifier side defines the PO mode
operation. For this mode the state space input
matrix is:
di
t
dt
dv
t
dt

0
1
L

1
C
t
v

1
L
0
V

B. Stability analysis:

The state space modeling has one major
advantage, as it is used to study about the internal
state of the system. Thus, stability of the system
using the state space matrix is found by plotting
the nyquist plot for the whole operation of resonant
converter. The equivalent circuit of this resonant
converter is shown in Fig.2.

Fig.2. Equivalent circuit of LLC resonant converter

The state space input matrix for this overall
equivalent circuit of LLC resonant converter is
given as :

0 1
0

i

0
1
L

The nyquist plot for this state space
representation is shown in fig.3. The stability of the
system is used to design the closed loop system
under stable operation. The nyquist plot shows the
real and imaginary axes with the poles and zero
plot for the LLC Resonant converter, from the
nyquist plot it is known that the closed loop system
is stable for the chosen LLC values. Since the
nyquist plot curve does not crosses the (-1+j0)
point in any situtaion so it is stated that the closed
loop system is stable.

Fig.3. Stability Analysis of LLC Resonant Converter
Usi
ng Nyquist Plot.

IV. DESIGN OF CLOSED LOOP FUZZY
CONTROL
The identical fuzzy logic controller is used to
control on both the side (i.e. primary and
secondary) of linear transformer to perform better
control action on input and output side. The fuzzy
logic control provides better controller action than
PI controller since it is very robust and can be
easily modified with the use of multiple input and
output sources and also quick and very cheap to


implement. Fig.1. shows the block diagram
representation of fuzzy control based LLC resonant
converter.

Fig.4. Block diagram of fuzzy control based LLC
Resonant converter
Fuzzy logic system is one of the types of
intelligence based system with work on both
Linguistic language and Boolean logic. The fuzzy
logic control structure is based on four main steps.
The four main steps are:
(a) Fuzzification:
The fuzzification step is used to match
the input variables to fuzzy sets with the
help of membership functions. In other
words, the linguistic/ crisp input variables
are converted into fuzzy sets with the help of
membership functions.
(b) Inference Mechanism:
The inference mechanism is based upon
the rules framed and along with the
membership function fuzzified.
(c) Rules and Database:
The rules are framed as IF THEN rules
with the logic operations either AND/ OR
operation to map the multiple input with
their membership functions.
The database is the membership
functions using the fuzzy rules in the fuzzy
sets
(d) Defuzzification:
The defuzzification is used to obtain
crisp output with the aid of converting fuzzy
output is mapped to a crisp output using the
membership functions.
The general structure of fuzzy controller in block
diagram representation is shown in fig.5

Fig.5.Structure of fuzzy controller

Thus in this proposed system the fuzzification of
seven triangular membership functions is used with
49 rules under AND logic operations. The
defuzzification is used with the centroid output
functions. The crisp output is obtained at the end of
defuzzification and used to generate pulse signal to
the power switches on the ZVS boost converter and
single phase full bridge inverter. The fuzzy rule
base table is shown in TABLE I which is easy to
use and understand the fuzzy logic.

TABLE I
FUZZY RULE BASE

The Fig.6.1 shows the closed loop fuzzy response
of LLC resonant converter start - up output voltage
with set point of 40V and nominal load of 100.
The Fig.6.2 shows the response of output voltage
under sudden line disturbance (40V 42V 40V)
at 2.5sec with nominal load of 100 and Fig.6.3
shows the responses of output voltage under

E
CE
NB NM NS Z PB PM PS
NB NB NB NM NM NS NS Z
NM NB NM NM NS NS Z PB
NS NM NM NS NS Z PB PB
Z NM NS NS Z PB PB PM
PB NS NS Z PB PB PM PM
PM NS Z PB PB PM PM PS
PS Z PB PB PM PM PS PS


sudden load disturbance (100 90 100 ) at
1sec with set point of 40V respectively with fuzzy
controller. Similarly, the closed loop PI control
responses for the performance comparison of
closed loop fuzzy controller with PI controller are
shown in TABLE II. The Fig.6.4 shows the closed
loop PI response of LLC resonant converter start -
up output voltage with set point of 40V and
nominal load of 100. The Fig.6.5 shows the
response of output voltage under sudden line
disturbance (40V 42V 40V) at 2.5sec with
nominal load of 100 and Fig.6.6 shows the
response of output voltage under sudden load
disturbance (100 90 100 ) at 1sec with
set point of 40V respectively. With these
simulation results, the comparison TABLE II is
drawn to clearly predict the performance of the
LLC resonant converter and the controller
importance in the system. The TABLE II shows the
performance of LLC resonant converter under
closed loop fuzzy control and PI control. The table
III shows the parameter specifications for LLC
resonant converter. . The Fig.6.6 shows the
comparison of simulated performances of closed
loop fuzzy control and PI control for LLC Resonant
converter by graphical representation.

Fig.6.1. Simulated start-up voltage of LLCRC
with set - point 40V and nominal load 100 (Fuzzy
Controller)

Fig.6.2. Simulated output voltage of LLCRC with
sudden line disturbances (40V 42V 40V) at t =
2.5sec (Fuzzy Controller)

sudden load disturbances (100 90 100) at
t = 1sec (Fuzzy Controller)

Fig.6.7. Simulated start-up voltage of LLCRC
with set - point 40V and nominal load 100 (PI
Controller)



Fig.6.9. Simulated output voltage of LLCRC
with sudden line disturbances (40V 42V
40V) at t = 2.5sec (PI Controller)

sudden load disturbances (100 90 100) at t =
1sec (PI Controller)

TABLE II
PERFORMANCE EVALUATION OF CLOSED LOOP FUZZY
CONTROLWITH PI CONTROL OF LLC RESONANT
CONVERTER

TABLE III
PARAMETERS SPECIFICATION FOR LLC
RESONANT CONVERTER

Fig.6.13. Comparison of Simulated Performances of
Closed Loop Fuzzy and PI Controller for LLCRC by
Graphical Representation

VI. CONCLUSION
Thus, the closed loop control of LLC resonant
converter performance was obtained using fuzzy
logic controller. The simulation result with lessen
rise time and elimination of steady state error
was obtained. The system execute better under
sudden line and load disturbance. The stability of
LLCRC was analyzed with the help of nyquist plot
and state space analysis. The closed loop fuzzy
logic controller and closed loop PI controller
characteristic performance was compared and
shows that the closed loop fuzzy control is less
sensitive to the line and load disturbances than
closed loop PI controller system.
REFERENCES

[1] Xiang Fang, Haibing Hu, Frank Chen, Utsav
Somani, Emil Auadisian, John Shen, and Issa
Batarseh, Efficiency oriented optimal design
of the LLC resonant converter based on peak gain
placement, in Proc. IEEE Trans. on Power
Electron., Vol. 28, No. 5, May 2013.
[2] R. L. Steigerwald, A comparison of half-bridge
resonant converter topologies, IEEE Trans.
Power Electron. , vol. 3, no. 2, pp. 174182, Apr.
1988.
[3] T. Liu, Z. Zhou, A. Xiong, J. Zeng, and J. Ying,
A novel precise design method for LLC series
resonant converter, in Proc. 28th Annul. Int.
Telecomm. Energy Conf.,2006, pp.1-6.
[4] C. Oeder, Analysis and design of a low-profile
LLC converter, in Proc. IEEE Int. Symp. Ind.
Electron. , Jul. 2010, pp. 38593864.
[5] X. Xie, J. Zhang, C. Zhao, Z. Zhao, and Z. Qian,
Analysis and optimization of LLC resonant
converter with a novel over-current protection
circuit, IEEE Trans. Power Electron., vol. 22,
no. 2, pp. 435443, Mar. 2007.
[6] M. P. Foster, C. R. Gould, A. J. Gilbert, D. A.
Stone, and C. M. Bingham, Analysis of CLL
voltage-output resonant converters using
describing functions, IEEE Trans. Power
Electron., vol. 23, no. 4, pp. 17721781, Jul.
2008.
[7] B. Lee, M. Kim, C. Kim, K. Park, and G. Moon,
Analysis of LLC resonant converter considering
effects of parasitic components, in Proc. IEEE
Int. Telecomm. Energy Conf., Oct. 2009, pp. 16.
[8] G. Ivensky, S. Bronshtein, and A. Abramovitz,
Approximate analysis of resonant LLC DCDC
converter, IEEE Trans. Power Electron., vol. 26,
no. 11, pp. 32743284, Nov. 2011.
[9] R. Beiranvand, B. Rashidian, M. R. Zolghadri,
and S. M. H. Alavi, Designing an adjustable
wide range regulated current source, IEEE
PARAMETERS VALUES
Input Voltage, V
dc
40V
Resonant Capacitor, C
r
470nF
Resonant Inductor, L
r
2.75H
Load Resistance, R
L
100
Resonant Inductor, L
m
7.67H
Output Voltage, V
o
220V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T
i
m
e
F
u


Trans. Power Electron., vol. 25, no. 1, pp. 197
208, Jan. 2010.
[10] T. Duerbaum, First harmonic approximation
including design constraints, in Proc. 20th Int.
Telecommun. Energy Conf.,, 1998, pp. 321328.
[11] W.-Y. Choi, J.-M. Kwon, and B.-H. Kwon,
High-performance front-end rectifier system for
telecommunication power supplies, Proc. Inst.
Elect. Eng., vol. 153, no. 4, pp. 473482, 2006.
[12] H. de Groot, E. Janssen, R. Pagano, and K.
Schetters, Design of a 1-MHz LLC resonant
converter based on a DSP-Driven SOI Half-
Bridge power MOS module, IEEE Trans. Power
Electron., vol. 22, no. 6, pp. 23072320, Nov.
2007.
[13] B. Yang, F. C. Lee, A. J. Zhang, and G. Huang,
LLC resonant converter for front end DC/DC
conversion, in Proc. IEEE Appl. Power
Electron. Conf. Expo., 2002, pp. 11081112.
[14] J. H. Cheng and A. F. Witulski, Analytic
solutions for LLCC parallel resonant converter
simplify use of two-and three-element
converters, IEEE Trans. Power Electron., vol.
13, no. 2, pp. 235243, Mar. 1998.
[15] X. Fang, H. Hu, J. Shen, and I. Batarseh,
Operation mode analysis and peak gain
approximation of the LLC resonant converter,
IEEE Trans. Power Electron., vol. 27, no. 4, pp.
19851995, Apr. 2012.
[16] B. Lu, W. Liu, Y. Liang, F. C. Lee, and J. D. van
Wyk, Optimal design methodology for LLC
resonant converter, in Proc. IEEE Appl. Power
Electron. Conf. Expo., Mar. 2006, vol. 2, p. 6.
[17] N. H. Kutkut, C. Q. Lee, and I. Batarseh, A
generalized program for extracting the control
characteristics of resonant converters via the state
- plane diagram, IEEE Trans. Power Electron.,
vol. 13, no. 1, pp. 5866, Jan. 1998.
[18] I. Batarseh, State-plane approach for the analysis
of half-bridge parallel resonant converters, Proc.
Inst. Elect. Eng., vol. 142, no. 3, pp. 200204,
Jun. 1995.
[19] A. K. S. Bhat, A generalized steady-state
analysis of resonant converters using two-port
model and Fourier-series approach, IEEE Trans.
Power Electron, vol. 13, no. 1, pp. 142151, Jan.
1998.
[20] I. Batarseh, R. Liu, A. Ortiz-Conde, A. Yacoub,
and K. Siri, Steady state analysis and
performance characteristics of the LLC-type
parallel resonant converter, in Proc. Power
Electron. Spec. Conf., 1994, pp. 597606.
[21] J. F. Lazar and R. Martinelli, Steady-state
analysis of the LLC series resonant converter, in
Proc. IEEE Appl. Power Electron. Conf. Expo.,
2001, vol. 2, pp. 728735.
[22] Y. Gu, Z. Lu, L. Hang, Z. Qian, and G. Huang,
Three-level LLC series resonant DC/DC
converter, IEEE Trans. Power Electron., vol. 20,
no. 4, pp. 781789, Jul. 2005.


Single-Level Single Switch Control for Transformerless Rectifier

Vijay.S
1
,Sudharsan.A.N
2
,Venkatesh Kumar.B
3
, P.Swethamarai
4

1,2,3,4
Electrical & Electronics Dept, R.M.D Engineering College, Kavaraipettai, India

ABSTRACT
This paper presents a high step-down
transformerless single-stage single-switch ac/dc
converter suitable for universal line applications (90
270 V
rms
). The topology integrates a buck-type
power-factor correction (PFC) cell with a buckboost
dc/dc cell and part of the input power is coupled to
the output directly after the first power processing.
With this direct power transfer feature and sharing
capacitor voltages, the converter is able to achieve
efficient power conversion, high power factor, low
voltage stress on intermediate bus (less than 130 V)
and low output voltage without a high step-down
transformer. The absence of transformer reduces the
component counts and cost of the converter. Unlike
most of the boost-type PFC cell, the main switch of
the proposed converter only handles the peak
inductor current of dc/dc cell rather than the
superposition of both inductor currents. Detailed
analysis and design procedures of the proposed
circuit are given and verified by experimental results.

Index TermsDirect power transfer (DPT),
integrated buck buckboost converter (IBuBuBo),
power-factor correction (PFC), single-stage (SS),
transformerless.

I. INTRODUCTION

SINGLE-STAGE (SS) ac/dc converters have received much
attention in the past decades because of its cost effectiveness,
compact size, and simple control mechanism. Among existing
SS converters, most of them are comprised of a boost power-
factor correction (PFC) cell followed by a dc/dc cell for output
voltage regulation [1][7]. Their intermediate bus voltage is
usually greater than the line input voltage and easily goes be-
yond 450 V at high-line application [8]. Although there are a
lot of efforts to limit this bus voltage, it is still near or above
the peak of the line voltage due to the nature of boost-type
PFC cell. For application with low output voltage (e.g.,
48V), this high inter-mediate bus voltage increases
components stresses on the dc/dc cell. With a simple step-
down dc/dc cell (i.e. buck or buckboost converter), extremely
narrow duty cycle is needed for the con-version. This leads to
poor circuit efficiency and limits the input voltage range for
getting better performance [9], [10]. Therefore, a high step-
down transformer is usually employed even when galvanic
isolation is not mandatory. For example, LED drivers without
isolation may satisfy safety requirement [11]. Also, in some
multistage power electronics system (e.g., in data center,
electrochemical and petrochemical industries, and subway
applications [12]), the isolation has been done in the PFC
stage, the second transformer in the dc/dc cell for the sake of
isolation is considered as redundant. Hence, non isolated ac/dc
converter can be employed to reduce unnecessary or
redundant isolation and enhance efficiency of the overall
system. Besides, leakage inductance of the transformer causes
high spike on the switch and lower conversion efficiency. To
protect the switch, snubber circuit is usually added resulting in
more component counts [13]. In addition, the other drawbacks
of the boost-type PFC cell are that it cannot limit the input
inrush current and provide output short-circuit protection [14].
To tackle the aforementioned problems, an effective way is to
reduce the bus voltage much below the line input voltage.
Several topologies have been reported [9], [10], [13], [15]
[18]. Although the recently reported IBoBuBo converter [13]
is able to limit the bus voltage under 400 V, it cannot be
applied to the low-voltage application directly due to the boost
PFC cell. On the other hand, the converters [9], [10], [15]
[18] employ different PFC cells to reduce the intermediate bus
voltage. Among those converters, [9] and [15] use a
transformer to achieve low output voltage either in PFC cell or
dc/dc cell. Therefore, the leakage inductance is unavoidable.
In [10], [17], and [18], the converters employ a buckboost
PFC cell resulting in negative polarity at the output terminal.
In addition, the topologies in [18] and [10] process power at
least twice resulting in low power efficiency. Moreover, the
reported converters, in [16], and [17], consist of two active
switches leading to more complicated gate control.
Apart from reducing the intermediate bus voltage, the
converter in [19] employs resonant technique to further
increase the step-down ratio based on a buck converter to
eliminate the use of intermediate storage capacitor. The
converter features with zero-current switching to reduce the
switching loss. However, without the intermediate storage, the
converter cannot provide hold-up time and presents substantial
low-frequency ripples on its output voltage. Besides, the duty
cycle of the converter for high-line input application is very


narrow, i.e., < 10%. This greatly increases the difficulty in its
implementation due to the minimum on-time of pulse-width-
modulation (PWM) IC and rise/fall time of MOSFET. More
details on comparing different approaches will be given in the
Section V.

In this paper, an intergrated buckbuckboost (IBuBuBo)
converter with low output voltage is proposed. The converter
utilizes a buck converter as a PFC cell. It is able to reduce the
bus voltage below the line input voltage effectively. In
addition, by sharing voltages between the intermediate bus
and output capacitors, further reduction of the bus voltage can
be achieved. Therefore, a transformer is not needed to obtain
the low output voltage. To sum up, the converter is able to
achieve:
1) low intermediate bus and output voltages in the
absence of transformer;
2) simple control structure with a single-switch;
3) positive output voltage;
4) high conversion efficiency due to part of input power
is processed once and
5) input surge current protection because of series
connection of input source and switch.

The paper is organized as follows: operation principle of the
proposed IBuBuBo converter is depicted in Section II and
followed by design consideration with key equations in
Section III. Experimental result and discussion of the
converter are given in Section IV and V, respectively. Finally,
conclusion is stated in Section VI.

II. PROPOSED CIRCUIT AND ITS OPERATING
PRINCIPLE

The proposed IBuBuBo converter, which consists of the
merging of a buck PFC cell (L
1
, S
1
, D
1
, C
o
, and C
B
) and a
buckboost dc/dc cell (L
2
, S
1
, D
2
, D
3
, C
o
, and C
B
) is il-
lustrated in Fig. 1(a). Although L
2
is on the return path of the
buck PFC cell, it will be shown later in Section III-A that it
does not contribute to the cell electrically. Thus, L
2
is not con-
sidered as in the PFC cell. Moreover, both cells are operated
in discontinuous conduction mode (DCM) so there are no
currents in both inductors L
1
and L
2
at the beginning of each
switching cycle t
0
. Due to the characteristic of buck PFC cell,
there are two operating modes in the circuit.
Mode A (v
in
() V
B
+ V
o
): When the input voltage v
in
()
is smaller than the sum of intermediate bus voltage V
B
, and
output voltage V
o
, the buck PFC cell becomes inactive and
does not shape the line current around zero-crossing line
voltage [20], owing to the reverse biased of the bridge
rectifier. Only the buckboost dc/dc cell sustains all the output
power to the load. Therefore, two dead-angle zones are
present in a half-line period and no input current is drawn as
shown in Fig. 1(b). The circuit operation within a switching
period can be divided into three stages and the corresponding
sequence is Fig. 2(a),(b), and (f). Fig. 3(a) shows its key
current waveforms.

1) Stage 1 (period d
1
T
s
in Fig. 3) [see Fig. 2(a)]: When
switch S
1
is turned ON, inductor L
2
is charged linearly
by the bus voltage V
B
while diode D
2
is conducting.
Output capacitor C
o
delivers power to the load.

2
T
s
in Fig. 3) [see Fig. 2(b)]: When
switch S
1
is switched OFF, diode D
3
becomes forward
biased and energy stored in L
2
is released to C
o
and the
load.

3
T
s
- d
4
T
s
in Fig. 3) [see Fig. 2(f)]: The
inductor current i
L

2
is totally discharged and only C
o

sustains the load current.

Mode B (v
in
() > V
B
+ V
o
): This mode occurs when the
input voltage is greater than the sum of the bus voltage and
output voltage. The circuit operation over a switching period
can be divided into four stages and the corresponding
sequence is Fig. 2(c), (d), (e), and (f). The key waveforms are
shown in Fig. 3(b).

1
T
s
in Fig. 3) [see Fig. 2(c)]: When
switch S
1
is turned ON, both inductors L
1
and L
2
are
charged linearly by the input voltage minus the sum of
the bus voltage and output voltage (v
in
() V
B
V
o
),
while diode D
2
is conducting.

2
T
s
in Fig. 3) [see Fig. 2(d)]: When
switch S
1
is switched OFF, inductor current i
L

1

decreases linearly to charge C
B
and C
o
through diode D
1

as well as transferring part of the input power to the load
directly. Meanwhile, the energy stored in L
2
is released
to C
o
and the current is supplied to the load through
diode D
3
. This stage ends once inductor L
2
is fully
discharged.

3
T
s
in Fig. 3) [see Fig. 2(e)]: Inductor
L
1
continues to deliver current to C
o
and the load until its
current reaches zero.

4
T
s
in Fig. 3) [see Fig. 2(f)]: Only C
o

delivers all the output power.


(a)

(b)
Fig. 1. (a) Proposed IBuBuBo SS ac/dc converter. (b) Input voltage
and current waveforms.

III. DESIGN CONSIDERATIONS

To simplify the circuit analysis, some assumptions are made
as follows:
1) all components are ideal;
line input source is pure sinusoidal, i.e. v
in
() = V
pk

sin() where V
pk
and are denoted as its peak voltage and
phase angle, respectively;
2) Both capacitors CB and C0 are sufficiently large such
that they are treated as DC constant voltages
without any ripples ;
3) the switching frequency fs is higher than the line
frequency such that the rectified line voltage
constant with the switching period.

(a)

(b)

(c)

(d)

(e)


(f)
Fig. 2. Circuit operation stages of the proposed ac/dc
converter.

IV. EXPERIMENTAL RESULTS

The performance of the proposed circuit is verified by the
prototype. To ensure the converter working properly with con-
stant output voltage, a simple voltage mode control is
employed. To achieve high performance of the converter for
universal line operation in terms of low bus voltage (< 150V)
and high power factor (> 96%), the inductance ratio has to be
optimized ac-cording to Figs. 4 and 5. The lower the bus
voltage of the converter, the lower voltage rating capacitor
(150 V) can be used.
In addition, the inductance ratio will affect the efficiency of
the converter. More detail will be given in Section V. Taking
the performance of the converter on bus voltage, power factor,
and efficiency into account, the inductance ratio around M =
0.4 is selected. Table II depicts all the components used in the
circuit, and its specification is stated as follows:
1) output power: 100 W;
2) output voltage: 19 V
dc
;
3) power factor: > 96%;
4) intermediate bus voltage: < 150V;
5) line input voltage: 90270 V
rm s
/50 Hz;
6) switching frequency (f
s
): 20 kHz.

TABLE II
CIRCUIT COMPONENTS
Parameters Values

IC Controller TL594

Input filter inductor L
f
2 mH
Input filter capacitor C
f
2 F
Inductor L
1
106 H
Inductor L
2
46 H
Inductance Ratio (M =
L
2
/L
1
) 0.434
MOSFET S
1
SPW47N60CFD
D
1
MUR3040PT
D
2
MUR3040PT
D
3
MUR3040PT
C
B
5 mF
C
o
5 mF

Fig. 7. Measured input characteristic of the converter at (a) 90 V
r m s

and b) 270 V
r m s
under 100-W condition.

Fig. 8. Comparison of IEC61000-3-2 Class D standard with
measured inp

Fig. 9. Measured output voltage (upper trace 10 V/div) and
intermediate bus voltage (bottom trace 40 V/div) at (a) 90 V
r m s
and


(b) 270 V
r m s
under full load condition.

The measured current harmonics met the IEC61000-3-2 class
D standard as shown in Fig. 8. In ad-dition, the measured
output and bus voltages under both low and high line
conditions are shown as in Fig. 9. It can be seen that the bus
voltage was kept at 123 V and well below 150 V at high-line
condition.

Fig. 10. Measured circuit efficiency under load variation.

Fig. 11. Comparison of measured intermediate bus voltage with its
predicted value.

Fig. 10 illustrates the conversion efficiency of the proposed
converter under different line input and out-put power
conditions. The maximum efficiency of the circuit is around
89% at low line application. Furthermore, Fig. 11 shows the
predicted intermediate bus voltage is in good agreement with
the measured value.

V. DISCUSSION

According to [13] and [21], the direct power transfer ratio n
under this type of capacitive coupling is V
o
/V
T
. It can be seen
that the portion of direct power transfer from input to output
decreases when V
B
becomes larger resulting in increase of V
T
.
In other words, the direct power transfer decreases when the
line input voltage increases. It matches with the discussion in
Section III-E. In addition, the increase of V
B
will lower the
conversion efficiency of dc/dc cell due to larger voltage
conversion around ten times at high-line condition, from V
B
=
123 V down to V
o
= 19 V. As a result, it further impairs the
efficiency of the converter at high-line operation. On the other
hand, from (2), decrease of V
B
extends the conduction angle of
the converter leading to higher power factor.
However, lower V
B
requires decrease of inductance ratio
resulting in higher peak inductor currents and causing higher
conduction loss. Thus, trade off has to be made for selecting
the inductance ratio among the peak current of both inductors,
bus voltage, and power factor. Never the less,the converter is
capable to be used under high-line condition with the full load
efficiency around 84% at 240 V
rm s
.

Here Ind. and Trans. are denoted as number of inductors and
number of transformers.

To continue with the comparison from Section I, Table III
shows the performances of recent topologies and the proposed
converter in more detail. In order to achieve low output
voltage and low intermediate bus voltage with high efficiency
for univer-sal line operation, the topologies employ different
approaches.
TABLE III
COMPARISON OF RECENTLY REPORTED
TOPOLOGIES

Di
od
e
Con
trol
Ma
gne
tic Capac
itors
Interme
diate
Bus
Inpu
t
Volt
age
Outpu
t
Maxi
mum
Switc
h
Compon
ents
Voltage
V
B

Vrm
s
Condi
tion
Effici
ency

[1
3] 3 1 2 Ind. 2 400 V
90 ~
270
Vrm
s
100
V/100
W 89.5%
[15] 4 1
1 Ind.
and 1
Trans. 2 220 V
90 ~
270
Vrm
s
48
V/100
W 82%
[9] 2 2
1 Ind.
and 1
Trans. 2 36 V
187
~
265
Vrm
s
56
V/100
W 85.5%
[10] 4 1 2 Ind. 2 86 V
110
Vrm
s
-20
V/50
W 77%
[17] 3 2 3 Ind. 2 209 V
85 ~
265
Vrm
s
-48
V/111
.52 W 83.1%
[18
] 6 1 3 Ind. 3
V
B1
=
70 V
85
Vrm
-5
V/20 80.5%


V
B2
=
30 V
s W

[19] 2 1 2 Ind. 2 N/A
90 ~
240
Vrm
s
19
V/13.
72 W 90.56%

Propo
sed 3 1 2 Ind. 2 130 V
90 ~
270
Vrm
s
19
V/100
W 88.9%
Furthermore, every converter has their best performance
when working at particular input and output conditions.
Although the input and output conditions for the converters in
the table are not the same, we have two criteria to compare
their performances. First, for a given power level, the lower
the output voltage of the converter, the lower the efficiency it
gets due to more current flowing in the circuit. Second, for
PWM converters, the fewer semiconductor devices used in the
converter, the lesser the con-duction and switching loss of the
converter will be. However, the operational parameters,
selection of switching frequency, and semiconductor will also
impact on the circuit efficiency. Therefore, it is hard to have a
fair efficiency comparison and, hence, circuit efficiencies
shown are just for the information pur-pose. Nevertheless,
apart from the efficiency, the performances on reducing the
bus voltage, the step-down ratio and circuit complexity are
less dependent on the input and output condi-tions, and
operational parameters, but the topology itself and the
inductance ratio. From the table and excluding all the isolated
converters, it can be seen that the proposed converter is able to
achieve the lowest bus voltage at high-line condition with low
output voltage and probably higher efficiency among all trans-
formerless topologies and its structure is simpler. In addition,
comparing with [10], [18] at low-line condition, the proposed
converter is also able to achieve the lowest bus voltage at
around 33.5 V with positive output voltage and probably
higher effi-ciency. Thus, the proposed converter has better
performance for lower output voltage operation.

VI. CONCLUSION

The proposed IBuBuBo single-stage ac/dc converter has
been experimentally verified, and the results have shown good
agree-ments with the predicted values. The intermediate bus
voltage of the circuit is able to keep below 150 V at all input
and output con-ditions, and is lower than that of the most
reported converters. Thus, the lower voltage rating of
capacitor can be used. More-over, the topology is able to
obtain low output voltage without high step-down transformer.
Owing to the absence of trans-former, the demagnetizing
circuit, the associated circuit dealing with leakage inductance,
and the cost of the proposed circuit are reduced compared with
the isolated counterparts. In addition, the proposed converter
can meet IEC 61000-3-2 standard, and provide both input
surge current and output short-circuit protec-tion. Thanks to
the direct power transfer path in the proposed converter, it is
able to achieve high efficiency around 89%.
REFERENCES

[1] Voltage and current stress reduction in single-stage power-
factor correction AC/DC converters with bulk ca-pacitor voltage
feedback, IEEE Trans. Power Electron., vol. 17, no. 4, pp.
477-484,Jul. 2002.
[2] Single phase power factor correction: A survey, IEEE Trans.
Power Electron., vol. 18, no. 3, pp. 749755, May 2003.
[3] Flyboost power factor correction cell and a new family of
single-stage AC/DC converters, IEEE Trans. Power Electron.,
vol. 20, no. 1, pp. 2534, Jan. 2005.
[4] A Single-Stage AC/DC con-verter With high power factor,
regulated bus voltage, and output voltage, IEEE Trans. Power
Electron., vol. 23, no. 1, pp. 218228, Jan. 2008.
[5] Practical design and evaluation of a 1 kW PFC power supply
based on reduced redundant power processing principle, IEEE
Trans. Ind. Electron., vol. 55, no. 2, pp. 665-673, Feb. 2008.

[6] Single-Stage AC/DC Boost: Forward converter with high
power factor and regulated bus and output voltages, IEEE
Trans. Ind. Electron., vol. 56, no. 6, pp. 21282132, Jun. 2009.
[7] Dynamic modelling and controller design for
a single-stage single-switch parallel boost-flybackflyback
converter, IEEE Trans. Power Electron., vol. 27, no. 2, pp.
816827, Feb. 2012.
[8] Design considerations for single-stage isolated power-factor-
corrected power supplies with fast regulation of the output
voltage, in Proc. IEEE Appl. Power Electron. Conf. Expo.,
1995, vol. 1,pp. 454458.
[9] New power factor correction AC-DC converter with reduced
storage capacitor volt-age, IEEE Trans. Ind. Electron., vol. 54,
no. 1, pp. 384397, Feb. 2007.
[10] Buckboost-type unity power factor rectifier with extended
voltage conversion ratio, IEEE Trans. Ind. Electron., vol. 55,
no. 3, pp. 11231132, Mar. 2008.
[11] Electrolytic capacitor-less, nonisolated PFC converter for
high-voltage LEDs driving, in Proc. IEEE Int. Conf. Power
Electron. and ECCE Asia, 2011, pp. 499506.
[12] Unity power factor isolated three-phase rectifier with two
single-phase buck rectifiers based on the scott transformer,
IEEE Trans. Power Electron., vol. 26, no. 9, pp. 26882696,
Sep. 2011.
[13] Implementation of an efficient transformerless single-stage
single-switch ac/dc converter, IEEE Trans. Ind. Electron., vol.
57, no. 12, pp. 40954105, Dec. 2010.
[14] Analysis and design of a tapped-inductor buckboost PFC
rectifier with low bus voltage, IEEE Trans. Power Electron.,
vol. 26, no. 9, pp. 26372649, Sep. 2011.
[15] Integrated buck-flyback converter as a high-power-factor off-
line power supply, IEEE Trans. Ind. Electron., vol. 55, no. 3,
pp. 10901100, Mar. 2008.
[16] Two buck choppers built-in single phase one stage PFC
converter with reduced DC voltage ripple and its specific
control scheme, in Proc. IEEE Appl. Power Electron. Conf.


Expo., 2008, pp. 13781383.
[17] Analysis and design of a single-phase ac/dc step-down
converter for universal input voltage, IET Electr. Power Appl.,
vol. 1, no. 5, pp. 778784, Sep. 2007.
[18] Integrated buckboost quadratic buck PFC rectifier for
universal input applications, IEEE Trans. Power Electron., vol.
24, no. 12, pp. 28862896, Dec. 2009.
[19] Resonance-assisted buck converter for offline driving of
power LED replacement lamps, IEEE Trans. Power Electron.,
vol. 26, no. 2, pp. 532540, Feb. 2011.
[20] Bridgeless high-power-factor buck con-verter, IEEE Trans.
Power Electron., vol. 26, no. 2, pp. 602611, Feb. 2011.
[21] An alternative to supply DC voltages with high power
factor, IEEE Trans. Ind. Electron., vol. 46, no. 4, pp. 703709,
Aug. 19


An Improved Full Bridge DC-DC Converter for On-
Board Electric Vehicle Battery Charging
Aswathi C P
1
, K.E.Lakshmiprabha
2
P G scholar, EEE Department, Karpaga Vinayaga college of engineering, Chennai, India
1

Associate Professor, EEE Department, Karpaga Vinayaga college of engineering ,Chennai, India
2

ABSTRACT
The battery charger plays the central role in the
development of electric vehicles. This project
focuses on the DC-DC converter for the electric
vehicle battery charger which is the second stage
of a two stage on board charger. The first stage
is a power factor correction rectifier used to
transform the 50Hz electrical quantities into DC
quantities with a good input power factor. The
second stage is a zero voltage switching full
bridge dc-dc converter which adjusts the levels
to the values required by the battery and
moreover provides a galvanic isolation. The
main objective of this project is to process and
deliver power efficiently, to minimize the
charger size, to reduce the switching losses, to
guarantee fast operation and to reduce the cost
of electricity drawn from utility.
Keywords: DC-DC converter, full bridge,
electric vehicle, zero voltage switching(ZVS),
battery charger
I. INTRODUCTION
Fossil fuels have been extensively used in past
several years and if this trend continues we would
end up completely exhausting them and it would
lead to a situation where we would face scarcity of
such fossil fuels. Use of electric energy for vehicles
is one of the alternative as well as ecological
solutions instead of using fossil fuels. Due to the
exhaustible oil reserves and harmful environmental
impacts of burning oil, it is essential to find
alternative energy sources in the field of
transportation. Alternative vehicle technologies to
replace conventional vehicles consist of electric
vehicles, hybrid electric vehicles (HEVs), plug in
hybrid electric vehicles (PHEV) or else commonly
called battery electric vehicles (BEVs), and fuel
cell vehicles (FCVs).
Battery Electric Vehicles (BEVs) refer to vehicles
propelled exclusively by electric motors. The
source of power stems from the chemical energy
stored in battery packs which can be recharged on
the electricity grid. The scope of such vehicles
strongly depends on the battery and battery charger
developments.
EV battery chargers can be classified as on-board
and off-board with unidirectional or bidirectional
power flow. Unidirectional charging limits
hardware requirements, simplifies interconnection
issues, and tends to reduce battery degradation. A
bidirectional charging system supports charge from
the grid, battery energy injection back to the grid,
and power stabilization with adequate power
conversion.
In order to make the charging easy, onboard
chargers have been developed. The charger should
to be able to plug into a socket and moreover, it
should to be a grid friendly in order not to pollute
the electrical network.
The most general charger topologies includes an
acdc converter with power factor correction (PFC)
[1] followed by an isolated dcdc converter. There
are many high efficiency full bridge dc-dc
converters [2]-[3] that can be used as the second
stage converter. Phase shifted gating scheme [4]-
[5] for full bridge dc-dc converter is most
commonly used. Soft switching for the switches is
achieved using an external inductor in addition to
the leakage inductance of the transformer and the
output capacitance of the switch. This converter
has many improvements [6]-[7] but these
improvements increase the number of components
and also losses.
Current fed topologies with capacitive output filter
naturally minimize diode rectifier ringing since the
transformer leakage inductance is effectively
placed in series with the supply side inductor .In
addition, high efficiency can be achieved with
ZVS, using pulse width modulation technique.



II. THE PROPOSED TWO STAGE BATTERY
CHARGER
The proposed on-board charger is shown in Fig.
1.The proposed charger consists of a front end
power factor correction converter and a second
stage full bridge dc-dc converter.

A. Front-End First Stage AC-DC PFC Rectifier
The interleaved PFC consists of two CCM boost
converters in parallel, which operate 180 out of
phase [ 8] [9] .The input current is the sum of the
inductor currents in LB1 and LB2. Since the
inductor ripple currents are out of phase, they tend
to cancel each other and reduce the input ripple
current.

B. Second Stage ZVS Full-Bridge DC-DC
Converter
The primary side of the second stage converter
consists of a full-bridge inverter. However, instead
of driving the diagonal bridge switches
simultaneously, the lower switches (Q3 and Q4)
are triggered at a fixed 50% duty cycle and the
upper switches (Q1 and Q2) are pulse width
modulated.

Fig 1.The proposed electric vehicle battery charger

This converter has six operating intervals. The
operating waveforms of full bridge dc-dc converter
with timing intervals are shown in Figure 2. The
operating intervals are determined by the ON/OFF
states of the four primary switches. In the analysis
that follows, the power semiconductor switches
have been modeled with parallel diodes and
parasitic capacitances. The rectifiers are assumed to
be ideal and the resonant inductor includes the
transformer leakage inductance.

Fig 2.Timing interval for full bridge dc-dc
converter

A. Interval 1
In interval 1, switches Q1 and Q4 are ON and Q2
and Q3 are OFF. The primary current flows
through Q1, resonant inductor L
R
, transformer
primary and Q4, which is shown in Fig.3.The rate
of change of current ( ) through L
R
depends
on the difference between the input voltage Vin
and the output voltage Vo. During this mode power
flows to the output through rectifier diodes D
R1
and
D
R4
and also energy is stored in L
R
. The resonant
inductor current using initial condition
= 0 is given by

Fig 3.Equivalent circuit for Interval 1

B. Interval 2
During Interval 2 the current through the inductor
L
R
does not reach zero on reaching the instant T2
and the rectifier diodes D
R1
and D
R4
are ON. At the
end of this interval,



The equivalent circuit for this interval is
as shown in the Fig.4.


C.Interval 3
At T2, Q3 turns ON and Q4 turns OFF. This toggle
time depends on the resonant delay that occurs
prior to Q2 turning ON. When Q3 is ON and Q4
OFF, the inductor current which flows through Q4
finds an alternate path by charging/discharging the
parasitic capacitances of switches Q4 and Q2 until
the body diode of Q2 is forward biased. Switch Q2
can be turned ON with ZVS if the resonant delay is
properly set. At T3 the complete energy stored in
is transmitted to the output and the current
becomes zero and the rectifier diodes D
R1
and D
R4

turn OFF. The resonant inductor current
using initial condition = is given by


D. Interval 4
In interval 4, switches Q2 and Q3 are ON and Q1
and Q4 are OFF. The primary current flows
through Q2, inductor L
R
, transformer primary and
Q3. The rate of increase of the current ( )
through L
R
is proportional to the difference
between the input voltage V
in
and the output
voltage Vo. In this mode power is transferred to the
output through output diodes D
R2
and D
R3
and
moreover energy is stored in L
R
. The equivalent
circuit for this interval is as shown in the Fig.6.


E. Interval 5
During Interval 5 the current through the resonant
inductor does not reach zero and the rectifier
diodes D
R3
and D
R4
are ON. The equivalent circuit
for this mode is shown in Fig.7


F. Interval 6
This interval is the negative equivalent of the
interval 3 as shown in Fig.8.

Fig 8.Equivalent circuit for Interval
III. SIMULATION
A.Simulation Without Power factor Corrector



The simulink circuit diagram of the system without
PFC is shown in Fig.9
.

Fig.9 Simulink circuit without PFC

B.Simulation With Power factor Corrector

Fig 10 Simulink circuit with PFC
Fig.10 illustrates the simulink circuit diagram of
the system with PFC. The power factor
measurement block is shown in Fig.11

Fig.11.Power factor measurement block

C.Simulation Results

Fig.12 Input voltage and current

Fig.13. Power factor corrector output voltage



Fig.14 Pulses to the ZVS converter

Fig.15 Voltage Across Transformer Primary Windings

Fig.16 Output DC Voltage across Full Bridge DC-DC
Converter

Fig.17 Input AC Voltage and Current without PFC

VII. CONCLUSIONS

The project presents an electric vehicle battery
charger using an improved ZVS full bridge dcdc
converter with capacitive output filter. The detailed
operating intervals were considered and the
simulation results were examined. The input power
factor with and without PFC has been discussed
and compared. The second stage of the proposed
charger attains soft switching for the full-bridge
primary switches, clamps the voltage across the
output rectifier to the output voltage and the current
through the rectifier diodes has a low ( ),
which helps to reduce reverse recovery losses.

REFERENCES
[1] B. S. Singh, B.N. ; Chandra, A. ; Al-Haddad, K.
; Pandey, A. ; Kothari, D.P. ; , "A review of
single-phase improved power quality AC-DC
converters," Industrial Electronics, IEEE
Transactions on vol. 50, pp. 962 - 981 2003.
[2] J. A. Sabate, V. Vlatkovic, R. B. Ridley, F. C.
Lee, and B. H. Cho, Design considerations for
high-voltage high-power full-bridge zero-
voltageswitched PWM converter, in Proc.
IEEE Appl. Power Electron.Conf. Expo., 1990,
pp. 275284.
[3] Y. Jang and M. M. Jovanovic, A new family
of full-bridge ZVS converters, IEEE Trans.
Power Electron., vol. 19, no. 3, pp. 701708,
May 2004.
[4] A. J. Mason, D. J. Tschirhart, and P. K. Jain,
New ZVS phase shift modulated full-bridge
converter topologies with adaptive energy
storage for SOFC application, IEEE Trans.
Jan. 2008.
[5] B.-Y. Chen and Y.-S. Lai, Switching control
technique of phase-shift controlled full-bridge
converter to improve efficiency under light-load
and standby conditions without additional
auxiliary components, IEEE Trans. Power
Electron., vol. 25, no. 4, pp. 10011012, Apr.
2010.
[6] G.-B. Koo, G.-W. Moon, and M.-J. Youn,
Analysis and design of phase shift full bridge
converter with series-connected two
transformers, IEEE Trans. Power Electron.,
vol. 12, no. 2, pp. 411419,Mar.2004.


[7] X.Wu, X. Xie, J. Zhang, R. Zhao, and Z. Qian,
Soft switched full bridge DCDC converter
with reduced circulating loss and filter
requirement,IEEE Trans. Power Electron., vol.
22, no. 5, pp. 19491955, Sep. 2007.
[8] L. Balogh ; R. Redl, "Power-factor correction
with interleaved boost converters in continuous-
inductor-current mode," in IEEE Applied
Power Electronics Conference and
Exposition,1993, pp. 168 174.
[9] M. M. Yungtaek Jang; Jovanovic, "Interleaved
Boost Converter With Intrinsic Voltage-
Doubler Characteristic for Universal- Line PFC
Front End," IEEE Transactions on Power
Electronics, vol. 22, pp. 1394 1401, July
2007.
ACKNOWLEDGEMENT
With deep gratitude and due regards I whole
heartedly and sincerely acknowledge with thanks
the opportunity provided to me by our respectful
guide ,Mrs. K.E.Lakshmiprabha, Assistant
Professor of the department, for her efforts and
very encouraging and proper guidance for the
completion of the project. I thank my parents for
their benevolence and blessings which stood me in
good stead during the course of the project.



A Comparative Study on Various Dc-Dc Converter
Configurations for Industrial Drives
D.Kanimozhi
1
, Prof K.Balakrishnan
2
PG Scholar, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
1
Professor , Karpaga Vinayaga College of Engineering & Technology, Chennai, India
2

ABSTRACT
A DC-DC converter consisting of resonant boost
converter followed by an LCL type Series Resonant
Converter (SRC) with isolation transformer and
capacitive output filter can provide ZVS (Zero
Voltage Switching) and hence high efficiency for all
load conditions. The load current in industrial drives
will vary from light load to full load. Usually the
efficiency of the drives will be maximum at full load.
It will be economical if the drive is designed to work
with high efficiency at all load conditions. The LCL
type series resonant converter consists of a bridge
inverter, LC resonant circuit, high frequency isolation
transformer and a diode bridge rectifier. The inverter
is switched to generate alternating current pulses in
primary, which will induce emf in secondary and the
emf is rectified and filtered to get constant dc for the
drive motor. Here another separate closed loop
control is employed by using PID control logic.

Keywords: Dc to Dc converter ,LCL type series
resonant converter ,zero voltage switching

I. INTRODUCTION
Power electronics is the field of electrical engineering
related to the use of emiconductor devices to convert
power from the form available from a source to that
required by a load. The load may be AC or DC, single-
phase or three-phase, and may or may not need isolation
from the power source [1-5]. The power source can be a
DC source or an AC source (single-phase or three-phase
with line frequency of 50 or 60 Hz), an electric battery, a
solar panel, an electric generator or a commercial power
supply [6-8]. A power converter takes the power
provided by the source and converts it to the form
required by the load. The power converter can be an AC-
DC converter, a DC-DC converter, a DC-AC inverter or
an AC-AC converter depending on the application
II COMPARISON OF VARIOUS DC DC
CONVERTER CONFIGURATIONS
1. fixed-frequency LCL SRC with an inductive output
filter
2. fixed frequency phase shifted ZVS PWM full bridge
converter
3. fixed-frequency LCL SRC with an capacitive output
filter
A. Fixed Frequency LCL SRC with an inductive
output filter:
This converter operates in lagging Power factor mode for
a very wide change in load and the supply voltage
variations.Thus facilitates ZVS for all the primary
switches. The peak current through the switches
decreases with load current and is approximately
clamped to the load current

B. Fixed frequency phase shifted ZVS PWM full
bridge converter
This converter has reduced peak current stresses
compared to a resonant converter. The ZVS for the
switches is realized by using the leakage inductance of
the transformer (together with an external inductor) and
the output capacitance of the switch.Although various
improvements have beensuggested for this converter , all
of them use the increased number of components and
suffer from one or another disadvantage (limited ZVS
range or high voltage ringing on the secondary-side
rectifier diodes or loss of duty cycle).
C. Fixed Frequency LCL SRC with capacitive
output filter
The converter operates in lagging powerfactor mode for a
very wide change in load and the supply voltage
variations, thus ensuring ZVS for all the primary


switches [9-10]. The peak current through the switches
decreases with load currentIn the case of first two
configurations, a snubber circuit is needed across the
output rectifier to clamp the voltage ringing due to diode
junction capacitance with the leakage inductance of the
transformer

III TWO STAGE APPROACH
LCL SRC with capacitive output filter has better
performance compared to other configurations, this
converter cannot alsomaintain ZVS for wide change in
input voltage and requires small Lr , which is very
difficult to realize in practice. Therefore, the proposed
solution is to boost the input voltage and then use the
LCL SRC with capacitive output filter as a second stage.
When this converter is operated with almost fixed input
voltage, duty cycle variation required is the least among
all the three converters. Thus, in this two-stage approach,
a ZVT boost converter generates approximately 100V as
the input (Vbus) to the resonant converter for the
specified input voltage (4060 V) while delivering the
output voltage of Vo =60V. This approach not only
achieves ZVS for all the switches but also simplifies the
design of Lr and Cs resonant components.

IV BLOCK DIAGRAM

The output voltage from the PV panel is given to the
ZVT boost converter.The stepped up voltage is then
given to the LCL series resonant converter.The resonant
tank in the LCL series resonant converter is series with
the load and act as a voltage divider.By changing the
frequency of the input voltage, the impedance of the
resonant tank will change.This impedance will divide the
input voltage with load.At resonant frequency maximum
gain obtained.The stepped up voltage is given to the
capacitive output filter and to the load.
V DC - DC CONVERTER
DC-DC converters are electronic devices used whenever
to change DC electrical power efficiently from one
voltage level to another. They are needed because unlike
AC, DC cannot simply be stepped up or down using a
transformer. In many ways, a DC-DC converter is the DC
equivalent of a transformer.Typical applications of DC
DC converters are where 24V DC from a truck battery
must be stepped down to 12V DC to operate a car radio,
CB transceiver or mobile phone; where 12V DC from a
car battery must be stepped down to 3V DC, to run a
personal CD player; where 5V DC on a personal
computer motherboard must be stepped down to 3V, 2V
or less for one of the latest CPU chips; where the 340V
DC obtained by rectifying 240V AC power must be
stepped down to 5V, 12V and other DC voltages as part
of a PC power supply;
P
in
= P
out
+ P
losses
Where Pin is the power fed into the converter, Pout is the
output power and Plosses is the power wasted inside the
converter.Of course if there is a perfect converter, it
would behave in the same way as a perfect transformer.
There would be no losses, and Pout would be exactly the
same as Pin.then say that:
V
in
. I
in
= V
out
.
Iout
Or by re-arranging, we get:
V
out
/V
in
= I
in
/I
out
In other words, if we step up the voltage we step down
the current, and vice-versa.Of course theres no such
thing as a perfect DC-DC converter, just as there are no
perfect transformers. So we need the concept of
efficiency, where:
Efficiency (%) = P
out
/P
in


Nowadays some types of converter achieve an efficiency
of over 90%, using the latest components and circuit
techniques. Most others achieve at least 80-85%, which
as you can see compares very well with the efficiency of
most standard AC transformers.

A.DIFFERENT TYPES OF DC - DC
CONVERTERS
There are many different types of DC-DC converter, each
of which tends to be more suitable for some types of
application than for others. For convenience they can be
classified into various groups, however. For example
some converters are only suitable for stepping down the
voltage, while others are only suitable for stepping it up;
a third group can be used for either.Another important
distinction is between converters which offer full
dielectric isolation between their input and output
circuits.
B. NON-ISOLATING CONVERTERS
The non-isolating type of converter is generally used
where the voltage needs to be stepped up or down by a
relatively small ratio (say less than 4:1), and there is no
problem with the output and input having no dielectric
isolation. Examples are 24V/12V voltage reducers,
5V/3V reducers and 1.5V/5V step-up converters.There
are five main types of converter in this non-isolating
group, usually called the buck, boost, buck-boost, and
Cuk and charge-pump converters
C.BOOST (STEP-UP) CONVERTER
The boost converter converts an input voltage to a higher
output voltage. The boost converter is also called a step-
up converter. Boost converters are used in battery
powered devices, where the electronic circuit requires a
higher operating voltage than the battery can supply, e.g.
notebooks, mobile phones and camera-flashes. The
switch S, is turned on and off by a pulse-width-
modulated control voltage Vcont..When switch S is
closed, diode is reversed. Thus output is isolated. The
input supplies energy to the inductor i.e., the voltage
across L is equal to Vin and the current I
L
increases
linearly
When switch S is opened, the current I
L
flows through
the diode and charges the output capacitor C. Thus the
output stage receives energy from the input as well as
from the inductor. Hence the output across the load is
large. The function of the boost converter can also be
described in terms of energy balance. During the on-time
of the switch the inductance is charged with energy and
during the off-time of the switch this energy is
transferred from the inductor through the diode to the
output capacitor. Output voltage is maintained constant
by virtue of large C.
D. LCL Type Series Resonant Converter
There are two types of high frequency resonant
convertors; series resonant and parallel resonant. While a
series resonant convertor has a problem on voltage
regulation, parallel resonant convertors have lower
efficiency due to reduced circulating currents. The main
advantages of resonant convertor operating in the above
resonance (lagging power factor) is that the circuit will
not require lossy snubber and di/dt limiting inductors. A
dc/dc high-frequency link LCL-type series resonant
converter suitable for operation above resonance. Below,
the half bridge version is shown.The LCL resonant
converter will create a smooth sinusoidal wave from the
choppy square wave output from the switching circuit.
The LCL term refers to an arrangement of electrical
inductors and capacitors (wire coils and charged plates)
which filter and define the shape of the signal.
E. HIGH FREQUENCY TRANSFORMER
High-frequency (HF) transformer isolated, HF switching
dc-to- dc converters are suitable for this application due
to their small size, light weight, and reduced cost. To
increase their efficiency and to further increase the
switching frequency while reducing the size, cost, and
electromagnetic interference problems, soft-switching
techniques will be used in this paper. Due to the high
power requirement, an interleaved multi cell
configuration that uses three cells in parallel with each
cell being phase shifted by 120. Each cell shares equal
power and the thermal losses are distributed uniformly
among the cells. Also, the input/output ripple frequency
of three-cell configuration becomes three times the
input/output ripple frequency of each cell. There are three
major types of HF transformer isolated soft switching


converter configurations possible: 1) voltage fed resonant
converters 2) current fed resonant converters and 3)
fixed-frequency resonant transition zero-voltage
switching (ZVS) pulse width modulation (PWM) bridge
converters.
F. ENERGY EFFICIENCY
Energy consumption can be reduced if energy efficiency
is increased. In the end energy saved is the cheapest
energy. In turn, drive technology can help to improve the
energy efficiency of many production lines, as the energy
for nearly all process of production and materials
transport is provided by electrical drives. Also in the case
of hydraulically and pneumatically operated drives, the
basic energy source is an electric motor that powers the
hydraulic pump or the air compressor. Futher more there
are many ancillary processes in the infrastructure of a
plant that are also equipped with electrical drives.In order
to obtain drives with a high energy efficiency, there are
no quick solutions such as those available when buying a
fridge.
VI SOFT SWITCHING TECHNIQUES
There are two types of resonant soft switching depending
on whether the voltage across switch or the current
through switch is made zero.
A . Zero-Current Switching (ZCS)
A switch that operates with ZCS has an inductor in series
with it and a series blocking diode if the switch is bi-
directional. The switch is turned on with ZCS as the
series inductor slows down the rate of rise of current after
voltage across switch goes to zero. If a negative voltage
from a resonant circuit is made to appear across the
switch-inductor combination, then the current through
switch will naturally reduce to zero and switch is turned
off with ZCS.
B. Zero-Voltage Switching (ZVS)
A switch that operates with ZVS has an anti- parallel
diode and a capacitor across it. If negative current is
forced to flow through the antiparalle1 diode then voltage
across switch reduces to zero and then the switch is
turned on with ZVS. During turn-off the capacitor across
switch reduces the rate of rise of voltage across device as
current reduces to zero ZVS is preferred over ZCS
because with ZVS the parasitic switch capacitance
dissipates its energy into the load. If there were no ZVS
this parasitic capacitance would dissipate as heat in the
switch which lowers the efficiency of the system.In this
project, the converter employs another LC resonant
circuit designed to resonate at switching frequency so
that ZVS condition is achieved during both buck and
boost operating modes.
VII MODES OF OPERATION
A. Mode 1(Between ot0 and ot1)
Periodic switching of the resonant energy tank voltage
between +Vs/2 and Vs/2 generates a square-wave
voltage across the input terminal. Since the output
voltage is assumed to be a constant voltage Vo, the input
voltage to the full-bridge rectifier is Vo when iLr2 (t) is
positive and is Vo when iLr2 (t) is negative.

Fig.6.1 Equivalent circuit of Mode I

In this mode, the power switches are turned on naturally
at zero voltage and at zero current. Therefore, the current
through the active power switch is negative after turning
on and positive before turning off. Although the current
in the switches is turned on at zero voltage and zero
current to eliminate turn-on losses, the switches are
forced to turn off a finite current, thus allowing turn-off
losses exit. Fortunately, small Capacitors can be placed
across the switches to function as snubber in order to
eliminate turn-off losses.
B. Mode 2 (Between ot1 and ot2):
The cycle starts at ot1 when the current iLr1 resonant
tank resonates from negative values to zero. At ot2,
before the half-cycle of resonant current iLr1 oscillation
ends, switch S1 is forced to turn off, forcing the positive
current to flow through bottom freewheeling diode D2.


Fig6.2 .Equivalent circuit of Mode 2
Figure shows the equivalent circuit. The positive dc input
voltage applied across the resonant tank causes the
resonant current that flows through the power switch to
go quickly to zero.
C. Mode 3 (Between ot3 and ot4)
A turn-off trigger signal is applied to the gate of the
active power switch S1. The inductor current then
naturally commutates from active power switch S1 to
freewheeling diode D2. Mode III begins at ot3, then the
system is considered as unstable. The L indices are
calculated for all the load buses and the maximum of the
L indices gives the proximity to the system to voltage
collapse.

Fig.6.3 Equivalent circuit of Mode 3

When diode D2 is turned on, subsequently producing a
resonant stage between inductors Lr1, Lr2 and capacitor
Cr. Inductors Lr1, Lr2, and capacitor Cr resonate. Before
ot4, trigger signal vgs2 excites active power switch S2.
This time interval ends when iLr1 (t) reaches zero at
ot4. Figure shows the equivalent circuit.

D.Mode 4 (Between ot4 and ot5)
When capacitor voltage iLr2 is positive, rectifier diodes
DR1 and DR2 are turned on with zero-voltage condition
at instant ot4. Figure shows the equivalent circuit.
When inductor current iLr2 changes direction, rectifier
diodes DR1 and DR2 are turned off at instant ot5, and
Mode IV ends.

Fig6.4 .Equivalent circuit of Mode 4

When driving signal Vgs1 again excites active power
switch S1, this mode ends and the operation returns to
mode I in the subsequent cycle. During the positive half-
cycle of the inductor current iLr2, the power is supplied
to the load through bridge rectifier diodes DR1 and DR2.
During the negative half-cycle of the inductor current, the
power is supplied to the load through bridge rectifier
diodes DR3 and DR4.

VIII SIMULATION RESULT
A.GATE PULSES OF S1,S2,S3 AND S4

B.INPUT VOLTAGE AND CURRENT


C. OUTPUT VOLTAGE AND CURRENT

D. EFFICIENCY

E.INPUT RIPPLE CURRENT

F.OUTPUT RIPPLE CURRENT

IX.CONCLUSIONS
The loaded-resonant converter with a bridge rectifier is
developed for the application of dc-to dc energy con-
version. The circuit structure is simpler and less
expensive than other control mechanisms, which require
many components. The developed topology is
characterized by zero-voltage switching, reduced
switching losses, and increased energy conversion
efficiency. The project is done with the help of
MATLAB software.
REFERENCES
[1] A. P. Bergen, Integration and dynamics of a
renewable regenerative hydrogen fuel cell system,
Ph.D. dissertation, Dept. Mechanical Eng.,
Univ.Victoria, Victoria, BC, Canada, 2008.
[2] D. Shapiro, J. Duffy, M. Kimble, and M. Pien,
Solar-powered regenerative PEM electrolyzer/fuel
cell system, J. Solar Energy, vol. 79,pp. 544550,
2005.
[3] F. Barbir, PEM electrolysis for production of
hydrogen from renewable energy sources, J. Solar
Energy, vol. 78, pp. 661669, 2005.
[4] R. L. Steigerwald, High-frequency resonant
Transistor DC-DC converter,
IEEE Trans. Ind. Electron., vol. 31, no. 2, pp.
181-184 may 1984.
[5] R. L. Steigerwald, A Comparison of half-bridge
resonant converter topologies, IEEE Trans. Power
Electron., vol. 3, no. 2, pp. 174182,Apr. 1988.
[6] J. A. Sabate and F. C. Lee, Off-line application of
the fixed-frequency clamped-mode series resonant
converter, IEEE Trans. Power Electron.,vol. 1, no. 1,
pp. 3947, Jan. 1991.
[7] F. S. Tsai, J. Sabate, and F. C. Lee, Constant-
Frequency zero voltage switched,
clamped-mode parallel-resonant converter, in Proc.
IEEE Int.Telecommun. Energy Conf., 1989, pp. 17.
[8] A. K. S. Bhat, Fixed frequency PWM series-


Parallel resonant converter,
in Proc. IEEE Ind. Appl. Soc. Annu. Meet.,
1981 vol 1 pp. 11151121.
[9] A. K. S. Bhat, Analysis and design of a fixed-
frequency LCL-type series resonantconverter with
capacitive output filter, IEE Proc.: Circuits,Devices
Syst., vol. 144, no. 2, pp. 97103, Apr. 1997.
[10] A. K. S. Bhat, Analysis and design of LCL-type
resonant converter,IEEE Trans. Ind. Electron., vol.
41, no. 1, pp. 118124, Feb. 1994.



High Step-Up Single-Stage SCI Dc-Dc Converter Using
Pulse Width Modulation

R. Dhamodharan
1
, B. Paramaeswara Reddy
2
1
2
Dhamodharan5303@gmail.com
1
,Parameswarareddyborra@yahoo.in
2

ABSTRACT
In battery operated vehicles, the battery voltage has
to be stepped up to very high value to drive the
motor. Hence it is planned to build up a mainly
efficient high step up Switched Inductor Capacitor
(SIC) dc-dc converter for such applications. In SIC
converters, an LC-circuit with high quality factor (Q-
factor) is employed to increase the dc input voltage
to required high voltage level. For this, MOSFET
power switch is employed to make and break a high
current pulse through the inductance. When current
is made to flow through inductance, energy is stored
in inductance and when this current is cut the stored
energy in inductance is transferred to capacitance,
which results In a high voltage across capacitor.
Closed loop PID control is also povided to achieve the
desired output voltage.

Keywords: DCDC converter, resonant, single-stage,
switched-capacitor inductor
(SCI).Capacitor,inductor,Mosfet.

I. INTRODUCTION
The basic switched-mode dcdc converters counting
buck ,boost, buckboost, cuk, zeta, and sepic have been
used in various electronic application due to their many
compensation such as simple structure, excellent
performance, high efficiency, easy design, and simple
control circuit. The resonant converters such as single-
ended and bridge type are also very popular in the last
decade [1-4]. And the basic switched-capacitor (SC)
converters also have wide application as their advantages
of nonmagnetic components employed and small size
and high power density [5-8].

Fig1.1 Conventional SC/switched-inductor converter.

II.NEW FAMILY OF SCI CONVERTERS

Fig 2.1(a ) Dual-input step-up converter (b) Single-input step-up
converter. (c) Dual-input step-down converter. (d) Single-input step-
down converter. (e) Inverting step-up converter.


A family of SCI converters is shown in Fig. 2. Each of
the circuits uses only one active switch Q and a very
small resonant inductor Lr which is working to limit the
current peak caused by capacitor C1 when the switch Q
is turned ON. The two energy storage components C1
and L1 are alternately connected in parallel and series
according to different switching states. shows the dual-
input step-up converter member .The two energy storage
components C1 and L1 are charged in parallel by input
sources V1 and V2 , correspondingly, when switch Q is
turned ON, and discharging in series to output terminal
when Q is turned OFF. When the values of the inductor
L1 and the capacitor C1 both are large practically and the
switching regularity is high enough, the voltage across
the capacitor C1 can be regarded as constant and is equal
to the input voltage level V1 , and the current flowing
though L1 can be also regarded as constant. Based on
voltsecond equilibrium across L1 , the voltage level
association of the output and inputs. can be expressed as
VO = V1 +1(1 d)V2 (1) where d is the duty ratio of the
converter, V1 and V2 are input voltages, and VO is the
output voltage. . 2(b) shows the single-input step-up
converter member. It is actually the special version of the
dual-input step-up converter when its two input terminals
both are connected to the same power source Vin , i.e.,
V1 = V2 = Vin . Its voltage transfer relationship therefore
can be derived from (1) and expressed as VO =2 d (1
d)Vin . (2) Fig. 2(c) shows the dual-input step-down
converter member. Its two energy storage components C1
and L1 are charged in series by the difference levels of
the two input sources V1 and V2 when the switch Q is
turned OFF, and discharge in parallel to output terminal
when Q is turned ON. The situation for the normal
operation of this converter is that the level of V1 is higher
than V2 . Based on the same assumption ]p/ that L1 and
C1 both are large reasonably and the switching frequency
is high enough, the voltage across the capacitor C1 can
be regarded as constant and is the same as the output
voltage level VO . And the voltage level relationship of
the output and inputs can be also derived by using volt
second balance across L1 and then expressed as VO = V1
(1 d)V2 . (3)The single-input step-down converter
member shown in is the special version of the dual-input
step-down converter [see Fig. 2(c)] when its lower level
input terminal V2 is connected together with the output
terminal VO as the new output, i.e., V2 = VO . Its voltage
transfer relationship therefore can be derived from (3)
and expressed as VO =1(2 d)Vin . (4)In addition to
aforementioned members, the new family also includes
an inverting step-up converter member as shown in Fig.
2(e). When switch Q is turned ON, L1 and C1 are
charged in parallel and discharges in series when switch
is turned OFF. Therefore, the voltage across C1 is the
same as input voltage Vin . The voltage transfer
relationship also can be derived using the same method
abovementioned and expressed as VO = 1(1 d)Vin .
(5) However, there is no member in Fig. 2 that can
provide high step-down and inverting step-down output
levels.

Fig 2.2 Block diagram of converter circuit

III Modes of operation
The operation of the proposed converter is as follows:

I State1: Switch S and Diode D1 ON, Diode
D2 OFF (t0-t1)
II State2: Switch S ON Diodes D1 and D2 OFF
(t1-t2)
III State3: Switch S and Diode D1 OFF, Diode D2
ON (t2-t3)

STATE 1



Fig 3.1 STATE 1

state 1 : Working

When the switch is turned ON, diode D2 is reverse
biased and D1 is forward biased. The resonant inductor
Lr is connected in series with C1 to form a resonant tank.
The input voltage V1 is developed across the resonant
tank that causes the resonant current Ic1 gradually
increases from zero in a sinusoidal manner; C1 begins to
be charged and its voltage increases from its minimum
value.

STATE 2

2 Fig 3.2 STATE

STATE 2 Working

After the resonance stops, both the diodes are overturn
biased and the switch continues to conduct. The inductor
current Il1 continues to rise linearly through the switch.
Since there is no current flowing through C1, its voltage
is maintained at the maximum value.

STATE 3

Fig 3.3 STATE 3

STATE 3 Working

When switch is turned OFF, diode D2 is forward biased
and D1 is reversely biased.
The capacitor C1 , the inductor L1 , and input source V2
are connected in series and discharge the maximum
voltage to output Vo .

IV DETAILED ANALYSIS AND DESIGN
CONSIDERATIONS

There are two inductors employed in each converter
member of the new family, the energy transfer inductor
L1 and the resonant inductor Lr . The function of L1 is to
transfer energy while Lr is just used to limit the current
peak caused by the capacitor C1 when the switch Q is
turned ON. Specifically, when switch Q is turned ON, the
capacitor C1 begins to be charged or to discharge, the
charging or discharging current will soar to a very high
peak at the moment of Q being ON if there are not any
measures to limit it. For this reason, a small inductor Lr
is added and connected in series with C1 to form a
resonant tank with the resonant frequency
fO =1/2LrC1 during the switching ON period. With
the resonant inductor, the charging or discharging current
of C1 gradually increases from zero when switch Q is
turned ON. In order to ensure that the current changes
back to zero before switch Q is turned OFF, the switch
conduction time should be longer than half of a period of
the resonant frequency, i.e.,dTS1(where TS and d are
the switching cycle period and duty ratio, respectively).

A. State Analysis for the Dual-Input Step-Up
Converter


For all members of the new family of SCI converters,
there are three working states for each of them in one
period of switching cycle. Taking the dual-input step-up
converter member

Fig 4.1 waveform of dual-input step-up converter
VI. SIMULATION RESULTS

Fig. 6.1. Simulink diagram of proposed converter

fig 6.2 Source voltage v1 and v2

Fig 6.3 Source Currents I1 and I2

Fig.6.4 .Control signal waveforms



Fig.6.5.Output voltage and current waveforms
VII. CONCLUSIONS
A family of single-stage SCI converters with different
voltage gains has been proposed in this paper. The
proposed converters employ two energy transfer
components (one SC and one inductor) and do not use
the cascade method like conventional SC/switched-
inductor converters [9-14]. The energy stored in the two
components both directly come from input power sources
and then directly
been released to
output terminal.
This design can
meet the high
efficiency
requirement
with a simple
structure. A
resonance
method is used
in this paper to
limit the current
peak caused by
the SC. Detailed analysis and design considerations are
also introduced. Compared with traditional switched-
mode converters, the proposed converters can provide
higher or lower voltage gains and the switch stress is
lower. The family includes two dual-input members
which can be used in two power sources applications.
The simulation and experimental results of the converter
members [see Fig. 1(a) and (b)] confirm their
functionality and verify the theoretical analysis
presented. Furthermore, the measured results of
efficiency and voltage under different output power are
compared with conventional converters, which indicate
that the proposed step-up converters 1(a) and (b)] can
meet high efficiency and good voltage regulation. The
other members of the proposed family have also been
simulated and their operations have been confirmed. The
same conclusion can be made to other members of the
proposed family because of similar structure and the
same design philosophy [15]. Of course, there are also
some regrets for the family of converters. For instance,
the output voltage of the single-input step-up converter
member [see Fig. 2(b)] is always higher than twice the
input voltage and is only suitable for high voltage gain
applications. Similar problem is also found in the high
step-down member [see Fig. 3(a)]. In addition, there is no
member in the family that can provide both higher and
lower voltage levels than input voltage under different
duty ratios. However, all these regrets will be the
direction of the further.

REFERENCES
[1] K. W. Exchange, Classical Switched Mode and
Resonant Power Converter.Kowloon, Hong
Kong: Hong Kong Polytechnic Univ., 2002, pp.
1556.
[2] B. W. Williams, Basic DC-to-DC converters,
IEEE Trans. Power Electron.,vol. 23, no. 1, pp.
387401, Jan. 2008.
[3] Y. Ren, M. Xu, J. Sun, and F. C. Lee, A family
of high power density unregulated bus
converters, IEEE Trans. Power Electron., vol.
20, no. 5,pp. 10451054, 2005.
[4] K. W. E. Cheng and P. D. Evans, Parallel-mode
extended-period quasiresonant convertor, IEE
Proc.-B, vol. 138, no. 5, pp. 243251, Sep.1991.
[5] C. K. Tse, S. C. Wong, and M. H. L. Chow, On
lossless switched capacitor power converters,
IEEE Trans. Power Electron., vol. 10, no. 3,pp.
286291, May 1995.
[6] J. M. Henry and J. W. Kimball, Switched-
capacitor converter state model generator,
IEEE Trans. Power Electron., vol. 27, no. 5, pp.
24152425, May 2012.
[7] Y.Yuanmao and K. W. E. Cheng, Level-
shiftingmultiple-input switched capacitor


voltage-copier, IEEE Trans. Power Electron.,
vol. 27, no. 2, pp. 828837, Feb. 2012.
[8] K. W. E. Cheng, Zero-current-switching
switched-capacitor converters, IEE Proc.-
Electr. Power Appl., vol. 148, no. 5, pp. 403
409, Sep. 2001.
[9] E. H. Ismail, M. A. Al-Saffar, and A. J. Sabzali,
A family of single switch PWM converters
with high step-up conversion ratio, IEEE
Trans. Circuits Syst. I, Reg. Papers, vol. 55, no.
4, pp. 11591171, May 2008.
[10] B. Axelrod, Y. Berkovich, and A. Ioinovici,
Switched-capacitor/ switched-inductor
structures for getting transformerless hybrid
DCDC PWM converters, IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 55, no. 2, pp.
687696, Mar. 2008.
[11] A. A. Fardoun and E. H. Ismail, Ultra step-up
DCDC convert with reduced switch stress,
IEEE Trans. Ind. Appl., vol. 46, no. 5, pp. 2025
2034, Sep./Oct. 2010.
[12] Y.-P. Hsieh, J.-F. Chen, T.-J. Liang, and L.-S.
Yang, Novel high step-up DCDC converter
with coupled-inductor and switched-capacitor
techniques for a sustainable energy system,
IEEE Trans. Power Electron.,
vol. 26, no. 12, pp. 34813490, Dec. 2011.
[13] S. Xiong, S.-C. Tan, and S.-C. Wong, Analysis
and design of a high voltage- gain hybrid
switched-capacitor buck converter, IEEE
Trans. Circuits Syst. I, Reg. Papers, vol. 59, no.
5, pp. 11321141, May 2008.
[14] R. C. N. Pilawa-Podgurski, D. M. Giuliano, and
D. J. Perreault, Merged two-stage power
converter architecture with soft charging
switched capacitor energy transfer, in Proc.
IEEE Power Electron. Spec. Conf., 2008, pp.
40084015.
[15] J. C. Rosas-Caro, J. M. Ramirez, F. Z. Peng,
and A. Valderrabano, A DC-DC multilevel
boost converter, IET Power Electron., vol. 3,
no. 1, pp. 129137, 2010.



A High Efficiency ZCS-ZVS Buck Converter with
Coupled Inductor

Josna Ann Joseph
1
, S.Bella Rose
2

1
PG Scholar, Karpaga Vinayaga College of Engineering and Technology, Chennai
2
Professor, Karpaga Vinayaga College of Engineering and Technology, Chennai

ABSTRACT
A novel topology for a soft-switching buck dc dc
converter with a coupled inductor is proposed. The
soft-switching buck converter has advantages over
the traditional hard- switching converters. The
most significant advantage is that it offers a lower
switching loss. This converter operates under a
zero-current switching condition at turn on and a
zero-voltage switching condition at turn off. It
presents the circuit configuration with a least
components for realizing soft switching. Because of
soft switching, the proposed converter can attain a
high efficiency under heavy load conditions.
Likewise, a high efficiency is also attained under
light load conditions, which is significantly
different from other soft switching buck converters

Keywords: Buck converter, coupled inductor, soft
switching, zero-current switching (ZCS), zero-
voltage switching (ZVS).
I. INTRODUCTION
Buck converters are step-down DC-DC converters that
are widely being used in different electronic devices
like laptops, cell phones and also electric vehicles to
obtain different level of voltages. These converters are
nothing but, high frequency switching devices
operating on PWM principle. The need for a lighter
and smaller electronic devices propels the need for
reduced size of converters operating at higher load
currents. With all these inadvertent conditions the
switching frequency has jumped from KHz range to
MHz range.
The switching devices are made to turn on and turn off
the entire load current at high di/dt, and also withstand
high voltage stress across them. Due to these two
effects there is an increased power losses in these
converters and reduces the efficiency significantly.
High switching frequency can be used to drop sizes
and weights of converters. Still, if converters work
under hard-switching conditions, switching losses will
rise as switching frequency increases, and the total
efficiencies will collapse. Soft switching technologies
are the best techniques to diminish switching losses,
and improve efficiencies and reliabilities. Thus, the
sizes of heat sinks can be reduced. The total weights
and sizes of converters will also be reduced. There are
many methods to gather soft switching, and the most
common is using extra quasi-resonant circuits. By
adding auxiliary switches, capacitors and inductors,
zero-current-switching (ZCS) conditions or zero-
voltage switching (ZVS) conditions can be simply
achieved in quasi-resonant converters. But, high
current stresses and high voltage stresses for power
switches are also created. It is not favorable to select
the suitable rank of power switches, because there are
additional conduction losses when using higher
voltage power switches. Moreover, in some
converters, auxiliary switches work under hard-
switching conditions. Thus, additional power losses
will be produced. Due to auxiliary switches, the
control technique is more complicated than that of
conventional pulse width modulation converters, and
extra measuring circuits of voltage and current are
desired. Great amount of research is done to develop
soft-switching techniques in dcdc converters. In these
converters, it is desirable to control the output voltage
by pulsewidth modulation (PWM) because of its
simplicity and constant frequency. The switch is
turned off under ZVS condition, due to the small
leakage inductance of the coupled inductors, a small
voltage spike appears across the switch, and then, the
switch voltage rises slowly to its final value. Thus,
actually, the switch is turned off under almost ZVS
condition even though the spike peak is usually much
smaller than the switch maximum voltage [1].
The switching loss mechanisms include the current
and voltage overlap loss during the switching interval
and the capacitance loss during turn on. The diode
reverse recovery also causes an additional conduction
loss and further contributes to the current and voltage
overlap loss. Active or passive soft-switching methods
have been reported to reduce these switching losses.


Recently, passive soft switching has received renewed
inspection as a better alternative to active methods,
because they do not require an extra switch or
additional control circuitry. The two necessary
components that must be added to the circuit to
achieve passive zero-current turn on and zero-voltage
turn off are a small inductor and capacitor. The
inductor provides zero-current turn on of the active
switch and limits the recovery current of the diodes
while the capacitor provides zero-voltage turn off of
the active switch. Traditionally, the Inductor and
capacitor have been placed in series and parallel with
the active switch, respectively. However, many other
locations are possible and can lower the component
count and reduce switch stress.[2]
To create ZC condition for switch turn-on is to have a
snubber inductor in series with the switch or diode.
However, at turnoff, this inductor will cause a voltage
spike on the switch. Therefore, a pulse current source
is required to provide the output current, and, thus, the
switch can be turned off under ZC condition while
preventing the voltage spikes. To reduce the number
of circuit elements, the pulse current source path and
the required snubber inductor to decrease turn-on
losses can be combined for a buck converter. A pulse
voltage source can be applied to the snubber inductor
and create the required pulse current source at switch
turnoff.[3]
The pulsewidth modulation technique is praised for its
high power capability, fast transient response, and
ease of control. The pulsewidth-modulated (PWM)
dcdc converters have also been widely used in
industry. For minimization of size and weight,
increasing switching frequency in the PWM converter
is required. However, increasing switching frequency
will result in more switching losses and
electromagnetic interference (EMI). Recently, for
solving this problem, a number of soft-switching
PWM techniques are available, aimed at combining
required features of both the conventional PWM and
resonant techniques. The zero-voltage-switching
(ZVS) methods are necessary for the majority of
semiconductor devices such as MOSFETs, since the
turn-on loss produced by the output capacitance is
large. The zero-current-switching (ZCS) approaches
are suitable for the minority of carrier semiconductor
devices. [4].
In most soft-switching converters, efficiencies can be
improved significantly under heavy load conditions,
but as in [5] effects are not good under light load
conditions. It is generally because of additional power
dissipations of auxiliary circuit . To solve the low-
efficiency problem at a light load, based on a ZVS
converter, an improved soft-switching buck converter
with coupled inductor is proposed.

Fig. 1. Topology of the proposed ZCSZVS buck converter.

Fig. 2 . The theoretical current waveforms of L
1
, L
2
, and L
3
of the proposed converter

II. PRINCIPLE OF OPERATION

Fig. 1 shows topology of the proposed ZCSZVS
buck converter. In this topology, inductors L
1
and L
2

are coupled [6][7]inductors. S
1
and D
1
are the main
power switches, like a conventional buck converter.
D
2
is an extra diode. The theoretical current
waveforms of L
1
, L
2
, and L
3
of the proposed converter
at steady state are shown in Fig.2. The main switch S1
and the diode D1 are in off condition .The load current


is freewheeling through the D2. Because L3 is very
small, the current of L3 drops quicker than that of L1,
and also reduces to zero before S1 turns ON. It offers
the ZCS condition for S1. Due to snubber capacitor
Cr1, S1 can turn OFF under a ZVS condition. Cp1 is
the parasitic capacitance of the MOSFET S1.
Associated on the waveforms of the inductor currents,
one switching period is allocated into five intervals, as
shown in Fig.2, Equivalent circuits for each interval
are established. In Fig.2, k
ij
shows a slope of inductor
currents at a different mode, where i denotes the
number of the inductor and j represents the number of
the different operating mode. The detailed theoretical
analyses for each mode will be given as follows.
A. Mode 1 [t0t1]:
At t
0
, S
1
is triggered to conduct. Due to L
3
, i
s1
will
increase slowly, so S
1
can turn ON under a ZCS
condition. Resonance occur between L
3
and C
r1
.Then,
i
3
and i
1
will increase, and i
2
will go down. Since L
3
is
very small, the current-rising level of L
3
is larger than
L
1
. At t
1
, i
3
and i
1
are equal. It means that D
2
turns
OFF automatically, and this mode ends. Fig 3(a)
shows Equivalent Circuit of Mode 1.
B. Mode2 [t1t2 ]
At t1, i
3
and i
1
are identical, and both increase linearly
and i
2
is zero. In this mode, D
2
is always OFF, and the
branch of L
2
does not work. At t
2
, S
1
turns OFF, and
this mode ends. It is similar to a conventional buck
converter. Fig 3(b) shows Equivalent Circuit of Mode
2.
C. Mode 3 [t2t3]
This begins with turn-off of S1, and then a
resonance occurs between inductors (L
1
, L
3
), parasitic
capacitor C
p1
, and snubber capacitors C
r1
. C
p1
is
charged, and C
r1
is discharged at the equal time. When
the voltage across C
r1
diminishes to zero, D
1
will
conduct. Because C
p1
is very small, it can be
neglected. Fig 3(c) shows Equivalent Circuit of Mode
3.

D. Mode 4 [t3t4]:
At t3 D
1
conducts, then D
2
will
conduct.When D1 conducts , voltage across output
inductor changes polarity .Because indutors L1 and L2
are tightly coupled .The voltage Vd2 become
negetive.Then D2 begines to conduct.Fig 3(d) shows
Equivalent Circuit of Mode 4.

E. Mode 5 [t4t5]
In this mode S1 and D1 are OFF, then a small
resonance between L
3
and C
r1
occurs, in which i
3

oscillates around zero and the amplitude is pretty
small, so i
3
is supposed to zero in this mode.As shown
in Fig. 2, the current just flows through L
1
and L
2
, i.e.,
i1 is equal to i
2

(a)

(b)

(c)



(d)

(e)
Fig. 3. Equivalent circuits for each operation mode
of buck mode. (a) Mode 1, t0 t1 . (b) Mode 2, t1 t2 . (c)
Mode 3, t2 t3 . (d) Mode 4, t3 t4 . (e) Mode 5, t4 t5

A common method of controlling this type of
circuit is pulse width modulation (PWM), which
controls the power switch by applying a voltage signal
to its gate and varying its ON and OFF times. The
ratio of ON time to switching period is the duty cycle.
With pulse-width modulation control, the regulation of
output voltage is achieved by varying the duty cycle of
the switch, keeping the frequency of operation
constant. Duty cycle refers to the ratio of the period
for which the power semiconductor is kept ON to the
cycle period. Idea of coupled inductor to create soft
switching and L1 is the main inductor[8]-[11].
Coupled inductors are used extensively in electrical
applications. Their properties allow for increasing or
decreasing voltage and current, transferring
impedance through a circuit, and they can isolate two
circuits from each other electrically.
When the ideal switches of a dc-dc converter
are implemented using current unidirectional and/or
voltage-unidirectional semiconductor switches, one or
more new modes of operation known as discontinuous
conduction modes (DCM) can occur. The
discontinuous conduction mode arises when the
switching ripple in an inductor current or capacitor
voltage is large to cause the polarity of the applied
switch current or voltage to reverse, the current- or
voltage-unidirectional assumptions made in gathering
the switch with semiconductor devices are violated.
The DCM is commonly witnessed in dc-dc converters
and rectifiers, and can also sometimes happen in
inverters or in other converters containing two-
quadrant switches. The discontinuous conduction
mode typically occurs with large inductor current
ripple in a converter operating at light load and
containing current-unidirectional switches. Since it is
usually required that converters operate with their
loads removed, DCM is frequently encountered.
Indeed, some converters are purposely designed to
operate in DCM for all loads.

III. SIMULATION
A. Simulation Circuit Diagram
The SIMULINK model of the buck converter is
shown in the Fig.4 and PWM generation via
Matlab is shown in figure 6. The design
parameters are listed as follows: input
voltage=24V, output voltage=12V, switching
frequency=20 kHz.

Fig 4 Simulation circuit for the proposed system

Fig 5 PWM generation
B. Simulation Results
Detailed Matlab simulation studies are carried out to
verify the circuit, and to predict the performance of
the converter under various load conditions. Fig.6
shows the buck converter input voltage, figure 7
shows the output voltage and figure 8 shows the
output current of the ZCS-ZVS buck converter. Figure
9 shows the inductor current of the small inductor.
The current of the small inductor is discontinuous. The
inductor ripple current magnitude depend on the
chosen inductor value , input output voltages and


switching frequency of the converter. The inductor
ripple current does not depend on the load current.
When the output current reduces below the ripple
level , the inductor current can go negative .This
negative current discharges the output capacitor and
causes additional losses.

Fig 6 Input voltage of proposed converter

Fig 7 Output Voltage of Proposed Converter

Fig 8 Output Current of Proposed

Fig 9 Inductor Current (L
3
) of Proposed Converter
CONCLUSION
A soft-switching buck converter with coupled inductor
has been proposed. By making inductor L3 to work
under DCM, ZCS turn on and ZVS turn off for S1 are
achieved. The detailed theoretical studies of the
operating principle at steady state have also given.
Moreover, no auxiliary MOSFET is added in this
topology, so the control method is as simple as that of
a conventional buck converter.
REFERENCES
[1] Reza Amini and Hosein Farzanehfard Novel
Family of PWM Soft-Single-Switched DCDC
Converters With Coupled Inductors IEEE Trans.
on Ind. Electron.,, Vol. 56, No. 6, June 2009
[2] K. Mark Smith and Keyue Ma Smedley
Properties and Synthesis of Passive Lossless
Soft-Switching PWM Converters IEEE Trans.
Power Electron., Vol. 14, No. 5, September 1999
[3] E. Adib and H. Farzanehfard, Family of zero-
current transition PWM converters, IEEE Trans.
Ind. Electron., vol. 55, no. 8, pp. 30553063, Aug.
2008
[4] C.-M. Wang, A new family of zero-current-
switching (ZCS) PWM converters,IEEE Trans.
Ind. Electron., vol. 52, no. 4, pp. 11171125, Aug.
2005.
[5] Y. Zhang and P. C. Sen, A new soft-switching
technique for buck, boost,and buckboost
converters, IEEE Trans. Ind. Appl., vol. 39, no.
6,pp. 17751782, Nov./Dec. 2003
[6] H.-L. Do, Zero-voltage-switching synchronous
buck converter with a coupled inductor, IEEE
Trans. Ind. Electron., vol. 58, no. 8, pp. 3440
3447, Aug. 2011.
[7] W. Li, J. Xiao, J. Wu, J. Liu, and X. He,
Application summarization of coupled inductors
in DC/DC converters, in Proc. 24th Annu. IEEE
Appl.Power Electron. Conf. Expo. , Feb. 1519,
2009, pp. 14871491.
[8] W. Yu, J.-S. Lai, and S.-Y. Park, An improved
zero-voltage switching inverter using two coupled
magnetics in one resonant pole, IEEE Trans.


Power Electron., vol. 25, no. 4, pp. 952961, Apr.
2010.
[9] Y. Berkovich and B. Axelrod, Switched-coupled
inductor cell for DCDC converters with very
large conversion ratio, IET Power Electron.,vol.
4, no. 3, pp. 309315, Mar. 2011.
[10] M. R. Mohammadi and H. Farzanehfard, New
family of zero-voltagetransition PWM bi-
directional converters with coupled inductors,
912919, Feb. 2012.
[11] C.-T. Tsai and C.-L. Shen, Interleaved soft-
switching buck converter with coupled inductors,
in Proc. IEEE Int. Conf. Sustain. Energy Technol.,
Nov. 2427, 2008, pp. 877882.



A Novel Inverter with Virtual DC Bus for Non Linear Load
PV Power System

E.Nirmal kumar
1
S.kamalakkannan
2
1

Associate Professor, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
2

ABSTRACT
The DC/AC inverters are used in grid-coupled
Photovoltaic (PV) energy fabrication systems as
the power meting out interface between the PV
power source and the electric grid. Compared to
the grid-coupled PV inverters that have galvanic
separation (either on the DC, or on the AC
side),the transformer-less PV inverters have the
advantages of lower cost, higher efficiency,
smaller size and lower weight. In the transformer-
less topology, the common-mode (CM) ground
leakage current may emerge on the parasitic
capacitor between the PV panels and the ground.
The transformer-less inverter is anticipated with
virtual DC bus to condense the leakage current
and electromagnetic losses. The PIC
microcontroller generates all control signals which
regulates the output voltage of DC/AC inverter
.Closed loop MPPT control is also provided to
achieve the desired output voltage .

Keywords - Common mode current,
Transformer-less Inverter, Unipolar SPWM
Technique, Virtual DC Bus, photovoltaic.

I. INTRODUCTION
The distributed photovoltaic (PV) power fabrication
systems have received rising attractiveness in both
the commercial and housing areas. In most occasions,
the inverters are used to afford for the PV power into
the utility grid. It is essential for the PV inverter to be
of high efficiency, due to the relatively high price of
the PV panels. Small size is also firmly wanted for
the low-power and single-phase systems especially
when the inverters are installed indoor. In the
conventional grid-connected PV inverters, either a
line frequency or a high frequency transformer is
utilized to provide a galvanic separation between the
grid and the PV panels. Removing the isolation
transformer can be an valuable way out to enhance
the efficiency and condense the size and cost. If the
transformer is not there, the common-mode (CM)
ground leakage current may emerge on the parasitic
capacitor between the PV panels and the ground. The
continued existence of the Common Mode current
may condense the power transfer efficiency, enhance
the grid current distortion, weaken the electric
magnetic compatibility, and more essentially give
rise to the safety threats. The proposed scheme is to
develop an improved transformer-less inverter with
virtual DC bus to eliminate common mode leakage
current for a PV connected power system by using
unipolar sinusoidal pulse width modulation (SPWM).
Other transformerless inverter topologies: (a)
Karschny inverter [8] (b) paralleled-buck inverter [9]
(c) H6 inverter with capacitor voltage divider [10]
II. VIRTUAL DC BUS CONCEPT
The idea of the virtual DC bus is shown in fig 2.1. By
linking the grid neutral line straight to the negative
pole of the PV panel, the voltage across the parasitic
capacitance C
PV
is clamped to zero. This prevents any
leakage current flowing through it.With reference to
the ground point N, the voltage at midpoint B is
either zero or +V
dc
, according to the state of the
switch bridge. The intention of introducing the virtual
DC bus is to create the negative output voltage,
which is essential for the function of the inverter. If a
appropriate technique is used to transmit the energy
between the real bus and the virtual bus, the voltage
across the virtual bus can be kept identical as the real
one. The positive pole of the virtual bus is linked to
the ground point N, so that the voltage at the
midpoint C is either zero or V
dc
. The spotted line in


the fig 2.1 indicates that this link may be realized
directly by a wire or indirectly by a power switch.
With points B and C coupled jointly by a smart
selecting switch, the voltage at point A can be of
three different voltage levels, specifically +V
dc
, zero,
and V
dc
.Since the Common Mode current is
eliminated as expected by the configuration of the
circuit, there is no restriction on the modulation
scheme, which means that the superior modulation
technology such as the unipolar SPWM can be used
to persuade a variety of PV applications.

Fig.2.1 Virtual dc bus concept
III. DERIVED TOPOLOGY AND
MODULATION SCHEME
From the virtual DC bus idea, a new inverter
topology is derived as a model to show the merit of
the planned methodology, which is shown in Fig. 3.1.
It consists of five power switches S
1
S
5
and only one
single filter inductor L
f
. The PV panels and capacitor
C
1
form the real DC bus though the virtual DC bus is
provided by C
2
.With the switched capacitor
technology, C
2
is charged by the real DC bus through
S
1
and S
3
to maintain a constant voltage. This
topology can be modulated with the unipolar SPWM
.The investigation is introduced as follows.

Fig 3.1Proposed topology
A. UNIPOLAR SPWM
The unipolar SPWM waveform of the planned
inverter is shown in Fig. 3.2. The gate drive signals
for the power MOSFETs are generated according to
the comparative value of the modulation wave u
g

and the carrier wave u
c
. During the positive half
grid cycle, u
g
>0, S
1
and S
3
are turned ON and S
2
is
turned OFF, while S
4
and S
5
commutate
complementally with the carrier frequency. The
capacitors C
1
and C
2
are in parallel and the circuit
rotates between the states 1 and 2 as shown in Fig.
3.1. During the negative half cycle, u
g
<0, S
5
is
turned ON and S
4
is turned OFF. S
1
and S
3

commutate with the carrier frequency synchronously
and S
2
commutates in balance to them. Now the
circuit rotates between the states 3 and 2. At state 3,
S
1
and S
3
are turned OFF while S
2
is turned ON. The
negative voltage is generated by the virtual DC bus
C
2
and the inverter output is at negative voltage
level. At state 2, S
1
and S
3
are turned ON while S
2
is
turned OFF. The inverter output voltage V
an
equals
zero; for the moment, C
2
is charged by the DC bus
through S
1
and S
3
.


Fig 3.2 Unipolar SPWM for the proposed topology
IV OPERATION STATES OF TRANSFORMER-
LESS INVERTER
The various operation states of different
switches (S1-S5) are tabulated as below and are
illustrated in figs.4.1 to 4.4.
TABLE I Different states
STATES SWITCHES
S1 S2 S3 S4 S5
1 ON OFF ON ON OFF
2 ON OFF ON OFF ON
3 OFF ON OFF OFF ON
4 OFF ON OFF ON OFF
A. STATE I
In the positive half grid cycle, u
g
> 0, S
1
and S
3

are turned on and S
2
is turned off, while S
4
and
S
5
commutate complementally with the carrier
frequency. The capacitors C
1
and C
2
are in
parallel and the circuit rotates between state 1
and state 2
B. STATE II
In the negative half cycle, u
g
< 0,S
5
is turned on
and S
4
is turned off. S
1
and S
3
commutate with
the carrier frequency synchronously and S
2

commutates in complement to them.The circuit
rotates between state 3 and state2.
C. STATE III
At state 3, S
1
and S
3
are turned off while S
2
is
turned on. The voltage across capacitor C
2

generated by the virtual DC bus and the inverter
output voltage are at negative level.
D. STATE IV
At state 4, S
1
and S
3
are turned off while S
2
is
turned on. The inverter output voltage V
an
equals
zero, meanwhile C
2
is charged by the DC bus
through S
1
and S
3
.

Fig 4.1

Fig 4.2


Fig 4.3

Fig 4.4
Fig 4.1- 4.4 Operation states of transformer less-inverter

V. CURRENT PATH DURING
COMMUTATION
A derived topology main concept is to reduce the
common mode current path. Here the various current
paths of proposed topology during commutation is
shown clearly below. It has four states of operation
during the switching over of one state to other. This
current path has figured out clearly.
.

Fig 5.1 State 2

Fig 5.2 State 3

Fig 5.3 Transition state between 2 and 3
A simulink model of PIC microcontroller based
transformer-less Inverter with virtual DC bus concept
for a non linear load- solar power system is shown in
fig.6.1. Fig 6.2 and fig 6.3 shows the Input, Output
voltage and current waveforms of proposed system
respectively. The output of transformer-less inverter
with virtual DC bus concept is fed to non linear load
arrangement through a well developed
microcontroller based inverter drive system. The
better THD range of proposed topology is shown in
fig 6.4 .The gating signals for MOSFET based
transformerless inverter and firing pulses for the
inverter are shown in fig 6.5. Fig 6.6 and 6.7 shows
the reactive power generation and output voltage
waveform of proposed system.


Fig 6.1 Simulink model of proposed transformer-less
inverter

Fig.6.2 Input voltage and current waveforms of inverter

Fig.6.3 Output voltage and current waveforms of inverter

Fig 6.4 Total Harmonic Distortion

Fig 6.5 Unipolar SPWM Pulse Generation

Fig 6.6 Simulation waveform for reactive power
generation.



Fig 6.7 Output voltage waveform of inverter
VII. CONCLUSIONS
The idea of the virtual DC bus is proposed to resolve
the Common Mode Current difficulty for the
transformer-less PV-connected inverter. By linking
the negative pole of the DC bus straight to the grid
neutral line, the voltage on the stray PV capacitors
clamped to zero. This eliminates the Common Mode
current entirely. In the meantime a virtual DC bus is
formed to provide the negative voltage level. The
essential DC voltage is only half of the half bridge
result while the presentation in eliminating the CM
current is superior to the full-bridge-based inverters.
Based on this design, a new inverter topology is
projected with the virtual DC bus concept by
adopting the switched capacitor technology. It
consists of only five power switches and a single
filter inductor. The proposed topology is especially
fitting for the small-power single-phase applications,
where the output current is comparatively small so
that the extra current strain caused by the switched
capacitor does not cause severe stress for the power
devices and capacitors. With outstanding presentation
in eliminating the Common Mode current, the virtual
DC bus concept provides an exceptional key for the
transformer-less PV connected inverters.
REFERENCES
[1] R.W. Erickson and A. P. Rogers, A micro inverter for
building-integrated photovoltaics, in Proc. 24th Annu.
IEEE Appl. Power Electron. Conf. Expos., Feb. 1519,
2009, pp. 911917.
[2] Stefanos Saridakis, Eftichios Koutroulis IEEE Optimal
Design of Modern Transformer less PV Inverter
Topologies Department of Electronic and Computer
Engineering, Technical University of Crete, Chania,
GR-73100.
[3] Tarak Salmi, Mounir Bouzguenda, Adel Gastli and
Ahmed Masmoudi A Novel Transformer less
InverterTopologywithoutZeroCrossingDistortionInter
national journal of renewable energy research Tarak
Salmi et al., Vol.2, No.1, 2012.
[4] Eftichios Koutroulis, Frede Blaabjerg Methods for
the Optimal Design of Grid-Connected PV
InvertersInternationalJournalOf Renewable Energy
Research, IJRER E .Koutroulis, F.Blaabjerg , Vol.1,
No.2, pp.54-64 ,2011.
[5] M. Martino1, C. Citro, K.Rouzbehi, P. Rodriguez
Efficiency Analysis of Single-Phase Photovoltaic
Transformer-less Inverters European Association
fortheDevelopmentofRenewableEnergies,
Environment and Power Quality (EA4EPQ).
[6] Lars E. Norum, Fritz Schimpf Grid connected
Converters for Photovoltaic, State of the Art, Ideas
for Improvement of Transformer less Inverters
NORPIE/2008, Nordic Workshop on Power and
Industrial Electronics, June 9-11, 2008.
[7] Xiaoqiang Guo, Marcelo C. Cavalcanti, Alexandre
M. Farias, and josep M. Guerrero Single-carrier
ModulationforNeutral-Point-Clamped
InvertersinThree-phaseTransformerless
photovoltaic SystemsPowerElectronics for Energy
Conversation and Motor drive of Hebei province ,
Department of
ElectricalEngineering,,YanshanUniversity,Qinhuan
gdao
[8] K. Dietrich, German PatentWechselrichter: DE
19642522 C1, Apr. 1998.
[9] S. V. Araujo, P. Zacharias, and R. Mallwitz,
HighlyefficientsinglephaseTransformerlessinverter
sforgrid-con
nectedphotovoltaicsystems,IEEETrans. Ind.
Electron., vol. 57, no. 9, pp. 31183128, Sep. 2010.
[10] D. Barater, G. Franceschini, and E. Lorenzani,
Unipolar PWM for transformer-less grid-
connected converters in photovoltaic plants, in
Proc. Int.Conf. Clean Electr. Power, Jun. 911,
2009, pp. 387392.
www.ijrde.com


An Efficient Technique
using Quasi-Resonant Boost Half Bridge Converter
S.Revathi
PG Scholar, Karpaga Vinayaga College of
Assistant Professor, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
ABSTRACT
Isolated boost DC-DC converters are finding an
increase in demand in many applications such as
fuel cell, PV systems and hybrid electric vehicles.
The DC-DC converters should possess high
voltage conversion ratio as the output obtained
from a single PV panel or a fuel cell is low.
Isolated boost converter is best suit
step-up due to small input current ripple, low
diode voltage rating and lower transformer ratio.
Quasi-Resonant Boost Half Bridge (BHB)
converter is one of the most suitable candidates
for high-current and high step-up voltage. It
consists of two half bridge converters, a
transformer and an output side rectifier. The two
half bridge circuits convert the input DC voltage
to AC, to which the QR principle is applied so
that switching losses are reduced. The AC voltage
obtained is given to the high
transformer and the output of the transformer is
further given to rectifier and also filtered using
capacitors. External capacitors are additionally
added to the boost half bridge converter to
further reduce the switching losses.
Keywords: Isolated boost DC-DC converters
Quasi-Resonant Boost Half Bridge Converter
high frequency transformer, external capacitors

I. INTRODUCTION
Quasi-Resonant converters, a high efficiency
resonant tank circuit connected around the switch
(transistor or freewheeling diode) employed to shape
the switch current and voltage so that high voltage
are not presented simultaneously. As a result stress
and switching losses in the devices are greatly
reduced. Depending on the high frequency resonant
circuit is connected to the switch; the QRCs can be
either ZCS-QRC or ZVS-QRC.
Quasi resonant Boost Half Bridge (QRBHB)
converter is one of the most suitable candidates for
ISSN: 2279-0500 Special Issue
n Efficient Technique for High Step-Up Application
Resonant Boost Half Bridge Converter

Revathi
1
, Dhivya Assistant Professor
2
Karpaga Vinayaga College of Engineering & Technology, Chennai, India
, Karpaga Vinayaga College of Engineering & Technology, Chennai, India

DC converters are finding an
nd in many applications such as
fuel cell, PV systems and hybrid electric vehicles.
DC converters should possess high
voltage conversion ratio as the output obtained
from a single PV panel or a fuel cell is low.
Isolated boost converter is best suited for high
up due to small input current ripple, low
diode voltage rating and lower transformer ratio.
Resonant Boost Half Bridge (BHB)
converter is one of the most suitable candidates
up voltage. It
wo half bridge converters, a
transformer and an output side rectifier. The two
half bridge circuits convert the input DC voltage
to AC, to which the QR principle is applied so
that switching losses are reduced. The AC voltage
obtained is given to the high frequency
transformer and the output of the transformer is
further given to rectifier and also filtered using
capacitors. External capacitors are additionally
added to the boost half bridge converter to

DC converters,
Bridge Converter,
high frequency transformer, external capacitors.
Resonant converters, a high efficiency
resonant tank circuit connected around the switch
freewheeling diode) employed to shape
the switch current and voltage so that high voltage
are not presented simultaneously. As a result stress
and switching losses in the devices are greatly
reduced. Depending on the high frequency resonant
ected to the switch; the QRCs can be
Quasi resonant Boost Half Bridge (QRBHB)
converter is one of the most suitable candidates for
high-current and high step-up application. In this
project a Quasi-Resonant switching technique fo
Boost Half Bridge (BHB) with active clamping is
introduced by which the turn-off switching loss is
reduced significantly. Half Bridge Boost Converter
is used to obtain high step-up output. Use of two
Half Bridge circuit produces the double boost
output. Efficiency of the converter is improved by
incorporating the soft switching technique of Zero
Voltage Switching with the reduction of turn
losses.
Fig.1. Block diagram of proposed system

II. PROPOSED TOPOLOGY
The proposed QRBHB converter consists
input filter inductors, four MOSFET switches, and
two auxiliary capacitors at the low voltage side. The
topology is basically two high
transformers and one output side rectifiers
employed for isolation, step-up, and rectification
e: pp- 065-069
65 | P a g e
Up Application
Resonant Boost Half Bridge Converter
Engineering & Technology, Chennai, India
1

, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
2

up application. In this
Resonant switching technique for a
Boost Half Bridge (BHB) with active clamping is
off switching loss is
reduced significantly. Half Bridge Boost Converter
up output. Use of two
Half Bridge circuit produces the double boost
. Efficiency of the converter is improved by
incorporating the soft switching technique of Zero
Voltage Switching with the reduction of turn off

Fig.1. Block diagram of proposed system
PROPOSED TOPOLOGY
The proposed QRBHB converter consists of two
input filter inductors, four MOSFET switches, and
two auxiliary capacitors at the low voltage side. The
topology is basically two high-frequency
and one output side rectifiers which are
up, and rectification,


are connected in series so that the diode-voltage
rating becomes half of the output voltage.

Fig.2. Proposed boost half bridge converter

The use of separate clamp capacitors for each phase
helps mitigate, without the need for current sensors,
the current imbalance problem caused by volt
second imbalance between the two inductors.
Furthermore, owing to the capacitor connection at
both sides of the transformer, there must be no dc
offset in the magnetizing current. In the proposed
converter, capacitors Cr1 Cr4 are used to not only
limit transient-surge voltage caused by transformer
leakage inductance, but also resonate with the
resonant inductors Lr1and Lr2 during switch turn-on
process so as to reduce turn-off current. The
resonant frequencies of the tanks Lr1-Cr1and Lr1-
Cr2 are defined, respectively, by

f
r1
=
.
(1)
f
r2
=
.
(2)
Fig.3. shows key waveforms of the proposed
converter to illustrate the operating principle. The
two legs are interleaved with a 180 phase shift, and
the upper and lower switches of each leg are
operated with asymmetrical complementary
switching to regulate the output voltage.

Fig.3. Waveforms of the proposed converter
III. MODES OF OPERATION
1) Mode 1 operation: When applied voltage to the
circuit a current starts flowing the circuit. But the
switches will conduct only when gate pulses are
given. When voltage is given, current iL1 starts
flowing through the path Vi positive, L1, S2 (D),
Cr2, Cr1and negative. When current flows in this
manner the capacitors Cr1 and Cr2 will get charged.
The current from Cr1 is getting divided to S1 and
negative of Vi. The above current path for upper
side of the transformer. Lower side of the
transformer current iL2 is Vi positive, iL2 (Cr3 &
S3), Lr2, transformer primary, Cr3, negative of the
Vi.
Switch S2 and S3 are turned ON at the moment S1
is turned OFF and ends at the moment capacitor
voltage reflected in the secondary, n, vCr, becomes
greater than capacitor voltage vCo1. Each switch
carries both the input-inductor current and the
leakage-inductor current. The voltage across the
leakage inductor of the transformer is a difference
between an auxiliary capacitor voltage (Vcr1 or
Vcr2) and an output-capacitor voltage (Vco1, Vco2,
Vco3, Vco4) referred to the primary.


2) Mode 2 operation: In the proposed converter
capacitor Cr2 resonates with inductor Lr1. The
current flows from the L1, Lr1 transformer primary,
Cr2, S2, Cr1 and Vi negative. And the primary side
voltage is induced to the transformer secondary and
its rectified, filtered the output voltage in the output
side transformer. Second half bridge current path is
Vi positive, lower side transformer, Lr2, S3,
negative and its Cr3 discharging.
3) Mode 3 operation: During this mode, first half
bridge converter current path is Vi positive, L1, Lr1,
Cr1 and Cr2 discharging through the switch S2, S1
(Cq1) and Vi negative. In second half bridge,
current flows from L2 to Vi through the switch S3.
4) Mode 4 operation: In this mode, the switch S2 is
turned off and S1 is turned on. The capacitor is
discharging though the path Cr1, Lr1, S1 and
negative. Second bridge, the current flow is L2, Lr2,
Cr4, S4, Cr2 and negative. D3 and Co3 rectifier and
filters the output.
5) Mode 5 operation: The S1 is still conducting by
the source current. In bridge II, the current path is
L2, Lr2, S3 and negative.

Fig.4. Circuit diagram of mode 1 operation







IV. SIMULATION RESULTS
The proposed Quasi-Resonant Boost Half Bridge
converter is simulated using MATLAB/Simulink
software package. The voltage gain is obtained to be
8. The increase in efficiency is higher than the PWM
current fed isolated converter.
For an input voltage of 20V, at 50 KHz the output
voltage of 145V and the power of 212W are
obtained. Thus a voltage gain of 7.3 is achieved. The
input and output waveforms are shown in Fig. 12 &
Fig 13.

Fig.9. Simulation diagram of proposed system

Fig.10. Input voltage and current waveforms

Fig.11.Output voltage and current waveforms
V. CONCLUSIONS
This work explains a Quasi-Resonant Boost Half
Bridge converter. The proposed converter achieves
ZVS turn ON of switches and ZCS turn OFF of
diodes. The turn OFF current of switches is reduced
by the resonant operation. By adding an external
capacitor across the lower switches the switching
losses can be further reduced. High voltage gain and
efficiency can be obtained. The proposed system
achieves a voltage gain of 7.3 and an efficiency of
58% greater than the converter.

REFERENCES

[1] Pan Xuewei, Student Member, IEEE, and Akshay K.
Rathore, Senior Member, IEEE, Novel Interleaved
Bidirectional Snubber less Soft-Switching Current-Fed
Full-Bridge Voltage Doubler for Fuel-Cell Vehicles
IEEE TRANSACTIONS ON POWER ELECTRONICS,
VOL. 28, NO.12, DECEMBER 2013.

[2]Zhe Zhang, Member, IEEE, Ziwei Ouyang, Student
Member, IEEE, Ole C. Thomsen, Member, IEEE, and
Michael A. E. Andersen, Member, IEEE, Analysis and
Design of a Bidirectional Isolated DCDC Converter for
Fuel Cells and Super capacitors Hybrid System, IEEE


TRANSACTIONS ON POWER ELECTRONICS, VOL.
27, NO. 2, FEBRUARY 2012.

[3] Eung-Ho Kim; Bong-Hwan Kwon; , "Zero-Voltage-
and Zero-Current-Switching Full- Bridge Converter With
Secondary Resonance, Industrial Electronics., IEEE
Transactions on, vol. 57, no. 3, pp. 1017-1025, March
2010.

[4] Tsai-Fu Wu, Senior Member, IEEE, Yung-Chu Chen,
Jeng-Gung Yang, and Chia-Ling Kuo, Isolated
Bidirectional Full-Bridge DCDC Converter With a
Flyback Snubber, IEEE TRANSACTIONS ON POWER
ELECTRONICS, VOL. 25, and NO. 7, JULY 2010.

[5] H. Kim, C. Yoon, and S. Choi, An improved current-
fed ZVS isolated boost converter for fuel cell application,
IEEE Trans. Power Electron., vol. 25, no. 9, pp. 2357
2364, Sep. 2010

[6] J. Kwon and B. Kwon, High step-up active-clamp
converter with input current doubler and output-voltage
doubler for fuel cell power systems, Trans. Power

[7] S. Han, H. Yoon, G. Moon, M. Youn, Y. Kim, and K.
Lee, A new active clamping zero-voltage switching
PWM current-fed half-bridge converter, Trans. Power
Electron., vol. 20, no. 6, pp. 12711279, Nov.2005.
[8] R. Watson and F. C. Lee, A soft-switched, full-bridge
boost converter employing an active clamp circuit, in
Proc. IEEE Conf. Power Electronics., Spec. Conf., Rec.,
2005, vol. 2,pp. 2005.
[9] S. Y. (Ron) Hui and Henry S. H. Chung , Resonant
and Soft-switching Converters, Department of
Electronic Engineering, City University of Hong K ng,
Tat Chee Avenue, Kowloon,HongKon



A Novel PWM Technique for Integrated Boost
Resonant Converters

Rose Philip
1
, Prof A.Balamani
2

1
P G scholar EEE Department, Karpaga Vinayaga College of Engineering and Technology,Chennai, India

2
Professor and Head, EEE Department ,Karpaga Vinayaga College of Engineering and Technology,Chennai,
India

ABSTRACT
Effective photovoltaic power conditioning
requires well-organized power conversion and
accurate maximum power point tracking to
neutralize the effects of panel mismatch, shading,
and variation in power output during a daily
cycle.This project presents a unique method for
widening the input range of pulse-width
modulation (PWM) of integrated resonant
converters and it maintains high conversion
efficiency. The technique primarily unites
constant-on, constant off, and fixed-frequency
control depending on the required duty cycle.
With hybrid-frequency control, the circuit also
retains zero current switching for the output
diodes, minimizes switching loss, and eliminates
circulating energy at the transformer across the
entire operating range.

Keywords: PWM, ZVS, Integrated resonant
converter, MPPT, ZCS.

I. INTRODUCTION
Rising prices for traditional fossil fuel sources,
coupled with rapidly falling prices for poly-
crystalline silicon panels, has resulted in an
increased acceptance rate for PV systems. The
voltage obtained is less, so it has to be boosted up to
a high value for various applications. Here
Integrated Boost converter with closed loop control
is focused.
With the most primitive switched-mode power
converters, it became evident that higher frequencies
allow smaller L's and C's and this result in smaller,
lighter, and less costly systems. The down side to
moving to higher frequencies, however, are the
problems of greater vulnerability to parasitic
capacitance and leakage inductance, larger stress in
the switching devices, and increased EMI and RFI.
A typical DC-DC converter is encompasses of
active switches such as MOSFETs or IGBTs,
diodes, magnetic components for example inductors
and transformers, and static devices like capacitors.
Magnetic components are heavier and needs more
volume than any other parts in a power electronic
converter. The size of the magnetic components is
conversely proportional to the switching frequency
of the DC-DC converter. In order to decrease the
volume and weight of converter, higher switching
frequency must be chosen [1].
A resonant mode system proffers the potential of
obtaining the benefits while avoiding many of the
disadvantages of higher frequencies. With a
resonant circuit in the power path, the switches can
be arranged to operate at either zero current or
voltage points in the waveform, greatly reducing
their stress levels; the resonant sine wave minimizes
higher frequency harmonics reducing noise levels;
and since the circuit now needs inductance and
capacitance, parasitic elements may improve rather
than detract from circuit performance. With the
benefits power systems operating in the range of 500
kHz to 2.0 MHz are practical and in fact are already
being produced by a few pioneering
manufacturers[2].

A. Boost Converter
The boost is an acknowledged non-isolated power
stage topology, sometimes called a step-up power
stage. Power supply designers desires the boost
power stage because the needed output is always
more than the input voltage. The input current for a
boost power stage is unremitting, or non-pulsating,
because the output diode conducts simply during a
segment of the switching cycle. The output capacitor
provides the entire load current for the remaining of
the switching cycle.


A power stage can work in continuous or
discontinuous inductor current mode. In continuous
inductor current mode, current flows continuously in
the inductor during the whole switching cycle in
steady-state operation[3]. In discontinuous inductor
current mode, inductor current is zero for a segment
of the switching cycle. It begins at zero, achieves
peak value, and return to zero through each
switching cycle. It is advantageous for a power stage
to stay in only one mode over its expected operating
conditions because the power stage frequency
response alters significantly between the two modes
of operation.

B. Integrated Boost Resonant Converters
The boost action when integrated into the resonant
converter forms an integrated boost converter.
Allows the resonant action to add four primary
benefits:
1) The output diodes D1 and D2 attain zero current
switching (ZCS);
2) Switching loss in the primary-side MOSFETs is
equal to a standard synchronous boost;
3) The transformer has no circulating energy;
4) The resonant stage gain is fixed and equivalent to
the transformer turns ratio (1:n) [4].

II. OPERATION OF THE PROPOSED
SYSTEM
A. Block Diagram
The block diagram of the proposed system is shown
below. The system is having a closed loop control.
In other words it can be called as feedback control.
Feedback control increases the accuracy and the
robustness of the system. The input to the system is
small DC voltage at around 9v to 12v from solar
panel. In this project the maximum power point of
the solar panel is tracked using Perturb and
Observation technique.

The IBR circuit contains
1. Boost circuit consisting of an inductor
and four MOSFETs
2. Resonant circuit consisting of four
capacitors and leakage inductor[5].

The DC input to full bridge inverter is inverted to
AC and given to the primary of high frequency
transformer, it is then rectified using diode full
bridge and given to the load. The gate pulses to the
MOSFETs are given by the controller circuit, which
in turn is produced based on the difference between
the reference voltage from MPPT and IBRs output
voltage. While designing the hardware an opto-
coupler will be placed in between the controller and
the IBR circuit. This is done in order to isolate the
high voltage power circuit from low voltage
controller part.

Fig. 2.1 Block Diagram of proposed System

B. Circuit Topology

Fig. 2.2 Circuit Topology of proposed System

The circuit can operate in a wide range of duty cycle
which is automatically adjusted and hence switching
period can be changed continuously. Here the width
of the pulses given to the switches are varying
automatically based on the insolation to ensure
maximum power at the output. Both fixed frequency
control and variable frequency control ,based on
feedback is possible. Double bridge IBR circuit is
proposed for further improving the voltage gain.
The circuit has a boost part, which encompasses an
inductor and four switches. The resonant part
includes four capacitors namely C1, C2, C3 and C4
along with the leakage inductor. Because Q1, Q2
and Q3, Q4 are switched complementary to one


another, the input inductor L operates in the
continuous conduction mode (CCM) and under no
conditions becomes discontinuous. The inductor
current rises linearly during modes 3 and 4, and
decreases linearly during modes 1 and 2. The energy
transfer between the combinations of C1, C2 and
C3, C4 is resonant, occurring only during modes 1
and 3. Though the boost converter is integrated into
the resonant circuit, the two elements are effectively
decoupled as long as the resonant modes are allowed
to fully complete. Thus, the consequent voltage gain
is merely the product of a boost converter voltage
gain and the gain of the resonant stage.

Mode 1

Figure 2.3 Circuit for Mode 1 Operation

Beginning with the turn off of Q3 and Q4 preceding
to t
0
, the current in the input inductor L flows into
the body diode of Q1, discharging its parasitic
capacitance and charging C1 and C2.Therefore Q1
is turned ON under ZVS conditions at t
0
. The upper
input-side capacitor C1 starts resonating with the
transformer leakage inductance L
k
and the output-
side capacitors, C3 and C4, through D1and D2.
Once the transformer current resonates back to zero,
D1 and D2 prevents the continue resonating in the
reverse direction, ending mode 1. The length of
mode 1 is given by

Mode 2
Q1 and Q2 are still active, however it only conduct
the input inductor current. The resonant elements
conduct zero current during this interval. Mode 2
ends with the turn-off of Q1 and Q2 and later the
turn-on of Q3 and Q4.


Mode 3

After the turn-off of Q1 and Q2, but prior to the
turn-on of Q3 and Q4, the inductor current is still
charging the series combination of C
1
and C
2
,
through the body diode of Q1. When Q3 and Q4 are
turned ON, the body diode of Q1and Q2 are hard
commutated. At t
2
, C2 starts to resonate with L
k
and
the parallel combination of C3 and C4 , through the
diode D2 .Simultaneously, the inductor current rises
linearly through Q2.Once the transformer current
resonates back to zero, D2 blocks the continued
oscillation, marking the end of mode 3.

Mode 4


The inductor current continues to flow through the
lower device, increasing until Q3and Q4 turned off
and the circuit returns to mode 1.

III. CLOSED LOOP CONTROL
TECHNIQUE

The input voltage reference is generated by the
maximum-power-point tracking (MPPT) loop,
passing a reference to the input voltage control
loop[6].



Figure 3.1 Closed loop control technique

The usual output of the digital compensator is
the only required input to the hybrid-frequency
modulator, and the output works normally with a
PWM comparator that requires both a switching
period length and a value for the main switch on-
time [7]. Once the required on-time and the
maximum switching period are determined, each
individual duty ratio corresponds to one switching
period and on-time combination.

IV. SWITCHING PERIOD ANALYSIS
UNDER PROPOSED MODULATION

The converter operates in constant on-time control
for duty ratios less than 50% [8]. The converter

Figure 4.1 Switching Period Analysis Under Proposed
Modulation

operates in constant off-time control for duty ratios
greater than 50%. Thus along the designed operating
range, neither the on-time nor the off-time will
decrease below a specified minimum. The total
switching period, defined as the sum of the on-time
and off-time, reaches a minimum at 50% duty cycle,
reducing the ac flux density in the transformer. For
duty ratios outside the desired operating range, the
converter operates in fixed frequency [9].
TABLE 1

Table showing various T
sw
, T
on
and T
off

V. SIMULATION
A. Simulation Circuit
The figure below shows the simulation circuit of the
entire project showing solar panel [10] connected as
the input to the full bridge IBR circuit. The pulses to
the switches are generated through MATLAB
program[11].

Figure 5.1 Complete Simulation Circuit

A. Simulation Results

The various simulation results are given below. The
simulation result for input voltage from the solar
panel is shown in Fig 5.2.Its value is 11V.The
simulation result for primary side voltage of
transformer is shown in Fig.5.4 with 30V. The
secondary side voltage of transformer is shown in
Fig.5.5 with a value of 194V. The output voltage
across the IBR circuit is shown in the diagram
Fig.5.6.Its value is 193V. The simulation result for
output current of IBR circuit is shown in Fig.5.7,
with a value of 0.0193A. The pulses generated using
MATLAB program for the switches Q1 and Q2 is
shown in Fig.5.8.



Figure.5.2 Input Voltage from Solar Panel.

Figure.5.4 Primary Voltage of Transformer

Figure.5.5 Secondary Voltage of Transformer

Figure.5.6 Output Voltage of IBR Circuit.

Figure.5.7 Output Current of IBR Circuit

Figure 5.8 Pulses Generated for Q1

Figure 5.8 Pulses Generated for Q2 at various insolations.

VI. CONCLUSIONS

The small DC voltage from Solar Panel is boost up
to a high value using full bridge IBR circuit. Solar
panel is modeled with MPPT technique to ensure
maximum power is been obtained. The algorithm
uses fixed frequency, constant-on, and constant off
techniques depending on the required duty cycle.
Thus at high or low duty cycles, the converter
operates under fixed frequency control to limit the


maximum switching period and prevent magnetic
saturation. The closed loop control technique
developed thus provides a high voltage gain.

REFERENCES

[1] C.-A. Yeh and Y.-S. Lai,Digital pulse width
modulation technique for a synchronous buck
dc/dc converter to reduce switching
frequency, IEEE Trans. Ind. Electron., vol.
59, no. 1, pp. 550561, Jan. 2012.
[2] R Beiranvand, B.Rashidian,M.R.Zolghadri,
and S.M.H.Alavi, Optimizing the
normalized dead-time and maximum
switching frequency of a wide-adjustable-
range LLC resonant converter, IEEE Trans.
Feb. 2011.
[3] J.Sun,Small-signal modeling of variable
frequency pulse width modulators,IEEE
Trans. Aerosp. Electron. Syst., vol. 38, no.
3, pp. 11041108, Jul. 2002
[4] C.-E. Kim, G.-W. Moon, and S.-K. Han,
Voltage doubler rectified boost integrated
half bridge (VDRBHB) converter for
digital car audio amplifiers, IEEE Trans.
Power Electron., vol. 22, no. 6, pp. 2321
2330, Nov.2007
[5] Z. Liang, R. Guo, J. Li, and A. Q. Huang,
A high-efficiency PV module integrated
dc/dc converter for PV energy harvest in
FREEDM systems, IEEE Trans. Power
Electron., vol. 26, no. 3, pp. 897909, Mar.
2011.
[6] Simulation & Proposed Hardware
Implementation of MPPT controller for a
Solar PV system. International Journal of
Advanced Electrical and Electronics
Engineering, (IJAEEE)
[7] An Integrated Boost Resonant Converter for
Photovoltaic Applications., IEEE
TRANSACTIONS ON POWER
ELECTRONICS, VOL. 28, NO. 3, MARCH
2013
[8] Mathematical Modeling of Photovoltaic
module and simulation.
[9] M. H. Todorovic, L. Palma, and P. N. Enjeti,
Design of a wide input range dc-dc
converter with a robust power control scheme
suitable for fuel cell power conversion,
12471255, Mar. 2008.
[10] X.Wang, F. Tian, and I. Batarseh,
Highefficiency parallel post regulator for
wide range input dc-dc converter, IEEE
Trans. Power Electron., vol. 23, no. 2, pp.
852858, Mar. 2008.
[11] www.mathworks.com.
ACKNOWLEDGEMENT
With profound gratitude and due regards I whole
heartedly and sincerely acknowledge with thanks the
opportunity provided to me by my guide Prof A.
Balamani, Professor and Head, Department of
Electrical and Electronics Engineering, for his
painstaking efforts and very encouraging and proper
guidance without which this project could not have
been completed. I thank our various faculty
members and friends for their timely help and
guidance in one way or other which went a long way
in the completion of this project. The love and
support of family is irreplaceable in both life and
graduate education, I will be failing in duty if I dont
thank my parents for their benevolence and
blessings which stood me in good stead during the
course of the project.


Methods Enriching Power and Energy Development (MEPED) 2014 76 | Page

Energy Efficient Zeta Converter with Coupled
Inductor for PV Applications

S.Subasree
1
, Prof A.Balamani
2
1

Professor and Head, Karpaga Vinayaga College of Engineering & Technology, Chennai, India
2

ABSTRACT
Dual-stage micro-inverters are generally used in
grid-connected photovoltaic (PV) systems. The
high step-up DC/DC converter is essential for the
grid-connected micro-inverter because the input
voltage from a single solar panel is very small. A
DC/DC Zeta converter with coupled inductor
which operates at moderate duty ratios is
proposed. High voltage gain is achieved by
employing high turns ratio to coupled inductor.
The leakage-inductor energy of the coupled
inductor is efficiently recycled to the load by
additional capacitors and diodes and thus
efficient energy-conversion is possible. The stress
on the active switch is also restrained. The
proposed Zeta converter with coupled inductor
topology is simulated and the results are
obtained. The voltage conversion ratio of 8 is
obtained for the proposed converter. The
increase in efficiency in terms of power is 58.66%
when compared to the conventional PWM Zeta
converter.

Keywords: Zeta Converter, Coupled Inductor

I. INTRODUCTION
Due to the decrease in worlds fossil fuel energy and
its inability to meet the energy demand in the near
future has lead to the use of renewable energy. As
the worlds photovoltaic (PV) market is growing
rapidly, the role of grid-connected PV systems in
distribution energy systems will become important,
and the PV inverter will also play an irreplaceable
role in this increasing market. The ac module, which
has been proposed to improve these problems, is
called the micro-inverter. Solar micro-inverter is an
inverter integrated to each solar panel module. The
dual-stage micro-inverter combines a high step-up
DC/DC converter and DC/AC inverter. By using
this dual-stage micro-inverter we can achieve
efficiency as high as the conventional PV string-
type inverter. The DC/DC converters used in the
dual-stage micro-inverter of the grid-connected PV
systems require high step-up voltage conversion.

Fig.1. Dual-Stage Micro Inverter

II. CONVENTIONAL PWM ZETA
CONVERTER

The pulse width modulation (PWM) Zeta converter
is a step up/down converter of non- inverting
polarity type and it can be designed to achieve low-
ripple output current with separate inductors
[1]
. Zeta
converter is used in power factor correction and
voltage regulation designs. The conventional Zeta
converter is configured of two inductors, a series
capacitor and a diode
[2]
. The most common
operating modes of these PWM converters are the
continuous inductor current mode (CICM or CCM)
and discontinuous inductor current mode (DICM or
DCM).
A. Continuous Conduction Mode
In CCM mode the switch has two sub-intervals in a
switching period.
Considering,
D
1
- the switch-on duty cycle
D
2
- the diode-on duty cycle


Fig. 2 Circuit diagram of PWM Zeta Converter

Assuming 100% efficiency, the duty cycle, D
1
, for a
Zeta converter operating in CCM is given by
D
1
= Vo/ (V
i
+ Vo)
where, V
i
and Vo are the input and output voltages
of PWM Zeta converter. This can be rewritten to
obtain the output voltage of the converter in CCM
mode,

D
1max
occurs at V
i(min)
and D
1min
occurs at V
i(max)
.
The DC voltage conversion ratio of PWM Zeta
converter with CCM is obtained as,

B .Discontinuous Conduction Mode
In DCM the switching period is divided into three
sub-intervals. The third time interval of operation
cycle is non-zero, not that either inductor current is
discontinuous. The three distinct time intervals are
namely D
1
T
s
, D
2
T
s
and D
3
T
s
with D
1
+ D
2
+ D
3
=
1 for a constant switching frequency. D
3
is the
switch and diode off ratio. The output voltage of the
converter in DCM is

The DC voltage conversion ratio is obtained as

III. COUPLED INDUCTOR
The coupled inductor consists of two
separate inductors wound on the same core; they
typically come in a package with the same length
and width as that of a single inductor of the same
inductance value, only slightly taller. The price of a
coupled inductor is also typically much less than the
price of two single inductors. The windings of the
coupled inductor can be connected in series, in
parallel, or as a transformer. Most of the coupled
inductors have the same number of turns i.e., a 1:1
turns ratio but some newer ones have a higher turns
ratio. The coupling coefficient, K, of coupled
inductors is typically around 0.95, much lower than
a custom transformers coefficient of greater than
0.99
[3]

The leakage inductance of the coupled inductors can
be employed to control the diode current falling rate
and to alleviate the diode reverse-recovery
problem
[4]
. A coupled inductor with a lower-voltage-
rated switch is used for raising the voltage gain
(whether the switch is turned on or turned off)
[5]
.
Moreover, a passive regenerative snubber is utilized
for absorbing the energy of stray inductance so that
the switch duty cycle can be operated under a wide
range, and the related voltage gain is higher than
other coupled-inductor-based converters
[5]
.
By replacing the input inductors of DC/DC
converters with a cell formed by a coupled inductor
and a diode leads to a family of converters with high
voltage ratio
[6]
. The energy accumulated in the
leakage inductance is transferred to the load through
the diode. Thus the stress in the switch is also
significantly reduced
[7]
.

IV. ZETA CONVERTER WITH COUPLED
INDUCTOR

The circuit configuration of the proposed DC to DC
converter is shown in Fig 3. This topology is
basically derived from a conventional Zeta converter
by replacing the input inductor by a coupled
inductor. The turns ratio of the coupled inductor
increases the voltage gain
[8]
and the secondary
winding of the coupled inductor is in series with a
switched capacitor for further increasing the
voltage
[9]
. In Fig 3 S
1
is the floating active switch.
The primary winding N
1
of a coupled inductor is
similar to the input inductor of the conventional
boost converter, except that capacitor C
1
and diode
D
1
recycles the leakage-inductor energy from N
1
.


The secondary winding N
2
is connected with another
pair of capacitor C
2
and diode D
2
which recycles the
leakage inductor energy from N
2
. Now N
2
, C
2
and
D
2
all three are in series with N
1
. The diode D
3

connects to the output capacitor C
3
and load R.

Fig. 3.Circuit diagram of the proposed system

Certain assumptions are made for the simplification
of the circuit analysis.

1) All components are ideal, except for the
leakage inductance of coupled inductor.
2) The turns ratio n of the coupled inductor winding
is equal to N
2
/N
1
.
3) The ON-state resistance R
DS(ON)
and all parasitic
capacitances of the main switch S
1
are neglected.
The equivalent series resistance (ESR) of the
capacitors C
1
, C2 and C
3
and the parasitic resistance
of coupled-inductor are neglected.
4) The forward voltage drops of the diodes D
1
, D2
and D
3
are also neglected. The capacitors C
1
, C2 and
C
3
are sufficiently large that the voltages across
them are considered to be constant. The various
modes of operation for the proposed converter in
continuous-conduction mode (CCM) are described
as follows.

A. CCM Operation
Mode I [t
0
, t
1
]:
In the transition interval [t
0
, t
1
], switch S
1
and diode
D
2
conducts. The current flow path is shown in
Fig.4. The source voltage V
in
is applied on
magnetizing inductor L
m
and primary leakage
inductor L
k1
; meanwhile, L
m
also releases its energy
to the secondary winding, and also charges capacitor
C
2
along with the decrease in energy. Thus the
charging current i
D2
and i
C2
also decreases. The
secondary leakage inductor current i
Lk2
is declines
according to i
Lm
/n .This mode ends when the
increasing i
Lk1
equals the decreasing i
Lm
at t = t
1
.

Fig.4. Current flow path in Mode I
Mode II [t
1
, t
2
]:
In the interval [t
1
, t
2
], switch S
1
remains ON and
diode D
3
conducts. The source energy V
in
is series
connected with C
1
, C
2
, secondary winding N
2
, and
L
k2
to charge output capacitor C
3
and load R.
Meanwhile, magnetizing inductor L
m
is also
receives energy from V
in
. The current flow path is
shown in Fig.5. The i
Lm
, i
Lk1
, and i
D3
are increasing
because the V
in
is crossing L
k1
, L
m
and primary
winding N
1
. L
m
and L
k1
are storing energy from V
in
;
meanwhile, V
in
is also in series with N
2
of coupled
inductor and capacitors C
1
and C
2
are discharging
their energy to capacitor C
3
and load R, which leads
to increase in i
Lm
, i
Lk1
, i
DS
, and i
D3
. This mode ends
when switch S
1
is turned off at t = t
2
.

Fig.5. Current flow path in Mode II



Mode III [t
2
, t
3
]:
In the interval [t
2
, t
3
], switch S
1
is turned OFF and
only diodes D
1
and D
3
conducts. The current flow
path is shown in Fig.6. The secondary leakage
inductor L
k2
keeps charging C
3
when switch S
1
is
off. The energy stored in leakage inductor L
k1
flows
through diode D
1
to charge capacitor C
1
instantly
when S
1
turns off. The voltage across S
1
is the
summation of V
in
, V
Lm
, and V
Lk1
. Currents i
Lk1
and
i
Lk2
are rapidly declining, but i
Lm
is increasing
because L
m
is receiving energy from L
k2
. Once
current i
Lk2
drops to zero, this mode ends at t = t
3.

Fig. 6.Current flow path in Mode III
Mode IV [t
3
, t
4
]:
During the transition interval [t
3
, t
4
], the energy
stored in magnetizing inductor L
m
releases
simultaneously to C
1
and C
2
. The current flow path
is shown in Fig 7. Only diodes D
1
and D
2
are
conducting. Currents i
Lk1
and i
D1
are persistently
decreased because leakage energy still flows
through diode D
1
and continues charging capacitor
C
1
. The Lm is delivering its energy through the
coupled inductor and D
2
2
. The
energy stored in capacitors C
3
is constantly
discharged to the load R. Currents i
Lk1
and i
Lm
are
decreasing, but i
D2
is increasing. This mode ends
when current i
Lk1
is zero at t = t
4
.

Fig.7. Current flow path in Mode IV
Mode V [t
4
, t
5
]:
During the interval [t
4
, t
5
], magnetizing inductor L
m

is constantly transferring energy to C
2
. The current
flow path is shown in Fig 8, and only diode D
2
is
conducting. The i
Lm
is decreasing due to the
magnetizing inductor energy flowing continuously
through the coupled inductor to secondary winding
N
2
and D
2
2
. The energy stored
in capacitors C
3
is constantly discharged to the load
R. The voltage across S
1
is the summation of V
in
and
V
Lm
. This mode ends when switch S
1
is turned on at
the the next switching period.

Fig. 8.Current flow path in Mode V

The typical waveform of several major components
during one switching period is shown in Fig. 9.



Fig. 9. Typical waveforms of the proposed converter at
CCM operation
V. STEADY STATE ANALYSIS OF
PROPOSED CONVERTER IN CCM
For the simplification of the steady-state
analysis, only modes II and IV are considered for
CCM operation, and the leakage inductances at
primary and secondary sides are ignored.
From mode II;
v
Lm
= V
in

v
N2
= nV
in

From mode IV;
v
Lm
= -V
c1

-v
N2
= V
c2

By applying a volt-second balance on the
magnetizing inductor Lm we get,

= 0

= 0

By solving the above two equations the voltages
across C1 and C2 are obtained as
1

The output voltage during mode II is,
V
o
= V
in
+ V
c1
+ V
N2
+V
c2

1

The dc voltage gain M
CCM
can be found as follows:

1
1

Voltage gain (M
CCM
) as a function of duty ratio (D)
by various turns ratio (n) is represented by a graph
and the straightness of the curve accounts for the
correction between turns ratio n and duty ratio (D)
under the voltage gain M
CCM
= 8.

Fig. 10. M
CCM
as a function of D by various turns
ratios, and the turns ratio versus duty ratio under voltage
conversion is 8
The proposed Zeta converter with coupled inductor
turns ratio of n=3, which is basically derived from a
conventional PWM Zeta converter, is simulated
using MATLAB/Simulink software package. The
voltage gain is obtained to be 8. The increase in
efficiency is found to be 58% higher than the
conventional Zeta converter.
For an input voltage of 20V, at 50 KHz the output
voltage of 145V and the power of 212W are
obtained. Thus a voltage gain of 7.3 is achieved. The
input and output waveforms are shown in Fig. 12 &
Fig 13.


Fig. 11.Simulation Diagram of proposed Zeta converter
with coupled inductor

Fig.12. Input voltage and current waveforms

Fig.13.Output voltage and current waveforms

VII. CONCLUSIONS
This work explains a DC/DC Zeta converter with
coupled inductor for dual-stage micro inverter. The
turns ratio of the coupled inductor increases the
voltage gain and the secondary winding of the
coupled inductor is in series with a switched
capacitor for further increasing the voltage. The
energy of the leakage inductor of the coupled
inductor is recycled to the load by using additional
capacitors and diodes. Thus the voltage stress across
the active switch is restrained and hence low ON-
state resistance is obtained. The proposed system
achieves a voltage gain of 7.3 and an efficiency of
58% greater than the conventional Zeta converter.

REFERENCES

[1] T. F. Wu, S. A. Liang, and Y. M. Chen Design
optimization for asymmetrical ZVS-PWM Zeta
converter, IEEE Trans. Aerosp. Electron. Syst.,
vol.39,no.2,pp.521532,2003.

[2]Elena Niculescu, Dorina Mioara-Purcaru, Marius-
Cristian Niculescu, Ion Purcaru And Marian Maria
A Simplified Steady-State Analysis of the PWM
Zeta Converter Proceedings of the 13th WSEAS
International Conference on Circuits,pp.108-113.

[3]Jeff FalinCoupled inductors broaden DC/DC
converter usage, Analog Applications
Journal,Texas Instruments Incorporated pp. 10-
12,2010.

[4] R. J. Wai and R. Y. Duan, High step-up
converter with coupled inductor, IEEE Trans.
Power Electron., vol. 20, no. 5, pp. 1025
1035,2005.

[5] L. S. Yang, T. J. Liang, H. C. Lee, and J. F.
Chen, Novel high step-up dc-dc converter with
coupled-inductor and voltage-doubler circuits,
IEEE Trans. Ind. Electron., vol. 58, no. 9, pp. 4196
4206,2011.

[6] Qun Zhao and Fred C. Lee High-Efficiency,
High Step-Up DCDC Converters Ieee


Transactions On Power Electronics, Vol. 18, No.
1,pp.65-73,2003.

[7] B. Axelrod, Y. Berkovich, S. Tapuchi, and A.
Ioinovici, Steep conversion ration Cuk, Zeta, and
sepic converters based on a switched coupled-
inductor cell, in Proc. IEEE Power Electron. Spec.
Conf , pp. 30093014,2008.

[8] J. Falin,(2010) Designing dc/dc converters
based on ZETA topology, Analog Appl,pp.16
21,http://focus.ti.com/lit/an/slyt372/slyt372.pdf

[9] B. Axelrod, Y. Berkovich, and A. Ioinovici,
Switched-capacitor/ switched-inductor structures
for getting transformerless hybrid dc-dc PWM
converters, IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 55, no. 2, pp. 687696,2008.



DC- DC Buck Converter for Low Voltage High Current using
Three State Switching Cell

V.Vanitha
1
, Prof K.Balakrishnan
2
1

2

ABSTRACT
This paper presents a pulse width modulation dcdc
non isolated buck converter using three-state
switching cell, organized by two active switches, two
diodes, and two coupled inductors. One part of the
load power is processed by the active switches,
reducing the peak current through the switches to half
of the load current, as higher power levels can be
attained by the propose topology. The size of reactive
elements, i.e., inductors and capacitors, is also
decreased since the ripple frequency of the output
voltage is twice the switching frequency. Due to the
fundamental characteristics of the topology, total
losses are distributed between all semiconductors.
Another advantage of this converter is the
reduced region for discontinuous conduction mode
when compared to the conventional buck converter or,
in other words, the operation range in continuous
conduction mode is increased, as confirmed by the
static gain plot. The theoretical approach is detailed
complete qualitative and qualitative analyses by the
application of the three-state switching cell to the buck
converter operating in non overlapping mode (D
<0.5). Besides, the mathematical analysis and
development of an experimental proto type rated at 1
kW are carried out. The main experimental results are
presented and adequately discussed to clearly identify
its claimed advantages.

Key WordsBuck converter, DcDc converters,
three-state switching cell (3SSC).

I. INTRODUCTION
Pulsewidth modulation (PWM) dcdc converters are
widely employed in numerous applications, e.g., audio
amplifiers [1], uninterruptible power supplies [2],
fuel cell powered systems [3], and fork lift vehicles [4]In
order to dazed such limitation, several soft switching
methods have been introduced in the literature. Soft
switching is theoretical to reduce the overlap between
voltage and current during the commutation, and can be
classified in either active or passive methods, as one
must choose between the above-mentioned snubber
for a given application. Active methods can reduce
the switching losses by using auxiliary switches. As the
power rating increases, it is frequently required to
secondary converters in series or in parallel. By using
interleaving techniques in high current
applications, the currents through the switches become
just portions of the input current [11]. Interleaving
successfully doubles the switching frequency and also
partially cancels the input and output ripples, as the size
of the energy storage inductors and differential-mode
EMI filter in resulting operations can be reduced.
A. Continuous Conduction Mode
In CCM mode the switch has two sub-intervals in a
switching period Considering,
D
1
- the switch-on duty cycle
D
2
- the diode-on duty cycle

Fig 1(a) Buck Converter

D
1
= Vo/ (V
i
+ Vo)
where,
V
i
and Vo are the input and output voltages of buck
converter. This can be rewritten to obtain the output
voltage of the converter in CCM mode,

D
1max
occurs at V
i(min)
and D
1min
occurs at V
i(max)
. The DC
voltage conversion ratio of buck converter with CCM is
obtained as,


B .Discontinuous Conduction Mode

In DCM the switching period is divided into three sub-
intervals. The third time interval of operation cycle is
non-zero, not that either inductor current is discontinuous.
The three distinct time intervals are namely D
1
T
s
, D
2
T
s

and D
3
T
s
with D
1
+ D
2
+ D
3
= 1 for a constant switching
frequency.D
3
is the switch and diode off ratio. The output
voltage of the converter in DCM is

The DC voltage conversion ratio is obtained as

II. COUPLED INDUCTOR

The coupled inductor consists of two separate inductors
wound on the same core; they typically come in a package
with the same length and width as that of a single inductor
of the same inductance value, only slightly taller. The
price of a coupled inductor is also typically much less
than the price of two single inductors. The windings of
the coupled inductor can be connected in series, in
parallel, or as a transformer. Most of the coupled
inductors have the same number of turns i.e., a 1:1 turns
ratio but some newer ones have a higher turns ratio. The
coupling factor K, of coupled inductors is naturally
around 0.95, much lower than a tradition transformers
coefficient of greater than 0.99
.

The leakage inductance of the coupled inductors can be
working to control the diode current falling rate and to
improve the diode reverse-recovery problem. A coupled
inductor with a lower-voltage-rated switch is used for
floating the voltage gain (whether the switch is turned on
or turned off). Furthermore, a passive regenerative
snubber is employed for absorbing the energy of stray
inductance so that the switch duty cycle can be operated
under a wide range, and the related voltage gain is higher
than other coupled-inductor-based converters.
By replacing the input inductors of DC/DC converters
with a cell designed by a coupled inductor and a diode
leads to a family of converters with high voltage ratio.
The energy stored in the leakage inductance is transferred
to the load through the diode. Thus the stress in the switch
is also significantly reduced.

III. BUCK CONVERTER WITH COUPLED
INDUCTOR

Fig 3. Circuit diagram
The circuit configuration of the proposed DC to
DC converter is shown in Fig 3. This topology is basically
derived from a conventional buck converter by replacing
the input inductor by a coupled inductor. The turns ratio
of the coupled inductor increases the voltage gain and the
secondary winding of the coupled inductor is in series
with a switched capacitor for further increasing the
voltage. In Fig 3 S
1
is the floating active switch. The
primary winding N
1
of a coupled inductor is similar to the
input inductor of the conventional boost converter, except
that capacitor C
1
and diode D
1
recycles the leakage-
inductor energy from N
1
. The secondary winding N
2
is
connected with another pair of capacitor C
2
and diode D
2

which recycles the leakage inductor energy from N
2
. Now
N
2
, C
2
and D
2
all three are in series with N
1
.
In the proposed system, the dc supply can be obtained by
rectifying the standard 250V, 50Hz ac supply. So that the
converter can be directly operated from standard ac
supply. In this converter two power switches are
connected in parallel to primary of high frequency
transformer for large load currents. To achieve large step-
down voltage ratios the power switches are turned ON
and OFF alternatively with a time gap so that there will be
Four switching states.
State1: Switch1 ON, Switch2 OFF
State2: Both Switch OFF
State3: Switch1 OFF, Switch2 ON
State4: Both switch OFF
The desired output voltage is achieved efficiently using
PID closed loop control. The output is measured using R-
Load. The Voltage measurement block measures the
instantaneous voltage between two electric nodes. The
output provides a simulink signal that can be used by
other simulink blocks. The output of the system can be
seen through the scope.
A .MODE 1 OPERATION


Stage 1 [t0, t1]:
Initially, switch S1 is turned ON, while switch S2 is
turned OFF. The current through the inductor is divided in
two parts. The first part flows through T1 and D2 with
energy being delivered to the load. The second part flows
through T2 and S1. Current sharing is continued since the
number of turns for T1 and T2 is the same.

Fig 3(a) Circuit diagram of mode 1 operation
B. MODE 2 OPERATION
Stage2 [t1, t2]:
Switch S1 is turned OFF, while switch S2 remains OFF.
The voltage across inductor L is inverted. Diode D1 is
forward biased while D2 remains conducting. The energy
stored in L during the previous stage is then transferred to
the load. The current flows through T1T2, according to
the given polarity, what reasons the magnetic flow in the
primaryto be null. The current returns to the source
analogously to the preceding stage. This stage finishes
when S2 is turned ON.
Fig 3(b) Circuit diagram of mode 2 operation

Fig 3(c) diagram of mode 3 operation

C. MODE 3 OPERATION
Stage 3 [t2, t3]:
Due to symmetry of the circuit, this stage is similar to the
first one, although switch S2 is turned ON instead and S1
remains turned OFF. Diode D1 keeps conducting and D2
is reverse biased.
D. MODE 4 OPERATION
Stage 4[t3, t4]: Switch S1 is turned OFF, while switch S2
remains OFF. The voltage across inductor L is inverted.
Diode D1 is forward biased while D2 remains conducting.
The energy stored during the earlier stage is then
transmitted to the load. The current yields to the source
analogously to the previous stage. This stage varnishes
when S2 is turned ON.

Fig 3(d) Circuit diagram of mode 4 operation



IV.SIMULATION RESULTS

Fig 4(a) Input and output waveform of voltage and current
waveform

Fig 4(b) Efficiency waveform

Fig 4(c) Output waveform 1

fig 4(d) Output waveform 2

The proposed method can be seen as the integration of
the interleaving technique and three SSC. The following
expedient characteristics can be then addressed to the
introduced topology:
1) Reduced dimension, weight, and capacity of
magnetics, which are designed for twice the switching
frequency analogously to the interleaved buck converter.
2) The current stress through each main switch is equal
to half of the total output current, allowing the use of
semiconductors with lower current ratings.
3) Losses are spread among the semiconductors, leading
to better heat distribution and subsequently more efficient
use of the heat sinks.
4) Part of the input power, i.e., 50%, is directly
transferred to the load through the diodes and the coupled
inductors (autotransformers), and not through the main
switches. As a consequence, conduction and switching
losses are reduced. This is the main difference between
the functionality of this approach and that of the
interleaved buck topology.


5) The use of three SSC permits the parallel connection of
switches and, therefore, inexpensive power devices and
drives can be used.
6) Energy is transferred from the source to the load during
most part of the switching period, which is a distinct
characteristic of the proposed converter, since in other
buck type converters, it only occurs during half of the
switching period. As a consequence, reduction of current
peaks and also conduction losses are expected.
7) The drive circuit of the main switches becomes less
complex because they are connected to the same reference
node, what does not occur in the interleaved buck
converter.

V. CONCLUSION
A dcdc buck converter based on the 3SSC has been
attainable. When the 3SSC is employed the current is
distributed among the semiconductors. Furthermore, only
part of the energy from the input source flows through the
active switches, while the remaining part is directly
transferred to the load without being processed by these
switches, i.e., this energy is delivered to the load through
passive components, such as the diodes and the
transformer windings. Despite the increase in the number
of semiconductors, the current levels on these devices are
reduced, enabling the use of inexpensive switches and
simplified command circuits because the isolated drive is
not required like in the interleaved buck converter. In
front of these characteristics, its use is recommended for
high-power high-current applications where the
traditional approach may be inadequate, while good
current sharing is achieved. In addition, the overall losses
are distributed among all semiconductors ,reducing the
heat sink efforts. The reactive components operate with
twice the switching frequency, with significant
reduction in weight and volume of such components.
Considering the operation in NOM (D <0.5) and the same
ratings, the following characteristics can be addressed
with the3SSC-based converter if compared with the
conventional buck topology:
1) Augmented number of semiconductor elements
2) Operating area in CCM is wider
3) Ripple current through the inductor is reduced, in
addition to the currents through the switches
4) Reactive elements are designed for twice the switching
frequency, causing the required precarious inductance to
be smaller, for example;
5) only 50% of the power is delivered to the load through
the main switches due to the magnetic coupling between
the transformer winding. Besides, an significant
advantage of the proposed converter operating in OM (D
>0.5) is the continuous wildlife of the input current,
which is essentially discontinuous in the conventional
buck converter, what may lead to the use of an input filter
for some applications.

VI.REFERENCES
[1] M. Berkhout and L. Dooper, Class-D audio
amplifiers in mobile applications,IEEE Trans. Circuits
Syst. I, Reg. Papers, vol. 57, no. 5,pp. 9921002, May
2010.
[2] E. K. Sato,M. Kinoshita, Y.Yamamoto, and T.
Amboh, Redundant highdensity
high-efficiency double-conversion uninterruptible power
system,IEEE Trans. Ind. Appl., vol. 46, no. 4, pp. 1525
1533, Jul./Aug. 2010.
[3] S. V. Araujo, R. P. Torrico-Bascope, and G. V.
Torrico-Bascope, Highly efficient high step-up
converter for fuel-cell power processing based onthree-
state commutation cell, IEEE Trans. Ind. Electron., vol.
57, no. 6,pp. 19871997, Jun. 2010.
[4] Z. Amjadi and S. S. Williamson, Power-electronics-
based solutions for plug-in hybrid electric vehicle energy
storage and management systems,IEEE Trans. Ind.
Electron., vol. 57, no. 2, pp. 608616, Feb. 2010.
[5] G. Yao, Y. Shen,W. Li, and X. He, A new soft
switching snubber for the interleaved boost converters,
in Proc. 35th Annu. IEEE Power Electron. Spec. Conf.,
Jun. 2004, pp. 37653769.
[6] I.Matsuura, K. M. Smith, Jr., and K. M. Smedley, A
comparison of active and passive switching methods for
PWMconverters, in Proc. 29th Annu.IEEE Power
Electron. Spec. Conf., May 1998, vol. 1, pp. 94100.
[7] G. Hua and F. C. Lee, Soft-switching techniques in
PWM converters,IEEE Trans. Ind. Electron., vol. 42, no.
6, pp. 595603, Dec. 1995.
[8] K. Fujiwara and H. Nomura, A novel lossless passive
snubber for softswitching
boost-type converters, IEEE Trans. Power Electron.,
vol. 14,no. 6, pp. 10651069, Nov. 1999.
[9] D. S. Oliveira, Jr., C. E. A. Silva, R. P. Torrico-
Bascope, F. L. Tofoli,C. A. Bissochi, Jr., J. B. Vieira, Jr.,
V. J. Farias, and L. C. de Freitas,Analysis, design, and
experimentation of a double forward converter with soft
switching characteristics for all switches, IEEE Trans.
Power Electron., vol. 26, no. 8, pp. 21372148, Aug.
2011.


[10] J. P. Rodrigues, S. A. Mussa,M. L.Heldwein, and A.
J. Perin, Three-level ZVS active clamping PWM for the
dcdc buck converter, IEEE Trans.Power Electron., vol.
24, no. 10, pp. 22492258, Aug. 2009.
[11] Y. Jang and M. M. Jovanovic, Interleaved boost
converter with intrinsic voltage-doubler characteristic for
universal-line PFC front end, IEEE Trans. Power
Electron., vol. 22, no. 4, pp. 13941401, Jul. 2007.
[12] D. J. Perreault and J. G. Kassakian, Distributed
interleaving of paralleled power converters, IEEE Trans.
Circuits Syst. I, Fundam.Theory Appl., vol. 44, no. 8, pp.
728734, Aug. 1997.
[13] S. V. Araujo, R. P. Torrico- Bascope, and G. V.
Torrico-Bascope, Highly efficient high step-up
converter for fuel-cell power processing based on three-
state commutation cell, IEEE Trans. Ind. Electron., vol.
57, no. 6, pp. 19871997, Jun. 2010.
[14] S. V. Araujo, R. P. Torrico-Bascope, G. V. Torrico-
Bascope, and L. Menezes, Step-up converter with high
voltage gain employing three state switching cell and
voltagemultiplier, in Proc. Power Electron. Spec. Conf.,
2008, pp. 22712277.
[15] R. A. da Camara, C.M. T. Cruz, and R. P. Torrico-
Bascope, Boost based on three-state switching cell for
UPS applications, in Proc. Brazilian Power Electron.
Conf., 2009, pp. 313318.



A High voltage gain Dc-Dc Boost Converter Integrated with
Voltage Multiplier Module
K.Suganya
1
, M.Purushothaman
2
1

2

ABSTRACT
A new high step-up converter is projected for a
photovoltaic system. An asymmetrical interleaved
high step-up converter achieves high step up gain
through a voltage multiplier module. The voltage
multiplier module is organised by a conventional boost
converter and coupled inductors. A conventional boost
converter is incorporated to achieve a considerably
higher voltage conversion ratio. This configuration
reduces the current stress through each power switch.
And also constrains the input current ripple, which
decreases the conduction losses of MOSFETs. Since
the energy stored in leakage inductances is recycled to
the output terminal, the efficiency of the system is
improved.
Keywords - Asymmetrical Interleaved Converter,
Coupled Inductor, High step up, PV system, Voltage
multiplier module.

I. INTRODUCTION

Mounting energy shortage has valued the use of
renewable energy systems like PV system. But the energy
obtained from renewable systems is considerably low.
Thus, high step-up dc-dc converters are widely engaged
in many renewable energy applications [7]. Photovoltaic
systems are predicted to play an important role in future
energy creation [12]. These systems convert light energy
into electrical energy, and by using step-up converter they
transfer low voltage into high voltage.

II. CONVENTIONAL ASYMMETRICAL
INTERLEAVED CONVERTER
An asymmetrical interleaved converter is extensively
used for achieving high step-up conversion and for high-
power application [14]. A conventional boost converter
and two coupled inductors are located in the voltage
multiplier module, which is mounted on a boost converter
to form an asymmetrical interleaved structure. Primary
windings of the coupled inductors are engaged to reduce
the input current ripple, and secondary windings of the

coupled inductors are connected in series to lengthen the
voltage gain.

Fig.1. Circuit diagram of proposed system
The proposed converter operates in continuous
conduction mode (CCM). The duty cycles during steady
operation are interleaved with a 180 phase shift and it is
greater than 0.5


Mode 1 [t0, t1]: At t=t0, The power switches S1 and S2
are turned ON. Now all the diodes are reversed-biased
and the Magnetizing inductors Lm1 and Lm2 as well as
leakage inductors Lk1 and Lk2 are linearly charged by the
input voltage source Vin.

Mode 2 [t1, t2]: At t=t1, the power switch S2 is turned
OFF, therefore the diodes D2 and D4 are turned ON. The
energy stored in the magnetizing inductor Lm2 is


transferred to the secondary side and it charges the output
filter capacitor C3. The input voltage source, and the
energy stored in magnetizing inductor Lm2, leakage
inductor Lk2, voltage-lift capacitor Cb is discharged to
the output filter capacitor C1 through the diode D2,
thereby extending the voltage on C1 .

Mode 3 [t2, t3]: At t=t2, the diode D2 automatically turns
OFF because the overall energy stored in the leakage
inductor Lk2 is entirely released to the output filter
capacitor C1. The Magnetizing inductor Lm2 transfers
energy to the secondary side and it charges the output
filter capacitor C3 through the diode D4 until t3.

ON and all the diodes are turned OFF. Now all the diodes
are reversed-biased and the Magnetizing inductors Lm1
and Lm2 as well as leakage inductors Lk1 and Lk2 are
linearly charged by the input voltage source Vin.

OFF, therefore diodes D1 and D3 are turned ON. Now
the energy stored in the magnetizing inductor Lm1 is
transferred to the secondary side and it charges the output
filter capacitor C2. The input voltage source and the
energy stored in the magnetizing inductor Lm1 is
completely released to the voltage-lift capacitor Cb
through the diode D1, which supplies extra energy to Cb.

Mode 6 [t5, t0]: At t=t5, the diode D1 is automatically
turns OFF because the entire energy stored in the leakage
inductor Lk1 is totally released to voltage-lift capacitor
Cb. Now the magnetizing inductor Lm1 transfers energy
to the secondary side and it charges the output filter
capacitor C2 through the diode D3 until t0.

IV. VOLTAGE GAIN

From the equivalent circuit of the proposed
converter, the first phase converter is considered as a
conventional boost converter. Thus the voltage
derived from VCb can be expressed as,

(1)
When the power switch S1 is switched ON and the
power switch S2 is turned OFF, the voltage VC1 can
be derived from,

+

=

(2)
The energy transformation from the primary side
charges the output filter capacitors C2 and C3. When the
power switch S2 is in turn-on state and the power switch
S1 is in turn-off state, VC2 is equal to the induced voltage
of Ns1 and the induced voltage of Ns. And when the
power switch S1 is in turn-on state and the power switch
S2 is in turn-off state, VC3 is also equal to induced
voltage of Ns1 and the induced voltage of Ns2.


Fig.2. Modes of operation of the proposed system

Fig.3. Steady Waveform of the Proposed Converter at CCM

As a result, voltages Vc2 and Vc3 can be derived
from,

= .
1 +
(3)

Fig.4. Voltage Gain versus Turns Ratio n and Duty Cycle

The output voltage V
0
can be derived from,
(4)

The voltage gain of the proposed asymmetrical interleaved
converter is expressed as,

(5)


When the duty cycle is merely 0.6, the voltage gain reaches 10
at a turns ratio n of 1. The voltage gain reaches 30 at a turns
ratio n of 5.

V. SIMULATION CIRCUIT DIAGRAM

Fig.5. Simulation Circuit of the Proposed System


Fig.6.Voltage and Current Waveform of MOSFET S1 And S2

Fig.7. Voltage and Current Waveform of Diodes D1 And D2



Fig.8. Voltage and Current Waveform of Diodes D3 And D4

Fig.9. Voltage and Current at CCM

Fig.10. Voltage and Current Waveform of Proposed System

Fig.11. Efficiency Waveform of the Proposed System

VII. CONCLUSION

This paper has offered the principles, steady state
analysis, and experimental results for a proposed
asymmetrical interleaved converter. The proposed
converter has been successfully employed in an
efficiently high step-up conversion without an excessive
duty ratio. The interleaved PWM scheme decreases the
currents that pass through each power switch and
constrained the input current ripple. The experimental
results indicate that leakage energy is recycled through
capacitor Cb to the output terminal. The voltage stresses
over the power switches are also restricted. Higher
efficiency is obtained. Thus, the proposed asymmetrical
interleaved converter is suitable for PV systems and other
renewable energy applications which need high step-up
and high-power energy conversion.

REFERENCES
[1] W. Li,W. Li, X. He, D. Xu, and B.Wu, General derivation
law of non isolated high-step-up interleaved converters with
built-in transformer, IEEE Trans. Ind. Electron., vol. 59, no. 3,
pp. 16501661, Mar. 2012.
[2] W. Li and X. He, Review of Nonisolated high-step-up
DC/DC converters in photovoltaic grid-connected
applications, IEEE Trans. Ind. Electron., vol. 58, no. 4, pp.
12391250, Apr. 2011.
[3] R. J. Wai, W. H. Wang, and C. Y. Lin, High-performance
stand-alone photovoltaic generation system, IEEE Trans. Ind.
Electron., vol. 55, no. 1,
pp. 240250, Jan. 2008.


[4] S. K. Changchien, T. J. Liang, J. F. Chen, and L. S. Yang,
Novel high step-up DC-DC converter for fuel cell energy
conversion system, IEEE Trans. Ind. Electron., vol. 57, no. 6,
pp. 20072017, Jun. 2010.
[5] Y. P. Hsieh, J. F. Chen, T. J. Liang, and L. S. Yang, Novel
high step-up dcdc converter with coupled-inductor and
switched-capacitor techniques for a sustainable energy system,
Dec. 2011.
[6] S. M. Chen, T. J. Liang, L. S. Yang, and J. F. Chen, A
safety enhanced, high step-up dc-dc converter for ac
photovoltaic module application,
Apr. 2012.
[7] J. T. Bialasiewicz, Renewable energy systems with
photovoltaic power generators: Operation and modelling, IEEE
Trans. Ind. Electron., vol. 55, no. 7, pp. 27522758, Jul. 2008.
[8] W. Li and X. He, A family of isolated interleaved boost and
buck converters with winding-cross-coupled inductors, IEEE
Trans. Power Electron., vol. 23, no. 6, pp. 31643173, Nov.
2008.
[9] D.Wang, X. He, and J. Shi, Design and analysis of an
interleaved flyback forward boost converter with the current
auto balance characteristic, IEEE Trans. Power Electron., vol.
25, no. 2, pp. 489498, Feb. 2010.
[10] W. Li, Y. Zhao, Y. Deng, and X. He, Interleaved
converter with voltage multiplier cell for high step-up and high-
efficiency conversion, IEEE Trans. Power Electron., vol. 25,
no. 9, pp. 23972408, Sep. 2010.
[11] W. Li, Y. Zhao, J. Wu, and X. He, Interleaved high step-
up converter with winding-cross-coupled inductors and voltage
multiplier cells, IEEE Trans. Power Electron., vol. 27, no. 1,
pp. 133143, Jan. 2012.
[12] H. Ghoddami and A. Yazdani, A single-stage three- phase
photovoltaic system with enhanced maximum power point
tracking capability and increased power rating, IEEE Trans.
Power Del., vol. 26, no. 2, pp. 1017 1029, Apr. 2011.
[13] C. T. Pan and C. M. Lai, A high-efficiency high step-up
converter with low switch voltage stress for fuel-cell system
applications, IEEE Trans. Ind. Electron., vol. 57, no. 6, pp.
19982006, Jun. 2010.
[14] C. M. Lai, C. T. Pan, and M. C. Cheng, High-efficiency
modular high step-up interleaved boost converter for DC-micro
grid applications, IEEE Trans. Ind. Electron., vol. 48, no. 1,
pp. 161171, Jan/Feb. 2012.



An Efficient Power Management Technique by Integrating Bi-
Directional Inverter with Buck-Boost Converter
S. Suriya
1
, K.E. Lakshmiprabha
2

1
PG Scholar, Karpaga Vinayaga College of Engineering and Technology, Chennai, Tamilnadu, India
2
Assistant Professor, Karpaga Vinayaga College of Engineering and Technology, Chennai, Tamilnadu, India

ABSTRACT
A single-phase bi-directional inverter with two
buck/boost maximum power point trackers (MPPTs) for
DC distribution applications. In a dc-distribution system,
a bi-directional inverter is essential to control the power
flow between dc bus and ac grid, and to regulate the dc
bus to a certain range of voltages. Since the photovoltaic
(PV) array voltage can vary from 0 to 600 V, especially
with thin-film PV panels, the MPPT topology is formed
with buck and boost converters to operate at the dc-bus
voltage around 120 V, reducing the voltage stress of its
followed inverter. In the proposed system battery back-
up can be employed for PV for better stabilization. The
system can be tested with the help of MATLAB software
using Simulink.

Keywords- Maximum Power Point Trackers (MPPT),
BUCK/BOOST converter, Bi-directional inverter.

I. INTRODUCTION
Power electronics is the field of electrical engineering
related to the use of semiconductor devices to convert power
from the form available from a source to that required by a
load. The load may be AC or DC, single-phase or three-
phase, and may or may not need isolation from the power
source. The power source can be a DC source or an AC
source (single-phase or three-phase with line frequency of
50 or 60 Hz), an electric battery, a solar panel, an electric
generator or a commercial power supply. A power converter
takes the power provided by the source and converts it to the
form required by the load. The power converter can be an
AC-DC converter, a DC-DC converter, a DC-AC inverter or
an AC-AC converter depending on the application. There are
some renewable energy resources that have attracted the
researches over many years [1]-[3] such as photovoltaic,
wind, tidal and geothermal energy. Many transformer less
inverter topologies were proposed [5]-[7] to avoid leakage
ground current running through PV arrays and ground.
Recently a conventional two-stage configuration is usually
adopted in the PV inverter systems [4]. Renewable energy
sources are becoming increasingly important recently with
focus turning towards clean electricity generation. In
particular, photovoltaic (PV) or solar power systems are one
of the most promising and attractive renewable energy
sources due to their low operational and maintenance costs,
pollution free power generation, long life cycles, and noise
free operation. Prior to installation, performance and
efficiency of solar power conditioning systems have to be
evaluated. Moreover, experimental validation and
verification of solar power conditioning systems under a
wide range of different environmental and load conditions
have to be done.
Solar or PV cells are used to directly convert sunlight into dc
power. PV cells exhibit nonlinear output current-voltage
characteristic. This current-voltage curve is characterized
with a unique maximum power point (MPP) and depends on
environmental conditions (solar irradiance, cell temperature,
wind speed, etc) and PV cell fabrication material.
Accordingly, a maximum power point tracking (MPPT)
algorithm is required in solar power conditioning systems in
order to maximize the generated output power.
In addition battery backup is also employed for PV array for
better stabilization. So in this project it is proposed a MPPT
based power management system for parallel connected PV
arrays by integrating buck-boost dc-dc converter with single
phase inverter. Recently a new control strategy of limiting
the dc-link voltage fluctuation was developed [8] for a back-
to-back pulse width modulation converter in a doubly fed
induction generator (DFIG) for wind turbine systems.
For dc-micro grid applications, the grid connection and
rectification has to be fulfilled by the bidirectional inverter
to regulate the dc bus to a certain range of voltages. There is
some wide inductance variation during the operation of the
inverter. This will be normalized by designing controller and
selecting key components to make inverter normal operation.
This approach was proposed by Tsai-Fu Wu [9].
Recently a dc-bus voltage control with a three-phase
bidirectional inverter was proposed [10] which includes one
line-cycle regulation approach (OLCRA) and one-sixth line-
cycle regulation approach (OSLCRA) which take into
account dc-bus capacitance and control dc-bus voltage to
track a linear relationship between the dc-bus voltage and


inverter inductor current. There is a detailed operation
analysis, controller design, and realization of a high-power
bidirectional quasi-Z-source inverter (BQ-ZSI) for electric
vehicle applications was proposed recently [11]. A dedicated
voltage controller with feed-forward compensation was
designed to reject the disturbance and stabilize the dc-link
voltage during a non-shoot-through state. Recently a hybrid
electric vehicle (HEV) based on a bidirectional z-source
nine-switch inverter [12] was proposed to allow bidirectional
power flow.
A bidirectional buck-boost cascade inverter was proposed by
Honglin Zhou [13]. This proposed inverter has the features
like bidirectional operation with bipolar buck-boost output
voltage, reduced output distortion, reduced size and weight
with only one main energy storage component, decoupled
linear controller design and a good steady-state with
dynamic performance including wide operation range, strong
robustness to load and input voltage variations, fast dynamic
response, and good overload protection.
A circuit configuration, a circuit topological family, a buck-
mode active clamped circuit, and an instantaneous output
voltage feedback control strategy of
combined bidirectional buckboost dcdc chopper-
mode inverter with high-frequency (HF) link (HFL) were
proposed [14] recently. The circuit configuration is
composed of two identical isolated bidirectional buck-boost
dc-dc choppers with the same input and output filters.
The dc capacitors voltage unbalancing is the main technical
drawback of a Diode-Clamped Multilevel Inverter (DCMLI),
with more than three levels. A voltage-balancing circuit
based on buck-boost chopper connected to the dc link of
DCMLI is a reliable and robust solution to this problem. A
recent study was presented [15] with four different schemes
for controlling the chopper circuit to achieve the capacitor
voltages equalisation. These can be broadly categorised as
single-pulse, multi-pulse and hysteresis band current control
schemes.
II. SOLAR POWER
The solar cell is the basic unit of a PV system. An individual
solar cell produces direct current and power typically
between 1 and 2 W, hardly enough to power most
applications. Solar Cell or Photovoltaic (PV) cell is a device
that is made up of semiconductor materials such as silicon,
gallium arsenide and cadmium telluride, etc. that converts
sunlight directly into electricity. The voltage of a solar cell
does not depend strongly on the solar irradiance but depends
primarily on the cell temperature. PV modules can be
designed to operate at different voltages by connecting solar
cells in series. When solar cells absorb sunlight, free
electrons and holes are created at positive/negative junctions.
If the positive and negative junctions of solar cell are
connected to DC electrical equipment, current is delivered to
operate the electrical equipment.
Renewable energy sources are becoming increasingly
important recently with focus turning towards clean
electricity generation. In particular, photovoltaic (PV) or
solar power systems are one of the most promising and
attractive renewable energy sources due to their low
operational and maintenance costs, pollution free power
generation, long life cycles, and noise free operation. Prior
to installation, performance and efficiency of solar power
conditioning systems have to be evaluated. Moreover,
experimental validation and verification of solar power
conditioning systems under a wide range of different
environmental and load conditions have to be done.
Solar or PV cells are used to directly convert sunlight into dc
power. PV cells exhibit nonlinear output current-voltage
characteristic. This current-voltage curve is characterized
with a unique maximum power point (MPP) and depends on
environmental conditions (solar irradiance, cell temperature,
wind speed, etc) and PV cell fabrication material.
Accordingly, a maximum power point tracking (MPPT)
algorithm is required in solar power conditioning systems in
order to maximize the generated output power

III. MPPT ALGORITHM
The nonlinear current-voltage characteristic of PV cells is
characterized with a unique MPP, which is highly dependent
on weather and load conditions. An MPPT algorithm is an
analog or digital based technique allows the PV cell to
operate at the MPP at any given environmental conditions.
MPPT controllers or algorithms are integrated with solar
power conditioning systems to maximize the output power
extracted from PV generator. Various MPPT techniques
have been proposed including, perturbation and observation
(P&O), incremental conductance, fractional open-circuit
voltage, fractional short-circuit current, fuzzy logic
controller, neural network, ripple correlation control, and dc
link capacitor droop control.
The perturbation and observation method is the most
commonly implemented technique among other algorithms
although oscillations around the MPP can occur. In this
technique, the controller adjusts the output voltage of the PV
cell based on its instantaneous output power. The
incremental conductance algorithm uses the slope of the
power-voltage curve of the PV cell to determine the voltage
reference. The derivative of the cell output power with


respect to the cell output voltage at the MPP is zero. This
method requires more computations relative to the P&O but
may reach the MPP faster.
MPPT or Maximum Power Point Tracking is an algorithm
that included in charge controllers used for extracting
maximum available power from PV module under certain
conditions. The voltage at which PV module can produce
maximum power is called maximum power point (or peak
power voltage).Maximum power varies with solar radiation,
ambient temperature and solar cell temperature. The MPPT
system is shown in Fig. 1

Fig 1: MPPT system

The MPPT is responsible for extracting the maximum
possible power from the photovoltaic and feed it to the load
via the boost converter which steps up the voltage to
required magnitude. The main aim will be to track the
maximum power point of the photovoltaic module so that
the maximum possible power can be extracted from the
photovoltaic module. The incremental conductance
algorithms utilized for MPPT to increase the efficiency of
the system. The MPPT configuration check is shown in Fig.
2.

Fig 2: Flowchart of online MPPT configuration check
IV. P & O METHOD
The MPPT controller tracks the maximum output power of a
PV array based on the perturbation and observation tracking
method. At the beginning, the controller will determine the
operation mode of the proposed MPPT. When the MPPT is
operated in boost mode, inductor current iLm is equal to
output current iPV of the PV array; thus, the output power of
the PV array can be expressed as follows:
PPV boost(n) = vPV(n) iLm(n)

On the other hand, when the proposed MPPT is
operated in buck mode, inductor current iLm is equal to
output current io ; thus, the output power of the PV array can
be expressed as follows:

PPV buck(n) = vdc(n) iLm(n)

With this control algorithm, the controller tracks the peak
power by increasing or decreasing the duty ratio periodically.
In this studied PV inverter system, there is a shared auxiliary
power supply for the MPPTs and the inverter. Because the
switching frequencies of the MPPT (25 kHz) and the
inverter (20 kHz) are different, their switching noises might
affect the accuracy of voltage and current sampling,
especially under high-power condition. To avoid noise
interference, the MPPTs are synchronized with the inverter,


and the controller will update the duty ratio of the MPPT
power stage every ten line cycles at the zero crossing of the
line voltage. Additionally, since the single-phase PV inverter
system has a twice line-frequency ripple voltage on the dc
bus, this synchronization approach can also eliminate the
ripple voltage effect and determine accurate output power of
the PV arrays. When the output power of the PV arrays can
be determined accurately, the proposed controller can track
the maximum power point precisely.

Fig 3: Functional block diagram of proposed system

Here the solar cell is represented by a block named
Photovoltaic cell. The MPPT and gating signal generator
are shown in a single unit called MPPT with Gating Signal
During boost operation, a LC-circuit with high quality factor
(Q-factor) is employed to amplify the dc input voltage to
required high voltage level. Here, a MOSFET power switch
is employed to make and break a high current pulse through
the inductance. When current is made to flow through
inductance, energy is stored in inductance and when this
current is cut the stored energy in inductance is transferred
to capacitance, which results in a high voltage across
capacitor and this high voltage is filtered and fed to dc-bus.
During buck operation, the high dc voltage is chopped by
using a MOSFET power switch in series with a source and
then the resultant pulsating dc is filtered and fed to dc-bus. A
bidirectional inverter is also interfaced to dc bus which is
used for energy transfer from dc bus to ac grid and vice
versa. When the dc power is excess, the inverter is used to
convert excess dc power to ac power and inject to grid, and
when there is efficiency in dc power the inverter is used to
convert ac power to dc power and supply to dc bus.
Pulse generators are employed to produce switching pulses
and pwm. The Simulation is done with the help of
MATLAB Software using Simulink. The Voltage
Measurement block measures the instantaneous voltage
between two electric nodes .The output provides a Simulink
signal that can be used by other Simulink blocks. The output
of the system can be viewed through the scope.

Fig 4: Circuit Diagram for Proposed System
V. CIRCUIT DISCRIPTION
When the PV voltage is greater than the DC bus output
voltage the MPPT will operate as a buck converter. During
this buck mode M1 is on and the current flow is from M1 to
Lm so the inductor is continuously charging here and the
inductor current will increase. When M1 is turned off then
the inductor will discharge and the current will flow through
the diode D1 and D2. During this buck mode iLm=ipv.
When the PV voltage is lesser than output dc voltage then
MPPT will operate as a boost converter. Now M1 and M2
gets turn ON. Now the current flow is from M1-Lm-M2.So
the inductor Lm continuously gets charging. When M2 gets
off then the inductor Lm will start to discharge and the
current flows through the diode D2.During this boost mode
iLm=Io

Fig 5: Simulation Circuit

I. SIMULATION RESULTS
The Simulation results for this work are shown in the
following fig.


Fig 6: Output Voltages from Solar Panel 1&2

Fig 7 Output Voltage of Converter 1

Fig 8 Output Voltage of Converter 2

Fig 9: Total Output Voltage of the Converter

Fig 10: AC Output Voltage without Filter

Fig 11: AC Output Voltage with Filter

Fig 12; AC Output Current

VI. CONCLUSION
A single-phase bidirectional inverter with two buck/boost
MPPTs has been designed and implemented. The inverter
controls the power flow between dc bus and ac grid, and
regulates the dc bus to a certain range of voltages. A droop
regulation mechanism according to the inductor current
levels has been proposed to balance the power flow and
accommodate load variation. Integration and operation of
the overall inverter system contributes to dc-distribution
applications significantly. The simulation is done with the
help of MATLAB software.
REFERENCES
[1] J. M. Carrasco, L. G. Franquelo, J. T. Bialasiewicz, E.
Galvan, R. C. P. Guisado, Ma. A. M. Prats, J. I. Leon, and N.
Moreno-Alfonso, Power-electronic systems for the grid
integration of renewable energy sources: a survey, IEEE
Trans. Ind. Electron., vol. 53, no. 4, pp. 10021016, Aug.
2006
[2] L. N. Khanh, J.-J. Seo, T.-S. Kim, and D.-J. Won, Power-
management strategies for a grid-connected PV-FC hybrid
system, IEEE Trans. Power Deliv., vol. 25, no. 3, pp. 1874
1882, Jul. 2010.
[3] Y. K. Tan and S. K. Panda, Optimized wind energy
harvesting system using resistance emulator and active
rectifier for wireless sensor nodes, IEEE Trans. Power
Electron., vol. 26, no. 1, pp. 3850, Jan. 2011
[4] J. Selvaraj and N. A. Rahim, Multilevel inverter for grid-
connected PV system employing digital PI controller, IEEE


Transactions on Ind. Electron., vol. 56, no. 1, pp. 149158,
January,2009.R. Chen et al., Toward Secure Distributed
Spectrum Sensing in Cognitive Radio Networks, IEEE
Commun. Mag., vol. 46,pp. 5055, Apr. 2008.
[5] J.-M. Shen, H.-L.Jou, and J.-C.Wu, Novel transformer less
grid connected power converter with negative grounding for
photovoltaic generation system, IEEE Transactions on
Power Electron., vol. 27, no. 4, pp. 18181829, April, 2012.
[6] S. V. Araujo, P. Zacharias, and R. Mallwitz, Highly efficient
single-phase transformer less inverters for grid-connected
photovoltaic systems, IEEE Transactions on Ind. Electron.,
vol. 57, no. 9, pp. 31183128, September, 2010.
[7] T. Kerekes, R. Teodorescu, P. Rodriguez, G. Vazquez, and E.
Aldabas, A new high-efficiency single-phase transformer
less PV inverter topology, IEEE Transactions on Ind.
Electron., vol. 58, no. 1, pp. 184191, January, 2011.
[8] J. Yao, H. Li, Y. Liao, and Z. Chen, An improved control
strategy of limiting the dc-link voltage fluctuation for a
doubly fed induction wind generator, IEEE Transactions on
Power Electron., vol. 23, no. 3, pp. 12051213, May, 2008.
[9] Tsai-Fu Wu, Kun-Han Sun, Chia-Ling Kuo and Chih-Hao
Chng, Predictive current controlled 5-kW Single-Phase
Bidirectional Inverter with Wide Inductance Variation for
DC-Microgrid Applications, IEEE Transactions on Power
Electronics., vol. 25, no. 12, pp. 3076-3084, October 2010.
[10] Wu. T-F, Chang C-H, Lin L-C and Chang Y-R, DC-Bus
Voltage Control with a Three-Phase Bidirectional Inverter for
DC Distribution Systems, IEEE Transactions on Power
Electronics., vol. 28, no. 4, pp. 1890-1899, October 2012.
[11] Feng Guo, Lixing Fu, Chien-Hui Lin, Cong Li, Woongchul
Choi and Jin Wang, Development of an 85-kW Bidirectional
Quasi-Z-Source Inverter With DC-Link Feed-Forward
Compensation for Electric Vehicle Applications, IEEE
Transactions on Power Electronics., vol. 28, no. 12, pp. 5477-
5488, December 2013.Ftjf
[12] Dehghan S.M, Mohamadian M and Yazdian A, Hybrid
Electric Vehicle Based on Bidirectional Z-Source Nine-
Switch Inverter, IEEE Transactions on Vehicular
Technology., vol. 59, no. 6, pp. 2641-2653, July 2010.Fjg
[13] Honglin Zhou, Shuai Xiao, Geng Yang and Hua Geng,
Modeling and Control for a Bidirectional Buck-Boost
Cascade Inverter, IEEE Transactions on Power Electronics.,
vol. 27, no. 3, pp. 1401-1413, March 2012.
[14] Chen D, Combined Bidirectional Buck-Boost DC-DC
Chopper-Mode Inverters with High-Frequency Link, IEEE
Transactions on Industrial Electronics., vol. 61, no. 8, pp.
3961-3968, October 2013.
[15] Shukla A, Ghosh A and Joshi A, Control of dc capacitor
voltages in diode-clamped multilevel inverter using
bidirectional buck-boost choppers, IEEE Transactions on
Power Electronics., vol. 5, no. 9, pp. 1723-1732, November
2012.



A Dual-Input DCDC Converter Combining a Boost-Half-
Bridge Cell and a Voltage-Fed Full-Bridge Cell

M.VinothKumar
1
, Dhivya Assistant Professor
2

1

2

ABSTRACT
This letter presents a new zero-voltage-
switching (ZVS) isolated dcdc converter which
combines a boost half-bridge (BHB) cell and a
full-bridge (FB) cell, so that two different type of
power sources, i.e., both current fed and voltage
fed, can be coupled effectively by the proposed
converter for various applica-tions, such as fuel
cell and supercapacitor hybrid energy system.
By fully using two high- frequency transformers
and a shared leg of switches, number of the
power devices and associated gate driver circuits
can be reduced. With phase-shift control, the
converter can achieve ZVS turn-on of active
switches and zero-current switching (ZCS) turn-
off of diodes. In this letter, derivation, analysis,
and design of the proposed converter are
presented. Finally, a 2550 V input, 300400 V
output prototype with a 600 W nominal power
rating is built up and tested to demonstrate the
effectiveness of the proposed converter topology.

Key Words- Boost half-bridge (BHB), dcdc
converter, dual-input, phase-shift, soft switching
and hybrid.

I. INTRODUCTION

The unregulated dc output voltage, the low
dynamics, and the discontinuity of renewable
energy sources, like solar energy and fuel cell,
generally, it is well known that not only a front-end
dcdc converter as an interface circuit is required,
but also an auxiliary power supply is needed to
compensate or regulate output power seamlessly at
different load conditions [1][3]. Therefore, an
efficient hybrid renew-able power conversion
system has become an interesting topic. In terms of
the applications with a galvanic isolation, various
system configurations have been investigated in the
last decade, and usually they can be divided into
three categories, i.e., direct hybridization, multiple-
stage conversion and multiple-port con-version
[4][9]. With different specifications and
requirements, the adequate converter and/or
configuration can be adopted. This letter proposes a
new step-up isolated dcdc converter with dual-
input ports by combining a current-fed BHB cell
[10], [11] and a voltage-fed FB cell, and the
proposed converter can be used in applications
such as hybrid electric vehicles, photovoltaic power
generation systems, and fuel cell systems [8].
Based on the cir-cuit topology, the derivation
process of the proposed converter is introduced.
The steady-state operating principles and features
are explained so as to demonstrate the merits of the
converter. Design considerations on some critical
parameters are studied. Finally, representative
experimental results from a 600-W proto-type are
provided to validate the proposed concept. The
salient advantages of the proposed converter can be
summarized as follows:

Ability of dual-input connection;
Reduced number of power devices and their
associated gate driver components;
ZVS turn-on of the main switches;
ZCS turn-off of the diodes without reverse
recovery issue.



Fig.1.Schematic of a dual-input converter with BHB and
FB cells.
II. PROPOSED SOFT-SWITCHED DCDC
CONVERTER
In order to hybridize the two inputs, i.e., V
in1

and V
in2
, a BHB cell can be paralleled with an FB
cell by adopting a mutual low voltage dc bus as
shown in Fig. 1. Because of the similarity of the
pulse width modulation pattern of BHB and FB
cells, the switch legs I and II can be merged as a
common bridge. Hereby, a new topology with full
function but a simpler connection com-pared to
the previous discrete cells is derived and
illustrated in Fig. 2. The proposed converter
consists of a current-fed port and a voltage-fed
port, which provides a larger flexibility in
practical applications with different type of power
sources. Transformers T
1
and T
2
which have the
turn ratios as n
1
: n
2
= 2:1 in this study are
connected in a special way: the dotted termi-nals
of the primary windings are connected in the
conjunction point A, while two secondary
windings are connected in series (it is also
possible to connect them in parallel depending on
different requirements). A voltage doubler circuit
is employed on the secondary side and the voltage
ringing over the diodes can inherently be clamped
by the output capacitor C
3
or C
4
. L
2
is essentially
the sum of the transformer leakage inductance and
an extra inductance. A dc blocking capacitor C
b
is
added in series with the primary winding of T
2
in
order to avoid trans-former saturation caused by
any asymmetrical operation in the FB circuit.

Fig.2.Topology of the proposed hybrid dc-dc converter.

Same as the dual active bridge (DAB) converters
[12], the pro-posed converter can be viewed as a
voltage source v
p
interfaced to another voltage
source v
s
through the energy interfacing element L
2

as shown in Fig. 3. In steady state, the timing
diagram and the key waveforms of the proposed
converter controlled by phase-shift angle between
the switch pairs, S
1
, S
2
and S
3
, S
4
, are presented in
Fig. 4, where V
L
= n
1
V
in1
, V
H
=
1
2
V
o
, and T
s
is
the switching period. In this letter, only the
symmetrical operation condition, i.e., the switching
duty cycle D is 50%, is discussed, so that S
1
and S
2

as well as S
3
and S
4
have the complementary
driving signals that gives V
in2
= 2V
in1
. Accordingly
output voltage and power transferred can only be
regulated by the phase-shift angle of the two
poles of the input bridge. The power factor of the
high frequency ac loop can be evaluated by the
angle which represents the phase delay between
the sec-ondary voltage and current. In order to
avoid high reactive power in the converter, the
regulated phase-shift angle will be limited in the
range: 0 , in the practical applications [13].
Since the output diode rectifier is current driven,
the following constrains must be satisfied: 1) when
i
s
is positive, v
s
must be positive; and 2) when i
s
is
negative, v
s
must be negative, and thereby based on
the waveforms shown in the Fig. 4(a), the operation
principle of the converter can be explained as
follows.


Fig. 3 Timing diagram and typical waveforms

During [t
0
, t
2
], as shown in Fig. 5(a), the body
diodes of S
1
and S
4
conduct and v
p
is clamped to a
voltage of 2V
L
until i
s
decreases with a slope (2V
L
+
V
H
)/L
2
to zero at t
2
. At t
0
, S
1
turns ON under ZVS.
During [t
2
, t
3
], when i
s
becomes positive and flows
through D
1
, S
1
and S
4
will conduct and i
s
increases
with a slope (2V
L
V
H
)/L
2
, as shown in Fig. 5(b).
During [t
3
, t
5
], when S
4
turns OFF at t
3
, C
S

3
and
C
S

4
start to resonate with L
2
until V
C S

3
= 0, and
then S
3
can turn ON under ZVS. Current in the
primary side flows through S
1
and D
S

3
that makes
v
p
equal to V
L
, and i
s
decreases with a slope (V
H

V
L
)/L
2
. The equivalent circuit is given in Fig. 5(c).
After t
5
the second half switching cycle starts.
Obviously, the diodes on the secondary side will
always turn OFF under ZCS in the whole operation
range.

IV.DESIGN CONSIDERATIONS
Generally, ZVS can be deduced on the precondition
that the anti parallel diode of switch must conduct
before the switch is triggered. In other words, the
main devices are turned OFF with a positive
current flowing and then the current diverts to the
opposite diode which allows the in-coming
MOSFET to be switched on under zero voltage.
Therefore, ZVS constraints depend on the
magnitude of primary side currents, i.e., (n1 + n2)*,
and , and have the relationships at driving instant



In fact, the condition for S1, S3, and S4 can be
easily satisfied, so ZVS can achieve over the whole
load range and is independent on the converters
parameters. While to ensure the ZVS turn-on of S2,
the following function of the circuit parameters and
the control variables must be satisfied:

For converters with low input voltage and high
current, turnoff loss of the switches on the low
voltage side is the predominating factor of the
switching loss [2], which cannot be ignored and is
closely related to the stress of switch-off current.
Moreover, during converter design, it is also
necessary to compute the root mean square (rms)
values of the switch current to estimate conduction
loss as for choosing MOSFETs, especially for the
power devices located in the high current path. As
an example, when input voltage is 30 V, Fig. 9
plots the values of transient turn-off current and
rms current of the devices on the primary side as a
function of . It can be seen that the current stress
is not distributed equally and among the switches,
S2 will have to handle highest current stress and
also high conduction loss owing to the BHB
structure [14]. Both the turn-off transient current
and the rms current of S2 are approximately
proportional to the phase-shift angle that means for
same output power, if decreases, switching and
conduction losses of S2 will become less, so as a
result the system efficiency can be improved.
Regarding to this fact as well as the ZVS operation,
an optimal design and trade off between switching
loss and conduction loss may be considered for the
future research.

Fig.5. Simulation diagram of proposed system
Fig.6.Input Current
Fig.7.Input Voltage



Fig.8.Output Voltage and Current
V. CONCLUSIONS
This project, proposed an improved switching
method for a dual input DC- DC converter
combining a boost half bridge cell and a voltage
fed full bridge cell for high step-up applications.
This circuit structure helps for mitigating without
the need for current sensors and the current
imbalance problems in existing system. The half
bridge and full bridge cells combining DC- DC
converter achieves ZVS turn ON of switches and
ZCS turn OFF of diodes. The new technique of
combining half bridge and full bridge inverters
gives an efficient result. A soft-switched isolated
dcdc converter with the ability of handling two
independent inputs is derived, investigated, and
designed.

REFERENCES
[1] F. Blaabjerg, Z. Chen, and S. B. Kjaer, Power
electronics as efficient interface in dispersed power
generation systems, IEEE Trans. Power Electron., vol.
19, no. 5, pp. 11841194, May 2004
[2] M.Nymand and M. A. E. Andersen, High-efficiency
isolated boost dcdc converter for high-power low-
voltage fuel-cell applications, IEEE Trans.Ind. Electron,
vol. 57, no. 2, pp. 505514, Feb. 2010
[3] J. Huusari and T. Suntio, Dynamic properties of
current-fed quadratic full-bridge buck converter for
distributed photovoltaic MPP-tracking systems, IEEE
Trans. Power Electron., vol. 27, no. 11, pp. 46814689,
Nov. 2012
[4] A. Payman, S. Pierfederici, and F. Meibody-Tabar,
Energy management in a fuel cell/super capacitor
multisource/multiload electrical hybrid system, IEEE
Dec. 2009
[5] W. Liu, J. Chen, T. Liang, R. Lin, and C. Liu,
Analysis, design, and control of bidirectional cascaded
configuration for a fuel cell hybrid power system, IEEE
Jun. 2010
[6] H. Tao, A. Kotsopoulos, J. L. Duarte, and M. A. M.
Hendrix, Transformer-coupled multiport ZVS
bidirectional DCDC converter with wide input range,
IEEE Trans. Power Electron., vol. 23, no. 2,pp. 771781,
Mar. 2008
[7] H. Krishnaswami and N. Mohan, Three-port series-
resonant DCDC converter to interface renewable energy
sources with bidirectional load 4902 IEEE transactions
on power electronics, vol. 28, no.11, November 2013 and
energy storage ports, IEEE Trans. Power Electron., vol.
24, no. 10, pp. 22892297, Oct. 2009.
[8] Z. Zhang, Z. Ouyang, O. C. Thomsen, and M. A. E.
Andersen, Analysis and design of a bidirectional
isolated dcdc converter for fuel cells and super-
capacitors hybrid system, IEEE Trans. Power Electron.,
vol. 27, no. 2, pp. 848859, Feb. 2012.
[9] Z. Zhang, O. C. Thomsen, M. A. E. Andersen, and H.
R. Nielsen, Dual input isolated full-bridge boost DC-DC
converter based on the distributed transformers, IET
Power Electron., vol. 5, no. 7, pp. 10741083, Aug. 2012
[10] C. Yoon, J. Kim, and S. Choi, Multiphase DC-DC
converters using a boost-half-bridge cell for high-voltage
and high-power applications, IEEE Trans. Power
Electron., vol. 26, no. 2, pp. 381388, Feb. 2011
[11] S. Jiang, D. Cao, Y. Li, and F. Z. Peng, Gird-
connected boost-half-bridge Photo voltaic micro inverter
system using repetitive current control and maximum
power point tracking, IEEE Trans. Power Electron., vol.
27, no. 11, pp. 47114722, Nov. 2012
[12] F. Krismer and J. Kolar, Efficiency-optimized high
current dual active bridge converter for automotive
applications, IEEE Trans. Ind. Electron., vol. 59, no. 7,
pp. 27452760, Jul. 2012


Unity-Power-Factor Operation of High Performance Single-
Phase ACDC Soft Switched Converter Based on Boost
Active Clamp Topology

R.Sivakumar
1
, N.Ananthan
2
, J .S. Sathiyanarayanan
3
1,2
PG Students, Arunai College of Engineering, Tiruvannamalai.
3
Professor, Arunai College of Engineering, Tiruvannamalai.

ABSTRACT
In this paper, a single phase acdc converter in
modular approach used for single phase pulse
width modulated active clamped, zero-voltage-
switched boost converter is presented. The active
clamp technique is used for zero-voltage switching
of the main and auxiliary switches. The operating
modes, analysis, and design considerations for the
proposed converter are explained. To evaluate the
performance of the proposed converter, finally
simulation and experimental results for a
prototype converter is presented. The proposed
converter operates at almost unity power factor
with reduced output filter size. The output voltage
is regulated without affecting zero-voltage-
switching, even under unbalanced input voltages.
Also one non linear load is added parallel with the
proposed converter and its performance are
analyzed with and without non linear load.
I. INTRODUCTION
Usage of Power electronic converters is ever
increasing in the processing of electrical energy in
industrial applications such as adjustable speed
drives, SMPS, UPS, etc [1-5]. The converters with
high power factor are increasingly required in
industries. In high-power range, mainly a three phase
system is employed. Most of Power electronics
system which get connected to AC utility mains use
diode rectifiers at the input , the nonlinear nature of
diode rectifiers cause significant line currents
harmonics generations thus they degrade,
Power quality
Increase losses
Failure of some crucial medical equipments
Loss of efficiency and so on.
Therefore, stringent international harmonics standard
are imposed, and hence power factor corrections
circuits are in-corporate in Power electronics system.
Earlier, to reduce rectifier-generated harmonics,
expensive and bulky filter inductors and capacitors
were installed [6-7].The above filters effectively
eliminate only certain harmonics. The active power
line conditioners (APLCs) used for harmonics
reductions are generally hard switched, hence the
components are subjected to high-voltage stresses
which increases further with increase in the switching
frequency. Hard switching results in low efficiency,
large. Electromagnetic interference (EMI).Soft
switching can also be achieved using resonant
converters [8-9]. But it has some of the draw backs,
like Resonant tank circuits are required to be
designed at a much higher KVA/Kw rating. Due to
the above reasons we prefer High performance AC-
DC Soft Switched Converter based on Boost active
clamp topology
A. CIRCUIT DESCRIPTION
Fig.1 shows a simplified circuit diagram of a single-
phase acdc converter. The proposed converter
consists of a small line filter comprising of Lf and Cf
followed by single-phase line rectifier (D1-D4) and a
very small high-frequency bypass capacitor Cin.
Unlike the conventional boost converter, in addition
to the boost inductor Lb and the high-frequency (HF)
rectifier output diode D; the resonant inductor Lr in
series and resonant capacitor Cr in parallel are
connected to the main switch Sm. The auxiliary
switch Sa with series connected clamping capacitor


Cc is connected between the drain of the Sm and the
cathode of the D. The small capacitor Cn is used as a
high-frequency bypass filter at the output of each
module. Both the switches are driven in a
complementary manner. The single output filter
capacitor Co is used at the output of the proposed
three-phase converter whose size get reduced
drastically owing to the fact that, like the three-phase
active rectifier, the dominant ripple frequency is six
times the input source frequency. By sensing boost
inductor current, output dc and input ac voltages,
gating pulses are generated accordingly using PFC-
PWM IC and fed to Driver IC. Drive IC provides
complementary gate drive pulses with sufficient dead
band. A PCB-mounted miniature current LEM is
used for sensing the boost inductor current. When
boost inductor current exceeds the set limit, drive
pulses are disabled, hence the converter is protected.
Proposed converter uses average current mode
control. In average current mode control, boost
inductor current is continuously monitored and
controlled to follow the reference signal proportional
to ac line voltage. Thus, input current is sinusoidal.
To regulate output voltage, a multiplier circuit
controls the amplitude of the sinusoidal current
reference signal in accordance with the voltage error
signal generated using the output voltage and
rectified input ac voltage. When the load decreases,
the output voltage increases. To maintain constant
load voltage, the control circuit senses the load
voltage and the pulse width are automatically reduced
in the switching cycle and the output voltage is
regulated and maintained almost constant. The
control circuit varies the duty ratio in switching
cycles over the input supply voltage cycle, as the
instantaneous input supply voltage is varying over the
cycle.

Fig.1 The proposed converter
Table:1.1 components of converter
s.no component values
1
MOSFET(Sm,Sa)

IRFP460

2
Boost inductor

1.75mH

3
Resonant inductor

8.624 H

4
Resonant Capacitor

0.47 nF

5
Input capacitor

1 F

6
Output capacitor

1 F

7
Clamping capacitor

1.1F

B. Operating Principle
To simplify the analysis and operating modes of the
circuit, the following assumptions are made.
[1] The semiconductor devices, inductors, and
capacitors are ideal.
[2] The output filter capacitor Co is large enough to
maintain constant output voltage Vo.
[3] The rectified output voltage Vin is constant over
one switching cycle as switching frequency is very
high compared to ac input frequency.
[4] The boost inductor Lb is much larger than Lr and
clamping capacitor Cc is much larger than capacitor


Fig.2 Key waveforms of the proposed converter.
Mode 1(t0-t1): Fig.3(a) shows the operating state of
the circuit during this interval. The auxiliary switch
Sa is already in an off-state. The body diode of the
main switch Sm starts conducting, and the output
diode D continues conduction. During this mode, the
boost inductor current ilD continues to decrease and
the output diode current ID also starts decreasing.
The negative resonant inductor current I lr continues
to decrease. This mode ends when it decreases to
zero, and the body diode of the main switch Sm
ceases to conduct. To turn-on the main switch Sm
with ZVS, a gate pulse must be applied during this
interval.

Fig.3: mode 1
Mode 2(t1-t2): Fig.3(b) shows the operating state of
the circuit during this interval. At t1, the main switch
Sm turns on and starts carrying the positive resonant
inductor current iLr. Thus, ZVS of switch Sm is
achieved. The boost inductor current ilb continues to
decrease. This mode ends when output diode current
iD becomes zero

Fig.3: mode 2
Mode 3(t2-t3): During this mode, the main switch
continues to conduct as shown in Fig.3.(c). A load is
supplied by the output filter capacitor. Input power is
stored in boost inductor Lb and resonant inductor Lr.
Therefore, the boost inductor current ilb starts
increasing. The resonant inductor current ilr
continues to increase. This mode ends when the main
switch Sm is turned off.

Fig.3: mode 3
Mode 4(t3-t4): As shown in Fig.3(d), the current,
which was flowing through the main switch, is
diverted to resonant capacitor Cr. The voltage across
the main switch (Vcr) starts increasing from zero, and


when it reaches Vo, this mode ends. As soon as the
main switch voltage reaches approximately equal to
Vo, the output diode D starts conducting. The body
diode of the auxiliary switch Sa starts conducting
only after the main switch voltage reaches (Vo+Vcc)
. Since the interval between the start of conduction of
the diode D and the start of conduction of the body
diode of auxiliary switch is very small compared to
switching cycle, this is not treated as a separate

Fig.3: mode4
Mode 5(t4-t5): Fig. 3(e) shows the operating state of
the circuit during this interval. The boost inductor
current ilb starts decreasing. The output diode D
continues conducting and its current iD starts
increasing. If clamping capacitor Cc is large, then
clamping capacitor voltage Vcc is almost constant,
and inductor current ilr decreases linearly, otherwise
varies resonantly. This mode ends when the resonant
inductor current ILR becomes zero. Thus, the body
diode of the auxiliary switch ceases to conduct.
During this interval, a gate pulse must be applied to
auxiliary switch in order to achieve ZVS.

Fig.3: mode 5
Mode 6: As shown in Fig.3(f), the auxiliary switch
starts conducting. Thus, ZVS of switch is achieved.
The boost inductor current continues to decrease.
This mode ends when the auxiliary switch is turned
off.

Fig 3: mode 6
Mode 7: Fig.3(g) shows the operating state of the
circuit during this interval. The boost inductor current
continues to decrease. The voltage continues to
decrease due to negative inductor current. When
becomes zero, the body diode of the main switch
starts conducting and this mode ends. The resonant
inductor and the resonant capacitor form a resonance
circuit. To achieve ZVS of the main switch, must
reach zero at the end of this mode. This requirement
compels that stored energy in the resonant inductor
must be greater than resonant capacitor.

Fig.3: mode7
SIMULATION AND EXPERIMENTAL
RESULTS


A. THEORITICALY ANALYSED WAVEFORMS
For inductors, Litz wires NELC175/40SPSN which
has 175 strands of 40 AWG is used. This reduces the
effective resistance of inductor as well as its skin
effects. For boost inductor, N87 ferrite core (Siemens
make) and for resonant inductor, N87 ferrite core
(Siemens make) is used. Fig.4(a) shows the simulated
clamping capacitor voltage, boost inductor current
and resonant inductor current at full load,
respectively. Fig.4(b) of boost inductor current shows
that the converter operates in continuous conduction
mode (CCM). The maximum resonant inductor
current is the same as that of maximum boost
inductor. The voltage across the clamping capacitor
is maximum at full load, which is 23.5 V in this case.
The experimental switch voltages and currents at full
load are shown in Fig5, and it is evident that both the
switches operate with ZVS. It is seen that the
proposed converter maintains unity power factor
even under unbalanced input voltages. Under
unbalanced input voltages, neutral current will have
triple harmonics. The performance characteristics of
the proposed converter under variable load condition
are given in Fig. 6. It is observed that the efficiency
varies from 94.9% to 92.5%, power factor varies
from 0.999 to 0.997, and total harmonic distortion
(THD) varies from 1.1% to 2.7% from full load to
25% of full load. In a hard-switched converter,
efficiency is nearly about 90% .The proposed
converter has a higher efficiency compared to other
soft switched converter.

Fig 4. Simulation results at full load. (a) Clamp capacitor
voltage (Vcc),
(b) boost inductor current (iLb ), and (c) resonant inductor
current (iLr )

Fig. 5. Experimental main switch voltage (vsm ) and main
switch current (ism ), and auxiliary switch voltage (vsa )


and auxiliary switch current (isa ) at full load (scales: 200
V/div., 5 A/div., 1 _s/div. (zoom view)).

Fig 6. Experimental performance characteristics of the
proposed converter (a)efficiency, (b) power factor, and (c)
% THD.

Fig. 7. Experimental main diode current (i D) and
resonant inductor current (iLr ) at full load (scales:
5/div., 5 _s/div.).

Fig 8. Source current and voltage waveform



Fig 9. Output current and voltage waveform
CONCLUSION
High power quality single phase and three-phase ac
dc converters are being widely used in the industries.
In this project, a single-phase module of acdc
converter used for three phase module adopting
active clamped boost topology has been presented.
The operating modes, analysis of the circuit, and
design considerations are explained. The simulation
and experimental results on laboratory prototype are
presented. The experimental results are in good
agreement with simulation results. The proposed
converter has smaller output filter capacitor and
lesser component count as compared to other
topologies. It operates at almost unity power factor,
low THD, and high efficiency. In addition, it
maintains unity power factor and regulated output
voltage with ZVS over the wide range of the load
even-with unbalanced input voltages.
REFERENCES
[1] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A.
Pandey, and D.P. Kothari, A review of three-phase
improved power quality acdcconverters, IEEE Trans.
Ind. Electron., vol. 51, no. 3, pp. 641660, Jun. 2004.
[2] B. M. Saied and H. I. Zynal, Minimizing current
distortion of a threephasebridge rectifier based on line
injection technique, IEEE Trans.
Power Electron., vol. 21, no. 6, pp. 17541761, Nov. 2006.
[3] M. R. Ramteke, H. M. Suryawanshi, and K. L. Thakre,
Single-phaseresonant converter in three-phase system in
modular approach, EPE
J., vol. 16, no. 4, pp. 513, Dec. 2006.
[4] A. K. S. Bhat and R. L. Zheng, Analysis and design of
a three-phase LCC-type resonant converter, IEEE Trans.
Aerospace Electron. Syst.,
vol. 34, no. 1, pp. 508518, Apr. 1998.
[5] S. S. Tanavade, H. M. Suryawanshi, and K. L. Thakre,
Novel single-phase ac-to-dc convertor using three-phase
modified series-parallel resonant converter, IEE Proc.
Elect. Power Appl., vol. 152, pp. 10271035, Jul. 2005.
[6] R. L. Steigerwald, A comparison of half bridge
resonant converter topologies, IEEE Trans. Power
Electron., vol. 3, no. 2, pp. 174182,
Apr. 1988.
[7] T.-F. Wu and S.-A. Liang, A systematic approach to
developingsingle-stage soft switching PWM converters,
Sep.. 2001.
[8] R. Watson, F. C. Lee, and G. C. Hua, Utilization of an
active clamp circuit to achieve soft switching in flyback
converters, IEEE Trans. Power Electron., vol. 11, no. 1,
pp. 162169, Jan. 1996.
[9] J. A. Cobos, O. Garcia, J. Uceda, J. Sebastian, and E.
Cruz, Comparison of high efficiency low output voltage
forward topologies, in Proc.
IEEE PESC, 1994, pp. 887894.


Wireless Electrical Energy Transfer

Nanda Kumar K
1
, N. Naha Renjini
2
and Rasmi Rajan
3

1,2,3
Assistant professor, EEE Department, Hindustan University, Chennai

ABSTRACT
The paper will detail the need and usefulness of
wireless power transmission and furthermore
the feasibility of using inductive coupling as the
means for wireless power transmission.
Nowadays usage of smart phones, laptops and
other portable electronic devices has been
increased. The users of these portable devices
need to recharge their devices in order to get an
uninterrupted service. The main problem faced
by them while recharging those devices is a need
of charging device. These problems can be
overcome by using a wireless connection
between the device and the output port. The
wireless connection can be made possible by
using the electromagnetic waves.

1. INTRODUCTION
The subject matter of the report will be directed
towards the knowledge level of an electrical
engineer. Thus some points about general circuits
may not be explicitly stated as they have been
taken as common knowledge for the intended
audience [1-8]. However, it is intended that anyone
with an interest in electrical circuits and more
importantly transformer theory or electromagnetic
fields would be able to understand and follow the
subject matter outlined in the following document.
The first section of the document will explicitly
illustrate the problem and what the group intended
to accomplish. With the complexity of the problem
in mind and what we must accomplish our team
then began research on the available means to
transmit power without a physical connection.
Once the initial background research was
accomplished it was necessary to layout the
advantages and disadvantages of all the available
means for wireless power transmission [5-10].
Once all the necessary criteria for each system were
known we chose the best solution for the problem.
After our team had chosen upon using inductive
coupling us all began to review the major theories
that would determine the constraints of the system
and what pieces of hardware must be designed to
achieve the transmission of wireless power.
Furthermore because we are transmitting power
through the surrounding area we had to be sure that
our system would not endanger others and be FCC
(Federal Communication Commission) compliant.
Once the basic system components were known our
team divided up the work load, set the necessary
deadlines, and began designing the following
circuits and hardware: power supply, oscillator,
transmission coil, receiving coil, and LED flashing
circuit. After the entire system was integrated into a
working unit it was time to determine how well the
system operated and the feasibility of wireless
power transfer through inductive coupling.
Additionally, future improvements that could
greatly improve the overall system will be
discussed.
1.1 Problem Statement
For the completion of this project, we had to
wirelessly transfer the power of an AC oscillating
waveform into a DC voltage on the receiving end
which will be used to light an LED to demonstrate
the instantaneous power transfer [11-15]. The
frequency of oscillation of the AC signal must not
exceed 100MHz. The power transfer needs to be
done over a two feet distance or greater. The
transferred AC power needs to be converted to DC
power and boosted up enough to drive a low power
display design, such as an LED in continuous
mode. The whole system must be FCC compliant.

1.2 Possible Solutions
In our research, as well as practical knowledge, we
knew of three possibilities to design a device [16-
17]. There are the use of antennas, inductive
coupling, and laser power transfer. In addition, we
had to be aware of how antennas and inductive
coupling would be affected by the frequency we
select.

1.2.1 Antenna
Antennas are the traditional means of signal
transmission and would likely work. In initial
research, it appears that system utilizing antennas
can receive power gains based upon the shape and
design of the antenna. This would allow more
power actually being sent and received while also
have a small input power. The difficulty comes in
the trade off of antenna size versus frequency. In


attempting to stay in a lower frequency, one would
be require using antennas of very large size.

1.2.2 Inductive Coupling
Inductive coupling does not have the need for large
structures transfer power signals. Rather, inductive
coupling makes use of inductive coils to transfer
the power signals. Due to the use of coils rather
than the antenna, the size of the actual transmitter
and receiver can be made to fit the situation better.
The tradeoff is for the benefit of custom size, there
will be a poor gain on the solenoid transmitter and
receiver.

1.2.3 Laser Power Transmission
The concept of laser power transmission is
addressed in the research of NASA and NASDA
solar programs. Lasers would allow for a very
concentrated stream of power to be transferred
from one point to another. Based upon available
research material, it appears that this solution
would be more practical for space to upper
atmosphere or terrestrial power transmission. This
option would not be valid to accomplish our tasks
because light wavelengths are higher than the
allowable operational frequencies.

2. BLOCK DIAGRAM & DESCRIPTION

Figure 2.1 Block Diagram

2.1 Block Diagram Description
A transformer is a static electrical device that
transfers energy by inductive coupling between its
winding circuits. A bridge rectifier is used for
conversion of an alternating current (AC) input into
a direct current (DC) output. A crystal oscillator is
an electronic oscillator circuit that uses the
mechanical resonance of a vibrating crystal of
piezoelectric material to create an electrical signal
with a very precise frequency. This frequency is
commonly used to provide a stable clock signal for
the driver circuit. The most common type of
piezoelectric resonator used is the quartz crystal, so
oscillator circuits incorporating them became
known as crystal oscillators. In order to generate
the maximum amount of flux which will induce the
largest voltage on a receiving coil, a large amount
of current must be transferred into the transmitting
coil. The oscillator is not capable of supplying the
necessary current, thus the output signal from the
oscillator will then be passed through a power
amplifier (Power MOSFET) to produce the
necessary current.

A loop antenna is a radio antenna consisting of a
loop (or loops) of wire, tubing, or other electrical
conductor with its ends connected to a balanced
transmission line. Within this physical description
there are two very distinct antenna designs: the
small loop (or magnetic loop) with a size much
smaller than a wavelength, and the resonant loop
antenna with a circumference approximately equal
to the wavelength. Small loops have a poor
efficiency and are mainly used as receiving
antennas at low frequencies. Self-resonant loop
antennas are larger. They are typically used at
higher frequencies, especially VHF and UHF,
where their size is manageable.
One of the major improvements made to the
coupling circuit was accomplished by impedance
matching. When a capacitor is put in series with the
transmitter coil and it is tuned to its resonant
frequency, then the phase differences of the
capacitor and inductor are equal and opposite.
jwL =-1/jwC
When this occurs the load will appear purely
resistive and the maximum amount of real power
will be transferred into the transmission coil as
voltage and current are in phase. This maximum
power transfer to the transmitter will ensure the
maximum amount of current which will produce
the most magnetic flux.
At the receiver circuit we utilized the same
concepts of impedance matching to tune the
receiver circuit to the same resonant frequency as
of the transmitter. This ensures that the maximum
power is transmitted to the receiver coil.
A parallel resonance circuit was used to maximize
voltage output to the load at the receiving end. A
LED is used in our circuit to indicate the power is
received by the receiver.
2.2 Circuit Diagram & Description


Figure 2.2 Circuit Diagram
2.3 Power MOSFET, Transmission & Receiving
Circuit

Figure 2.3 Transmission & Receiving Circuit
In order to generate the maximum amount of flux
which will induce the largest voltage on a receiving
coil, a large amount of current must be transferred
into the transmitting coil.
The oscillator is not capable of supplying the
necessary current, thus the output signal from the
oscillator will then be passed through a power
amplifier to produce the necessary current. The key
design aspects of the power amplifier are
generating enough current while producing a clean
output signal without large harmonic distortions. If
the output from the amplifier was not clean with
harmonic distortions the system would cease to be
FCC compliant.
Transmitter and Receiver Design
The transmitter and receiver circuit combined can
be called the coupling circuit. It is the heart of the
entire system as the actual wireless power transfer
is carried out here. The efficiency of the coupling
circuit determines the amount of power available
for the receiver system as well as how far the LED
can be from its actual power source.

Solenoid Design
A solenoid configuration was used for the design of
the transmitter and receiver. A solenoid is a long
cylinder upon which wire is wound in helical
geometry as shown in figure 2. The magnetic field
at the center of the solenoid is very uniform.
Usually, the length of a solenoid is several times of
its diameter. The longer the solenoid the more
uniform the magnetic field at the middle. In this
way a solenoid is a very practical way to generate a
uniform controlled magnetic field .

Figure 2.4 Flux density in a solenoid

The magnetic flux density in a solenoid can be
approximated by the following equation:

B =
0
nI

Where B is the magnetic flux density,
0
is the
permeability of free space, n is number of turns of
wire per unit length and I is the current flowing
through the wire. To maximize the flux linked to
the receiver coil, it is imperative to increase the
magnetic flux density as much as possible.
The equation shows that one of the ways to
increase B is to increase the current (I) going into
the wire. Since all wires have some resistance, this
process requires increase in the voltage put across
the wires which can result in more heating in the
coil. B can also be increased by increasing n. This
can be accomplished by decreasing the wire size or
winding wires closely. Winding wires closely can
increase the overall resistance of the coil and thus
increase the heating in the coil. Another way of
increasing n is by winding several layers of wire
which can cause insulations problems as well as
decrease the diameter to length ratio. It is apparent
that there are several parameters that we have to


manipulate to select the appropriate tradeoff that
might fit our systems needs.

As the input power to our transmitter is limited to
1W, it certainly limits the amount of current that
can be pushed through the transmitter coil. Thus
one of the design goals of the team was to keep the
resistance low to maximize the current. In addition
to that, we also strived to increase the number of
turns per unit length without drastically
increasing the resistance. Initially our team
was using shielded wire for the coils. A major
advancement was made in decreasing wire size
by replacing it with magnetic wires. This wire
is common copper wire but rather than having
a thick insulation over the copper, it is simply
coated in enamel which keeps the overall
diameter of the wire much thinner compared to
shielded wire. Magnetic wires also have low
resistance and therefore can carry much higher
current.
We also utilized two complete layers of wires for
the transmitter coil to increase the number of turns
even more.

These steps improved the performance of our
system to a great extent.
Initial Experimentation
In addition to the solenoid parameters, it was also
necessary to determine certain parameters such as
relative size of the transmitter and receiver coil, the
orientation of the coils, the turns ratio as well as the
operating frequency. To establish these parameters,
we conducted few experiments. For our
experiments we made two handmade inductive
coils of different diameters (approximately 1.5 ft
and 6 inches), but with equal turns (N=10). First we
tried supplying the large diameter coil with a 7 volt
21 kHz sine waveform to act as the transmitter and
the small diameter coil was placed next to it at
various distances and the resulting voltage received
was measured.

Figure 2.5 Bigger Transmitter and Smaller Receiver Coil

Next we conducted the same experiment however
this time the coils were oriented in such a way
where they were along the same axis as shown
below.

Figure 2.6 Transmitter and Receiver Coil sharing the
same axis
The following data was collected with this
arrangement.

BIG LOOPS
transmitter

SMALL
LOOPS
receiver

Separation distance

MEASURED VOLTAGE

3inches

7V

30mV

BIG LOOPS FOR
TRANCEIVER
SMALL LOOPS
FOR RECEIVER
Separat
ion
distance
MEASURED VOLTAGES
0inch 7V 43mV
2inches 7V 18mV
5inches 7V 8mV


Higher frequency is preferred for greater power
transmission over all distances. This agrees with
Faradays Law as the induced voltage is dependent
on the frequency. The large number of turns at the
transmitter would create more magnetic flux
density which can result in high flux linkage. The
major concern at the receiver was to find the
optimum number of turns while keeping the
resistance of the receiver coil minimal. Further
experimentation showed that the turns ratio of
transmitter and receiver coil had no effect on the
system whatsoever due to the large distance
between the coils.
From these simple tests we realized four major
points of emphasis that would be crucial in
designing an efficient inductive coupling system:
The coils should be oriented such that they
share the same axis
The receiver should be larger than the
transmitter
The higher the frequency the more power
can be transferred over a given distance
After conducting several experiments with
longer solenoids and different number of
turns, we arrived at the final parameters
that seem to provide the maximum power
transfer between the transmitter and
receiver coils.
3. HARDWARE DESCRIPTION

3.1 System Design
With all the necessary background research
completed it became clear what basic design
components the entire system would require. First
we needed a method to power the transmission side
of the system. The power supply would then power
an oscillator which would provide the carrier signal
with which to transmit the power. Oscillators are
not generally designed to deliver power, thus it was
necessary to create a power amplifier to amplify the
oscillating signal. The power amplifier would then
transfer the output power to the transmission coil.
Next, a receiver coil would be constructed to
receive the transmitted power. However, the
received power would have an alternating current
which is undesirable for lighting a LED. The entire
system can be seen in the figure.

Figure 3.1 Project hardware
3.2 Power Supply Enclosure

Figure 3.2 Power Supply Enclosures
The main design aspects our team wanted to
incorporate in the power supply was that it could
use the 230 V AC voltage found in any basic wall
outlet, and use that voltage to power any necessary
circuits to the system. Initially, 230volts is too large
for our small circuits so we incorporated a small
transformer to step down the voltage. Furthermore
for any basic electrical components it would be
necessary to have a DC power supply available,
thus the stepped down AC voltage converted to DC
by a full-wave bridge rectifier. The full-wave
bridge rectifier is the KBU4D. Large capacitors
were then connected to the output of the full-wave
bridge rectifier to ensure that a steady DC voltage
could be maintained.
3.3 Crystal oscillator, Driver Circuit & MOSFET
Enclosure


Figure 3.3 Crystal oscillator & Driver Hardware
During the operation, the oscillation is being
sustained by the crystal oscillator by taking a
voltage signal from a quartz resonator. The signal
is fed back to the resonator after being amplified. In
this circuit, the frequency is being micro tuned by
the presence of 47 F capacitor. The 1 6Hz
converted frequency can be obtained from the pin
12 of IC as it serves as its output. Based on the
components used in the circuit, it will no longer
require additional adjustments for the circuit to
function well.
3.4 Transmitting and Receiving antenna

Figure 3.4 Transmitting antenna

Figure 3.5 Receiving antenna
4. FUTURE IMPROVEMENTS
There are several improvements that can be made
to the system to increase its overall performance.
The oscillator output wasnt a very clean sine wave
signal which increased the harmonic distortion of
the signal. A pure sine wave can be generated by
using better filters at the output. Currently our
system is powered by a transformer that provides
+18V/-18V volt rails. Our system can work with
lower power. Thus one of the future improvements
could be an implementation of a solar cell array to
make our system more mobile. The coupling circuit
can be made more efficient by altering the design
in several ways. Increasing the input current to the
transmitter coil would definitely enhance its
performance. We can also make the signals more
directional in the z direction by using a conical coil
as a transmitter instead of the solenoid coil.
5. CONCLUSION

Large number of institutions such as medical,
industrial, educational etc. need wireless electricity
transmission mechanism for its products to work
efficiently, effectively and at potentially reduced
costs. Plus it reduces the hassle of wires, non-
rechargeable batteries and power cords at small
scale. On the other hand transmission
of power using wireless electricity mechanism
helps to reduce the cost of power
being supplied. Plus the source of power is clean
and environmental friendly. The proposed research
would attain following goals:
1. Development of wireless electric
transmission mechanism for small scale
(private sector) which is efficient and
effective
2. Development of wireless electric
transmission mechanism for large scale
(public sector) which is efficient, effective
and aimed at lower electricity production
cost.
3. Determine whether the radiations from the
wireless electric transmission system have
biological impact.

REFERENCES

[1] G. L. Peterson, THE WIRELESS
TRANSMISSION OF ELECTRICAL
ENERGY, IEEE[online document], 2004,
[cited 12/10/04],
http://www.tfcbooks.com/articles/tws8c.htm
[2] [U.S. Department of Energy, Energy Savers:
Solar Power Satellites, [online document] rev
2004 June 17, [cited 12/10/04],
http://www.eere.energy.gov/consumerinfo/fact
sheets/l123.html
[3] S. Kopparthi, Pratul K. Ajmera, "Power
delivery for remotely located Microsystems,"


Proc. of IEEE Region 5, 2004 Annual Tech.
Conference, 2004 April 2, pp. 31-39.
[4] Tomohiro Yamada, Hirotaka Sugawara,
Kenichi Okada, Kazuya Masu, Akio Oki and
Yasuhiro Horiike,"Battery-less Wireless
Communication System through Human Body
for in- vivo Healthcare Chip,"IEEE Topical
Meeting on Silicon Monolithic Integrated
Circuits in RF Systems, pp. 322-325, Sept.
2004.
[5] Category:Radio spectrum -Wikipedia, the free
encyclopedia, [online document], 2004 Aug
26 [cited 12/11/04],
http://en.wikipedia.org/wiki/Category:Radio_s
pectrum.
[6] Zia A. Yamayee and Juan L. Bala, Jr.,
Electromechanical Energy Devices and Power
Systems, John Wiley and Sons, 1947, p. 78.
[7] Code of Federal Regulations, Title 47, Volume
1,Revised as of October 1, 2003 ,From the U.S.
Government Printing Office via GPO Access,
CITE: 47CFR15.3, Page 686-689
[8] Oscillator Basics, October 2004,
http://www.electronics-
tutorials.com/oscillators/oscillator- basics.html
DiscreteSemiconductors, 2N2222, November
2004,
http://www.semiconductors.philips.com/acroba
t_download/datasheets/2N2222_CNV_2.pdf.
[9] All Data Sheets, AD711JN Operational
Amplifier, November 2004,
http://www.alldatasheet.com/datasheet-
pdf/view/AD/AD711JN.html.
[10] 2.3 Class B September 2004, http://www.st-
andrews.ac.uk/~www_pa/Scots_Guide/audio/p
art2/page2.html.
[11] Texas Insturments, OPA13442 Operational
Amplifier, September 2004,
http://focus.ti.com/lit/ds/sbos058/sbos058.pdf.
[12] Digikey, TIP31 BJT,
http://rocky.digikey.com/WebLib/On-
Semi/Web%20Data/TIP31_A_B_C,%20TIP32
_A_B_C.pdf.
[13] Digikey,TIP42,BJT,http://rocky.digikey.com
/WebLib/ST%20Micro/Web%20Data/TIP41A,
B,C_42A,C.pdf.
[14] Barry.Solenoid Physics (Barrys CoilGun
Design Site) [online] 2004,
http://www.oz.net/~coilgun/theory/solenoidphy
sics.htm (Accessed: September 27, 2004).
[15] Fawwaz T. Ulaby, Fundamentals of Applied
Electromagnetics 2001 Media Edition, Prentice
Hall, 2001.
[16] The Spark Transmitter. 2. Maximising Power,
part 1. November 2004,
http://home.freeuk.net/dunckx/wireless/maxpo
wer1/maxpower1.html
[17] R. Victor Jones, Diode Applications, [Online
Document], 2001 Oct 25, [cited 2004 Dec 11],
http://people.deas.harvard.edu/~jones/es154/lec
tures/lecture_2/diode_circuits/diode_appl.html



Speed Control of PMBLDC Motor Using PFC Cuk
Converter for Air-Conditioner

K.Barathi
1
, S.Suganthi
2

1
PG Scholar in Power Electronics and Drives, Mailam Engineering College, India
2
Professor, Department of Electrical and Electronics Engineering, Mailam Engineering College, India

ABSTRACT
The diode bridge rectifier incorporating DC
DC cuk converter fed from single phase AC
mains is designed to drive a permanent magnet
brushless DC motor (PMBLDCM). The cuk
converter power switch is driven with the aid of
single stage power factor correction (PFC)
converter control. The closed loop operation of
sliding mode controller (SMC) is designed
within the power factor correction (PFC)
converter circuit. The permanent magnet
brushless DC motor (PMBLDCM) is controlled
with the help of DC DC cuk converter input
fed to the three phase voltage source inverter
(VSI) bridge circuit which inturn to regulate
the motor. The electronic commutator is used to
operate the three phase voltage source inverter
(VSI) bridge rectifier which is used to run
PMBLDC and it drives an air conditioning
compressor. Thus the speed of the permanent
magnet brushless DC motor (PMBLDCM) is
controlled with the help of the controller and
produce better output performance with the
reduction in total harmonic distortion (THD).
The output performance characteristic of the
SMC controller is compared with the
conventional (PI) controller. Thus in this
proposed work SMC controller is designed to
provide reduction in total harmonic distortion
and the better speed control over a wide range
of variation of the input ac mains of the
PMBLDC system. This proposed work is
constructed for the main application of air
conditioner. The power quality is improved as
the total harmonic distortion (THD) is reduced
for this system and their corresponding
simulation results are developed with the help of
MATLAB SIMULINK software.
Keywords: Power factor correction (PFC),
Permanent magnet brushless DC (PMBLDC)
motor, Sliding Mode controller (SMC), Cuk
converter, Voltage Source Inverter (VSI).
I. INTRODUCTION
The main features of permanent magnet brushless
DC (PMBLDC) motor as wide speed range with
high efficiency and low maintenance leads to their
vast use of applications in low power appliances [2]
[5]. The 3 synchronous motor has rugged
construction with the permanent magnet rotor. The
electrical commutation in permanent magnet
brushless DC motor is achieved by power switches
of 3 VSI. With the maintenance of air
conditioner temperature at the reference set value,
the PMBLDC motor in the application of air
conditioning compressor provides better efficiency.
When PMBLDC motor is operated under speed
controlled, the air conditioner leads to constant
torque operation. The air conditioner with
PMBLDC motor used for low power appliances
due to their advantages as reduced running rate,
extended life and reduction of mechanical stress
and electrical stress.
Among different converter configuration, power
factor correction (PFC) converter is more expected
for a permanent magnet brushless DC (PMBLDC)
motor [5], [6]. The IEC 61000 3 2 standards of
power quality for low power appliances [8], give
attention on nearer to unity pf and low harmonic
contents which is drawn by these drives from ac
mains.
Though there are many works describing about
permanent magnet brushless DC (PMBLDC) motor
with PFC converter topologies such as battery
charging applications and PFC converter with
switched mode power supplies. This proposed
work deals with the speed control of permanent
magnet brushless DC (PMBLDC) motor
integrating with power factor correction (PFC)
converter. In this work, the DC DC Cuk
converter is employed as a power factor correction
(PFC) converter. Since DC DC Cuk converter has
advantageous such as small output filter and wide
range of output voltage with the continuous input
and output currents than other converter topologies
[9] [10].



II. SPEED CONTROL METHOD OF
PROPOSED SYSTEM
The speed control method of permanent magnet
brushless DC (PMBLDC) motor for air
conditioner compressor with the aid of sliding
mode controller which drives DC DC cuk
converter is designed and shown in block diagram
representation in Fig.1.

Fig.1.Speed Control Method of Proposed System
The proposed system block diagram explains the
control operation and speed control of permanent
magnet brushless DC (PMBLDC) motor. The
single stage AC source is used for the generation of
reference current which also has the input I
c
from
SMC controller output. This reference current
generator is used to produce the output of current
I
d
*. The current I
d
*
act as the input to PWM current
controller which compares with current I
d
obtained
from the output of diode bridge rectifier. The error
output from the PWM current controller act as
pulse generating signal for the power
semiconductor switches of DC DC cuk converter.
The input for sliding mode controller is generated
from the output error signal of DC DC cuk
converter voltage V
dc
comparison with reference
voltage V
dc
*
. The permanent magnet brushless DC
(PMBLDC) used for the application air
conditioner compressor is fed from three voltage
source inverter (VSI). The voltage source inverter
(VSI) get the driving signals with the aid of
electronic commutator.
Thus the cuk converter is mainly used to control
the speed of permanent magnet brushless DC
(PMBLDC) motor with the aid of dc link voltage
input to the voltage source inverter (VSI). The
power semiconductor switches of metal oxide
semiconductor field effect transistor (MOSFET)
and insulated gate bipolar transistor (IGBT) are
used for the proposed power factor correction
(PFC) converter and voltage source inverter (VSI)
circuit for the high and low frequency operation
respectively. The electronic commutator output is
generated based upon the Hall Effect sensor
signals. The switching sequence of the power
semiconductor switching sequence and the hall
effect signals are tabulated and shown in TABLE I
[6], [11].
TABLE I
ELECTRONIC COMMUTATOR OUTPUT
BASED UPON HALL EFFECT SENSOR
SIGNALS

From the TABLE I show that the values of 0 and
1 as the operation of ON and OFF condition of
power semiconductor switches IGBTs of the
voltage source inverter (VSI). The upper switches
are named in order as S
a1
, S
b1
, S
c1
and the lower
switches as S
a2
, S
b2
, S
c2
.

III. SLIDING MODE CONTROLLER
The sliding mode controller is mainly an adaptive
control which generates the robust characteristics
of a system with the load torque T
L
disturbance and
also parameter variation. The drive response is used
to slide along a path or reference trajectory with the
help of switching algorithm. The sliding mode
controller is used for the various applications as
drive applications, machine tool control and also
for converter applications. The sliding mode
controller is generally a variable structure
controller.
www.ijrde.com

Methods Enriching Power and Energy Development (

The sliding surface of the system is considered as
trajectory or path along the switching sequence
waveform is shown in Fig.2. The sliding surface
s with the time control switching conditio
or 0 is represented in this figure as s>0 or s<0
respectively. The chattering effect in the system is
reduced with the help of developing any one of the
piece wise linear functions as shown in Fig.3.
Fig.2. General sliding mode surface along the switches
waveforms

Fig.3.Piece Wise Linear Functions
The sliding mode controller for the closed loop
control of the system is shown in Fig.4.
ISSN: 2279-0500 Special Issue:
The sliding surface of the system is considered as
trajectory or path along the switching sequence
waveform is shown in Fig.2. The sliding surface
s with the time control switching condition of 1
or 0 is represented in this figure as s>0 or s<0
respectively. The chattering effect in the system is
the help of developing any one of the
wise linear functions as shown in Fig.3.

along the switches

The sliding mode controller for the closed loop
control of the system is shown in Fig.4.
Fig.4.Sliding Mode Controller of the Closed Loop
Control System.
The voltage loop generates voltage error due to the
disturbances if the DC DC cuk converter is under
open loop control. The PI controller is used to
eliminate this error and produce the current i
voltage loop of the system is given by the equation
representation as,
I
*
= I
1d
+ I
c
The current loop for the switching manifold of
sliding mode current controller is represented by
the equation as:
S= I
1
I*

The control signal for the cuk converter power
switches with the aid of piece
function characteristics of sign as:
U = 0.5 (1 sign(s)) = 1if S<0 or if S>0
The condition of sliding mode existence can be
derived with a candidate Lyapunov function can be
P = 0.5S
2
>0 if S 0
Differentiating this equation as:
S = - (1 u)

With Eq. (3.2.15), the derivative of P is
P = ss
2 21

The sufficient condition for P < 0 is
2E 2L1i* V1- V1 < 0
Special Issue: pp- 120-124
122 | P a g e

Fig.4.Sliding Mode Controller of the Closed Loop
tage error due to the
DC cuk converter is under
open loop control. The PI controller is used to
eliminate this error and produce the current i
c
. The
voltage loop of the system is given by the equation
The current loop for the switching manifold of
sliding mode current controller is represented by
converter power
switches with the aid of piece wise linear
function characteristics of sign as:
sign(s)) = 1if S<0 or if S>0
The condition of sliding mode existence can be
derived with a candidate Lyapunov function can be
0

With Eq. (3.2.15), the derivative of P is
1 1
The sufficient condition for P < 0 is
V1 < 0


In the steady state, one has L
1
I* = 0 due to constant
I*, V2 = Vd, V1d = V1, and V2 = E V1 < 0 due
to Eq.(3.2.10). The inequality 12 leads to
0 < E L
1
I* < E V
2

And also, V
2
is negative and |V
2
| can be greater
than or less than E.


The simulation result of the proposed system is
shown in following figures. The Fig.5.1. shows
response of the pulse generated to the cuk converter
power switches. The Fig.5.2. shows the output
voltage response of cuk converter with the
reference set point of 298V. The Fig.5.3. shows
the response of speed control characteristics for the
reference set point of 298V. The Fig.5.4. shows the
response of THD analysis of proposed system with
SMC controller. The TABLE II shows the
performance of the proposed system result with the
representation of THD%, rate of speed, DC link
voltage V
dc
, the supply current I
s
.

Fig.5.1. Pulse Generated to Cuk Converter

Fig.5.2. Output voltage of Cuk converter with the
reference set point of 298V.

Fig.5.3. Output speed waveform for the reference set
point of 298V.
www.ijrde.com


Fig.5.4.THD analysis for proposed system using SMC
controller.

TABLE II
PERFORMANCE OF THE PROPOSED SYSTEM
RESULT

V. CONCLUSION
In this proposed work, the better speed control of
the system was obtained with the help of sliding
mode controller (SMC) and the reference value of
DC link voltage V
dc
which is referred as reference
speed. The simulation result performance was also
obtained for this proposed work with the reduction
in the total harmonic distortion (THD) value due to
SMC controller, which is less than the result
obtained with conventional (PI) controller. Thus
one of the power quality (PQ) problem (reduced
THD value) is limited in this proposed system.
REFERENCES
[1] T. Kenjo and S. Nagamori, Permanent Magnet
Brushless DC Motors.Oxford, U.K.: clarendon,
1985.
[2] T. J. Sokira and W. Jaffe,Brushless DC Motors:
Electronic Commutation and Control. New York:
Tab, 1989.
[3] J. R. Hendershort and T. J. E. Miller, Design of
Brushless PermanentMagnet Motors. Oxford, U.K.:
Clarendon, 1994.

Fig.5.4.THD analysis for proposed system using SMC
FORMANCE OF THE PROPOSED SYSTEM
In this proposed work, the better speed control of
the system was obtained with the help of sliding
mode controller (SMC) and the reference value of
which is referred as reference
speed. The simulation result performance was also
ed for this proposed work with the reduction
in the total harmonic distortion (THD) value due to
SMC controller, which is less than the result
obtained with conventional (PI) controller. Thus
one of the power quality (PQ) problem (reduced
ited in this proposed system.
T. Kenjo and S. Nagamori, Permanent Magnet
Brushless DC Motors.Oxford, U.K.: clarendon,
T. J. Sokira and W. Jaffe,Brushless DC Motors:
Electronic Commutation and Control. New York:
and T. J. E. Miller, Design of
Brushless PermanentMagnet Motors. Oxford, U.K.:
[4] J. F. Gieras and M. Wing,Permanent Magnet Motor
TechnologyDesign and Application. New York:
Marcel Dekker, 2002.
[5] B. Singh, B. N. Singh, A. Chandra, K. Al
A. Pandey, and D. P. Kothari, A review of single
phase improved power quality ac
981, Oct. 2003.
[6] N. Mohan, M. Undeland, and W. P. Robbins,Power
Electronics: Converters, Applications a
Hoboken, NJ: Wiley, 1995. Limits for Harmonic
Current Emissions (Equipment Input Current
Per Phase), Int. Std. IEC 61000-3-2, 2000
[7] R. A. Kordkheili, M. Yazdani-Asrami, and A. M.
Sayidi., Making DC-DC converters easy to
understand for undergraduate students,in 2010
IEEE Conf. on Open Systems, Dec. 2010, pp. 28
33.
[8] T. F. Wu and S. A. Liang, A systematic approach
to developing single-stage soft switching PWM
sonverters, IEEE Trans. Power Electron., vol. 16,
no. 5, pp. 581-593, Feb. 2001.
[9] H. T. moon, H. S. Kim and M. J. Youn, A
Discret Time Predictive Current Control for
PMSM IEEE Trans. Power Electronic., vol.18,
no.1, pp. 464-472, Janvier. 2003.
[10] B.BOSSOUFI, M.KARIM, S.IONITA,
A.LAGRIOUI, The Optimal Direct Torque
Control of a PMSM drive: FPGA
Implementation with Matlab & Simulink
Simulation Journal of Theoretical and Applied
Information Technology JATIT, pp63
No.2, 30th June 2011.
V
dc
THD Speed
298 1.15% 1501
265 1.29% 1327
233 1.25% 1159
200 1.24% 999.37
183 1.26% 899.3
151 1.15% 731.1
135 1.27% 648.9
104 1.28% 490.3
124 | P a g e
J. F. Gieras and M. Wing,Permanent Magnet Motor
Design and Application. New York:
B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad,
A. Pandey, and D. P. Kothari, A review of single-
phase improved power quality acdc converters,
N. Mohan, M. Undeland, and W. P. Robbins,Power
Electronics: Converters, Applications and Design.
Hoboken, NJ: Wiley, 1995. Limits for Harmonic
Current Emissions (Equipment Input Current16 A
2, 2000
Asrami, and A. M.
DC converters easy to
graduate students,in 2010
IEEE Conf. on Open Systems, Dec. 2010, pp. 28-
T. F. Wu and S. A. Liang, A systematic approach
stage soft switching PWM
sonverters, IEEE Trans. Power Electron., vol. 16,
T. moon, H. S. Kim and M. J. Youn, A
Discret Time Predictive Current Control for
PMSM IEEE Trans. Power Electronic., vol.18,
B.BOSSOUFI, M.KARIM, S.IONITA,
A.LAGRIOUI, The Optimal Direct Torque
ntrol of a PMSM drive: FPGA-Based
Implementation with Matlab & Simulink
Simulation Journal of Theoretical and Applied
Information Technology JATIT, pp63-72, Vol. 28
I
s
7.003
8.025
6.721
5.23
4.875
3.794
3.289
2.355


A ZVS-PWM Three Phase Current Fed Push Pull DC-DC
Converter with Reduced Harmonics

Arunraj.M
1
, Dhinesh.AR
2,
Jenson George
3
, Priya.S
4
, K Sathiyasekar
5

1,2, 3
UG Student, Department of EEE, S.A. Engineering College, Chennai.
4
Assistant professor, Department of EEE, S.A. Engineering College, Chennai.
5
Professor, Department of EEE, S.A. Engineering College, Chennai.

Abstract- In this paper, a ZVS-PWM three-phase current
fed pushpull dcdc converter with reduced harmonics is
proposed. When compared to single-phase topologies, the
three-phase dcdc conversion increases the power density,
uses the magnetic core of the transformer more efficiently,
reduces the stress on switches, and requires smaller filters
since the frequency for its design is higher. The proposed
converter employs an active clamping technique by
connecting the primary side of the transformer to a multi
level inverter and a clamping capacitor and secondary
side with three-phase full wave rectifier. This circuit
allows the energy from the leakage inductances to be
reused, increasing the efficiency of the converter. If
appropriate parameters are chosen, soft-commutation of
the switches (ZVS) can also be achieved. The soft-
commutation improves the efficiency even further, allows
higher switching frequencies is to be used, and reduces the
electromagnetic interference significantly. Applications
such as fuel cell systems, transportation, and
uninterruptable power supplies are some examples that
can benefit from the advantages presented by this
converter.
Index TermsActive clamping, dcdc power conversion,
multiphase, soft-commutation, matlab.
I.INTRODUCTION
Three-phase systems are well known by their use in electric
power generation transmission and distribution. The cost
saving that they provide by employing less material than
single-phase systems assured success in these areas and led to
three-phase rectifiers, inverters, and also dcdc converters.
After this, other three-phase dcdc converter topologies were
developed and compared, and techniques to increase the
efficiency even more using soft-commutation [2][4] and
reducing the number of semiconductors in the output rectifier
bridge were studied. Most studies conclude that the three-
phase structures perform better than their single-phase
counterparts [5]. Depending on the topology, the voltage
across the switches is not naturally clamped, requiring
passive voltage clampers that dissipate energy stored in the
leakage inductances [6][8] to prevent overvoltage which
reduces efficiency. In order to avoid this problem, active
clamping techniques have already been presented for single-
phase converters and have successfully reused the energy that
would be dissipated both in nonisolated [9] and isolated
topologies [10].
The introduction of high-frequency three-phase transformers
on dcdc converters brought the possibility of increasing
power density, using the magnetic cores more efficiently and
reducing the current stress on power switches. In addition,
the increase in the high-frequency component seen by the
filters allowed the use of much smaller inductors and
capacitors. The voltage across the switches is not naturally
clamped, requiring passive voltage clampers that dissipate
energy stored in the leakage inductances to prevent
overvoltage.
In this topology, a full three-phase bridge and a clamping
capacitor on the primary side of the transformer are
responsible for the active clamping without the need for an
extra switch [11]. Compared to single phase inverter
multilevel inverter reduces harmonics and enhances the
efficiency compared to the converter in [1]. In the future, the
proposed converter could be applied as a high-efficiency
alternative to many applications such as the energy
processing of photovoltaic arrays and fuel cell systems
[12][13] or automotive devices and fuel cell powered
vehicles [14], where the three-phase dcdc conversion is
already showing its benefits.
II.PROPOSED ZVS PWM THREE PHASE DC-DC
CONVERTER


A. Circuit Description
The circuit for the proposed ZVS-PWM three phase current
fed push pull dc-dc converter is shown in Fig.1. Switches
S1-S12 and capacitor C
g
1-C
g
6 is added to the converter
presented in [8] for active clamping. Inductance Ld1, Ld2,
Ld3 are responsible for maintaining current during the
commutation level. They represent the sum of the leakage
inductance of the transformer and an external inductance,
which is added to each phase if needed.

Fig 1. simplified version of the active clamped zvs-pwm push-pull
dc-dc converter with 11-level inverter.
B. Modulation
The gate signals are generated by the comparison of the
modulating signal VM and ten triangular carriers 36
o
of
phase from each other. V
G1
, V
G2
, V
G3
, V
G4
, V
G5
V
G6
, V
G7
,
V
G8
, V
G9
, V
G10
, V
G11
and V
G12
are the gate signals of S
1
, S
2
,
S
3
,S
4
,S
5
,S
6
,S
7
,S
8
,S
9
,S
10
,S
11
and S
12
respectively, and
V
G1
, V
G2
, V
G3
, V
G4
, V
G5
V
G6
, V
G7
, V
G8
, V
G9
, V
G10
,
V
G11
and V
G12
are the gate signals of S
1
, S
2
, S
3
,S
4
,S
5

,S
6
,S
7
,S
8
,S
9
,S
10
,S
11
and S
12
switches respectively.
The converter proposed in this paper can work in all the
twelve regions simultaneously as defined TABLE I which is
different from [1][8]. Thus decreasing the switching losses.
TABLE I
OPERATION REGIONS
Region Duty cycle Switches
simultaneously on
R1
0< D <

None
R2
< D <

Up to two
R3
< D <

Up to three
R4
< D <

Up to four
R5
< D <

Up to five
R6
< D <

Up to six
R7
< D <

Up to seven
R8
< D <

Up to eight
R9
< D <

Up to nine
R10
< D <

Up to ten
R11
< D <

Up to eleven
R12
< D < 1
Up to twelve
In this paper, this converter will be analyzed for operation in
region R12. Operating in region R12 proves the principle of
the active clamping in this topology for the worst case as,
higher the duty cycle is, the higher is the voltage across the
switches. A good design for the other regions could achieve
an even better result.
C. Working
At the beginning all the switches are kept open. In this stage
no current will flow through the transformer. So the sine
wave will have zero carriers and zero step will be produced.
Now in the next step switch S
1
and S
2
are switched ON,
keeping all the other switches OFF. In this stage current from
V
G1
will pass through the switch S
1
and S
2,
then to inductor
L
d1
and finally to the rectifier bridge. Thus producing the
positive step one output from the inverter. Now switch S
3
and
S
4
are switched ON keeping switch S
1
and S
2
ON and all
other switches OFF. This will produce a current output from
the equivalent voltage of bridge 1 and 2. Bridge 1 and 2 are
interconnected and thus the current from them is the voltage
equivalent. To get third positive step we will switch ON the
combination of 1-2 and 2-3 bridges and thus increasing the
number of bridges raising the positive step.
To obtain the negative part of the 11 step output the voltage
from V
G1
is applied to the opposite leg of the bridge1 that is
to the switch S
1
and S
2
. Thus the first negative output is
obtained. To obtain the second negative step output switch
S
3
and S
4
is switched ON keeping the switch S
1
and S
2
ON
and keeping all other switches OFF.
Thus the bridges will be operated in the order of 1-2,1-3,1-
4,1-5,1-6,2-4,2-6,3-4,3-5,4-6,5-6

III.SIMULATION
Simulation circuit for the project is shown in Fig 2. The
output from the 11 level inverter is shown in Fig. 3. The
output voltage produced for the input of 36V is produced in
the Fig. 4


Fig 2.MATlab simulation circuit for zvs-pwm push pull dc-dc
converter

Fig 3. 11-level step output from the multi level inverter

Fig 4. Output voltage from the rectifier
IV. PROROTYPE DESCRIPTION
A prototype implementing the proposed converter was built
in order to validate the simulation results. The prototype is
made for single phase and the output with respect to three
phases is validated. The main specifications and components
used are shown in TABLE II. A photograph of the prototype
can be seen in Fig. 5.

Fig 5.Photograph of prototype

TABLE II
MAIN SPECIFICATION AND COMPONENTS OF THE
PROTOTYPE

Description Quantity Values
Input voltage(Vi) - 36V
Output Voltage(Vo) - 71V
7 tapping step-down
transformer
2 230/12V
3 tapping step down
transformer
1 230/6/12/24V
Step up transformer 1 6/12V
Polypropylene output
capacitor
4 1000F/63V
External commutation
capacitor
12 1000f/25V
MOSFETS 12 IRF840
RECTIFIERS 4 MUR860
PIC Mi-Controller 1 PIC16F877A
Optocoupler 16 TLP250

V.CONCLUSION
In this paper, a ZVS-PWM three-phase current-fed pushpull
dcdc converter with reduced harmonics has been proposed.
The operation stages were described, and the main
waveforms were plotted. A prototype was built for a rated


power of 4 kW based on the parameters calculated in the
design example. This prototype was able to operate with
active clamping and soft-commutation (ZVS) of the
MOSFETs. The waveforms acquired through the matlab
validate the output, and the measured efficiency for full load
was 93.2%, remaining above 94% for most of the load range.
As an isolated topology, this converter presents competitive
efficiency and can be applied with good performance as an
energy processing stage for many renewable sources. The
most suitable applications include distributed generation,
uninterruptable power supplies, and transportation.

REFERENCES

[1] Romero Leandro Andersen and Ivo Barbi, A ZVS-PWM Three-
Phase Current-Fed PushPull DCDC Converter, IEEE Trans. Ind.
Electron., vol. 60, no. 3, pp 838-846 march 2013.

[2] R. W. A. A. De Doncker, D. M. Divan, and M. H. Kheraluwala,
A three-phase soft-switched high power-density dc/dc converter for
high-power applications, IEEE Trans. Ind. Appl., vol. 27, no. 1, pp.
63 73, Jan./Feb. 1991.

[3] J. Jacobs, A. Averberg, and R. De Doncker, A novel three-phase
dc/dc converter for high-power applications, in Proc. Power
Electron. Spec. Conf., Aachen, Germany, vol. 3, pp. 18611867.

[4] D. S. Oliveira, Jr. and I. Barbi, A three-phase ZVS PWM dc/dc
converter with asymmetrical duty cycle for high power
applications, IEEE Trans. Power Electron., vol. 20, no. 2, pp. 370
377, Mar. 2005.

[5] J. Aguillon-Garcia and G. W. Moon, A high efficiency three-
phase ZVS PWM converter utilizing a positive double-star active
rectifier stage for server power supply, IEEE Trans. Ind. Electron.,
vol. 58, no. 8, pp. 3317 3329, Aug. 2011.

[6] S. V. G. Oliveira and I. Barbi, A three-phase step-up dcdc
converter with a three-phase high frequency transformer, in Proc.
IEEE ISIE, Dubrovnik, Croatia, Jun. 2005, vol. 2, pp. 571576.

[7] S. V. G. Oliveira and I. Barbi, A three-phase step-up dcdc
converter with a three-phase high-frequency transformer for dc
renewable power sources applications, IEEE Trans. Ind. Electron.,
vol. 58, no. 8, pp. 35673580, Aug. 2011.

[8] R. L. Andersen and I. Barbi, A three-phase current-fed push
pull dcdc converter, IEEE Trans. Power Electron., vol. 24, no. 2,
pp. 358368, Feb. 2009.
[9] C. M. C. Duarte and I. Barbi, An improved family of ZVS-
PWM active clamping dc-to-dc converters, IEEE Trans. Power

[10] F. J. Nome and I. Barbi, A ZVS clamping mode-current-fed
pushpull dcdc converter, in Proc. IEEE ISIE, Pretoria, South
Africa, Jul. 710, 1998, vol. 2, pp. 617621.

[11] H. Cha, J. Choi, and P. N. Enjeti, A three-phase current-fed
dc/dc converter with active clamp for low-dc renewable energy
sources, IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2784
2793, Nov. 2008.

[12] S. R. Moon and J. S. Lai, Multiphase isolated dcdc converters
for low voltage high-power fuel cell applications, in Proc. 22nd
Annu. IEEE APEC, Anaheim, CA, Feb. /Mar. 2007, pp. 10101016.

[13] H. Cha and P. Enjeti, A novel three-phase high power current-
fed dc/dc converter with active clamp for fuel cells, in Proc. Power
Electron. Spec. Conf., Orlando, FL, Jun. 2007, pp. 24852489.

[14] L. Tang and G.-J. Su, Experimental investigation of a soft-
switching three-phase, three-voltage bus dc/dc converter for fuel cell
vehicle applications, in Proc. IEEE Power Electron. Spec. Conf.,
Rhodes, Greece, Jun. 2008, pp. 585591.


Novel Approach to Reduce Harmonic Distortion using
Pseudorandom PWM Technique
S. Saravanan
1
, D. Dhinakaran
2
, J. Yuvaraj
3

1
Assistant professor, Department of Electrical and Electronics Engineering
ARM College of Engineering and Technology, Chennai, India.
2,3
Research Scholar, Department of Electrical and Electronics Engineering
ARM College of Engineering and Technology, Chennai, India.

ABSTRACT
Several methods have been used to eliminate or
minimize harmonics of Multilevel Inverter (MLI)
output. Even though several methods have been
proposed, we are unable to reach minimum Total
Harmonic Distortion (THD). A new carrier
modulation technique (Pseudorandom Carrier
Modulation) for multilevel inverter is proposed in
this paper. Conventionally single triangular carrier
is used to produce the fixed frequency PWM
signal and cause discrete frequency harmonics,
Electro-magnetic interference and audible
switching noise. The proposed pseudorandom
carrier is produced through the random selection
of two triangular signals that are of same
frequency but in opposite phase. The random
selection of triangular carrier is decided by the
Pseudorandom Binary Sequence (PRBS). The
PRBS bits are generated using shift registers and
EXCLUSIVE OR gates. Multiplexers are used as
random selectors to produce the pseudorandom
(PR) frequency carrier waveform. The produced
random carrier is modulated using any modulation
technique to produce PWM signals for switching
devices. The modulated signals are used for the
H-bridge multilevel inverter. Here the PWM
pulses for each HBML inverter switches can be
obtained by comparing the sinusoidal reference
signal with the phase disposition arrangement of
eight random carriers to obtain nine level output
voltage. The multilevel inverter with
Pseudorandom Carrier Modulation drives a 5HP
Induction motor with reduced THD compared to
conventional method.
Keywords: Pseudorandom Pulse Width
Modulation, Pseudorandom Numbers, Linear
Feedback Shift Register (LFSR), Multilevel
Inverter and Harmonics
I. INTRODUCTION
Integrating multilevel inverters into medium and
high voltage industrial applications such as motor
drives, Flexible AC Transmission System (FACTS)
equipment, HVDC and renewable energy systems
is the issue of many ongoing researches. The main
advantages of multilevel inverters includes High
power and voltage ratings, power quality, more
electromagnetic compatibility, lower switching
losses, higher efficiency, higher voltage capability
and lower total harmonic distortion. Basically there
are three conventional topologies for multilevel
inverters such as Flying Capacitor, diode-clamped
and cascaded multi-level inverter with separate dc
sources [1-5]. Among them, the cascaded
multilevel inverter has received special attention
due to its modularity and simplicity of control
method. The principle operation of this inverter is
based on synthesizing the desired output voltage
waveform from several steps of voltage, which is
typically obtained from DC voltage sources. The
best way to reduce the audible switching Noise
radiated from the induction motor is to increase the
PWM switching frequency up to 20 kHz [6-7]. By
such a method, the Noise problem can be solved,
but it increases the switching loss of the inverter.
Generally, the random PWM scheme can be
implemented by using a microcontroller based on
space vector PWM or just hardware circuits.
Random pulse position PWM scheme randomly
varies the pulse position in every switching cycle.
Although many random PWM schemes have been
reported, the randomized switching frequency
modulation is the most popular technique. The
randomized switching frequency modulation can be
achieved through randomly varying the slope of the
PWM carrier triangular wave. In order to
implement the randomized switching frequency
modulation, using just hardware circuits, a PWM
triangular carrier generation circuit with


randomized frequency is needed. This circuit must
be made using high-precision analog and digital
elements [8-10].
In this paper, a pseudorandom triangular carrier
modulation is proposed and its total harmonic
distortion is discussed. The proposed
pseudorandom carrier is acquired by randomly
composing two triangular carriers, each of the same
fixed frequency, but of opposite phase. The random
selection of the two triangular carriers is decided by
low or high states of the pseudorandom binary
sequence (PRBS) random bits. Linear Feedback
Shift Register (LFSR) is used for the generation of
PRBS random bits. Here PRB sequences are
generated using 8 bit and 12 bit LFSR. The
comparative study has been proposed. Multiplexers
with two input/one output, which generates the
resultant carrier with pseudorandom frequency, are
used as random selector of the PRBS random bits.
To verify the proposed scheme, a 170 V
rms
single-
phase 9-level H-Bridge Multilevel (HBML)
inverter to drive a 5HP Capacitor Start Induction
Motor was simulated. Experiment shows that the
less total harmonic distortion (THD) for output
voltage of a multilevel inverter and induction motor
main winding current are discussed. Finally, the
proposed scheme can be applicable to the existing
power electronics converters, by changing the fixed
switching frequency triangular carrier generator
into the proposed random carrier generator.
II. PSEUDORANDOM CARRIER
SCHEME
The overall Block diagram of a Pseudorandom
Carrier Modulation Technique is shown in Figure
1. The proposed method having function generator
to generate two triangular carriers each of opposite
in phase but frequency and magnitude are same.
The random selection of two carriers can be done
through multiplexer. The multiplexer needs control
signals to select any one of the signal to composite.
The control signals are the pseudorandom bits
(PRB) which can be generated through Linear
Feedback Shift Register (LFSR). Now the
pseudorandom carrier is generated through
multiplexer with the help of pseudorandom bits.

Figure 1: Pseudorandom Carrier Modulation Scheme
overall block diagram
The Pseudorandom carrier is compared with the
help of phase decomposition comparator. The
phase decomposition comparator gives the PWM
signals for the multilevel inverter. Initial value of
LFSR is called Seed. An LFSR is a shift register
that, when clocked, advances the signal through the
register from one bit to the next most-significant
bit. Some of the outputs are combined in exclusive-
OR configuration to form a feedback mechanism.
A linear feedback shift register can be formed by
performing exclusive-OR on the outputs of two or
more of the flip-flops together and feeding those
outputs back into the input of one of the flip-flops.
Linear feedback shift registers make extremely
good pseudorandom pattern generators. When the
outputs of the flip-flops are loaded with a seed
value (anything except all 0s, which would cause
the LFSR to produce all 0 patterns) and when the
LFSR is clocked, it will generate a pseudorandom
pattern of 1s and 0s. Note that the only signal
necessary to generate the test patterns is the clock.
A maximal-length LFSR produces the maximum
number of PRPG patterns possible and has a
pattern count equal to 2n 1, where n is the
number of register elements in the LFSR. It
produces patterns that have an approximately equal
number of 1s and 0s and have an equal number of
runs of 1s and 0s. Because there is no way to
predict mathematically if an LFSR will be maximal
length, Peterson and Weldon have compiled tables
of maximal-length LFSRs to which designers may
refer.
Table 1: Truth Table of Multiplexer
www.ijrde.com


PRBS State Output R
0 C

1 C
Table 1 shows the truth table of the multiplexer
illustrating the relation between PRBS states and
output R, which is dependent only on C and
shown in Figure. 2, the triangular carriers with
fixed frequency C and the triangular carriers with
fixed frequency with opposite phase C
the 21 multiplexer. Frequency of C and

equal. Then C and C
are randomly selected by the

output PRBS bits 0 or 1 of the random bits
generator. Choice of C and C
is dependent on the
output P of the PRBS random bits generator. In
case that the P is 1 then .R is selected as C, and if P
is 0 then R is selected as C

Figure 2: Pseudorandom Carrier Generation
Consequently, it means that the proposed random
carrier R can be synthesized with a pseudorandom
frequency. Because the proposed random carrier R
is made from the two triangular waveforms with
same fixed frequency, but of opposite phase, the
proposed scheme is named pseudorandom carrier
scheme.
shows the truth table of the multiplexer

illustrating the relation between PRBS states and
output R, which is dependent only on C and C
. As
shown in Figure. 2, the triangular carriers with
fixed frequency C and the triangular carriers with
C
are input to
the 21 multiplexer. Frequency of C and C
are
are randomly selected by the
output PRBS bits 0 or 1 of the random bits
is dependent on the
generator. In
R is selected as C, and if P
Figure 2: Pseudorandom Carrier Generation
Consequently, it means that the proposed random
carrier R can be synthesized with a pseudorandom
frequency. Because the proposed random carrier R
is made from the two triangular waveforms with
same fixed frequency, but of opposite phase, the
me is named pseudorandom carrier
Figure 3: Detailed waveforms of Pseudorandom carrier
Generation
Figure 3 shows the detail waveforms of the
proposed method in Figure. 1 the output P of the
PRBS random bits generator is similar to the
conventional random leadlag PWM. The random
leadlag PWM is the early version among random
PWM, and its pulses are randomly placed between
first position and last position in the modulation
interval.
Figure 4: Simulated waveforms of generated Pseudo
random carrier using 2 kHz carriers C and C
The modulation is done using phase shifted
Pseudorandom carriers and sinusoidal reference
signal. Figure 5 shows the phase shifted
pseudorandom carrier with sinusoidal reference
signal. For 9-level inverter output 8
sue: pp- 129-135
131 | P a g e

Figure 3: Detailed waveforms of Pseudorandom carrier
Figure 3 shows the detail waveforms of the
proposed method in Figure. 1 the output P of the
PRBS random bits generator is similar to the
lag PWM. The random
lag PWM is the early version among random
PWM, and its pulses are randomly placed between
first position and last position in the modulation
Figure 4: Simulated waveforms of generated Pseudo-
dom carrier using 2 kHz carriers C and C
The modulation is done using phase shifted
Pseudorandom carriers and sinusoidal reference
signal. Figure 5 shows the phase shifted
pseudorandom carrier with sinusoidal reference
level inverter output 8 carriers (A to


H) are required to produce 4 pairs of PWM signals
for four H-Bridges as shown in figure 6. A & B
pulses are used for bridge1, C & D pulses are used
for bridge2, E & F pulses are used for bridge3 and
G & H pulses are used for bridge4. For 5-level
inverter output 4 carriers are enough to produce 2
pairs of PWM signals for two H-Bridges. The
carrier frequency is increased to get less distorted
quality output. Here carrier frequency is selected as
2kHz and 4kHz for comparison. The
Pseudorandom PWM signals are used as switching
signals for cascaded multilevel inverter switches
which gives the output of 9-level, 50Hz, 170 Vrms.
This output voltage used to drive the 5HP
Capacitor Start Induction Motor. The multilevel
inverter output voltage is subjected to FFT analysis
for the calculation of THD and to determine
harmonic spectra.

Figure 5: Simulated phase shifted Pseudorandom carriers
with sine wave
II. SIMULATED
EXPERIMENTALSYSTEM
Multilevel inverter is used for the verification
of PRPWM Technique. H-Bridge MLI is
selected for the experimental setup. Figure 6
shows the experimental setup of a 170-Vrms
single phase HBML inverter based on the
proposed method. The insulated-gate bipolar
transistors (IGBTs) are chosen as the switching
devices of H-bridge inverters. A switched-
mode power supply (SMPS) (Vd= 60 V) are
adopted as dc voltage sources of each H-bridge
inverters (cell inverters). The resultant voltage
(V0 = 170Vrms) is synthesized by adding the
output voltages (V1,V2,V3,V4) of each H-
bridge inverters, and it supplies to 5HP
Capacitor Start Induction Motor. A cascade
connection of four H-bridge inverters produced
a nine-level output waveform. For isolation of
each H-bridge inverters and load, a coupling
transformer with winding ratio 1:1 is
employed.

Figure 6: Single phase Cascaded Multilevel Inverter
In general, the switching frequency of random
PWM scheme for dc-to-ac inverter is below 5
kHz. Hence, the carrier frequency of the
proposed scheme is selected as 2 kHz and
4kHz. Figure 2 illustrates the configuration of
the proposed pseudorandom carrier generator.
As shown in Figure 2, a triangular carrier
waveform with fixed frequency and clock
pulses for PRBS random bit generator are
generated. The PRBS random bits generator is
implemented, using a shift register and an
EXCLUSIVE OR.

Figure 7: Simulated Experimental System
The bidirectional switch is employed as a
multiplexer, and it generates the pseudorandom
frequency carrier R. To apply it to a multilevel


inverter, the resultant carrier R is arranged for
phase disposition, where four carriers (R1
~R4) are in phase, as shown Figure 5. The
PWM pulses (1-cell ~4-cell) of each HBML
inverters can be obtained by comparison a
reference sinusoidal waveform with the phase-
disposition arrangement of eight
pseudorandom carriers. The output of the
inverter is applied to the 5HP Capacitor Start
Induction Motor. Figure 7 shows the simulated
circuit using MATLAB/SIMULINK.
The generated Pseudorandom PWM is used for
multilevel inverter switching which gives the
output voltage of 170 Vrms as shown in Figure
8. The output of the multilevel inverter drives
the 5HP Induction motor. Figure 9 illustrates
the harmonic spectra analysis for the MLI
output voltage using Figure 9(a). SPWM
Technique and Figure 9(b). PRPWM
Technique with 12 bit LFSR and 4kHz Carrier
Frequency. The result shows the best
performance than conventional.

Figure 8: H-Bridge 9-level inverter output voltage

(a)

(b)
Figure 9: Harmonic Spectrum of MLI output voltage
using (a). SPWM Technique, (b). PRPWM Technique
with 12 Bit LFSR and 4kHz Carrier
Here it shows that it has four bridges, those are
having separate DC sources, every bridge having
four controllable switches and the pulses for the
controllable switches. Every separate DC sources
giving +60V inputs to the bridges. The pulse
generation for those switches are explained in the
above chapters. The output of the individual
bridges is shown in figure 6. The 9-level output
voltage waveform is shown in figure 8. The RMS
voltage of the multilevel inverter output voltage is
about 170Vrms.
The output of the inverter is used to feed Induction
Motor of rating 5HP, 240V, 50Hz. The


performance of Induction Motor is shown in fig 10.
The Induction Motor performance parameters are
a).Main winding current (amp), b).Auxiliary
winding current (amp), c). Capacitor Voltage
(volts), d).Electromagnetic Torque (Nm), e). Rotor
Speed (rpm).

TABLE 2: Comparative Study of Harmonics In MLI
Output Voltage For Different PWM Techniques

Conventio
nal Method
(SPWM)
Pseudorandom PWM
8bits 12bits
2kHz 2kHz 4kHz 2kHz 4kHz
V
rms
182.5V
178.4
V
169.7
V
169.8
%
169.7
V
V
Pea
k

258.1V
252.3
V
240V
240.1
%
240V
TH
D
11.78%
6.87
%
7.69
%
7.56%
7.69
%
H
3
3.88%
1.89
%
0.02
%
0.05%
0.03
%
H
5
2.36%
1.73
%
0.01
%
0.05%
0.02
%
H
7
1.38%
0.97
%
0.03
%
0.03%
0.05
%
H
9
0.47%
0.49
%
0.06
%
0.11%
0.02
%
H
11
0.42%
0.32
%
0.06
%
0.05%
0.04
%
H
13
0.34%
0.20
%
0.05
%
0.17%
0.05
%
H
15
1.21%
0.28
%
0.00
%
0.10%
0.02
%
H
17
1.81%
0.11
%
0.02
%
0.07%
0.04
%
H
19
0.91%
0.06
%
0.04
%
0.25%
0.15
%

Figure 10: Performance of Induction motor driven with
9-level Inverter
V. CONCLUSION
In this paper, the simulation of the proposed
method is quite simple and it has the merit that the
random carrier can be generated from fixed
frequency carrier. A pseudorandom frequency
carrier scheme has been proposed as a new method
to generation a random carrier. The proposed
scheme produces the pseudo triangular carrier
waveform with the random frequency through the
random composition of the two triangular carriers,
each of the same fixed frequency but of opposite
phase. The random composition of two triangular
carriers can be done through multiplexer with the
help of pseudorandom bit sequence generated by
the 2kHz Linear Feedback Shift Register. The
pseudorandom carriers are used to produce the
PWM pulses for the 170-Vrms single-phase 9 level
HBML inverter. The multilevel inverter has four H-
bridges which are having input of 60V DC in
individual H-bridges. For the PWM generation
pseudorandom carriers and sinusoidal signals were
used. The multilevel inverter output is used to drive
the 5HP Induction motor. The pseudorandom
PWM technique is done for the different
configurations such as Pseudorandom PWM
technique with 8bit shift register and 2 KHz carrier
frequency, Pseudorandom PWM with 8bit shift
register and 5 KHz carrier frequency,
Pseudorandom PWM 12bit shift register and 2 KHz
carrier frequency and Pseudorandom PWM 12bit
shift register and 5 KHz carrier frequency. The
harmonic distortion of multilevel inverter voltage
for these configurations are studied and compared.
From the analysis the Pseudorandom PWM with
8bit shift register, 2 KHz carrier frequency shows
the improved results when we taking multilevel
inverter output voltage. If we took lower order
harmonics redution as a parameter for analysis,
PWM with 8bit shift register, 5 KHz carrier
frequency shows the improved results. Finally, the
proposed random carrier generator is simulated
using MATLAB/SIMULINK, the proposed scheme
can be applicable to the existing power electronics
converters by changing the fixed switching
frequency triangular carrier generator into the
proposed random carrier generator.
REFERENCES


[1] Young-Cheol Lim, Seog-Oh Wi, Jong-Nam Kim, and
Young-Gook Jung, A Pseudorandom Carrier
Modulation Scheme, IEEE transactions on power
electronics, vol. 25, no. 4, april 2010
[2] F.Mihalic and D. Kos, Reduced conductive EMI in
switched-mode dc-dc power converters without EMI
filters: PWM versus randomized PWM, IEEE Trans.
Power Electron., vol. 21, no. 6, pp. 17831794, Nov.
2006.
[3] M. M. Bech, J. K. Pedersen, and F. Blaabjerg,
Random modulation techniques with fixed switching
frequency for three-phase power converters, IEEE
Trans. Power Electron., vol. 15, no. 4, pp. 753761, Jul.
2000.
[4] C. M. Liaw and Y. M. Lin, Random slope PWM
inverter using existing system background noise:
Analysis, design and implementation, IEE Proc. Electr.
Power Appl., vol. 147, no. 1, pp. 4554, 2000.
[5] V. Blasko, M. M. Bech, F. Blaabjerg, and K.
Pedersen, A New hybrid random pulse width modulator
for industrial drives, in Proc. IEEE APEC2000, pp.
932938.
[6] S. Y. R. Hui, I. Oppermann, and S. Sathiakumar,
Microprocessor-based random PWM schemes for DC-
AC power conversion, IEEE Trarns. Power Electron.,
vol. 12, no. 2, pp. 253260, Mar. 1997.
[7] K. S. Kim, Y. G. Jung, and Y. C. Lim, A new hybrid
random PWM scheme, IEEE Trans. Power Electron.,
vol. 24, no. 1, pp. 192200, Jan. 2009.
[8] A. M. Hava and E. Un, Performance analysis of
reduced common-mode voltage PWM methods and
comparison with standard PWM methods for three-phase
voltage-source inverters, IEEE Trans. Power Electron.,
vol. 24, no. 1, pp. 241259, Jan. 2009.
[9] D. V. Ghodke, K. Chatterjee, and B. G. Fernandes,
Three-phase three level, soft switched, phase
shiftedPWMDCDC converter for high-power
applications, IEEE Trans. Power Electron., vol. 23, no.
3, pp. 12141227, Jun. 2008.
[10] R. Yang, B. Zhang, D. Qiu, and Z. Liu, Time
frequency and wavelet transforms of EMI dynamic
spectrum in chaotic converter, IEEE Trans. Power
Electron., vol. 24, no. 4, pp. 10831092, Apr. 2009.



Photovoltaic Based implementation of Coupled Inductor
Interleaved Boost Converter with LC Filter for Ripple Free
Current

S.Tony Richard
1
, R.G.Nirmala
2

1
(M.E Power Electronics and Drives, St. Josephs College of Engineering, India)
2
(Assistant Professor, Department of EEE, St. Josephs College of Engineering, India)

ABSTRACT
This paper presents coupled inductor interleaved boost
converter with LC filter for ripple free current. In
addition to coupled inductor interleaved boost converter
two LC filter and one coupled inductor is added to
proposed circuit. So the proposed converter achieves
reduced input and output current ripple. Hence the
ripple ratio of input and output current is reduced. In
order to verify that, a proposed converter of 20v input
voltage from PV panel and 40v output voltage operating
at 50 khz is constructed. And simulations are verified by
using MATLAB Simulink. So the ripple free proposed
circuit is used for various photovoltaic generation
purpose.

Key words Coupled inductor,dc-dc converter, Mutual
inductance
1. INTRODUCTION
Nowadays, boost converter is used in most of the
photovoltaic generation application. It uses PV panel as a
electrical source. Here input current has more ripple, which
is directing from the PV panel is a major problem in dc-dc
boost converter.
The input current ripple of the dc-dc converter is
inversely proportional to input inductor current value. So the
larger inductor value results in low ripple, on other
increasing the inductor value the total weight of the
converter gets increased [1-3]. The proposed converter aims
that without increasing the inductor value the ripple should
be reduced. So that interleaving of the converter technique is
used. By using interleaving technique the ripple is reduced
but the weight of the converter is not reduced.
So that the new technique called coupled inductor
interleaved boost converter technique is used. Here the
ripple is reduced than interleaving technique and the weight
of the converter is reduced since the core is shared, and
inductor was coiled in single core [4-5]. However, the
leakage inductance of the coupled inductor increases the
current stress of the output diodes. The soft switching
technique is the solution for this type of the problem but
however, the control strategy of this circuit is too complex
and not cost-effective.
In order to overcome the disadvantage of
conventional converters, the new topology called coupled
inductor interleaved boost converter with LC filter is
developed. This converter uses two coupled inductor and
two LC filter connected series to the coupled inductor. Here
the LC filter is used to eliminate di / dt and gives ripple free
input and output current.

Fig.1 PV Panel



Fig.1 Proposed Coupled inductor interleaved boost converter
with LC Filter
II. COUPLED INDUCTOR INTERLEAVED
BOOST CONVERTER AND ITS OPERATING
PRINCIPLE
If the two inductors were coupled together, the input
and output current ripple can be reduced than interleaved
boost converter. We can get high power density because of
using only one core. The coupled inductor interleaved boost
converter has same switching sequence as the conventional
converter. However, the leakage inductance of the coupled
inductor increases the current stress of the output diodes,
introducing extra electromagnetic interference (EMI)
problems ,the circuit is simplified into two typical stages and
the corresponding equivalent circuits is shown below

Fig.2 Coupled inductor interleaved boost converter

Mode 1 [ t0, t1 ]:At t0, S1 turns ON and switch S2 turns
OFF. During this period, the inductor L1 linearly charged by
the input voltage. Due to this IL1 increases linearly. Due to
reverse bias condition Do1 maintains OFF stage, because of
the voltage stress across the diode is equal to the output
voltage. Meanwhile the energy stored in the inductor L2
gets transferred to load Ro, because of the coupled relation
between two inductor ,the current IL2 decreases more.

Fig.3 Mode 1

Mode 2 [ t1 , t2 ]:At t1.both switches S1 and S2 are in
OFF state ,meanwhile the energy from inductor L1 and L2
gets transfer to the load Ro. So the current across the
inductor IL1 and IL2 decreases linearly. During this the
voltage across the switch S1 and S2 equals to the output
voltage .In this mode the coupled inductor branches still
work as a filter to minimize the input and output current
ripple.

Fig.4 Mode 2

Input current ripple is given by

2 2. .
.

Input ripple current is given by
2 15 10
2 10.605 10
. 36 10.605 10
15 10
. 50
15 10
10.605 10

40 20
40
. 10

.

Input ripple current ratio is given by

*100

.
*100
. %
Output ripple current is given by
.

Output ripple current ratio is given by

*100

.
.
*100
. %



III.COUPLED INDUCTOR INTERLEAVED
BOOST CONVERTER WITH LC FILTERAND
ITS OPERATIONAL PRINCIPLE

Mode 1 [ t0, t1 ]:At t0, S1 turns ON and switch S2 turns
OFF. During this period, the inductor L1 linearly charged by
the input voltage. Due to this IL1 increases linearly. Due to
reverse bias condition Do1 maintains OFF stage, because of
the voltage stress across the diode is equal to the output
voltage. Meanwhile the energy stored in the inductor L2 gets
transferred to load Ro, because of the coupled relation
between two inductor, the current IL2 decreases more. Due
to this the zero current rippleis achieved.

Fig.5 Mode 1

Equations

Mode 2 [ t1 , t2 ]: At t1.both switches S1 and S2 are in
OFF state ,meanwhile the energy from inductor L1 and L2
gets transfer to the load Ro. So the current across the
inductor IL1 and IL2 decreases linearly. During this the
voltage across the switch S1 and S2 equals to the output
voltage .In this mode the coupled inductor branches still
work as a filter to minimize the input and output current
ripple

Fig.6 Mode 2

Equations

Here,Input ripple current is given by

.

1 2
0.98515 10
15 10



5.395 10
2 10
3.4 10
2 36 50
5.395 10
15 10
2 10
15 10
3.4 10

40 20
40
. 10

Input ripple current is given by
0.25A


0.25
10

. %

Output ripple current is given by
0.0015A


0.0015
2.38

. %


A 20v-40v proposed dc-dc converter operating at
50 khz switching frequency is designed and simulated to
verify the proposed concept. Simulations of the proposed
converter are carried out in MATLAB and the key
parameters are listed in Table I. Duty cycle of each
converter is 0.5. Here the PV panel also simulated by using
SIMULINK. And the output of the PV panel is about 20V
dc voltage. Which are used as a input source to proposed
converter.

Fig.7 Matlab Simulation diagram of PV Panel

Fig.8Matlab Simulation diagram of conventional converter



Fig.9 Matlab Simulation diagram of proposed converter

Fig.10 PV Panel output voltage waveform

Fig.11 Conventional converter-Input current ripple waveform

Fig.12 : Conventional converter-Output current ripple
waveform

Fig.13 Proposed converter-Input current ripple waveform


Fig.14 Proposed converter-Output current ripple waveform

Table I: Input parameters

S.No Parameters Value
1 Input voltage (
20 V
2 Output voltage (
40 V
3 Switching frequency (
) 50 Khz
4 Main Inductor
15 H
5 Coupled inductor (
,
) 2 H
6 Inductor (
3.4H
7 Coupling coefficient (K) 0.985
8 Capacitor (
10 F
9 Output capacitor (
470 F

Table II: Simulation output summary

V. CONCLUSION

It is concluded that, the proposed converter achieves
huge reduction of input current ripple. Which are from PV
panel connected to dc-dc converter.In addition to that the
load side output current ripple also reduced. At last, a 20v
input40v output PV type prototype circuit is implemented
to verify the expected performance. The simulation and
experimental results shows that the proposed converter
achieves input and output current ripple reduction than
conventional one. It shows that the proposed converter has
great potential to be used in photovoltaic generating system.

VII.REFERENCES

S
.
N
O
PARAMETERS
COUPLED
INDUCTOR
INTERLEA
VED BOOST
CONVERTE
R
COUPLED
INDUCTO
R
INTERLE
AVED
BOOST
CONVERT
ER WITH
LC
FILTER
1
INPUT CURRENT
RIPPLE (A)
2.9 0.25
2
INPUT CURRENT
RIPPLE RATIO
(%)
20.71 2.5
3
OUTPUT
CURRENT RIPPLE
(A)
0.00166 0.0015
4
OUTPUT
CURRENT RIPPLE
RATIO (%)
0.0877 0.063


1. J. R. Pinheiro, H. A. Grundling, D. L. R. Vidor, and J. E.
Baggio,Control strategy of an interleaved boost power factor
correction converter, in Proc. IEEE Power Electron. Spec. Conf.,
1999, pp. 137142

2. M. Pahlevaninezhad, P. Das, J. Drobnik, P. K. Jain, and A.
Bakhshai, AZVS interleaved boostAC/DC converter used in plug-
in electric vehicles, IEEE Trans. Power Electron., vol. 27, no. 8,
pp. 35133529, Aug. 2012.

3. Y. Jang and M. M. Jovanovic, Interleaved boost converter with
intrinsic voltage-doubler characteristic for universal-line PFC front
end, IEEE Trans. Power Electron., vol. 22, no. 4, pp. 13941401,
Jul. 2007.

4. S. Park, Y. Park, S. Choi, W. Choi, and K. B. Lee, Soft-
switched Interleaved boost converters for high step-up and high-
power applications, IEEE Trans. Power Electron., vol. 26, no. 10,
pp. 29062914, Oct. 2011.

5. R. Martinelli and C. Ashley, Coupled inductor boost converter
with input and output ripple cancellation, in Proc. Appl. Power
Electron. Conf. Expo., 1991, pp. 567572

6. Y. Hu,Y.Xie, H. Tian, and B. Mei, Characteristics analysis of
two channel interleaved boost converter with integrated coupling
inductor, in Proc.IEEE Power Electron. Spec. Conf., Jun. 2006,
pp. 16.



Power Quality Issues, Problems and
Solution: Special Feature

Vipul Kumar
1
, Om Shivam
2
, Raj Kumar Sharma
3
, Tanmaya Kumar Patel
4
*EEE, Dr. M.G.R. Educational and Research Institute, University, Maduravoyal, Chennai- 95, TamilNadu,
India

ABSTRACT
This paper outlines the power quality problems,
issues and its solution. The Power generation
industry is undergoing major changes and
increasingly power quality is at the forefront.
Industry as a whole is concerned about the
reliability of supply, whether it is disturbances,
interruptions or major outages to be able to
manage the power quality. Power quality is an
issue that is becoming increasingly important to
electricity consumers at all levels of usage.
Sensitive equipment and non-linear loads are now
more commonplace in both the
industrial/commercial sectors and the domestic
environment. Because of the power quality issues
now days affecting the electricity supply that were
once considered acceptable by electricity
companies and users are now often considered a
problem to the users of everyday equipment. In
solution part some of the method related
international standards, the effect of power quality
problems and methods to improve the power
quality problems.

Keywords: IEEE 519, Power quality problems,
Voltage Sag, Harmonics, International Electrical
Standards.

I. INTRODUCTION
This paper analyzes the key issues in the Power
Quality [27] [28] problems [1] [2], especially the
present trend towards more distributed generations and
consequent restructuring of power transmission and
distribution networks. As the prominent power quality
problems [3] are Voltage sags and harmonics. The
origin, consequences and mitigation techniques of
voltage sag and harmonics problems have been
discussed in detail [1]. Sag is defined as the variation
of RMS voltage from its normal value for a time
greater than 0.5 cycles of the power frequency but less
than or equal to 60 seconds. Short duration variation is
caused by fault conditions, the energization of large
loads which requires high starting current. Harmonics
are a sinusoidal component of a periodic wave or
quantity having a frequency that is an integral multiple
of the fundamental power frequency. The equation
representing a harmonic frequency is f
h
= f
1
* h.
Harmonic distortion exists due to the nonlinear
characteristics of the devices and loads on the power
system, these devices act as current sources that inject
harmonic currents into the power system. Important
Power quality standards are defined in the IEEE, IEC,
CENELEC, ANSI, and NER. The most universally
accepted standards for power quality are IEC and IEEE
standards. For research purposes, the flexibility and the
ability of easy prototyping are often more crucial
aspects than computational efficiency.

A. Power Quality Problems & Issues:
In recent survey says that the 50% of all Power
Quality problems are related to grounding, ground
bones, and neutral to ground voltages, ground loops,
ground current or other ground associated issues.
Electrically [2] [3] [6] [9] [27] operated or connected
equipment is affected by Power Quality. The
commonly used terms those describe the parameters of
electrical power that describe or measure power
quality are Voltage sags, Voltage variations,
Interruptions [16][17][18][19] Swells, Brownouts,
Blackouts, Voltage imbalance, Distortion, Harmonics,
Harmonic resonance, Inter harmonics, Notching,
Noise, Impulse, Spikes (Voltage), Ground noise,
Common mode noise, Critical load, Crest factor,
Electromagnetic compatibility, Dropout, Fault,
Flicker, Ground, Raw power, lean ground, Ground
loops, Voltage fluctuations,
Transient[4][8][10][24][30], Dirty power, Momentary
interruption, Over voltage, Under voltage, Nonlinear


load, THD, Trip lens, Voltage dip, Voltage regulation,
Blink, Oscillatory transient[26][36] etc. The
distortion in the quality of supply power can be
introduced /enhanced at various stages; however,
some of the primary sources of distortion
[1][2][3][23][27][28] can be identified as below:
i. Power Electronic Devices
ii. IT and Office Equipments,
iii. Arcing Devices,
iv. Load Switching,
v. Large Motor Starting,
vi. Embedded Generation,
vii. Electromagnetic Radiations and Cables,
viii. Storm and Environment Related Causes etc.

While power disturbances occur on all electrical
systems [4][7][23], the sensitivity of todays
sophisticated electronic devices makes them more
susceptible to the quality of power supply [2] [3]. A
power voltage spike can damage valuable components.
Some of the common power quality issues [19] [25]
and their prominent impact are summarized in the table
1 below:

Table 1: Various power quality problems, causes
and their effects
Problems Causes Effects
Voltage
Sags
Faults in the
transmission or
distribution
network.
Connection of
heavy loads or
motors.
Tripping of contractors
and electromechanical
relays, Disconnection
and loss of efficiency in
electric rotating
machines, etc.
Voltage
Spikes
Lightning,
Switching of lines
or power Factor
correction
capacitors,
removing of
heavy loads.
Destruction of
components and of
insulation materials,
Data processing errors
or data loss,
Electromagnetic
interference, etc.
Voltage
Swells
Start/stop of
heavy loads,
Poorly
dimensioned
power sources,
Poorly regulated
transformers.
Flickering of lighting
and screens, Damage or
stoppage or damage of
sensitive equipment, etc.
Voltage
fluctuation
Arc furnaces,
Frequent start/stop
of electric Motors
Most consequences are
common to under
voltages, Flickering of
(for instance
elevators),
oscillating loads.
lighting and screens, etc.
Voltage
Unbalance
Large 1 phase
loads (induction
furnaces, traction
loads), Incorrect
distribution of
loads by The three
phases of the
system.
The most affected loads
are three phase
induction machines,
Increase in the losses,
etc.
Harmonic
Distortion
Switched mode
power supply,
Fluorescent
lighting, 3-phase
rectifier,
Adjustable speed
drive
Conductor overheating,
Neutral overloads,
Increased probability of
occurrence of resonance,
Nuisance tripping of
thermal protections,
Loss of efficiency in
electric machines, etc.

B. Power Quality Standards:

Power quality [27] is a worldwide issue [17] [18] [20],
and keeping related standards current is a never-
ending task. It typically takes years to push changes
through the process. Most of the ongoing work of the
IEEE in harmonic standards [3] [20] [23] [30]
development has shifted to modifying Standard 519-
1992.

1. IEEE 519
i. IEEE 519 Standards for Current
Harmonics.
ii. IEEE Standard for Voltage Harmonics.

2. IEC 61000-3-2 and IEC 61000-3-4 (formerly
1000-3-2 and 1000-3-4).
i. IEC 61000-3-2 (1995-03)
ii. IEC/TS 61000-3-4 (1998-10
3. IEEE Standard 141-1993, Recommended
Practice for Electric Power Distribution for
Industrial Plants.
Practice for Grounding of Industrial and
Commercial Power Systems.
Practice for Emergency and Standby Power
Systems for Industrial and Commercial
Applications.
Practice for Design of Reliable Industrial and
Commercial Power Systems.
www.ijrde.com


Practice for Powering and Grounding Sensitive
Electronic Equipment.
8. IEEE Standard 1159-1995,
Practice for Monitoring Electric Power Quality.
9. IEEE Standard 1250-1995, Guide for Service to
Equipment Sensitive to Momentary Voltage
Disturbances.
10. IEEE Standard 1346-1998 Recommended
Practice for Evaluating Electric Power System
Compatibility with Electronic Process
Equipment.
11. Standards related to Voltage Sag and Reliability.
12. Standards related to Flicker.
13. Standards related to Custom Power.
14. Standards related to Distributed Generation.

II. SOLUTION TO POWER Q
PROBLEMS
Power quality problems [3] [5] [13] [16] [
basically start at four levels of the system that delivers
electric power, first one, includes Power plants and the
entire area transmission system. The second one is
Transmission lines, major substations where as third
one includes distribution substations, primary [17]
[18], and secondary power lines, and distribution
transformers and last and fourth one includes service
equipment and building wiring.

Figure 1: Present Power system components end to end
(generation to household user).

Their performance of the devices depends on the
power rating and the speed of response.
However, with the restructuring of the power
sector and with the shifting trend towards
distributed and dispersed generation, the line
conditioning systems or utility side solutions will
1999, Recommended
Practice for Powering and Grounding Sensitive
1995, Recommended
Practice for Monitoring Electric Power Quality.
1995, Guide for Service to
Equipment Sensitive to Momentary Voltage
1998 Recommended
Practice for Evaluating Electric Power System
with Electronic Process
Standards related to Voltage Sag and Reliability.
Standards related to Custom Power.
Standards related to Distributed Generation.
QUALITY
problems [3] [5] [13] [16] [19] can
basically start at four levels of the system that delivers
electric power, first one, includes Power plants and the
entire area transmission system. The second one is
Transmission lines, major substations where as third
ibution substations, primary [17]
], and secondary power lines, and distribution
transformers and last and fourth one includes service

Figure 1: Present Power system components end to end
to household user).
Their performance of the devices depends on the
power rating and the speed of response.
However, with the restructuring of the power
sector and with the shifting trend towards
distributed and dispersed generation, the line
conditioning systems or utility side solutions will
play a major role in improving
supply quality [21] [10]; some of the effective
and economic measures can be identified as
summarized in the below:

Proper designing of the Load equipment.
Application of passive, active and hybrid
harmonic filters.
Proper designing of the power supply
system
Application of voltage compensators.
Use of uninterruptible power supplies
(UPSs)
Reliability of standby power
Constant Voltage Transformers
Grid Adequacy
Lightening and Surge Arresters
Electronic tap changing transformer
Thyristor Based Static Switches
Distributed Generation (DG)
Reciprocating engines
Micro turbines
Fuel Cells
Energy Storage (restoring technologies)
Electrochemical batteries
Flywheels
Super capacitors
SMES (Superconducting Magnetic
Energy Storage)
Compressed air
The various power quality disturbances as shown
table 2 and suitable mitigating devices are
tabulated below:

Table 2 : Power Quality disturbances with mitigating
equipments.
Type
of
Equip
ments
Types of Disturbances
Tr
an
sie
nt
S
a
g
S
w
ell
Inte
rru
ptio
n
Dist
orti
on
(Ha
rmo
nics)
Surge
Suppr
essor
Ye
s
N
o
N
o
No No
Filter No N N No Yes
sue: pp- 143-149
145 | P a g e
play a major role in improving the inherent
]; some of the effective
and economic measures can be identified as
Proper designing of the Load equipment.
Application of passive, active and hybrid
Proper designing of the power supply
Application of voltage compensators.
Use of uninterruptible power supplies
Reliability of standby power
Constant Voltage Transformers

Lightening and Surge Arresters
Electronic tap changing transformer
Thyristor Based Static Switches

Energy Storage (restoring technologies)
Superconducting Magnetic
The various power quality disturbances as shown
table 2 and suitable mitigating devices are
Table 2 : Power Quality disturbances with mitigating
Types of Disturbances
Fli
ck
er
N
oi
se
Fre
que
ncy
De
via
tio
ns
No
N
o
No
No Y No


o o es
Isolati
on
Transf
ormer
Ye
s
N
o
N
o
No No No
Y
es
No
Voltag
e
Regul
ator
No
Y
e
s
Y
es
No No No
N
o
No
Power
Condit
ioner
Ye
s
Y
e
s
Y
es
No No No
N
o
No
UPS
Ye
s
Y
e
s
Y
es
Yes Yes
Ye
s
Y
es
Yes
SPS No
N
o
N
o
Yes No No
N
o
No

III. COMMON PROBLEMS
Define After studying the paper I got the most the
common problems in the power system is voltage sag
[16] and harmonics [17] [18] [19] [21].
A. Voltage sags
By IEEE, is a reduction in voltage for a short time
.The voltage reduction magnitude is between 10%and
90% of the normal root mean square voltage at
50Hz/60Hz. Voltage sags is the most common type of
power quality disturbance in the distribution system. It
can be caused by a fault in the electrical network or by
the starting of a large induction motor. The available
voltage sag mitigation devices described below.

Reactive power compensation principle
compensator.
Shunt Compensation.
Series Compensation
Traditional VAR generators.
Fixed or mechanically switched
capacitors.
Synchronous Condensers
Thyristorized VAR Compensators
Self Commuted VAR Compensators.
Commuted VAR Compensators
Semiconductor Devices used for
Self-Commutated VAR
Compensators.
Comparison between Thyristorized
and Self commutated Compensators.
New VAR Compensators Technology
Static Synchronous Compensator
(STATCOM).
Static Synchronous Series
Compensator (SSSC).
Dynamic Voltage Restorer (DVR)
Unified Power Flow Controller
(UPFC).
Interline Power Flow Controller
(IPFC)
Superconducting Magnetic Energy
Storage (SMES)
VAR Generation Using Coupling
Transformers.
i. Comparison between Thyristorized and
Self Commuted Compensators

As compared with thyristor - controlled capacitor [12]
and reactor banks, self-commutated VAR
compensators have the following advantages and
summarize the comparative merits of the main types
of VAR compensators [14] [24] [26]. The significant
advantages of self commutated compensators [28] as
tabulated in table 3 make them an interesting
alternative to improve compensation [29]
characteristics and also to increase the performance of
AC power systems.
Table 3: Comparison of Basic Types of
Compensators [25].

Synchro
nous
Conden
ser
Static Compensator

Self
commu
tated
Compe
nsator
TCR
(with
shunt
Capacito
rs if
Necessar
y)
TSC
(with
TCR if
Necessar
y)
Accura
cy of
Compe
nsation
Good
Very
Good
Good,
very
good
With
TCR
Excelle
nt
Control
Flexibil
ity
Good
Very
Good
Good,
very
good
With
TCR
Excelle
nt
Reactiv
e Power
Capabil
ity
Leading/
Lagging
Lagging/
Leading
Indirect
Leading/
Lagging
Indirect
Leading
/Laggin
g
Control
Continu
ous
Continuo
us
Discontin
uous
(cont.
Continu
ous


With
TCR)
Respon
se Time
Slow
Fast, 0.5
to 2
cycles
Fast, 0.5
to 2
cycles
Very
fast but
depends
on the
control
system
and
switchin
g
frequen
cy
Harmon
ics
Very
Good
Very
high
(larger
size
filters are
needed)
Good,
filters are
Necessar
y with
TCR
Good,
but
depends
on
switchin
g
pattern
Losses
Moderat
e
Good,
but
increase
in
lagging
mode
Good,
but
increase
in
leading
mode
Very
good,
but
Increase
with
Switchi
ng
frequen
cy
Phase
Balanci
ng
Ability
Limited Good Limited
Very
good
with 1-f
units,
limited
with 3-f
units
Cost High Moderate Moderate
Low to
moderat
e

B. Harmonics
It is a sinusoidal component of a periodic wave or
quantity having a frequency that is an integral
multiple of the fundamental power frequency.
Available solution for harmonizing:
Passive filters
Active filters
Active Series
Active Shunt
Hybrid of Active Series and Passive
Shunt
Hybrid of Active Shunt and Active
Series
The different types of filters [6] [9] [11] [12] [15] its
various applications and differentiate as per the
preferable filter are tabulated below in table 4:

Table 4: Active filter's for compensation in order of
preference. Active filters Configuration with higher number
of * is more preferred.
S. no
Compensati
on for
particular
Application
Active Filters
Acti
ve
Seri
es
Act
ive
Shu
nt
Hyb
rid
of
Acti
ve
Seri
es
and
Pass
ive
Shu
nt
Hyb
rid
of
Acti
ve
Shu
nt
and
Acti
ve
Seri
es
I.
Voltage
Harmonics
**
*

*
*
*
II.
Current
Harmonics

*
*
*
*
*
*
III.
Reactive
Power

*
*
*
*
*
*
IV.
Load
Balancing

*

V.
Voltage
Regulation
**
*
*
*
*
*
VI.
Neutral
Current

*
*
*

VII.
Voltage
balancing
**
*

*
*
*
VIII.
Voltage
Flicker
**
*
*
*

*
IX.
Voltage Sag
& Dips
**
*
*
*
*
*
X.
Current
harmonics
&
Reactive
power

*
*
*
*
*
*
www.ijrde.com


Figure.2. sample labels of electrical household
equipments. (Source BEE)

IV. CONCLUSION

The Power quality is important in all the area
well-defined field with rising interest being shown in
the solutions to problems, equipment, regulations and
statistical analysis of customers expected levels of
disturbance. Due to rising non-linear load
harmonic problems are increased. This paper deals the
important universal power quality standard. Power
quality measures can be applied both at the user end
and also at the unity level. The equipment to
the power quality issues. This paper wi
beginners to understand the power quality.
REFERENCES
[1] Bhim Singh, Kamal Al-Haddad, Ambrish
Chandra A Review of Active Filters for Power
Quality Improvement IEEE TRANSACTIONS
ON INDUSTRIAL ELECTRONICS, VOL. 46,
NO. 5, OCTOBER 1999.
[2] Anbal T. de Almeida Power Quality Problems
and New Solutions Universidade de Coimbra,
Universidade de Coimbra, Vigo, April 9
2003.
[3] S.Khalid & Bharti Dwivedi Power qualities
issuses , problems, standered & there effects in
industry with corrective means IJA
2011, ISSN: 2231-1963.
[4] C. E. Lin, T. C. Chen, and C. L. Huang, "A real
time calculation method for optimal reactive
power compensator," IEEE Trans. Power Syst.,
vol. 4, pp. 643-652, May 1989..
[5] W. M. Grady, M. J. Samotyj, and A. H. Noyola,
"Minimizing network harmonic voltage
distortion with an active power line conditioner,"

Figure.2. sample labels of electrical household
equipments. (Source BEE)

Power quality is important in all the areas. It is
defined field with rising interest being shown in
the solutions to problems, equipment, regulations and
statistical analysis of customers expected levels of
linear loads the
his paper deals the
important universal power quality standard. Power
quality measures can be applied both at the user end
equipment to improve
the power quality issues. This paper will help the
beginners to understand the power quality.
Haddad, Ambrish
Chandra A Review of Active Filters for Power
Quality Improvement IEEE TRANSACTIONS
ON INDUSTRIAL ELECTRONICS, VOL. 46,
e Almeida Power Quality Problems
and New Solutions Universidade de Coimbra,
Universidade de Coimbra, Vigo, April 9 11,
S.Khalid & Bharti Dwivedi Power qualities
issuses , problems, standered & there effects in
industry with corrective means IJAET May
C. E. Lin, T. C. Chen, and C. L. Huang, "A real
time calculation method for optimal reactive
IEEE Trans. Power Syst.,
W. M. Grady, M. J. Samotyj, and A. H. Noyola,
g network harmonic voltage
distortion with an active power line conditioner,"
IEEE Trans. Power Delivery, vol. 6, pp. 1690
1697, Oct. 1991.
[6] H. Akagi, Y. Tsukamoto, and A. Nabae,
"Analysis, design of an active power filter using
quad-series voltage source PWM converters,"
IEEE Trans. Ind. Applicat., vol. 26, pp. 93
Jan./Feb. 1990.
[7] I. Takahashi, "A flywheel energy storage system
having distorted power compensation," in
IPEC-Tokyo, 1983, pp. 1072-1083.
[8] H. Akagi, Y. Tsukamoto, and A. Nabae,
quad-series voltage source PWM converters,"
IEEE Trans. Ind. Applicat., vol. 26, pp. 93
Jan./Feb. 1990.
[9] F. Z. Peng, H. Akagi, and A. Nabae, "A study of
active power filters using quad
source PWM converters for harmonic
compensation," IEEE Trans. Power Electron.,
vol. 5, pp. 9-15, Jan. 1990.
[10] J. C. Wu and H. L. Jou, "A new UPS scheme
provides harmonic suppression, input power
factor correction," IEEE Trans. Ind. Electron.,
vol. 42, pp. 629-635, Dec. 1995.
[11] J. H. Choi, G. W. Park, and S. B. Dewan,
"Standby power supply with active power filter
ability using digital controller," in
APEC'95, 1995, pp. 783-789
[12] P. Enjeti, W. Shireen, and I. Pitel
design of an active power filter to cancel
harmonic currents in low voltage electric power
distribution systems," in Proc. IEEE IECON'92,
1992, pp. 368-373.
[13] K. K. Sen and A. E. Emanuel, "Unity power
factor single-phase power conditioning," in
IEEE PESC'87, 1987, pp. 516-524.
[14] A. Alexandrovitz, A. Yair, and E. Epstein,
"Analysis of a static VAR compensator with
optimal energy storage element,"
Ind. Electron., vol. IE-31, pp. 28-
[15] J. Uceda, F. Aldana, and P. Martinez
filters for static power converters,"
Elect. Eng., vol. 130, pt. B, no. 5, pp. 347
Sept. 1983.
[16] T. J. E. Miller, Reactive Power Control in
Electric Systems. Toronto, Canada: Wiley,
1982, pp. 32^8.
[17] J. S. Subjak Jr. and J. S. Mcquilkin, "Harmonics
causes, effects, measurements, analysis: An
update," IEEE Trans. Ind. Applicat.,
1034-1042, Nov./Dec. 1990.
[18] T. C. Shuter, H. T. Vollkommer, Jr., and J. L.
Kirkpatrick, "Survey of harmonic levels on the
American electric power distribution system,"
IEEE Trans. Power Delivery, vol. 4, pp. 2204
2213, Oct. 1989.
sue: pp- 143-149
148 | P a g e
vol. 6, pp. 1690-
H. Akagi, Y. Tsukamoto, and A. Nabae,
WM converters,"
vol. 26, pp. 93-98,
I. Takahashi, "A flywheel energy storage system
having distorted power compensation," in Proc.
1083.
H. Akagi, Y. Tsukamoto, and A. Nabae,
design of an active power filter using
series voltage source PWM converters,"
vol. 26, pp. 93-98,
F. Z. Peng, H. Akagi, and A. Nabae, "A study of
active power filters using quad-series voltage-
nverters for harmonic
IEEE Trans. Power Electron.,
J. C. Wu and H. L. Jou, "A new UPS scheme
provides harmonic suppression, input power
IEEE Trans. Ind. Electron.,

J. H. Choi, G. W. Park, and S. B. Dewan,
"Standby power supply with active power filter
ability using digital controller," in Proc. IEEE
P. Enjeti, W. Shireen, and I. Pitel, "Analysis,
design of an active power filter to cancel
harmonic currents in low voltage electric power
Proc. IEEE IECON'92,
K. K. Sen and A. E. Emanuel, "Unity power-
phase power conditioning," in Proc.
524.
A. Alexandrovitz, A. Yair, and E. Epstein,
"Analysis of a static VAR compensator with
optimal energy storage element," IEEE Trans.
-33, Feb. 1984.
J. Uceda, F. Aldana, and P. Martinez, "Active
filters for static power converters," Proc. Inst.
vol. 130, pt. B, no. 5, pp. 347-354,
Reactive Power Control in
Canada: Wiley,
Mcquilkin, "Harmonics-
causes, effects, measurements, analysis: An
IEEE Trans. Ind. Applicat., vol. 26, pp.
T. C. Shuter, H. T. Vollkommer, Jr., and J. L.
Kirkpatrick, "Survey of harmonic levels on the
ower distribution system,"
vol. 4, pp. 2204-


[19] IEEE Working Group on Power System
Harmonics, "Power system harmonics: An
overview," IEEE Trans. Power App. Syst, vol.
PAS-102, pp. 2455-2460, Aug. 1983.
[20] Orr J. A., and Eisenstein B.A., Summary of
Innovations in Electrical Engineering Curricula,
IEEE Trans. Education, Vol. 37, No. 2, May
1994, pp. 131-135.
[21] Carnovale, Daniel J., Price and Performance
Considerations for Harmonic Solutions. Power
Quality Conference 2003, Chicago, IL.
[22] Ching-Yin Lee, Wei-Jen Len, Yen-Nien Wang
and Jyh-Cheng Gu, Effects of Voltage
Harmonics on the Electrical and Mechanical
Performance of a Three-phase Induction Motor,
IEEE, 1998.
[23] M. H. J. Bollen, Understanding Power Quality
ProblemsVoltage Sags and Interruptions
Piscataway, New York: IEEE Press, 2000.
[24] M.H.Haque Compensation of distribution
system voltage sag by DVR and DSTATCOM
Power Tech Proceedings, 2001 IEEE Porto ,
Volume: 1 , 10-13 Sept. 2001 Pages:5 pp. vol.1
[25] F. Z. Peng, H. Akagi, and A. Nabae,
Compensation characteristics of the combined
system of shunt passive and series active filters,
IEEE Trans. Ind. Applicat., vol. 29, pp. 144151,
Jan./Feb. 1993.
[26] N.G. Hingorani and L. Gyugyi, Understanding
FACTS: Concepts and Technology of Flexible
AC Transmission Systems, 1st edition, The
Institute of Electrical and Electronics Enginee
rs,2000.
[27] John Stones and Alan Collinsion Introduction to
Power Quality power engineering journal 2001
pages: 58 -6
[28] Ray Arnold Solutions to Power Quality
Problems power engineering journal 2001
pages: 65-73.
[29] J. W. Dixon , Y. del Valle, M. Orchard, M.
Ortzar, L. Morn and C. Maffrand, A Full
Compensating System for General Loads, Based
on a Combination of Thyristor Binary
Compensator, and a PWM-IGBT Active
PowerFilter, IEEE Transactions on Industrial
Electronics, Vol. 50, N 5, October 2003, pp.
982-989.
[30] S. Torseng, Shunt-Connected Reactors and
Capacitors Controlled by Thyristors, IEE Proc.
Part C, vol. 128, n 6, pp. 366-373, Nov. 1981.



An Efficient Way of Improving Power Quality in Facility
Side Using Modified UPQC (Unified Power Quality
Controller)
M.Balaji
1
V.Dhamodharan
2
K.Veerakavi
3
Department of EEE,VelTechMultiTechDr.RangarajanDr.Sakunthala Engineering College.

ABSTRACT
The main aim of this paper is to improve, the
power quality in the Facility side i.e. in
Distribution side by the help of the Unified
Power Quality Conditioner. The UPQC is a
customer power device, which is used to mitigate
the power quality problems. By the help of the
UPQC, the various power quality concerns such
as voltage sag, swell, harmonics can be
eliminated. In our paper the modified, three
phase four wire distribution is used to control
the reactive power in the line. And also it uses,
the both voltage source inverter which are
connected in back to back manner with the help
of reduced d.c. link capacitor. A detailed
approach for the design of the VSI with
capacitor has been carried out with the help of
the MATLAB Simulink and graphs are shown
and the prototype model also developed.
keywords: customer power device, DC link
capacitor, harmonics, unified power quality
conditioner, voltage source inverter.
I.INTRODUCTION
With the advancement of power electronics and
digital control technology, the renewable energy
sources are increasingly being connected to the
distribution systems [1-4]. On the other hand, with
the proliferation of the power electronics devices
,nonlinear loads and unbalanced loads have
degraded the power quality (PQ) in the power
distribution network. Custom power devices have
been proposed for enhancing the quality and
reliability of electrical power. Unified Power
Quality Conditioner (UPQC) is a versatile custom
power device which consists of two inverters
connected back-to-back and deals with both load
current and supply voltage imperfections. UPQC
can simultaneously act as shunt and series active
power filters. The series part of the UPQC is known
as dynamic voltage restorer (DVR). It is used to
maintain balanced, distortion free nominal voltage
at the load. The shunt part of the UPQC is known
as distribution static compensator (DSTATCOM).
This paper proposes a new topology/structure that
can be realized in UPQC-based applications, in
which the series transformer neutral used for series
inverter, can be used to realize a 3P4W system
even if the power supplied by utility is three phase
three-wire (3P3W) [5-7]. This new functionality
using UPQC could be useful in future UPQC-based
distribution systems. The unbalanced load currents
are very common and yet an important problem in
3P4W distribution system. In case of the UPQC,
the dc-link voltage requirement for the shunt and
series active filters is not the same [8-10]. Thus, it
is a challenging task to have a common dc-link of
appropriate rating in order to achieve satisfactory
shunt and series compensation. The shunt active
filter requires higher dc-link voltage when
compared to the series active filter for proper
compensation [11-13]. In order to have a proper
compensation for both series and shunt active filter,
the researchers are left with no choice rather
common dc-link voltage based on shunt active filter
requirement. The simulation studies are carried out
using MATLAB Simulink, and detailed results are
presented in the paper .prototype of three-phase
UPQC is developed in the laboratory to verify the
proposed concept, and the detailed results are
presented in this paper .
II THREE PHASE FOUR WIRE
DISTRIBUTION SYSTEM
Generally, a 3P4W distribution system is realized
by providing a neutral conductor along with three
www.ijrde.com


power conductors from generation station or by
utilizing a three-phase Y transformer at
distribution level. Fig. 1 shows a 3P4W network in
which the neutral conductor is provided from the
generating station itself, whereas Fig. 2 shows a
Fig 1: 3P4W network with
conductor
III .PROPOSED THREE PHASE UPQC
In this section, the details of the proposed three
phase Unified Power Quality Conditioner
were described. The proposed model consists of
two inverters, which are connected back
manner along with the d.c. link capacitor. It
consists of both the series active filter and the shunt
active filter [13-17]. The Four Wire distribution
system involves four leg to control the VSI in the
circuit, but in this model the fourth leg is avoided,
it can be achieved by the usage of the splitlink
capacitor [18-20]. But the usage of the capacitor
will lead to increase the rating of the capacitor,
since both the series active filter as well as the
shunt active filter needs different rating of the
capacitor. Because the active series filter require
the largest rating of the capacitor while the shunt
active filter requires the low value capacitance. In
our proposed model, the both active and series
filter are combined by the help of the single
capacitor and also the rating of the capacitor also
reduced, the control of the each leg independent
also achieved. By the controlling the leg
independently, the switching frequency get reduce

IV DESIGN OF C
F
FOR PROPOSED
MODEL
The design of the C
f
depends on the value to which
the dc-link voltage is reduced. In general the
with only non-linear components of the current is
Enriching Power and Energy Development (MEPED) 2014
power conductors from generation station or by
Y transformer at
distribution level. Fig. 1 shows a 3P4W network in
which the neutral conductor is provided from the
generating station itself, whereas Fig. 2 shows a
3P4W distribution network considering a
transformer.

with neutral
Fig 2: 3P4W distribution network considering a
transformer
III .PROPOSED THREE PHASE UPQC
In this section, the details of the proposed three
phase Unified Power Quality Conditioner (UPQC)
were described. The proposed model consists of a
two inverters, which are connected back-back
manner along with the d.c. link capacitor. It
consists of both the series active filter and the shunt
. The Four Wire distribution
tem involves four leg to control the VSI in the
circuit, but in this model the fourth leg is avoided,
it can be achieved by the usage of the splitlink
. But the usage of the capacitor
will lead to increase the rating of the capacitor,
e both the series active filter as well as the
shunt active filter needs different rating of the
capacitor. Because the active series filter require
the largest rating of the capacitor while the shunt
active filter requires the low value capacitance. In
r proposed model, the both active and series
filter are combined by the help of the single
capacitor and also the rating of the capacitor also
reduced, the control of the each leg independent
By the controlling the leg
tching frequency get reduce
and the control of the VSI also achieved
effectively. The proposed system works for both
the power quality problems such as voltage sag and
swell. In this topology, the system neutral was
connected to the negative terminal of th
along with the capacitor C
f
in series with the
interfacing inductance of the active shunt filter
passive capacitor C
f
has the capability
apart of there active power required by
and the active filter will compensate
reactive power and the harmonics present
load. The addition of capacitor in series
interfacing inductor of the shunt act
significantly reduce the dc-link voltage requirement
and consequently reduces the average
frequency of the switches.
Fig.3 Modified UPQC
FOR PROPOSED
depends on the value to which
link voltage is reduced. In general the load
linear components of the current is
very rare, and most of the electrical loads are
combination of the linear inductive and non
loads. The design of the value of C
f
the maximum load current, i.e., with
load impedance to ensure that the
will perform satisfactorily at all other
151 | P a g e
3P4W distribution network considering a Y

3P4W distribution network considering a Y
and the control of the VSI also achieved
effectively. The proposed system works for both
the power quality problems such as voltage sag and
swell. In this topology, the system neutral was
connected to the negative terminal of the dc bus
in series with the
ance of the active shunt filter. The
capability to supply
required by the load,
compensate the balance
harmonics present in the
in series with the
active filter will
oltage requirement
erage switching
UPQC
very rare, and most of the electrical loads are
combination of the linear inductive and non-linear
f
is carried out at
with the minimum
that the designed C
f
all other loading


conditions. If S
max
is the maximum kVA rating of
a system and V
base
is the base voltage of the
system, then the minimum impedance in the system
is given as Zmin = V 2Base / Smax== |Rl+ jXl|
(say). In order to achieve the unity power factor,
the shunt active filter current needs to supply the
required reactive component of the load current,
i.e., the fundamental imaginary part of the filter
current should be equal to the imaginary part of the
load current. The filter current and load current in a
particular phase are given
I
filter
= Vinv1 Vl1 / Rf+ j(Xlf Xcf)

I
load
=Vl1/ Rl+ jXl

where, Xlf= 2fLf, Xl = 2fLl, Xcf= 1/2fCf, and f
is the supply frequency of fundamental voltage.
Neglecting the interfacing resistance and equating
the imaginary parts of the above equations. to rate
the dc-link voltage at lower value than
conventional design. The designer has a choice to
choose the value of dc-link voltage to be reduced,
such that the LC filter in the active filter leg of
each phase offers minimum impedance to the
fundamental frequency and higher impedance for
switching frequency components. In the modified
topology along with the series capacitor in the
shunt active filter, the system neutral is connected
to the negative terminal of the dc bus capacitor.
This will introduce a positive dc voltage
component in the inverter output voltage. This is
because, when the top switch is ON, +Vd bus
appears at the inverter output, and 0 V appears
when the bottom switch is ON. Thus, the
inverter output voltage will have dc voltage
component along with the ac voltage. The dc
voltage is blocked by the series capacitor, and thus
the voltage across the series capacitor will be
having two components, one is the ac component,
which will be in phase opposition to the PCC
voltage, and the other is the dc component.
Whereas, in case of the conventional topology, the
inverter output voltage varies between +Vdc when
top switch is ON and Vdc when the bottom
switch ON. Similarly, when a four-leg topology
is used for shunt active filter with a single dc
capacitor, the inverter output voltage varies
between +Vd bus and Vd bus. Thus the value of
the capacitor had been chosen for the proposed
model.
V. GENERATION OF REFERENCE
COMPENSATOR CURRENT

In this work, the load currents are unbalanced and
distorted, these currents flow through the feeder
impedance and make the voltage at terminal
unbalanced and distorted. The series active filter
makes the voltages at PCC balanced and sinusoidal.
However, the voltages still contain switching
frequency components and they contain some
distortions. If these terminal voltages are used for
generating the shunt filter current references, the
shunt algorithm results in erroneous compensation
To remove this limitation of the algorithm,
fundamental positive sequence v+ la1(t), v+lb1(t),
and v+lc1(t) of the PCC voltages are extracted and
are used in control algorithm for shunt active filter.
The expressions for reference compensator currents
are given in. In this equation, Pl avg is the average
load power, P loss denotes the switching losses and
ohmic losses in actual compensator, and it is
generated using a capacitor voltage PI controller.
The term Pl avg is obtained using a moving
average filter of one cycle window of time T in
seconds. The term is the desired phase angle
between the source voltage and current. Once the
reference quantities and the actual quantities are
obtained from the measurements, the switching
commands for the VSI switches are generated
using hysteresis band current control method.
Hysteresis current controller scheme is based on a
feedback loop, generally with two-level
comparators. The switching commands are issued
whenever the error
limit exceeds a specified
tolerance bandh. Unlike the Predictive
controller,
the hysteresis controller has the
advantage of peak current limiting capacity apart
from other merits such as extremely good dynamic
performance, simplicity in implementation and
independence from load parameter variations. The
disadvantage with this hysteresis method is that the
converter switching frequency is highly dependent
on the ac voltage and varies with it. The switching
control for shunt active filter is given as follows.
If ifa ifa+ h1, then bottom switch is turned ON
whereastop switch is turned OFF (Sa= 0, S_a= 1).
If ifa ifa h1, then top switch is turned ON
whereas bottomswitch is turned OFF (Sa = 1, S_a=
0).
Similarly the switching commands for series active
filter are given as follows. If vdvra vdvra+ h2,
then bottom switch is turned ON whereas top
switch is turned OFF (Saa= 0, S_aa= 1). If vdvra


vdvra h2, then top switch is turned ON
whereasbottom switch is turned OFF (Saa= 1, S_
aa= 0). The control circuitry for both the topologies
is same andis shown.. Only six switching
commands are to begenerated. These six signals
along with the complementarysignals will control
all the 12 switches of the two inverters. The values
of the reference voltage and the current are
estimated and by the help of the controller, the
values are comparing and the values are used to
trigger the gate pulse,

Fig 4: Control Circuit

VI SIMULATION RESULT

Fig 5: Three phase line to line voltage

Fig 6: Three phase line to line voltage

Fig 7: Triggering Pulse For Switch
Sa,Sb,Sc,Sa1,Sb1,Sc1

Fig 8: DC Link Voltage

Fig 9: Three Phase Voltage
www.ijrde.com


Fig 10: Three Phase Output Current

Fig 11: Power Quality output

Fig 12: THD of output current
Table 1: Average switching frequenc
Inverter Switches (Khz)
Enriching Power and Energy Development (MEPED) 2014

: Three Phase Output Current

output

of output current
ency of the

VII CONCLUSION
By the help of the Unified Power Quality
Conditioner, the voltage sag, swell and other power
quality problem can be removed. The design of the
modified three phase four wire topology had given
and the reduction of the dc link capacitor are
discussed. The reduction of average switching loss
can be achieved by the help of the control of each
leg independently. The control circuit for the
UPQC and the generation of the reference current
are also explained. The output of the UPQC for the
various conditions had been explained by the help
of the simulation result. The average switching loss
details are explained in the tabulated manner
the study, it is found that the modified topology has
less average switching frequency, less THDs in the
source currents, and load voltages with reduced dc
link voltage as compared to the conventional
UPQC topology.

REFERENCE

[1]. R.Gupta, A.Ghosh, and A.Joshi, Characteristic
analysis for multi sampled digital implementation of
fixed-switching-frequency closed-
of voltage-source inverter, IEEE
.Electron., vol.56,no.7,pp.23822392,Jul.2009.

[2]. B.Singh and J. Solanki, A comparison of control
algorithms for STATCOM,
TransInd.Electron., vol.56,no.7,pp.2738
Jul.2009.

[3]. S.Rahmani,N.Mendalek,andK.Al
Haddad,Experimentaldesignofanonlinearcontrolte
chniqueforthree-
phaseshuntactivepowerfilter,IEEE
on.,vol.57,no.10,pp.33643375,Oct.2010.

[4]. V.Corasaniti,M.Barbieri,P.Arnera,andM.
ridactivefilterforreactiveandharmonicscompensatio
ninadistributionnetwork,IEEETr
vol.56,no.3,pp.670677,Mar.2009.

[5]. M.Milane Montero, E. Romero-
Barrero-Gonzalez, Hybrid multi co
conditioner topology for high-power applications,
154 | P a g e
By the help of the Unified Power Quality
Conditioner, the voltage sag, swell and other power
quality problem can be removed. The design of the
modified three phase four wire topology had given
and the reduction of the dc link capacitor are
eduction of average switching loss
can be achieved by the help of the control of each
leg independently. The control circuit for the
UPQC and the generation of the reference current
are also explained. The output of the UPQC for the
been explained by the help
of the simulation result. The average switching loss
details are explained in the tabulated manner. From
the study, it is found that the modified topology has
less average switching frequency, less THDs in the
and load voltages with reduced dc-
link voltage as compared to the conventional
R.Gupta, A.Ghosh, and A.Joshi, Characteristic
analysis for multi sampled digital implementation of
- loop modulation
IEEE Trans. Ind
2392,Jul.2009.
omparison of control
TCOM, IEEE
ol.56,no.7,pp.27382745,
,N.Mendalek,andK.Al-
Haddad,Experimentaldesignofanonlinearcontrolte
IEEETrans.Ind.Electr
3375,Oct.2010.
.Arnera,andM.Valla,Hyb
eandharmonicscompensatio
rans.Ind.Electron.,
.2009.
-Cadaval, and F.
Gonzalez, Hybrid multi converter
wer applications,


2292, Jun.2011.

[6]. J.Nielsen, M.Newman, H.Nielsen, and F.Blaabjerg,
Control and testing of a dynamic voltage restorer
(DVR) at medium voltage
level,IEEETrans.PowerElectron.,vol.19,no.3,pp.80
6813,May2004.

[7]. Y.W.Li,P.C.Loh, F.Blaabjerg, and D.Vilathgamuwa,
Investigation and improvement of transient
response of DVR at medium voltage level,
IEEETrans.Ind.Appl.,vol.43,no.5,pp.1309
1319,Sep./Oct.2007.

[8]. Y.W.Li,D.MahindaVilathgamuwa,
F.Blaabjerg,andP.C.Loh, A robust control scheme
for medium-voltage-level DVR implementation,
IEEETrans.Ind.Electron.,vol.54,no.4,pp.2249
2261,Aug.2007.

[9]. J.BarrosandJ.Silva,Multileveloptimalpredictivedyna
micvoltagerestorer,IEEETrans.Ind.Electron.,vol.57,
no.8,pp.27472760, Aug.2010.

[10]. D.Vilathgamuwa, H.Wijekoon,and S.Choi, A
novel technique to compensate voltage sags in
multi line distribution system The inter line
dynamic voltage restorer, IEEE Trans. Ind
.Electron., vol.53,no.5, pp.16031611,Oct.2006.

[11]. M.Kesler and E.Ozdemir, Synchronous-reference-
frame-based control method for UPQC under
unbalanced and distorted load
conditions,IEEETrans.Ind.Electron.,vol.58,no.9,p
p.39673975,Sep.2011.

[12]. K.H.Kwan, Y.C.Chu, and P.L.So, Model-based
H
infty
control of a unified power quality
conditioner, IEEETrans. Ind. Electron.,vol.56,
no.7,pp.24932504,Jul.2009.

[13]. V.Khadkikar and A.Chandra, A novel structure for
three-phase four-wire distribution system utilizing
unified power quality conditioner (UPQC),
IEEETrans.Ind.Appl.,vol.45,no.5,pp.1897
1902,Sep./Oct.2009.

[14]. V.Khadkikar and A.Chandra, A new control
philosophy for a unified power quality conditioner
(UPQC) to coordinate load-reactive power demand
between shunt and series inverters, IEEE Trans
.Power Del., vol.23,no.4,pp.25222534,Oct.2008.

[15]. H.Akagi and R.Kondo, A transformerless hybrid
active filter using a three-level pulse width
modulation (PWM) converter for a medium-
voltage motor drive, IEEE Trans. Power Electron.,
vol. 25, no. 6, pp.13651374,Jun.2010.
[16]. H.Jou,K.Wu,J.Wu,C.Li,and M.Huang, Novel
power converter topology for three phase four-wire
hybrid power filter, IET Power Electron.,
vol.1,no.1,pp.164173,Mar.2008.

[17]. T.Zhili,L.Xun, C.Jian, K.Yong, and D.Shanxu, A
direct control strategy for UPQC in three-phase
four-wire system, inProc.CES/IEEE
IPEMC,Aug.2006,vol.2,pp.15.

[18]. M.Brenna,R. Faranda, and E. Tironi, A new
proposal for power quality and custom power
improvement: Open UPQC,IEEETrans.PowerDel.,
vol.24,no.4,pp.21072116,Oct.2009.

[19]. V.George and M.K.Mishra, DSTATCOM
topologies for three phase high power
applications,Int.J.PowerElectron.,vol.2,no.2,pp.10
7124,Feb.2010.

[20]. Y.Pal,A.Swarup, and B.Singh, A comparative
analysis of three-phase four-wire UPQC
topologies, in Proc .Joint Int.Conf. PEDES Power
India,Dec.2010,pp.16.





Power Quality Management in Commercial Buildings
Harish Kumar.S
1
,Vengatesh.V
2
,Bhuvaneswaran.E
3
123
Electrical and Electronics Engineering, SVIST,Tiruvallur,Tamilnadu,India

ABSTRACT
This paper presents a study of distributed
passive harmonic filter design to minimize
harmonic distortions caused by nonlinear loads
in commercial buildings. Unfortunately, no
single universally suitable representation has
been accepted as a prototype for this power
component. The main objectives in this study
are: 1) to improve the power factor, 2) to reduce
current and voltage distortions to standard
limits, and 3) to reduce electrical losses. In this
sense, several measurements that were carried
out in our college campus, have characterized as
the main harmonic distribution current sources
the third, fifth, and seventh harmonic
components. According to the results obtained
and considering the impacts caused in the
distribution grid, a distributed filtering strategy
is proposed using passive detuned filters of low
costs to be installed in the customers.
Key wordsHarmonics, measurement,
passive detuned filters, power distribution
systems, power quality.
I. INTRODUCTION
Almost all modern commercial buildings take their
supplies at 415 volts from the secondary of the
delta/ star connected 11kV/415V transformers. In
recent years a large number of distorting, non-
linear load such as computer equipments have been
extensively used in commercial buildings. The
result of using such highly non-linear load is that
the current waveform is distorted, causing
excessive harmonic voltages to be generated.
Although modern non-linear loads such as
computer equipments are small in size (power
consumption), but they are large in number. For
example a 3 floor building could have as many as
300 PCs [1-5]. Also the close proximity of many of
these commercial buildings (Hotels, offices,
departmental stores, shopping centres, and
hospitals) will definitely contribute to the distortion
of the electric power quality of feeder which
supplies these buildings. Harmonic currents
injected by some of these loads are usually too
small to cause a significant distortion in
distribution networks. However, when operating in
large numbers, the cumulative effect has the
capability of causing serious harmonic distortion
levels [5-10]. These do not usually upset the end-
user electronic equipment as much as they overload
neutral conductors and transformers and, in
general, cause additional losses and reduced power
factor [1014].
The low-voltage customers of a distribution grid
may be considered as harmonic current sources that
typically produce the third, fifth, and seventh
harmonic components with significant distortion
level, and the ninth and 11th current har-monics
with less significance [15]. In order to better
evaluate the impacts that those distributed
harmonic sources have in the power quality, a set
of measurements was carried out in our college
campus. Those measurements were carried out
directly at college energy installation [16]. Based
on the obtained results, prototypes of low-cost-
detuned passive filters were designed,
manufactured, and installed in our college
facilities. The projected filters are series RLC
filters that are detuned in the fifth, and seventh
harmonic components. In this paper, results
comparing the impacts over the distribution grid
considering the adoption of this proposed strategy
of harmonic filtering at the low voltage customers
are presented.
The main objectives in this study are:
1) to improve the power factor of the customer's
electrical installation;


2) to reduce current and voltage distortions to
standard limits;
3) to reduce active and reactive losses.

Fig 1:Proposed system with the 5kVAr Capacitor and
5kVAr De-tuned Reactor filter for
the Electrical lab section in our college campus.

Fig 2: Represent the control circuit diagram for the
control block that is to Start and Stop
the Capacitor from remote location. Section II presents
some considerations about the f results used to determine
the filter parameters. The results obtained with the
application of the filter at domestic customers are in
Section IV. Section V presents the conclusions of the
paper.
II. FILTER DESIGN
This work proposes the use of a series passive R of
189Hz ie.,p=7%, which corresponds, respectively,
to the third, fifth, and seventh harmonic
components. The project consists in the
determination of the R, L, (resistance, inductance,
and capacitance, respectively) values for each
branch of the filter that is to be connected in
parallel with the nonlinear customer's load in order
to obtain the minimal impedance at the desired
detuning frequencies. According to the type of
customer, one-phase, two three, six, or nine
branches, and may be installed at the customer's
energy entrance, which is connected at the low-
voltage side of the distribution transformer, a three-
phase customer. At the tuning frequency (w0), the
inductive and capacitive are equal, resulting in the
relationship given in (1) [3]

The filter's impedance is given as
Zf = R+j(wL-1/Wc)
where Zf is the filter's impedance at frequency W0,
expressed ohms ().
Considering the resistance equal to 0.5 in (2) and
the capacitance C varying according to the interval
of 2F<=C<= 50F due to commercial reasons, one
can obtain the values that represent the locus of
minimum Zf for the frequencies of 50, 180, 300,
and 420 Hz, with the inductance varying according
to the interval of 2mH <=L<=200mH. A good
solution, which simultaneously minimizes the filter
impedance some specific harmonic frequency and
maximizes the filter impedance to 50 Hz in order to
limit the losses caused by current at fundamental
frequency, may be obtained. At the same
frequency, the capacitance value is inversely
proportional to the inductance value, and one may
choose a combination that has a capacitor value
that may be easily available in the market. It is also
recommended to give preference to pairs of


inductor and capacitor with smaller dimensions and
low weight. However, when the loads are not in
operation, the passive filter becomes power factor
correction capacitor if it is not completely isolated
from the load. The passive filter then injects
excessive reactive power (KVAR) causing voltage
regulation problem to the network at light or no
load. This problem can be overcome by using the
Active or a Hybrid Filters. But the cost of those
filters are so high as compared to the passive
filters. Because in this case we are handling the
residential and commercial loads ie., low level
customers.So cost much be taken into the
consideration. So as an Engineer we must required
to give a exact solution with good result and a
suitable price inorder to keep the Quality of Power
to a Standard level which inturn will save a huge
amount to Kilowatts and reduce the losses greatly.
TABLE I
EXAMPLE OF CURRENT MEASUREMENT AT
ATYPICAL SINGLE-PHASE CUSTOMER
Harmonics Order RMS Current
Fundamental (I1) 490A
3rd (I3) 108A
5th (I5) 092A
7th (I7) 050A

TABLE II
VALUES FOR L AND C OF THE PASSIVE
SINGLE-PHASE SHUNT FILTER
Frequency (Hz) L (mH) C (F)
180 78 10
300 47 6
420 24 6
For this we brought a solution that we can able to
operate the series detuned capacitor bank from the
remote location of the user.The fig.2 shows the
control circuit diagram so the start/stop from the

remote location to the capacitor bank based upon
the load requirement can be applied.
III. COMPUTER SIMULATION
The proposed strategy is to design a passive tuned
filter at the third, fifth, and seventh harmonic
components and to apply that filter to all of the
customers of the energy distribution grid that
present the same energy consumption
characteristic, mainly current capacities and
voltage levels. To the filter design, typical single-
phase and three-phase customers fed by a
distribution transformer of 45 kVA, 13.8
kV/220/127 V, with a leakage reactance of 3.5%,
were chosen. The values of the fundamental current
(I1) and of the harmonic currents I3, I5, and I7, as
shown in Table I, are typical values that were
obtained through measurements carried out in
many single-phase customers. These current values
are used to design and manufacture single-phase
filters to be installed in single-phase customers
with similar harmonic characteristics. For testing
capacitance values varying from 2 to 10 F the
corresponding inductance values were obtained
aiming the maximization of filter's impedance at
fundamental frequency in order to assure that a
minimum portion of the current at that frequency
will pass the filter and, at the same time,
minimizing the harmonic impedance under interest,
considering the limitations of the R, L, and C
components: resistance can neither be very large
because the filter's impedance cannot be higher
than the system's impedance nor very small,
because it would not represent a real value. The
capacitance and inductance values are constrained
by size and cost limitations, which would make the
installation of the filters at the consumers'
Fig.3:Third harmonic current (180 Hz) that is filtered [I(I3) in black] &
third harmonic current that is generated by the load [I(L3) in gray].


residences infeasible.

After several simulations using the software
PSPICE, the best to performance obtained has
provided the results shown in Table II for the
branches of third, fifth, and seventh harmonics that
form rent the single-phase filter adopted. In all
cases, the values of the branches' resistances, due to
project reasons, were specified as 0.5. This
resistance corresponds to the project value to be
attained when manufacturing the respective
inductors. The results of the PSPICE simulations
for the values of L, C, and R chosen for the
branches of the filter are shown in Figs. 3-6,
respectively, for the branches of the third, fifth, and
seventh harmonics. In those graphs, it can be
observed that the harmonic currents (in gray) are
being filtered in some percentage, and that the
currents in the fundamental frequency that cross the
filter's branches are less than 0.8 A. It should be
pointed out that in the PSPICE simulations that the
equivalent impedance of the system was considered
as being the impedance of the transformer, and not
the Thevenin's equivalent impedance at the point of
the consumer's connection in the grid. Despite that
inaccuracy, the results obtained with the filter have
shown a filtering rate of 41.76, 34.78, and 54.00%
for the third, fifth, and seventh harmonic currents,
respectively, when compared with the case without
the filter. It is worth mentioning that the grounding
resistance used in these simulations is not the
theoretical value of 0.5 assumed earlier, but the
real value of 23 that is very common to be found
among the low-voltage customers of the
distribution grid. This is the main reason why the
theoretical results presented in Figs. 3-6 do not
filter completely the harmonic currents as expected
of a good filter design.
IV. APPLICATION OF THE FILTERS AT
DOMESTIC CUSTOMERS
After the installation of the designed filter in our
colleges of the low-voltage distribution grid, its
operation was monitored continuously in order to
evaluate its performance according to the natural
variation of the loads. It should be noticed that the
filter was projected for a certain load condition and
that the configuration of the distribution grid and
its parameters do not necessarily correspond to the
projected conditions. The measurements performed
in threephase of the EB Supply in our college are
shown next. It was observed, in general, that the
filter presented a load-depending behavior. Its
performance was better in some periods when the
load condition was next to that considered in the
filter design.
A. Three Phase Measurements of Our College
Main Building:
The power quality has been reviewed and different
terminologies of power quality were introduced.
International professional bodies have established
standards by which PQ could be defined as
mentioned earlier on. One of such bodies is the
European Standard EN-50160 [15]. What may be
considered as quality power to one customer may
not meet the standard required by another end user.
Therefore Benchmarking indices serving as metrics
came to be developed. Benchmark levels for
Fig.6:Fifth harmonic
current of the customer
with 23- grounding
resistance
Fig. 4: Fifth harmonic
current (300 Hz) that is


electricity suppliers, consumers and even
manufacturers have been introduced. Some of these
International bodies include Electric Power
Research Institute (EPRI), Institute of Electrical
Electronics Engineering (IEEE), International
Electrotechnical Commission (IEC), American
National Standards Institute (ANSI) and National
Electrical Manufacturers Association (NEMA).
Quality of service is determined by first selecting
the metrics to be used, deciding on what PQ data to
be collected and then determining the pattern of the
data with predetermined target level set by both the
power supplier and the consumer. The supplier, the
consumer and the regulatory agencies need to reach
a compromise. Another level considered to be very
important is the Performance Level introduced by a
specific consumer, which is different but always
higher or equal to the Benchmark values.
In this a commercial buildings case study was
introduced and investigated. The case study
consists of real data which was collected over a
period of time in our academic Institution. The
building consists of equipments associated with
probably with more computers, TVs, florescent
lighting with magnetic and electronic ballasts,
motors, as well as the usual electric loads and
various electronic devices for the laboratory. The
data was then analysed for each of the phases, the
results

critically analysed and some recommendations
proposed for improvement of the quality. The
below graph will tell about the level of Current and
Voltage Harmonics in our College Campus. Also
the total KW and ITHD,VTHD,5th,7th level
Current Harmonics readings are being recorded
during the time of measurement. The
Measurement is carried out by two ways one is
Without Filter and another is With Filter. From this
we able to see the effect of Filter which is being
employed to reduce the level of current and voltage
Harmonics to a level.

Fig.7:5th level Current Harmonics Without Filte&
Fig.8:Total Current Harmonic Distortion(ITHD)
WithFilter

Fig.9:5th level Current Harmonics Without Filter


Fig.10:5th level Current Harmonics With Filter

Fig.11:7th level Current Harmonics Without Filter

Fig.12:7th level Current Harmonics With Filter

Fig.14:Total Voltage Harmonic Distortion(VTHD)
With Filter
Without Filter
Figs. 7-12 show the ITHD%, 5th and 7th level
Current Harmonics performance when the
harmonic filter is installed in phases A, B, and C,
respectively, of a three-phase customer. The
measurements were performed in small periods of
time in order to have as small a deviation of the
system operation state as possible for the two
measured conditions: with the filter and without the
filter.A reduction ITHD% was observed in some
periods, depending on the load variation. After the
measurement it was shown that the voltage


harmonic distortion at the input was not high. The
maximum total harmonic distortion did not reach
5% as shown in Fig.13 during the data collection
period. The maximum was 4.3% on line 3. The
EN50160 gives the limit of 8% for THDV for LV
system, in monitoring for a period and Fig.13shows
that the highest THDV was 4.3% on phase 3.
Therefore the limit is not violated The individual
voltage harmonics showed that the 5th and 7th
harmonics are present as. The highest distortion
was the 5th harmonic which was 3%, and the 7th
harmonic was about 2.5%. The International
standard EN50160 gives the limits of 5th harmonic
distortion to be 6% and the 7th to be 5%. These
limits were not violated.

V. CONCLUSION:
The harmonic impacts over the distribution grid
produced by currents injected by low-voltage
customers ie from the college campus can be
reduced by the use of passive filters detuned to the
frequencies of 189, 300, and 420 Hz,ie,. p=7%,14%
which correspond to the third, fifth, and seventh
harmonics, respectively. In this sense, this paper
presented some preliminary results involving the
installation of de-tuned passive filters in some
customers of the low-voltage distribution grid.
Although it has not been observed, a regular
reduction in the harmonic current distortion for all
load conditions, as was expected with the passive
filter, the use of the filter has contributed, in the
average, to better performance of the domestic
electrical plant concerning:
Power factor improvement;
THDV% reduction;
Reduction of reactive power demand from the
grid.
If this distributed filtering strategy is to be applied
to a considerable number of customers in the low-
voltage distribution grid, it is expected that the
system will exhibit, in general, better performance
with respect to power-quality indicators
Without Filter Fig.14:Total Voltage Harmonic
Distortion(VTHD) With Filter concerning voltage
and current distortions. Also, due mainly to the
capacitance presented by the passive RLC
proposed filter, there is a local reactive power
compensation for each individual customer that
may sum up to a large amount when considering
the set of customers in the distribution grid. This
strategy is of low-cost implementation and may
alleviate the reactive power required from the grid,
but special attention must be given to the problem
of harmonic resonance that may arise when using
the distributed filtering strategy.
Future Research:
There are many points which can be further
investigated in this field. Some of these points are
summarised below:
- The present approach establishing a relation
between voltage and power consumption both for
active and reactive power is not conclusive. It was
proved that power consumption figures would be
significantly less at lower voltage level, but more
investigations into residential, commercial and
industrial loads are needed to establish this. When
commercial consumers voltage level increases
significantly it produces high unwanted power
consumption, because of heavy presence of passive
and resistive loads.
This needs further research. - Mass application of
Compact fluorescent lamps with electronic gear in
modern and commercial establishments is
becoming as bad in generating harmonic distortions
as computers and other SMPS. These CFLs cause
network voltage distortion, occurring due to their
distorted currents, with high level of harmonic
components. Further research analyses dealing with
the influence of CFLs on power systems are
necessary, especially on massive residential
distribution network intermingled with modern
commercial buildings. The production of harmonic
currents causing corresponding system harmonic
voltage, mostly the triple-n harmonics could mean
major power quality problems for the MV/LV


subtransmission transformers of the delta-wye
types.

REFERENCES:
[1] M. E. de Lima Tostes, U. H. Bezerra, J. N.
Garcez, A. A. A. Tupiassu, and C. A. Sena,
"Development of experimental models for
harmonic representation of low voltage customers,"
in Proc. 2001 IEEEPorto Power Tech, Porto,
Portugal.
[2] Chapman, D.; Power Quality Application Guide
- The Cost of Poor Power Quality; Copper
Development Association.
[3] Bollen, M.H.J. Understanding Power Quality
Problems IEEE Press Series on Power
Engineering.
[4] IEEE 519:1992, IEEE Recommended Practices
and Requirements for Harmonics Control in
Electrical Power Systems.
[5] R. Lamerica, A. Prudenzi, E. Tiroli, and D.
Zaninelli, "A model of large load areas for
harmonic studies in distribution networks," IEEE
Trans. Power Del., vol. 12, no. 1, pp. 418- 425,.
[6] IEEE 1159; IEEE Recommended Practice for
Monitoring Electric Power Quality.
[7] IEC 61000-4-3; Testing and measurement
techniques Power quality measurement methods,
pp. 81, 7, 19.
[8] Ewalk, F.; Masouum, M. A. S.; Power Quality
in Power Systems and Electrical Machines.
Elsevier Academic Press 2008.
[9] Jain Sandesh, Thakur Shivendra Singh and
Phulambrikar S.P, Improve Power Factor and
Reduce the Harmonics Distortion of the System,
Research Journal of Engineering Sciences ISSN
2278 9472 Vol. 1(5), 31-36, November (2012).
[10] Hussein A. Kazem, Harmonic Mitigation
Techniques Applied to Power Distribution
Networks, Hindawi Publishing Corporation
Advances in Power Electronics Volume 2013,
Article ID 591680.
[11] A.Mansoor,W. M. Grady, A. H. Chowdhury,
andM. J. Samotyi, An investigation of harmonics
attenuation and diversity among distributed single-
phase power electronic loads, IEEE Transactions
on Power Delivery, vol. 10, no. 1, pp. 467473,
1995.
[12] A. Mansoor, W. M. Grady, R. S. Thallam, M.
T. Doyle, S. D.Krein, andM. J. Samotyj, Effect of
supply voltage harmonics on the input current of
single-phase diode bridge rectifier loads,IEEE
Transactions on Power Delivery, vol. 10, no. 3, pp.
14161422, 1995.
[13] G. Carpinelli, F. Iacovone, P. Varilone, and P.
Verde, Single phase voltage source converters:
analytical modelling for harmonic analysis in
continuous and discontinuous current conditions,
International Journal of Power and Energy
Systems,vol. 23, no. 1, pp. 3748, 2003.
[14] E. F. El-Saadany and M. M. A. Salama,
Reduction of the net harmonic current produced
by single-phase non-linear loads due to attenuation
and diversity effects, International Journal of
Electrical Power and Energy Systems, vol. 20, no.
4, pp. 259268, 1998.
[15] T. Key and J. S. Lai, Analysis of harmonic
mitigation methods for building wiring systems,
IEEE Transactions on Power Systems, vol. 13, no.
3, pp. 890897, 1998.
[16] EN 50160:2000, Voltage characteristics of
electricity supplied by public distribution systems.
ACKNOWLEDGEMENT
We deeply indebted to our Management for
supporting and facilities to make this as a
successful project.
We thank PROJCET GUIDE Mr.Ethirajulu for
having given technical information and suggestions
to carry out this project.
We thank Mr.Thagarajan,Project Co-Ordinator for
having given us extreme moral support and gave
permissions to use the literature and data collection
during working hours.
We thank Dr. Duraivel, principal, SVIST for his
consistent encouragement to complete the Protect .


We thank Mr.ChellaMuthu for valuable guidance
and permit us to use equipment for the real time
analysis.
We thank Mr.Paranthaman for his valuable
guidance and support interms of practically.
We thank Mr.Renny Son for his support in last
minute of our project and the guidance.
We thank all our Department faculty members of
Electrical and Electronics Engineering and Faculty
members of Other Department for their suggestions
to carry out this project.


Fault Detection and Compensation in Low Voltage AC
System Using UPFC
M.Kamatchi Valli
1
, Asst Prof M.Vennila
2

1
PG Scholar,Karpaga Vinayaga College Of Engineering & Technology, Chennai, India

2
Assistant Professor, Karpaga Vinayaga College Of Engineering & Technology, Chennai, India

ABSTRACT
The goals of the proposed scheme are to detect
the fault in the bus between devices and to
separate the faulted section so that the system is
operating without affecting the complete system.
A fault in ac power system involves reactive
power loss. It is proposed to develop a UPFC
device to compensate the reactive power loss
during faults in low voltage ac system. In the
proposed system fault compensation will be
employed, so that system will have fault override
capability during transient faults or short
duration faults. Closed loop PID control is also
provided to pull off the required output voltage.
The Simulation is primed with the help of
MATLAB Software using Simulink.

Keywords: Unified Power Flow Control, DC-DC
Converters, Inverter

I.INTRODUCTION

DC-DC converters are electronic devices
used whenever we want to change DC electrical
power efficiently from one voltage level to another.
They are needed because unlike AC, DC cannot
simply be stepped up or down using a transformer.
In many ways, a DC-DC converter is the DC
equivalent of a transformer [1-2]. The DC energy
from one voltage level to another to be changed,
while wasting as little as possible in the process. In
other words, we want to perform the conversion
with the highest possible efficiency [3-4]. Another
important distinction is between converters which
offer full dielectric isolation between their input
and output circuits, and those which dont.
Needless to say this can be very important for some
applications, although it may not be important in
many others.

II. AC-DC CONVERTER
An ac to dc converter is an integral part of
any power supply unit used in the all electronic
equipments. Also, it is used as an interface between
utility and most of the power electronic equipments.
These electronic equipments form a major part of
load on the utility. Generally, to convert line
frequency ac to dc, a line frequency diode bridge
rectifier is used. To reduce the ripple in the dc
output voltage, a large filter capacitor is used at the
rectifier output. But due to this large capacitor, the
current drawn by this converter is peaky in nature.
The input current is rich in low order
harmonics. Also, as power electronics equipments
are increasingly being used in power conversion,
they inject low order harmonics into the utility. Due
to the presence of these harmonics, the total
harmonic distortion is high and the input power
factor is poor. Due to problems associated with low
power factor and harmonics, utilities will enforce
harmonic standards and guidelines which will limit
the amount of current distortion allowed into the
utility and thus the simple diode rectifiers may not
in use. So, there is a need to achieve rectification at
close to unity power factor and low input current
distortion. Initially, power factor correction
schemes have been implemented mainly for heavy
industrial loads like induction motors, induction
heating furnaces etc., which forms a major part of
lagging power factor load. However, the trend is
changing as electronic equipments are increasingly
being used in everyday life nowadays. Hence, PFC
is becoming an important aspect even for low
power application electronic equipments.AC/DC
line commentated converter or, as they also called
converter with natural communication or passive
rectifier, are the most usual choice application,
where a single-phase and three- phase supply is

available. This is due to simplicity of the circuits
requiring a minimum number of active and passive
components. Thyristors are the main line-
communes power switches. The term line-
commutated describes the type of commutation. to
turn on a thyristors, an injection of a current pulse
into its gate is required. In low power applications,
vehicle, medicine, and household devices, where
there is no ac supply or where reactive current and
harmonics caused by a line commutation would be
unreachable, it is accepted to employ forced
commutated converter having a more complex
circuitry and sometimes involving higher losses. A
special situation exists also with dc and ac loads,
where the response of a line-commuted converter
may be insufficient to cope with the stringent
dynamic and energy efficiency demand and where
an additional converter supplied by a dc link and
operated with a higher switching frequency is
necessary.

III.UNIFIED POWER FLOW
CONTROLLER (UPFC)

A combination of static synchronous
compensator (STATCOM) and a static series
compensator (SSSC) which are coupled via a
common dc link, to allow bidirectional flow of real
power between the series output terminals of the
SSSC and the shunt output terminals of the
STATCOM, and are controlled to provide
concurrent real and reactive series line
compensation without an external electric energy
source. The UPFC, by means of angularly
unconstrained series voltage injection, is able to
control, concurrently or selectively, the
transmission line voltage, impedance, and angle or,
alternatively, the real and reactive power flow in
the line. The UPFC may also provide independently
controllable shunt reactive compensation. In UPFC,
which combines a STATCOM and an SSSC the
active power for the series unit (SSSC) is obtained
from the line itself via the shunt unit STATCOM.
The latter is also used for voltage control with
control of its reactive power. This is a complete
controller for controlling active and reactive power
control through the line, as well as line voltage
control. Additional storage such as super
conducting magnet connected to the dc link via an
electronic interface would provide the means of
further enhancing the effectiveness of the UPFC.
The controller exchange of real power with an
external source, such as storage is much more
effective in control of system dynamics than
modulation of the power transfer within a system.
The UPFC was derived for the real time
control and dynamic compensation of ac
transmission systems, providing multifunctional
flexibility required to solve many of the problems
facing the power delivery industry. Within the
framework of traditional power transmission
concepts, the UPFC us able to control,
simultaneously or selectively, all the parameters
affecting power flow in the transmission line (i.e.,
voltage, impedance, and phase angle), and this
unique capability is signified by the adjective
unified in its name. Alternatively, it can
independently control both the real and reactive
power flow in the line. The reader should recall
that, for all the Controllers discussed in the
previous chapters, the control of real power is
associated with similar change in reactive power,
i.e., increased real power flow also resulted in
increased reactive line power. In order to increase
the system reliability and provide flexibility for
future system changes, the UPFC installation was
required to allow self-sufficient operation of the
shunt converter as an independent STATCOM and
the series converter as an independent Static
Synchronous Series Compensator (SSSC). It is also
possible to couple both converters together to
provide either shunt only or series only
compensation over a doubled control range.

IV.UPFC OPERATION STRATEGY

During system disturbances, mechanically
switched shunt capacitor banks and associated
controls are generally slow to react. Under actual
system contingency conditions, all of these banks
may not switch on (hunting concerns) or some may
over-correct the voltage and lock-out. To resolve
this situation, the UPFC is required to maintain a
predetermined reactive power margin to maximize
the shunt converters dynamic reactive power
reserve for system contingency conditions. This
ensures that the controllable reactive power range
of the shunt converter is available at all times to
compensate for dynamic system disturbances. The
shunt capacitor banks will be switched on and off to
maintain the reserve UPFC and SVC margins
during steady state load fluctuations.

V.DESCRIPTION OF THE UPFC

The Unified Power Flow Controller is
designed to meet the defined system
requirements, in particular, to provide fast
reactive shunt compensation. In order to
increase the system reliability and provide
flexibility for future system changes, the UPFC
installation was required to allow self-
sufficient operation of the shunt converter as
an independent STATCOM and the series
converter as an independent Static
Synchronous Series Compensator (SSSC). It is
also possible to couple both converters
together to provide either shunt only or series
only compensation over a doubled control
range.

VI.BLOCK DIAGRAM

Figure 1.Represent the block diagram of the proposed
system

VII.BLOCK DIAGRAM DESCRIPTION
A fault in ac power system involves
reactive power loss. Its proposed to develop a
UPFC device to compensate the reactive power loss
during faults in low voltage ac system. The
proposed system consists of one inverter, two
converter, and UPFC device between each line and
ground. Both ac and dc source, power-electronic
converters are required to connect a variety of
sources and loads to a common bus. Using a dc bus
requires fewer stages of conversion. The proposed
scheme detects the fault and separates the faulted
section so that the rest of the system keeps
operating. The loop-type dc bus is suggested for the
proposed scheme to make the system robust under
faulted conditions. It has also been reported that the
loop-type bus has good system efficiency especially
when the distribution line is not long. Closed loop
PID control is also provided to achieve the desired
output voltage. Pulse generators are employed to
produce switching pulses and PWM. The Voltage
Measurement block measures the instantaneous
voltage between two electric nodes.

VIII.SIMULATION CIRCUIT

Figure 2. Represent the simulation circuit for the
proposed system

The above circuit gives the simulation
circuit for fault detection and isolation in dc bus
using UPFC. DC voltage from battery is given to
converter and also AC voltage is given to ac-dc
converter where dc voltage is obtained as output.
The dc voltage is given to inverter and then to load.
Fault is occurred in between inverter and load. The
faulted current is made to flow to the UPFC and
then to transformer and then to load without
affecting the load.

IX. SIMULATION RESULTS
Simulation results for the simulation
diagram is given below. The figure(3-a) gives the
output voltage measured form the inverter. The
figure(3-b) gives the current waveform measured at
the output of inverter. The figure(3-c) gives the
voltage waveform when measured before the load.
The figure(3-d) gives the current waveform when
measured before the load. The figure(3-e) gives the
current waveform of the UPFC. The figure(3-f)

gives the voltage waveform of the UPFC. The next
figure(3-g) results the compensated voltage during
faulted condition. Figure(3-h) gives the comparison
of load voltage and source voltage.

Figure 3a. Source voltage obtained from inverter output.

Figure 3b.Source current obtained from inverter output.

Figure 3c.Load voltage which is obtained before the load.

Figure 3d.Load current obtained before the load

Figure 3e.Result is for UPFC current

Figure 3f. Result is for UPFC voltage


Figure 3g.Result is for compensated voltage during
fault condition

Figure 3h. Result is for comparing load voltage and
source voltage

X.CONCLUSION

A fault detection and isolation scheme for
the low-voltage dc-bus micro grid system is
developed with compensation method. The
proposed protection scheme is capable of detecting
abnormal fault current in the bus and separating the
faulted segment to avoid the entire system
shutdown. The UPFC regulates the voltage of the
bus as well as regulates the active and reactive
power of the buses and the lines within specified
limits. So the efficiency will be improved.

XI.REFERENCES

[1] Frede Blaabjerg, Remus Teodorescu, Marco Liserre,
and Adrian V. Timbus Overview of Control and Grid
Synchronization for Distributed Power Generation
Systems IEEE Transactions on Industrial Electronics,
Vol. 53, No. 5, October 2006.
[2] WanMin Fei, YanLi Zhang, and ZhengYu L, Novel
Bridge-Type FCL Based on Self-Turnoff Devices for
Three-Phase Power Systems IEEE Transactions on
Power Delivery, Vol.23, NO. 4, October 2008.
[3] Lianxiang Tang and Boon-Teck Ooi, Locating and
Isolating DC Faults in Multi-Terminal DC Systems
IEEE Transactions on Power Delivery, Vol. 22, No. 3,
JULY 2007.
[4] Daniel Salomonsson, Lennart Sder, and Ambra
Sannino, Protection of Low-Voltage DC Microgrids
IEEE Transactions on Power Delivery, Vol. 24, No. 3,
July 2009.



Using Distributed Power Flow Controller to Compensate
Unbalanced Currents in Transmission Line

V.Aathithya
1
, S. Suresh
2
EEE Department, B.S.Abdur Rahman University, Chennai, Taminadu, India

ABSTRACT

Distributed Power Flow Controller is a new
device within the family of FACTS. The DPFC has
the same control capability as the UPFC, but with
much lower cost and higher reliability. This paper
addresses one of the applications of the DPFC
namely compensation of unbalanced currents in
transmission systems. Since the series converters
of the DPFC are single phase, the DPFC can
compensate both active and reactive, zero and
negative sequence unbalanced currents. To
compensate the unbalance, two additional current
controllers are supplemented to control the zero
and negative sequence current respectively.

Keywords: FACTS, DPFC, modelling ,
Unbalanced currents, Zero sequence

I. INTRODUCTION

There is a great demand of power flow
control in power systems of the future and
combined FACTS devices are the most suitable
devices [1-3]. However, due to the cost and the
reliability issues given above, there are many
hurdles to the widespread application of
combined FACTS devices. The new concept is
Distributed Power Flow Controller (DPFC). It is
a combined FACTS device, which has taken a
UPFC as its starting point. The DPFC has the
same control capability as the UPFC;
independent adjustment of the line impedance,
the transmission angle and the bus voltage. The
DPFC eliminates the common DC link that is
used to connect the shunt and series converter
back-to- back within the UPFC. By employing
the Distributed FACTS concept as the series
converter of the DPFC, the cost is greatly
reduced due to the small rating of the
components in the series converters. Also, the
reliability of the DPFC is improved because of
the redundancy provided by the multiple series
converters [4-5]. The elimination of the
common DC link also allows the DSSC concept
to be applied to series converters. In that case,
the reliability of the new device is further
improved due to the redundancy provided by the
distributed series converters [6]. By applying the
two approaches eliminating the common DC
link and distributing the series converter, the
UPFC is further developed into a new combined
FACTS device: the Distributed Power Flow
Controller (DPFC), as shown in fig 1

Fig 1. Flow chart from UPFC to DPFC

II. DISTRIBUTED POWER FLOW
CONTROLLER (DPFC)

By introducing the two approaches outlined in
the previous section (elimination of the common DC
link and distribution of the series converter) into the
UPFC, the DPFC is achieved. Similar as the UPFC,
the DPFC consists of shunt and series connected
converters. The shunt converter is similar as a
STATCOM, while the series converter employs the
DSSC concept, which is to use multiple single-phase


converters instead of one three-phase converter. Each
converter within the DPFC is independent and has its
own DC capacitor to provide the required DC
voltage. DPFC configuration shown in fig 2

Fig. 2 DPFC configuration

As shown, besides the key components - shunt
and series converters, a DPFC also requires a high
pass filter that is shunt connected to the other side of
the transmission line and a star-delta transformer on
each side of the line. The unique control capability of
the UPFC is given by the back-to-back connection
between the shunt and series converters, which allows
the active power to freely exchange. To ensure the
DPFC has the same control capability as the UPFC, a
method that allows active power exchange between
converters with an eliminated DC link is required.

III. DPFC OPERATING PRINCIPLE

A)ACTIVE POWER EXCHANGE WITH
ELIMINATED DC LINK
Within the DPFC, the transmission line
presents a common connection between the AC ports
of the shunt and the series converters. Therefore, it is
possible to exchange active power through the AC
ports. The method is based on power theory of non-
sinusoidal components. According to the Fourier
analysis, non-sinusoidal voltage and current can be
expressed as the sum of sinusoidal functions in
different frequencies with different amplitudes. The
active power resulting from this non-sinusoidal
voltage and current is defined as the mean value of
the product of voltage and current. Since the integrals
of all the cross product of terms with different
frequencies are zero, the active power can be
expressed by:

Where V
i
and I
i
are the voltage and current at the
i
th
harmonic frequency respectively, and is the
corresponding angle between the voltage and current.
Equation shows that the active powers at different
frequencies are independent from each other and the
voltage or current at one frequency has no influence
on the active power at other frequencies. The
independence of the active power at different
frequencies gives the possibility that a converter
without a power source can generate active power at
one frequency and absorb this power from other
frequencies.
By applying this method to the DPFC, the
shunt converter can absorb active power from the grid
at the fundamental frequency and inject the power
back at a harmonic frequency. This harmonic active
power flows through a transmission line equipped
with series converters. According to the amount of
required active power at the fundamental frequency,
the DPFC series converters generate a voltage at the
harmonic frequency, thereby absorbing the active
power from harmonic components. Neglecting losses,
the active power generated at the fundamental
frequency is equal to the power absorbed at the
harmonic frequency.
For a better understanding, Figure 3 indicates
how the active power is exchanged between the shunt
and the series converters in the DPFC system. The
high-pass filter within the DPFC blocks the
fundamental frequency components and allows the
harmonic components to pass, thereby providing a
return path for the harmonic components. The shunt
and series converters, the high pass filter and the
ground form a closed loop for the harmonic current.

B) USING THIRD HARMONIC COMPONENTS
Due to the unique features of 3
rd
harmonic
frequency components in a three-phase system, the
3
rd
harmonic is selected for active power exchange in
the DPFC.


Fig.3 Active power exchange between DPFC converters

In a three-phase system, the 3
rd
harmonic in
each phase is identical, which means they are zero-
sequence components. Because the zero-sequence
harmonic can be naturally blocked by star-delta
transformers and these are widely incorporated in
power systems (as a means of changing voltage),
there is no extra filter required to prevent harmonic
leakage. As introduced above, a high-pass filter is
required to make a closed loop for the harmonic
current and the cut-off frequency of this filter is
approximately the fundamental frequency. Because
the voltage isolation is high and the harmonic
frequency is close to the cut-off frequency, the filter
will be costly. By using the zero-sequence harmonic,
the costly filter can be replaced by a cable that
connects the neutral point of the star-
delta transformer on the right side in Fig 3 with the
ground. Because the delta winding appears open-
circuit to the 3rd harmonic current, all harmonic
current will flow through the Y-winding and
concentrate to the grounding cable as shown in Fig 4.
Therefore, the large high-pass filter is eliminated.

Fig. 4 Utilize grounded star-delta transformer to filter zero-
sequence harmonic

Another advantage of using the 3
rd
harmonic to
exchange active power is that the grounding of the
star-delta transformers can be used to route the
harmonic current in a meshed network. If the network
requires the harmonic current to flow through a
specific branch, the neutral point of the star-delta
transformer in that branch, at the side opposite to the
shunt converter, will be grounded and vice versa. Fig
5 shows a simple example of routing the harmonic
current by using the grounding of the star-delta
transformer. Because the floating neutral point is
located on the transformer of the line without the
series converter, it is an open-circuit for 3
rd
harmonic
components and therefore no 3
rd
harmonic current
will flow through this line.

Fig.5 Route the harmonic current by using the grounding of
the star-delta Transformer

The harmonic at the frequencies like 3rd, 6th,
9th... are all zero-sequence and all can be used to
exchange active power in the DPFC. However, the 3
rd

harmonic is selected, because it is the lowest
frequency among all zero-sequence harmonics. The
relationship between the exchanged active power at
the i
th
harmonic frequency and the voltages
generated by the converters is expressed by the well
known the power flow equation and given as:

Where X
i
is the line impedance at i
th

frequency|V
Sh
|and|V
se
| the voltage magnitudes of the
i
th
harmonic of the shunt and series converters, and
(
sh,i

se,i
) is the angle difference between the two
voltages. As shown, the impedance of the line limits
the active power exchange capacity. To exchange the
same amount of active power, the line with high
impedance requires higher voltages. Because the


transmission line impedance is mostly inductive and
proportional to frequency, high transmission
frequencies will cause high impedance and result in
high voltage within converters. Consequently, the
zero-sequence harmonic with the lowest frequency
the 3
rd
harmonic has been selected.

IV. ADVANTAGES AND LIMITATION OF
THE DPFC

The DPFC can be considered a UPFC that
employs the D-FACTS concept and the concept of
exchanging power through the 3rd harmonic. In this
way, the DPFC inherits all their advantages:

High controllability:
The DPFC can simultaneously control all the
parameters of the transmission network: line
impedance, transmission angle and bus voltage.
High reliability:
The redundancy of the series converter gives
high reliability without increasing cost. In addition,
the shunt and series converters are independent and
failure of one will not influence the other converters.
Low cost:
There is no phase-to-phase voltage isolation
required between the series converters of different
phases. The power rating of each converter is also
low. Because of the large number of the series
converters, they can be manufactured in series
production. If the power system is already equipped
with the STATCOM, the system can be updated to
the DPFC with only low additional costs. However,
there is a drawback to using the DPFC.
Extra currents:
Because the exchange of power between the
converters takes place through the same transmission
line as the main power, extra currents at the 3rd
harmonic frequency are introduced. These currents
reduce the capacity of the transmission line and result
in extra losses within the line and the two star-delta
transformers. However, because this extra current is
at the 3rd harmonic frequency, the increase in the
RMS value of the line current is not large and through
the design process can be limited to less than 5% of
the nominal current.

V.SIMULATION AND RESULTS OF DPFC

A) Modelling Of DPFC Shunt Converter:

The modeling of this converter is done by using
MATLAB software and the modeling diagram is
shown in the fig 6 Simulation circuit for the modeling
of Shunt converter.

Fig 6. Simulation circuit for the modeling of Shunt
converter

Fig 7. Shunt converter Input voltage

Fig 8. Shunt converter Output voltage

Fig 9. Shunt converter Input current



Fig 10. Shunt converter output current

When fault is applied between 0.5 to 2 second,
current is increased to 150 A, thereby voltage reduced
to 8 times the normal value. When the shunt
compensator is connected at 0.6 second, current is
increased and thereby simultaneously the voltage
value is reduced. Analysis of shunt converter shown
in table 1. In order to compensate the voltage, a series
compensator is used.

Table 1 Analysis Of Shunt Converter

Supply
current(A)
100
A
Fault
Occurring
period(Sec)
0.5-
2 S
Current
during fault
period(A)
150
A
Compensated
current
200
A

B)Modelling of DPFC Series Converter
The modeling of this converter is done by
using MATLAB software and the modeling
diagram is shown in the figure 8 Simulation
circuit for the modeling of Series converter.

Fig. 11 Simulation circuit for the modeling of Series
converter

Fig. 12 Series Compensated Output Voltage and Current

When fault is applied between 0.5 to 2
second, voltage is reduced to 180v, thereby
current increased to 8 times the normal value.
When the series compensator is connected at 0.6
second, voltage is increased and thereby
simultaneously the current value is reduced.
Analysis of series converter shown in table 2. In
order to compensate the current, a shunt
compensator is used.

Table 2 Analysis Of Series Converter

C) DPFC Modelling

The modeling of this converter is done by
using MATLAB software and the modeling
diagram is shown in the figure 10 Simulation
circuit for the DPFC modeling.

Supply Voltage(V) 400 V
Fault Occurring
period(Sec)
0.5-2 S
Voltage during fault
period(V)
180 V
Compensated voltage 390 V


Fig 13 simulation circuit for the DPFC modelin

Fig 14 DPFC modelling Output

VI. CONCLUSION

This paper investigates the capability of the
DPFC to balance a network. It is found that the DPFC
can compensate both negative and zero sequence
components, consequently the DPFC is more
powerful than other FACTS device for compensation
of unbalanced currents. Additional controllers are
supplemented to existing DPFC controller, and their
principle is to monitor the negative and
zerosequences of the current through the transmission
line, and to force them to be zero by applying an
opposing voltage. As a side effect, the DPFC
generates non-zero sequence 3rd current during the
unbalance situation, which can not be blocked by the
Y- transformer. However the magnitude of the
nonzero sequence 3rd current is much smaller than
the nominal current at the fundamental frequency,
less than 4% typically.

REFERENCES

[1] L. Gyugyi, Unified power-flow control concept for
flexible ac transmission systems, Generation,
Transmission and Distribution [see also IEE Proceedings-
Generation, Transmission and Distribution], IEE
Proceedings C, vol. 139, no. 4, pp. 323331, 1992.

[2] Y. Ikeda and T. Kataoka, A upfc-based voltage
compensator with current and voltage balancing function,
in Applied Power Electronics Conference and Exposition,
2005. APEC 2005. Twentieth Annual IEEE, vol. 3, 2005,
pp. 18381844 Vol. 3.

[3] Z. Yuan, S. W. H. de Haan, and B. Ferreira, A new
facts component: Distributed power flow controller (dpfc),
in Power Electronics and Applications, 2007 European
Conference on, 2007, pp. 14.

[4] D. Divan and H. Johal, Distributed facts - a new
concept for realizing grid power flow control, in Power
Electronics Specialists Conference, 2005. PESC 05. IEEE
36th, 2005, pp. 814.

[5] M. Milosevic, G. Andersson, and S. Grabic,
Decoupling current control and maximum power point
control in small power network with photovoltaic source,
in Power Systems Conference and Exposition, 2006. PSCE
06. 2006 IEEE PES, 2006, pp. 10051011.

[6] H. Namho, J. Jinhwan, and N. Kwanghee, A fast
dynamic dc-link power-balancing scheme for a pwm
converter-inverter system, Industrial Electronics, IEEE
Transactions on, vol. 48, no. 4, pp. 794803, 2001.



Power System Restoration in Transmission Network Using
Dijkstras Algorithm
Naveen.G
1
, Arther Jain.A
2
, Vimal Raj.A
3
Electrical and Electronics Engineering,Thangavelu Engineering College,Chennai,India

ABSTRACT
A graph theory based methodology called
dijkstras algorithm is used to find the
energizing path of power to flow for a given
network after a complete blackout is proposed
here. Whenever a blackout occurs in the
transmission network, the power system
operators are under immense pressure to
restore the network. The main aim of the power
system restoration is to restore as much load as
possible & as quickly as possible. After a
blackout occurs first all the generators has to be
energized and then synchronized. After
synchronization of generators only all the loads
can be supplied. For energizing the generators a
sequential procedure has to be followed. If the
sequence used is wrong then it may lead to
cascaded outages.The Dijkstra's algorithm helps
in finding the sequence to energize the
generators based on least impedance path called
minimum spanning tree. Newton Raphson based
load flow technique is applied to this resultant
minimum spanning tree(power flow path).
Based on the results (voltage, current and power
flow) obtained from the load flow solutions,
other constraints of the restoration problem are
applied.
Keywords: Black out, graph theory, minimum
spanning tree, load flow solution.
I. INTRODUCTION
Power system is a complex network involving the
flow of power, which is generated using various
techniques to meet the need of the industries or
domestic consumers [1-3]. In normal mode of
operation all the constraints are satisfied. Reserve
margin is sufficiently high too make the system
well secure by the system security level falls below
certain level or the probability of disturbances
increases the system may be in alert state [4-6].
II. BROWN OUT
A brownout is an intentional drop in
voltage in an electrical power supply system used
for load reduction in an emergency. The reduction
lasts for minutes or hours, as opposed to short-term
voltage sag or dip [7]. The term brownout comes
from the dimming experienced by lighting when
the voltage sags. A voltage reduction may be an
effect of disruption of an electrical grid, or may

occasionally be imposed in an effort to reduce load
and prevent a blackout.

Fig 1 : Power System Operating States
III LOAD FLOW ANALYSIS
Power flow studies are of great
importance in planning & designing the future
expansion of power system as well as in
determining the best operation of existing systems.
The principle information obtained from power
flow study is the magnitude & phase angle of
voltage at each bus the real & reactive power
following in each line. Power flow calculations
usually employ iterative techniques such as
Newton-Raphson method solves the polar form of
power flow equations until P & Q mismatches at
all buses fall within specified tolerances.
IV GRAPH THEORY
Graph theory is a branch of data structures
concerned about how the networks can be encoded
& their properties measured. A graph (G) is a set of
points called vertices & the lines connecting the
points called Edges. The graphs are broadly
classified into two types. One type of classification
is Directed Graph & Undirected Graphs.An
www.ijrde.com


undirected graph G= (V, E) consist of finite set of
vertices V & set of edges E.
Fig 2 : Example Problem

V DIJKSTRAS ALGORITHM
Dijkstra's algorithm, conceived by
Dutch computer scientist Edsger Dijkstra in
1959, is a graph search algorithm that solves
the single-source shortest path problem for a
graph with nonnegative edge path costs,
producing a shortest path tree. This algorith
is often used in routing.
Fig 3 : Minimum Spanning Tree by Dijkstras
Algorithm
Table 1 : Comparison of results of various Algorithm
ALGORITHM DISTANCE CALCULATED
FROM MINIMUM
TREE
Prims Algorithm 1.03
Dijkstras
Algorithm
0.83
Kruskals
Algorithm
1.03
Reverse Delete
Algorithm
1.03

VI RECOVERY PROCESS
undirected graph G= (V, E) consist of finite set of

Problem

Dijkstra's algorithm, conceived by
Dutch computer scientist Edsger Dijkstra in
1959, is a graph search algorithm that solves
source shortest path problem for a
graph with nonnegative edge path costs,
producing a shortest path tree. This algorithm

Minimum Spanning Tree by Dijkstras
Table 1 : Comparison of results of various Algorithm
DISTANCE CALCULATED
SPANNING
The whole recovery process is divided into 3
stages.
(A) BLACK START:
Due to any critical fault or transient in the
network a complete blackout will be occurring.
(B) SYSTEM RECONSTRUCTION
The generator (Slack bus) started first &
based on the sequence of starting & starting time
the generators on the network are started.
(C) LOAD RECOVERY:
Initially the critical loads are fed & later
after stabilization of the critical loads all other
loads are connected.
Fig 4 : Initial Network

Table 2 : Bus Data Of Initial Network
sue: pp- 177-184
178 | P a g e
The whole recovery process is divided into 3
Due to any critical fault or transient in the
network a complete blackout will be occurring.
RECONSTRUCTION:
The generator (Slack bus) started first &
based on the sequence of starting & starting time
the generators on the network are started.
Initially the critical loads are fed & later
ical loads all other

Fig 4 : Initial Network
Table 2 : Bus Data Of Initial Network


Fig 5 : System Reconstruction Stage
VII OUTPUT OF INITIAL NETWORK
Power Flow Solution by Newton-Raphson
Method
Maximum Power Mismatch = 3.83432e-005
No. of Iterations = 4

Table 3 : Output Of Initial Network
Bus
No
Bus
Code Voltage
Load Generator
MW Mvar MW Mvar
1 0 1 0 0 0 0
2 0 1 0 0 0 0
3 0 1 322 2.4 0 0
4 0 1 500 184 0 0
5 0 1 0 0 0 0
6 0 1 0 0 0 0
7 0 1 233.8 84 0 0
8 0 1 522 176 0 0
9 0 1 0 0 0 0
10 0 1 0 0 0 0
11 0 1 0 0 0 0
12 0 1 7.5 88 0 0
13 0 1 0 0 0 0
14 0 1 0 0 0 0
15 0 1 320 153 0 0
16 0 1 329 32.3 0 0
17 0 1 0 0 0 0
18 0 1 158 30 0 0
19 0 1 0 0 0 0
20 0 1 628 103 0 0
21 0 1 274 115 0 0
22 0 1 0 0 0 0
23 0 1 247.5 84.6 0 0
24 0 1 308.6 -92 0 0
25 0 1 224 47.2 0 0
26 0 1 139 17 0 0
27 0 1 281 75.5 0 0
28 0 1 206 27.6 0 0
29 0 1 283.5 26.9 0 0
30 2 1 0 0 250 0
31 1 1 9.2 4.6 0 0
32 2 1 0 0 650 0
33 2 1 0 0 632 0
34 2 1 0 0 508 0
35 2 1 0 0 650 0
36 2 1 0 0 560 0
37 2 1 0 0 540 0
38 2 1 0 0 830 0
39 2 1 1104 250 1000 0


Total 6097
1409 6145 1445.9 0

Fig 6 : Load Recovery Stage

VIII Results Of Newton-Raphson
Method
--Line-- Power at bus & line flow
--Line loss--
From To MW Mvar MVA
MW Mvar
1 0.000 0.000 0.000
2 -125.392 24.820 127.824 0.671 -
61.246
39 125.392 -24.820 127.824 0.158 -
71.359

2 0.000 0.000 0.000
1 126.063 -86.066 152.640 0.671 -
61.246
3 363.659 94.209 375.664 1.924 -
2.131
25 -239.722 66.443 248.759
4.534 -8.760
Bus
no Voltage Angle Load Generation Injected
MW Mvar MW Mvar Mvar
1 1.004 -8.408 0 0 0 0 0
2 0.985 -5.3 0 0 0 0 0
3 0.966 -8.525 322 2.4 0 0 0
4 0.944 -9.657 500 184 0 0 0
5 0.95 -8.525 0 0 0 0 0
6 0.953 -7.782 0 0 0 0 0
7 0.942 -10.22 233.8 84 0 0 0
8 0.942 -10.77 522 176 0 0 0
9 0.988 -10.47 0 0 0 0 0
10 0.962 -4.966 0 0 0 0 0
11 0.958 -5.922 0 0 0 0 0
12 0.937 -5.876 7.5 88 0 0 0
13 0.957 -5.712 0 0 0 0 0
14 0.951 -7.457 0 0 0 0 0
15 0.947 -7.538 320 153 0 0 0
16 0.961 -7.538 329 32.3 0 0 0
17 0.965 -5.752 0 0 0 0 0
18 0.964 -8.098 158 30 0 0 0
19 0.979 0.195 0 0 0 0 0
20 0.976 -0.81 628 103 0 0 0
21 0.959 -2.97 274 115 0 0 0
22 0.976 2.178 0 0 0 0 0
23 0.973 1.939 247.5 84.6 0 0 0
24 0.967 -5.612 308 -92 0 0 0
25 0.996 -3.796 224 47.2 0 0 0
26 0.987 -5.072 139 17 0 0 0
27 0.97 -7.291 281 75.5 0 0 0
28 0.989 -1.128 206 27.6 0 0 0
29 0.992 1.96 283 26.9 0 0 0
30 1 -2.668 0 0 250 87.276 0
31 1 0 9.2 4.6 525.41 227.41 0
32 1 2.801 0 0 650 234.37 0
33 1 5.394 0 0 632 141.95 0
34 1 4.497 0 0 508 133.09 0
35 1 7.64 0 0 650 195.64 0
36 1 10.907 0 0 560 133.3 0
37 1 3.416 0 0 540 336.39 0
38 1 9.433 0 0 830 65.866 0
39 1 -10.19 1104 250 1000 190.66 0


30 -250.000 -74.586 260.889 0.000
12.691

3 -322.000 -2.400 322.009
2 -361.736 -96.340 374.345 1.924 -2.131
4 90.339 85.188 124.170 0.241 -16.229
18 -50.603 8.752 51.355 0.034
-19.479

4 -500.000 -184.000 532.781
3 -90.098 -101.416 135.657 0.241 -16.229
5 -140.702 -43.228 147.193 0.190 -8.983
14 -269.200 -39.356 272.062 0.661
-1.741

5 0.000 0.000 0.000
4 140.892 34.245 144.995 0.190 -8.983
6 -457.407 -77.875 463.988 0.476 2.265
8 316.514 43.629 319.507 0.911 -0.462

6 0.000 0.000 0.000
5 457.883 80.139 464.843 0.476 2.265
7 420.738 84.670 429.173 1.223 8.594
11 -362.412 -21.029 363.021 1.014 -0.800
31 -516.210 -143.780 535.859 0.000 79.029

7 -233.800 -84.000 248.432
6 -419.516 -76.076 426.358 1.223 8.594
8 185.716 -7.924 185.885 0.155 -5.140

8 -522.000 -176.000 550.872
5 -315.604 -44.092 318.669 0.911 -0.462
7 -185.560 2.784 185.581 0.155
-5.140
9 -20.836 -134.692 136.294 0.371 -29.592

9 0.000 0.000 0.000
8 21.207 105.100 107.218 0.371 -29.592
39 -21.207 -105.100 107.218 0.027
-117.899

10 0.000 0.000 0.000
11 364.020 65.127 369.800 0.593
-0.339
13 285.980 73.760 295.339 0.379
-2.637
32 -650.000 -138.887 664.673 0.000
95.486

11 0.000 0.000 0.000
6 363.425 20.229 363.988 1.014 -0.800
10 -363.427 -65.466 369.276 0.593
-0.339
12 0.001 45.237 45.237 0.036
0.971

12 -7.500 -88.000 88.319
11 0.034 -44.266 44.266 0.036
0.971
13 -7.534 -43.734 44.379 0.036
0.976

13 0.000 0.000 0.000
10 -285.601 -76.397 295.642 0.379
-2.637
14 278.031 31.687 279.830 0.774
-6.998
12 7.570 44.710 45.347 0.036
0.976

14 0.000 0.000 0.000
4 269.861 37.615 272.470 0.661 -1.741
13 -277.256 -38.685 279.942 0.774
-6.998
15 7.395 1.070 7.472 0.007
-32.872


15 -320.000 -153.000 354.696
14 -7.388 -33.942 34.737 0.007
-32.872
16 -312.612 -119.058 334.516 1.106
-4.022

16 -329.000 -32.300 330.582
15 313.718 115.036 334.144 1.106
-4.022
17 230.494 -60.279 238.246 0.425
-7.052
19 -502.095 -35.931 503.379 4.372
24.659
21 -328.465 35.266 330.353 0.953
-7.401
24 -42.651 -86.392 96.347 0.028
-5.761

17 0.000 0.000 0.000
16 -230.070 53.226 236.147 0.425
-7.052
18 208.966 -6.651 209.072 0.328
-8.420
27 21.104 -46.575 51.134 0.020
-29.845

18 -158.000 -30.000 160.823
3 50.638 -28.231 57.976 0.034 -19.479
17 -208.638 -1.769 208.645 0.328
-8.420

19 0.000 0.000 0.000
16 506.468 60.590 510.079 4.372
24.659
33 -629.063 -82.369 634.433 2.937
59.579
20 122.595 21.779 124.515 0.113
2.230

20 -628.000 -103.000 636.391
34 -505.518 -83.451 512.360 2.482
49.640
19 -122.482 -19.549 124.032 0.113
2.230

21 -274.000 -115.000 297.155
16 329.418 -42.667 332.170 0.953
-7.401
22 -603.418 -72.333 607.738 3.202
32.014

22 0.000 0.000 0.000
21 606.620 104.347 615.529 3.202
32.014
23 43.380 25.408 50.273 0.019
-17.229
35 -650.000 -129.755 662.825 0.000 65.891
23 -247.500 -84.600 261.560
22 -43.361 -42.636 60.811 0.019 -17.229
24 354.204 1.205 354.206 2.924 12.573
36 -558.343 -43.168 560.009 1.657 90.132

24 -308.600 92.000 322.022
16 42.680 80.631 91.230 0.028 -5.761
23 -351.280 11.369 351.464 2.924 12.573

25 -224.000 -47.200 228.919
2 244.256 -75.204 255.571 4.534 -8.760
26 69.987 -3.567 70.078 0.173 -48.698
37 -538.242 31.571 539.168 1.758 67.958

26 -139.000 -17.000 140.036
25 -69.813 -45.131 83.131 0.173 -48.698
27 261.018 80.848 273.252 1.102
-11.383
28 -140.507 -24.706 142.663 0.879
-66.490


29 -189.697 -28.011 191.754 2.134
-77.314

27 -281.000 -75.500 290.966
17 -21.084 16.731 26.915 0.020
-29.845
26 -259.916 -92.231 275.795 1.102
-11.383

28 -206.000 -27.600 207.841
26 141.386 -41.784 147.431 0.879
-66.490
29 -347.386 14.184 347.676 1.737
-5.691

29 -283.500 -26.900 284.773
26 191.831 -49.304 198.066 2.134
-77.314
28 349.123 -19.874 349.688 1.737
-5.691
38 -824.454 42.278 825.537 5.546
108.145

30 250.000 87.276 264.796
2 250.000 87.277 264.797 0.000 12.691

31 516.208 222.807 562.239
6 516.210 222.809 562.242 0.000 79.029

32 650.000 234.370 690.963
10 650.000 234.373 690.964 0.000 95.486

33 632.000 141.947 647.745
19 632.000 141.948 647.745 2.937
59.579

34 508.000 133.091 525.145
20 508.000 133.091 525.145 2.482
49.640

35 650.000 195.644 678.805
22 650.000 195.646 678.806 0.000
65.891

36 560.000 133.300 575.646
23 560.000 133.301 575.647 1.657
90.132

37 540.000 36.387 541.225
25 540.000 36.388 541.225 1.758
67.958

38 830.000 65.866 832.609
29 830.000 65.867 832.609 5.546
108.145

39 -104.000 -59.340 119.738
1 -125.234 -46.539 133.602 0.158 -71.359
9 21.234 -12.799 24.793 0.027
-117.899

Total loss 48.310 36.862

IX.CONCLUSION
This paper presents the use of
Dijkstras Algorithm for service restoration
plan after a complete blackout. The large
number of possible outage conditions & the
need to provide a restoration plan in minimum
time are argument in favor of this technique.
By application of graph theory the process had
been made simple and user friendly. In order
to demonstrate the efficiency of dijkstras
algorithm it has been applied to IEEE 10
Generator 39 Bus System. We carry out three
stages of recovery process by using dijkstras
algorithm. Newton-Raphson method is used to
carry out load flow analysis. The simulation
results show that Newton-Raphson method is
effective and promising. It has been found that
by application of dijkstras algorithm the


transmission losses can be reduced to
significant extent.The advantages are (1)
solution procedure leads to the optimum
solution & (2) avoid combinational explosion
of the number of the number of configurations
to be tested. This it is believed that the results
from Dijkstras algorithm in power system
restoration results in better plan, so it can be
considered for real time application.Since the
simulation implementation is done only for 39
bus system it can be extended to networks
with more number of buses.
REFERENCES
[1] M.M. Adibi, R.J. Kafka, and D.P. Milanicz, Expert
System Requirements For Power System
Restoration, IEEE Transactions on Power
Systems, vol. 9, no. 3, pp. 15921598, 1994.
[2] M.M. Adibi, P. Clelland, and L. Fink et al., Power
System Restoration- A Task Force Report, IEEE
Transactions on PowerSystems, vol. 2, no. 2, pp.
271277, 1987.
[3] M.M. Adibi, J.N. Borkoski, and R.J. Kafka, Power
System Restoration -- The Second Task Force
Report, IEEE Transactions on Power Systems, vol.
2, no. 4, pp. 927933, 1987.
[4] M.M.Abidi & R.J.Kafka, Power System Restoration
Issues, 1990.
[5] Ancona J.J,A framework for power system
restoration following major power failure ,IEEE
Transactions on power systems, Vol 9,pp.1480-
1485,August 1995.
[6] Black-Start Network Partitioning Considering Time
limits & Subsystem Restoration Sequences Liang
Hai-ping, Ma Hui-yuan, Gu Xue-ping IEEE
transactions on Power System,2011.
[7] Development of an Interactive rule based system
for bulk power system restoration ,C.Y.Teo &
Weishen,IEEE transaction on Power System, Vol-
15, Num-2, May 2000.

Methods Enriching Power and Energy Development (MEPED) 2014 185 |P a g e

Fuzzy Logic Controller with Maximum Power Point
Tracking for Three-Phase Grid-Connected
PV System
V.Bala
1
, G.Rajeswari
2

Department Of EEE, Valliammai Engineering College, Chennai

ABSTRACT
A simple closed loop controller has been developed
for interfacing PV array with utility grid through a
three-phase line-commutated inverter. The closed
loop controller has been employed to track and
feed maximum power to the grid. A PIC
microcontroller together with a multiplier and op
amp signal conditioning circuit has been used for
the generation of firing pulses to the thyristors in
the inverter. The firing angle is automatically
adjusted by the closed loop controller to extract
maximum power from the solar PV array, which is
fed to the utility grid. The simulink model of the
proposed scheme employing Fuzzy Logic
Controller has been developed using
MATLAB/PSB. The results obtained from the
experimental investigation and simulation studies
of the proposed scheme are compared and the value
of firing angle at which maximum power is fed to
the grid is found to be in close agreement. To
reduce the current harmonics introduced by the
line-commutated inverter on the grid side, a
capacitor bank is connected across the utility grid.

Keywords: Fuzzy systems, Inverters,
Maximum power point tracking, Photovoltaic
I. INTRODUCTION
With the industrial development, the problem of
energy shortage is more and more aggravating. The
Photovoltaic (PV) system technologies are rapidly
expanding and have increasing roles in electric
power technology and regarded as the green energy
of the new century [1]. The solar cell has an
optimum point corresponding to the maximum
power. The output power of a PV array varies
according to the sunlight conditions, atmospheric
conditions including cloud cover, local surface
reflectivity, and temperature. To obtain maximum
power from photovoltaic array, photovoltaic power
system usually requires maximum power point
tracking (MPPT) controller [2]. Various
approaches have been reported to implement
MPPT. The Perturb and Observe (P&O) method
needs to calculate dP/dV to determine the
maximum power point (MPP) [3],[4]. Though it is
relatively simple to implement, it cant track the
MPP when the irradiance changes rapidly; and it
oscillates around the MPP instead of directly
tracking it. The Incremental Conductance method
can track MPP rapidly but increases the complexity
of the algorithm, which employs the calculation of
dI/dV [5]. The Constant Voltage method [6], which
uses 76% open circuit voltage as the MPP voltage,
and the Short- Circuit Current method [7] are
simple, but they do not always accurately track
MPPs. A single-stage PV generation system was
presented by Liang et al. [8], but it needs nontrivial
calculations for MPPT and the control loop is
complex. MPPT for grid-connected PV system
have been proposed using three-arm rectifier-
inverter [9]. This describes a single-phase system
and employs line-frequency switching only for
common arm of the inverter, in order to reduce the
switching loss. MPPT using fuzzy logic have also
been reported [10], [11]. These studies show that
the fuzzy control algorithm is capable of improving
the tracking performance as compared with the
conventional methods for both linear and non-
linear loads. However, these schemes supply only
an isolated load. In this paper, a fuzzy logic
controller is proposed for maximum solar power
tracking of the PV array with a line-commutated
inverter for a three-phase grid-connected system.
This method requires only the linguistic control
rules for maximum power point; the mathematical
model is not required.
II. PROPOSED SCHEME

The block diagram of the proposed scheme is
shown in Fig.1. This scheme of power generation


consists of PV array, a line-commutated SCR
inverter, a step-up transformer and the fuzzy logic
controller. The PV array converts the solar into
electrical power.
Fig.1 Basic PV system integrated with three phase
utility grid
This is fed to the 6-pulse Thyristor Bridge, which
acts as line-commutated inverter through dc link
inductance. This inductance is used to obtain a
steady direct current from the PV panels. The line-
commutated inverter transfers the power from the
PV panels to the utility grid via the step-up
transformer.
The FLC takes two inputs, namely the actual
power output P
o
at the output of the transformer
and the maximum reference power which is
calculated based on V
oc
and I
sc
of the PV array as
explained in section III. It is to be noted that the
V
oc
of the array will vary with temperature and I
sc

will vary with irradiation. The error between the
actual power and the reference power is used for
modulating the firing angle delay for the line-
commutated inverter, so that maximum power is
fed to the grid. The FLC produces an output which
is used for varying the firing angle of the inverter
till the actual power equals the maximum power.
The transformer is used to adjust the voltage level
of the inverter output to match that of utility for
proper operation of the system.

A. PV Array Model
The classical equation of a PV cell describes the
relationship between current and voltage of the cell
(neglecting the current in the shunt resistance of the
equivalent circuit of the cell) as [12]

I
pv
- Iph- Io[
1
which is written as

(2)
where,

10
(3)
since,

The above equations can be used to determine the
characteristics of a panel or an array, as it is evident
that the characteristics of a panel made up of
identical cells can be obtained by appropriately
scaling the I-V characteristics of the individual
cells.
Neglecting the effect of the recombination losses
in the i-layer, the analytical model yields the
following expression:
ln
(4)
The PV model developed using the above
equation is used for simulation in the proposed
scheme.
B. Line - Commutated Inverter
It is well known that a fully controlled SCR
converter shown in Fig. 2 can operate both as
rectifier and inverter depending upon the range of
firing angle. In the proposed scheme, the converter
operates as an inverter. The dc output voltage and
the current in phase-a, of the three-phase full
converter, for a firing angle = 150
o
are shown in
Fig. 3. If the thyristors are numbered as shown in
Fig. 2, the normal firing sequence is 12, 23, 34, 45,
56 and 61. So, if the load is capable of supplying
power, then the direction of power flow can be
reversed by reversal of the dc voltage, the current
direction being unchanged. The delay angle must
be greater than 90
o
. In the present case, no extra
effort is required to synchronize the inverter output
with grid supply. This of course is possible only
with SCR converters.
Line-
commutat
ed inverter
a
V
R L
Three
-
phase
Firing
pulse

P
V
+
_

V
I
Fuzzy
Logic

V

I
b
Filter
P
Pr
Three
-
phase
c


Fig 2: Circuit of three-phase fully controlled bridge
converter

Fig 3: Voltage and current waveforms of three phase full
converter
(i) Harmonics:
The rms value of n
th
harmonic current in phase-a is
given by,
sin

(5)
The rms value of the fundamental current is
= 0.7797
(6)
The total rms current in phase a is given by,

()
= 0.8165

(7)
Now, harmonic factor (HF) or total harmonic
distortion (THD) is given by,
HF=
= 0.3108 i.e THD = 31.08%

(8)
The active and reactive powers in three-phase full
converters at the fundamental frequency
respectively are given by,
=
cos() (9)
=

sin() =
sin() (10)
III. FUZZY LOGIC CONTROLLER
The classical (P, PI, PID) control technique has
been the basis in simple control systems. Since
classical controllers are fixed-gain feedback
controllers, they cannot compensate the parameter
variations in the plant and cannot adapt changes in
the environment. In classical conventional
techniques, mathematical modeling of the plants
and parameter tuning of the controller have to be
done before implementing the controller.
Therefore, a classical controller is not suitable for
nonlinear control application. The need to
overcome such problems and to have a controller
well-tuned not only for one operating point but also
for a whole range of operating points has motivated
the other control techniques and the idea of an
adaptive controller. In a fuzzy logic control system,
there is no necessity for a plant model. The plant
can be single input single output (SISO) or multi
input multi output (MIMO) in nature. The block
diagram of fuzzy logic control scheme is shown in
Fig. 4. Fuzzy logic controller is composed of 3
parts: fuzzification, inference engine and
defuzzification as described below.
A. Fuzzification
The values of membership function are assigned to the
linguistic variables using seven fuzzy subsets called
negative big (nb), negative medium (nm), negative small
(ns), zero (zr), positive small (ps), positive medium (pm),
positive big (pb). Variables e and de are selected as input
variables, where e is the error between the reference
power (P
ref
) and the actual power (P
act
) of system; de is
the change in error in the sampling interval. The output
variable is the change in firing angle, dalpha. Triangular
membership functions (trimf) are selected for all these
singletons. The membership functions of the variables
error, change in error and change in firing angle are
Pact
e
d
e

FLC

Plant
Pref
+

-
-
v
bc

v
ab
-v
ca
v
bc
-
v
ab

v
ca

PV
L
Three-
phase
R
T4 T T
T T
Step -
up
T
+
-


D
e
g
r
e
e

o
f

m
e
m
b
e
r
s
h
i
p

dalpha
D
e
g
r
e
e

o
f

m
e
m
b
e
r
s
h
i
p

de
shown in Figs. 5, 6 respectively. The range of each
membership function is decided by the previous
knowledge of the proposed scheme parameters. Error is
limited between -50 and 50 watts since the change in
actual power fed to the grid and the reference maximum
power has been found to be within this limit from the
open loop scheme of the proposed model.

Fig. 4. Fuzzy Logic Control Scheme

and change in firing angle is set between -45 to 45
degrees because the range of firing angle of an
inverter is 90. The reference power, variable e and
de are expressed as follows:
The peak voltage, V
mp
and peak current, I
mp
of
Fig. 6. Membership function plots de the PV
array are obtained by
V
mp
= k
1
V
oc
(11)
I
mp
= k
2
I
sc
(12)

Fig. 5. Membership function plots e

Fig.6.Membership functions for dalpha

where, k
1
, k
2
are proportional constants [13],[14].
Thus, the peak power of the PV array can be
obtained from (11) and (12). The error and change
in error during the sampling instant k are given as

e(k) = P
ref
P
act
(13)
de (k) = e(k) e(k-1) (14)
Therefore, e(k) is zero at the maximum power
point of a PV array.
B. Inference Engine
Inference engine mainly consists of two sub
blocks namely, fuzzy rule base and fuzzy
implication. The inputs which are now fuzzified are
fed to the inference engine and the rule base is then
applied; the output fuzzy sets are then identified
using fuzzy implication method. Table I shows the
rule base of fuzzy logic controller, where all the
entries of the matrix are fuzzy sets of error (e),
change in error (de) and change in firing angle
(dalpha) to the line-commutated inverter. The
consequent fuzzy region is restricted to the
minimum (MIN) of the predicate truth while
selecting output fuzzy set. The output fuzzy region
is updated by taking the maximum (MAX) of these
minimized fuzzy sets during shaping of output
fuzzy space.
C. Defuzzification
After fuzzy implication, output fuzzy region is located.
As the final desired output is a non-fuzzy value of
control, a defuzzification stage is needed. Bisector
defuzzification method is used for defuzzification in the
proposed scheme. Here, the actual value of the change in
firing angle is calculated by (15), which partitioned the
area under the aggregate fuzzy set into two equal parts as
shown in the Fig. 8.
Fig. 7. Bisector Defuzzification Method.

( ) ( )
d d
d
d d d
d
d =
0
0

(15)

TABLE I: Fuzzy associative memory for the proposed

e
nb Nm ns Zr ps pm pb
nb nb Nb nb Nb nm ns zr
nm nb Nb nb Nm ns zr ps
ns nb Nb nm Ns zr ps pm
zr nb Nm ns Zr ps pm pb
ps nm ns zr Ps pm pb pb
pm ns zr ps Pm pb pb pb
pb zr ps pm Pb pb pb pb
de
d
(d)
d
o



system .

IV. COMPUTER SIMULATION
The PV array in the proposed scheme consists of
solar PV array of 54V, 12A (three panels of 18V,
4A in series and three such cascaded arrangements
connected in parallel). The actual power fed to the
grid is compared with the reference maximum
power that can be obtained at the grid for a given
V
oc
and I
sc
. The error is calculated and accordingly
the firing angle delay to the inverter is changed in
order to deliver maximum power to the grid. Every
time the change in firing angle is added to the
previous firing angle, the thyristors will be fired
accordingly.
The model of PV array has been implemented in
PSB using an independent current source (I
sc
), a
controlled current source (I
d
), measurement blocks
and arithmetic blocks. The three-phase converter
circuit has been modeled using the power
electronic switches available in PSB. The PV
model developed is appropriately connected to the
inverter through the dc link and the output is
connected to the three-phase utility grid. The PV
array in the proposed scheme consists of three
panels each rated for 18V, 4A connected in series
and three such strings connected in parallel. The
closed loop model of the proposed scheme is
obtained. The simulation results of the controller
showing the variation of error, firing angle delay
and the active power fed to the grid with time are
shown.
It is seen that the error decreases with time and
finally reaches zero, ensuring that the error
between the maximum reference power and the
actual power fed to the grid is zero. The variation
of firing angle delay, shows that the delay angle
is increased to reach the maximum power point,
and once the error reaches zero, the delay angle
remains constant. It is seen that the time delay in
the firing of thyristor 1 after the zero crossing
detection is 6.1 ms. Hence the firing angle delay at
which the maximum power is fed to the grid is
6.4*(360/20) = 115.2.

V. CONCLUSIONS AND FURTHER RESEARCH
A simple power electronic controller for
interfacing photovoltaic arrays with the three-phase
grid through a line-commutated inverter and step-
up transformer has been developed. Simulation
studies of the closed loop scheme with Fuzzy Logic
Controller have been carried out. The fuzzy control
is an effective tool in feed back systems to track
and extract maximum power to the grid. There are
no difficulties like proportional and integral gain
adjustments. The use of SCR converter in inverter
mode has resulted in less complicated power
circuit. Further, it has the advantage of lesser
switching power loss over forced commutated
inverter with self-commutating devices such as
IGBTs and power MOSFETs. However, due to the
inverter used in the proposed scheme, certain
harmonics have been introduced in the grid current.
A three-phase capacitor bank is kept across the grid
to reduce the current harmonics induced by the
line-commutated inverter. This has improved the
grid-current waveform and hence reduced
harmonics in the three-phase grid current, thereby
decreasing the THD. The harmonic spectrum for
the grid current waveforms with and without filter
have been obtained to prove that the introduction of
capacitor filter across the grid has eliminated the
lower order harmonics to a great extent, thus
bringing down the THD to within 10%.
REFERENCES
[1] Takashi Hiyama, Shinichi Kouzuma, Tomofui
Imakubo, Evaluation of Neural Network Based
Real Time Maximum Power Tracking Controller
For PV system, IEEE Transactions on Energy
Conversion, Vol. 10, No.3, September 1995.
Table II: Comparative simulation results
Parameters Simulation Results
Firing angle at which
maximum power
occurs,
115.6
DC link voltage, V
dc
(
V)
-31.3
DC link current, I
dc
( A) 6.4
Grid current, I
rms
( A) 4.44
Active power fed to the
grid, P
grid
( W)
-128.4


[2] T. Ohnishi, S. Takata, Comparisons of Maximum
Power Tracking Strategy of Solar Cell Output and
Control Characteristics Using Step Up/Down
Chopper Circuit, Trans. IEEJ, 112-D, 3, 250/257
(1992).
[3] O. Wasynczuk, Dynamic behavior of a class of
photovoltaic power systems, IEEE Trans. Power
App. Syst.., Vol. PAS-102, pp. 30313037,
Sept. 1983.
[4] E. Koutroulis, K. Kalaitzakis, N.C.
Voulgaris,Development of a Microcontroller
Based, Photovoltaic Maximum Power Point
Tracking Control System, IEEE Transactions on
Power Electronics, Vol. 16, No.1, pp. 46-54,
January 2001.
[5] K.H. Hussein, I. Muta, Maximum Photovoltaic
Power Tracking: An Algorithm for Rapidly
Changing Atmospheric Conditions, IEEE
Proceedings on Generation, Transmission, and
Distribution, Vol. 142, No.1, pp. 59-64, January
1995.
[6] T. Noguchi, S. Togashi, R. Nakamoto, Short-
Current Pulse-Based Adaptive Maximum-Power-
Point Tracking for a Photovoltaic Power Generation
System, Electrical Engineering in Japan, Vol. 139,
No.1, pp. 65-72, 2002.
[7] J.H.R .Enslin, M.S. Wolf, D.B. Snyman, W.
Swiegers, Integrated Photovoltaic Maximum
Power Point Tracking Converter, IEEE
Transactions on Industrial Electronics, Vol.44,
No.6, pp. 769-773, December 1997.
[8] T.J. Liang, Y.C. Kou, J.R. Chen, Single-Stage
Photovoltaic Energy Conversion System, IEE
Proceedings on Electrical Power Application,
Vol.148, No.4, pp. 339-344, July 2001.
[9] J. M. Chang, W. N. Chang, S. J. Chiang, Single-
Phase Grid- Connected using Three-Arm
Rectifier-Inverter, IEEE Transactions on
Aerospace and Electronic Systems, Vol. 42, No. 1,
pp. 211-219, January 2006.
[10] M. Veerachary, T. Senjyu, K. Uezato,
Feedforward Maximum Power Point Tracking of
PV Systems using Fuzzy Controller, IEEE
Transactions on Aerospace and Electronic Systems,
Vol. 38, No. 3, pp. 969981,July 2002.
[11] C.Y. Won, D.H. Kim, S.C. Kim, W.S. Kim, H.S.
Kim, A new maximum power point tracker of
photovoltaic arrays using fuzzy controller,
Proceedings of PESC, pp. 396-403, 1994.
[12] S. Arul Daniel, N. Ammasai Gounden, A Novel
Hybrid Isolated Generating System Based on PV
Fed Inverter-Assisted Wind-Driven Induction
Generators, IEEE Transactions on energy
conversion, Vol. 19, No. 2, pp. 416-422, June
2004.
[13] Dong-Yun Lee, Hyeong-Ju Noh, Dong-Seok Hyun,
Ick Choy, An Improved MPPT converter Using
Current Compensation Method for Small Scaled
PV-Applications, IEEE Conference, 2003, Vol. 3,
pp. 540-545.
[14] S. Yuvarajan, Shanguang Xu, Photo-Voltaic Power
Converter with a Simple Maximum-Power-Point-
Tracker, IEEE conference, 2003, Vol. 3, pp. 399-
402.



Enhancement of Managing Load of PV System with Grid
Tied Inverter Using MPPT Estimate PERTURB
PERTURB Method

VIVEK.A
1
,JENSEN FERNANDO
2
1,2
St. Josephs college of engineering,Chennai,INDIA

ABSTRACT
The present energy scenario needs to be
developed using renewable energy sources to
avoid pollution free air and to keep the natural
resources for some more extend. According to
our scheme, an optimized design of grid-tied PV
system without storage is proposed which is
suitable for Industries as it requires less
installment cost. Higher PV system power
output can be withdrawn with the help of
implementing MPPT estimate perturb perturb
algorithm. This project is trying to propose an
optimized scheme which would be suitable to
demonstrate how the grid-tied PV systems can
be organized with an efficient use of solar
energy. One of the main objectives of the project
is to reduce the Electricity Tariff and to reduce
the usage of fuel for power production in order
to avoid the future demand, this project
proposes an optimized design of grid-tied PV
system without storage. Use of solar energy in
industries is never been tried widely due to
technical inconvenience, and high installment
cost and this project is that to mitigate these
problems (mainly for heavy load areas).

I. INTRODUCTION TO THE
ENERGY SCENARIO

Solar energy is the real and unpolluted energy
forever. Demand of electrical energy and less
availability of present resources. In our project, we
would like to improve the present solar collector
system to produce more electrical power.
According to our system, our time investment will
lead good payback. Before investigating the solar
power, we would like to look the energy scenario
of India till 2006

1.1 MAJOR POWER GENERATION

a) Thermal-64.4% b) Atomic-2.7% c)
Renewable-4.9% d) Hydro -26%
In the power production scenario, solar power
doesnt play any role and not contributing even

1%.But India is the country, where sunlight
intensity is very high and thats the main natural
resource also [1]. To keep the above in mind, we
would like to develop an efficient power collection
and advanced intelligent charging system for solar
based power generation. The main drawbacks of
PV systems are high fabrication cost and low
conversion efficiency, which are partly caused by
their nonlinear and temperature dependent V-I and
P-I characteristics. To overcome these problems,
the maximum power operating point of the PV
system is tracked using online or offline algorithms
and the system operating point is forced toward this
optimal condition.

2. MAXIMUM POWER POINT
TRACKING

Maximum Power Point Tracking (MPPT) is used
in photovoltaic (PV) systems to continuously tune
the system, so that it draws maximum power from
the solar array irrespective of weather or load
conditions [2-3]. The problem of nonlinear and
temperature dependent V-I and P-I characteristics
are solved with the help of MPPT is depicted in fig
1. Many maximum power point tracking techniques
have been proposed and implemented [4]. They are
categorized as follows
Perturbation & Observation (P&O)
method
Modified Perturbation & Observation
method
Estimate perturbation & perturbation
(EPP) method



Fig 1 - Typical PV module I-V and P-V characteristics
A MPPT tracks the maximum power
point, which is going to be different from the STC
(Standard Test Conditions) rating under almost all
situations. Under very cold conditions a 75 watt
panel is actually capable of putting over 80 watts
because the output goes up as temperature goes
down. On the other hand under very hot conditions,
the power drops and the power lost as the
temperature goes up. MPPT are most effective
under these conditions: Winter, and/or cloudy or
hazy days - when the extra power is needed. Cold
weather - solar panels work better at cold
temperatures, but without a maximum power
tracker you are losing most of that. Cold weather is
most likely in winter - the time when sun hours are
low and you need the power the most.

2.1 MPPT TECHNIQUE
PERTURBATION & OBSERVATION
(P&O) METHOD

The P&O algorithm is also called hill-climbing,
but both names refer to the same algorithm
depending on how it is implemented. Hill-climbing
involves a perturbation on the duty cycle of the
power converter and P&O a perturbation in the
operating voltage of the DC link between the PV
array and the power converter .Based on this, EPP
has been developed.
2.2 PROPOSED SYSTEM ESTIMATE
PERTURBATION & PERTURBATION (EPP)
METHOD
A MPPT system has been developed, consisting
of a boost type Dc - Dc converter, which is
controlled by a microcontroller-based unit. The
main difference between the method used in the
proposed MAXIMUM PPT system and other
techniques used in the past is that the PV array
output power is used to directly control the dc/dc
Converter, thus reducing the complexity of the
system. The resulting system has high-efficiency,
lower-cost. The results show that the use of the
proposed MPPT control increases the PV output
power by as much as 15%.A microcontroller is
used to measure the PV array output power and to
change the duty cycle of the dc/dc converter control
signal. By measuring the array voltage and current,
the PV array output power is calculated and
compared to the previous PV array output power.
Comparing with the MP&O algorithm, the EPP
algorithm has a tracking speed of 1.5 times faster
but has the same delay time

Fig-2: EPP method

Between the estimate process and the perturb
process. In each iteration, the dc/dc converter input
voltage and current are measured and the input
power is calculated. The input power is compared
to its value calculated in the previous iteration and
according to the result of the comparison; the duty
cycle of PWM is either incremented, decremented
or remains unchanged. The MPPT process is shown
in fig-2 the starting points vary, depending on the
atmospheric conditions, while the duty cycle is
changed continuously, according to the above-
mentioned algorithm, resulting in the system steady
www.ijrde.com


state operation around the maximum power point.
The main supply voltage is monitored continuously
and, if it exceeds or decrease certain level, the
synchronizing operation is stopped in orde
prevent damage to the grid. The PV array output
fed to the inverter can be maximized using MPPT
control system. This EPP method is more reliable
than the systems in which the converter duty
cycle is arranged such that the maximum
power is supplied to load.

3 .BASIC BLOCK DIAGRAM FOR THE
WHOLE SYSTEM

fig -3: Block diagram

3.1 GRID TIED INVERTER:
A grid-tie inverter (GTI) or
inverter is a special type of power inverter
converts direct
current (DC) electricity into alternating
current (AC) and feeds it into an existing electrical
grid. GTIs are often used to convert direct current
produced by many renewable energy sources, such
as solar panels or small wind turbines,
alternating current used to power homes and
state operation around the maximum power point.
The main supply voltage is monitored continuously
and, if it exceeds or decrease certain level, the
stopped in order to
The PV array output
fed to the inverter can be maximized using MPPT
control system. This EPP method is more reliable
converter duty
cycle is arranged such that the maximum
FOR THE
synchronous
power inverter that
alternating
(AC) and feeds it into an existing electrical
grid. GTIs are often used to convert direct current
produced by many renewable energy sources, such
wind turbines, into the
d to power homes and
businesses. Fig 3- denotes the block diagram for
GTI. The technical name for a grid
"grid-interactive inverter". Grid
inverters typically cannot be used in standalone
applications where utility power is
During a period of overproduction from
the generating source, power is routed into the
power grid, thereby being sold to the local power
company. During insufficient power production, it
allows for power to be purchased from the power
company. The circuit for proposed system is shown
in fig 4
fig-4 : circuit for the proposed system

3.2 SYNCHRONIZATION IN GRID TIED
INVERTER
Synchronization is the process of
the produced power with the grid power
be done by changing the voltage, frequency
and phase angle of the produced power
according to the grid power. This can be done
by writing coding in the PIC controller
are two types of synchronization.
Normal synchronization and accu
synchronization.

sue: pp- 191-196
193 | P a g e
denotes the block diagram for
The technical name for a grid-tie inverter is
interactive inverter". Grid-interactive
inverters typically cannot be used in standalone
applications where utility power is not available.
During a period of overproduction from
source, power is routed into the
power grid, thereby being sold to the local power
company. During insufficient power production, it
allows for power to be purchased from the power
The circuit for proposed system is shown

circuit for the proposed system
ONIZATION IN GRID TIED
Synchronization is the process of combining
produced power with the grid power. It can
be done by changing the voltage, frequency
and phase angle of the produced power
according to the grid power. This can be done
by writing coding in the PIC controller. There
synchronization. They are
Normal synchronization and accurate


fig-5 : synchronization representation
3.2.1 NORMAL SYNCHRONIZATION
It is the easy way of synchronizing the grid power
with the produced power. It will treat the grid
voltage, frequency are constant and changes can be
done to the produced power according to the
constant value. This type of open loop
synchronization is only of small load systems
alone.

3.2.2 ACCURATE SYNCHRONIZATION
It is a tedious way of synchronizing the grid
power with the produced power. It is the closed
loop system which checks the voltage, frequency
and phase angle and changes can be done to the
produced power frequently. This can be included
for both large as well as small systems Frequency F
1, voltage V 1, Phase angle P 1 (PV) &
Frequency F 2, voltage V 2, Phase angle P 2
(Grid) Microcontroller collects the data from the
grid and the PV systems and give the signal to the
inverter. Inverter will change the voltage,
frequency, phase angle of the produced energy in
the PV system according to the grids voltage,
frequency, phase angle
If V 1 = V 2, F 1 = F 2, P 1 = P 2, then
synchronization will occur and the produced power
can easily mingle with the grid power.

4. OPERATION

There are three separate sections. They are
4.1 PV SECTION:
Solar energy is converted into electrical energy
using solar cells in PV array. The produced voltage
depends on the PV array sizing and rating.
Generated energy is send to a collection of boost
converters which are connected in series. This
boost converter is operated at different levels which
are controlled by a microcontroller. This comprises
the MPPT EPP function. The coding of the MPPT
EPP algorithm is dumped into the microcontroller
which gets the PV voltage data and switches the
boost converter correspondingly. The output of the
boost converter will be a DC voltage of 24 V. The
output of the DC to DC converter and the flow
shown in fig 6.

fig-6 : PV section

4.2 LOCAL GRID
The generated AC voltage from the inverter is
given to the synchronizing circuit which also
receives the supply voltage from the local grid. If
the voltage, frequency, phase angle are equal, the
synchronizing circuit syncs the energy of both PV
and grid. If there is any change in the phase angle
and frequency in the grid, the microcontroller give
signal to the inverter to change the phase angle,
frequency of the produced energy according to the
Grid energy. If suppose the Grid voltage falls
below certain level or zero, the total system shuts
down automatically. This is a safety measure
because there is a possibility of power exporting
from the PV system to the grid, this may affect the
line workers working in the grid. Thus this inverter
provides a safety islanding scheme. The connection
to the local grid is shown in the fig 7

www.ijrde.com


fig-7: connection to local grid

4.3 DIESEL GENERATOR:
The main disadvantage of the system is that
if there is a power cut, total system does not
work and the energy is being generated is
wasted. In order to overcome this
disadvantage, a diesel generator is connected
to a system. Since many industries already
have a diesel generator, it requires a bus bar to
tie DG with PV system either manually or
automatically. This also have an advantage
that, since the grid is disconnected from the
PV system and Diesel generator there will be
no exporting of power to the grid.

5. SIMULATION CIRCUIT

to local grid
The main disadvantage of the system is that
if there is a power cut, total system does not
work and the energy is being generated is
wasted. In order to overcome this
a diesel generator is connected
Since many industries already
have a diesel generator, it requires a bus bar to
with PV system either manually or
also have an advantage
disconnected from the
PV system and Diesel generator there will be
SIMULATION CIRCUITS
Fig 8:Circuit of PV system
6. SIMULATION RESULTS:
Fig 9: PV Voltage

Fig 10: Grid Voltage

sue: pp- 191-196
195 | P a g e
Fig 8:Circuit of PV system
6. SIMULATION RESULTS:

Fig 10: Grid Voltage


The variation of V ,I ,P,T, Light in the PV system
is shown below: (using VB)

Fig 11: PV data graph

CONCLUSION
This grid-tied system enables a home owner to
use an alternative generation from solar energy. If
the alternative power being produced is inadequate,
the deficit will be sourced from the electricity grid.
If the grid power is not available, still the system
will continue to supply critical on-site loads. A
typical solar system would require a large bank of
batteries to store the energy. This represented a
huge investment for the industries before they
could build a functional alternative energy system.
By removing the need for an expensive battery
pack and replacing the large, expensive grid-tied
inverters with smaller, cheaper units that dont need
batteries .Also a new MPPT algorithm called
Estimate Perturb Perturb is proposed in order to
achieve effective tracking of solar energy.

FUTURE SCOPE
Space Based Solar Power Generation is the
latest research topic and if the project is properly
worked out, this project may help to synchronize
the produced energy with the grid energy which
may satisfy the load demand. If the system is
implemented in residential areas, this will reduce
the present Load demand and there is a possibility
of sending the extra generated energy to the grid
and thereby reducing the usage of nonrenewable
resources in order to save that for future generation

REFERENCE:
[1] Bangladesh Energy Crisis: Soul Searching, Energy
Bangladesh, June, 2009.
[2] Islam Sharif Renewable energy development in
Bangladesh, Executive Exchange on the use and
integration of Renewable Energy in the Power Sector,
Madrid, Spain, October 19-23, 2003
[3] Bangladesh Renewable Energy Report, APCTT-
UNESCAP
[4] Islam Sharif Renewable energy development in
Bangladesh, Executive Exchange on the use and
integration of Renewable Energy in the Power Sector,
Madrid, Spain, October 19-23, 2009



Harmonic Reduction in Wind Energy by Using Multi
Pulse Converter
1
G.Selvalakshmi,
2
D.Ramya Devi,
3
V.Chitra,
4
P.Manikandan

1,2,3
UG EEE FINAL YEAR,
4
Assistant Professor & Head of EEE
Sree Sowdambika College Of Engineering Chettikurichi 626115,Virudhunagar Dist, Tamilnadu, India.

ABSTRACT
Todays world carries many power quality
problems in power system areas. Especially, wind
power plants introduce a great number of non-
linear power electronic devices. A large number of
non-linear power electronic devices can have
significant effect on the harmonic emissions. These
harmonics can become serious threat to the power
quality. So this paper handles the reduction of
harmonics in wind energy. For that, many
techniques are used. Here, multi pulse technique is
used to decrease the Total Harmonic Distortion
(THD) level from both converter and wind energy.
6 and 12 pulse converter have been designed and
simulated in MATLAB/SIMULINK software. By
increasing the number of pulses, the level of
harmonic is reduced. Only one set of controlled
converter has been employed for generating multi
pulses. Switching losses also get reduced through
this operation.

I. INTRODUCTION
The number of wind power plants (WPP) increases
world widely and the nominal power of an average
wind power plant increases. In many countries
wind power has already taken an important part in
the electrical energy production mix. Due to the
importance of wind power, the manufacturers and
transmission system operators (TSO) cannot ignore
the effects of wind power plants on the power
quality and power system stability. Wind power
plants introduce a great number of non-linear
power electronic devices. A large number of non-
linear power electronic devices include an effect of
harmonic emissions [5]. For that, the reduction of
harmonics there are many techniques are used like
filtering and cancellation [3],[4]. So it becomes
harmful to the power quality. That is why harmonic
analysis is developed and taken as an integrated
part of wind power plant design. Because every
power network is unique and has different
characteristics, the effect of the harmonics on every
power system varies. Even if the percentage of the
harmonics seemed small, the harmonic emission
becomes a significant issue when the capacity of a
wind power plant is hundreds of megawatts.
Harmonics are sinusoidal voltages and currents
with frequency multiply integer of the fundamental
frequency that is 50 or 60 Hz in a typical power
system. This can be expressed mathematically as

f
h
= h.f
Where,
h= order of the harmonic (h=1, 2, 3,n),
f= fundamental frequency (harmonic of the
order 1 refers to the fundamental frequency)
f
h
= frequency of the harmonic

In harmonic free power systems currents and
voltages always maintain sinusoidal form. Usually
this is not the case as there are many non-linear
power electronic devices and loads that do not
consume power in a sinusoidal form but for
example consume only some parts of the sinusoidal
current and voltage. This causes distortion in the
current and might distort the voltage waveform and
the result can be seen as harmonic currents. Non-
linear apparatus can be seen as sources of
harmonics that inject harmonic currents or voltages
into the power system. The majority of the
harmonic sources are treated as harmonic current
sources.
The performance improvement of multi-pulse
converter is achieved for Total Harmonics
Distortion (THD) in supply current, DC voltage
ripples and form factor. Pulse number is defined as
the number of pulses in the dc output voltage
within one time period of the ac source voltage. In
high-power applications, AC-DC converters based
on the concept of multi pulse, namely, 12, 18 pulses
are used to reduce the harmonics in ac supply
currents. These are named as multi pulse
converters. They use either a diode bridge or


thyristor bridge, which is connected with special
arrangement of zigzag transformer. This zigzag
transformer also reduces second harmonics. All the
simulations have been done for similar ratings of
RL Load, for all the multi-pulse converters
configurations, so as to represent a fair comparison
among controlled continuations of multi-pulse
converters. The presented simulation results show
the reduced THD at supply side.

MULTI PULSE METHODS
Multi-pulse methods involve multiple converters
connected so that the harmonics generated by one
converter are cancelled by harmonics produced by
other converters. By this means, certain harmonics
related to number of converters are eliminated from
the power source. In multi-pulse converters,
reduction of AC input line current harmonics is
important as regards to the impact the converter has
on the power system[6].
The Multi pulse Converter theory deals with the
reduction of harmonics present on the source side.
This theory involves with the phase shifting of the
input voltage and thereby breaking the input
voltage into number of pulses [1]. As the pulse
number increases, the harmonics present in the
input decreases and the Total Harmonic Distortion
(THD) reduces.
Multi pulse methods are characterized
by the use of multiple converters or
multiple semiconductor devices with a
common load. Fig 1 show various
techniques used widely for the reduction
of harmonics [8].

Harmonic reduction
Technique

Multi pulse

Filters

PWM
rectifier

converter

Active Passive

Six Twelve Eighteen
Twenty
four Thirty

Figure 1. Various Harmonic Reduction Techniques

The term multi-pulse method is not
defined precisely. In principle, it could be
imagined to be simply more than one pulse.
However, by proper usage in the power
electronics industry, it has come to mean
converters operating in a three phase system
providing more than six pulse of DC per cycle.
Multi-pulse systems result in two major
accomplishments namely,
1. Reduction of ac input line
current harmonics.

2. Reduction of DC output voltage ripple.
Reduction of ac input line current
harmonics is important as regards the
impact the converter has on the power
system[7].
Multi-pulse methods are characterized by the use of
multiple converters or multiple semiconductor
devices with a common load [2].
Phase shifting transformers are an essential
ingredient and provide the mechanism for
cancellation of harmonic current pairs, e.g. the 5th
and 7th harmonics or the 11th and 13th so on. Thus
for harmonic current reduction the multi- pulse
converters are fed from phase shifting transformers.
The phase shift has to be appropriate.

THREE PHASE CIRCUIT BREAKER:
The Three-Phase Breaker block implements a
three-phase circuit breaker where the opening and
closing times can be controlled either from an
external Simulink signal (external control mode), or
from an internal control timer (internal control
mode).
The Three-Phase Breaker block uses three Breaker
blocks connected between the inputs and the
outputs of the block. You can use this block in
series with the three-phase element you want to
switch. See the Breaker block reference pages for
details on the modeling of the single-phase
breakers.
If the Three-Phase Breaker block is set in external
www.ijrde.com


control mode, a control input appears in the block
icon. The control signal connected to this input
must be either 0 or 1, 0 to open the breakers, 1 to
close them. If the Three-Phase Breaker block is set
in internal control mode, the switching times are
specified in the dialog box of the block. The three
individual breakers are controlled with the same
signal.

Figure 2: Three phase breaker
CIRCUIT DIAGRAM OF CONTROLLED
TWELVE PULSE CONVERTER

Figure 3: Circuit diagram for 12 pulse

SIMULATION OF CONTROLLED MULTI
PULSE CONVERTERS:

Three-phase twelve-pulse converter twelve
thyristors are connected in a bridge manner. A
three-phase supply is connected across the input
terminal of the converter. The output of this
converter is connected to the dc load. Because
thyristor are unidirectional, dc current flows only in
one direction. For generating 12 pulses per
fundamental ac cycle synchronized 12
generator is used.

Simulation Diagram

control mode, a control input appears in the block
The control signal connected to this input
must be either 0 or 1, 0 to open the breakers, 1 to
Phase Breaker block is set
in internal control mode, the switching times are
specified in the dialog box of the block. The three
ual breakers are controlled with the same
Three phase breaker
CIRCUIT DIAGRAM OF CONTROLLED
TWELVE PULSE CONVERTER
converter
SIMULATION OF CONTROLLED MULTI
pulse converter twelve
thyristors are connected in a bridge manner. A
phase supply is connected across the input
terminal of the converter. The output of this
converter is connected to the dc load. Because
nal, dc current flows only in
one direction. For generating 12 pulses per
fundamental ac cycle synchronized 12-pulse

Figure 4: Simulation of 12 pulse

Figure 5: THD Waveform

Figure 6: Voltage and current

SIMULATION DIAGRAM FOR
CONVERTER UNIT:

Figure 7: Converter unit

sue: pp- 197-200
199 | P a g e
Simulation of 12 pulse converter
THD Waveform Distortion
Voltage and current waveform
SIMULATION DIAGRAM FOR
Converter unit


Figure 8: Output voltage waveform

PULSE GENERATOR UNIT:

The Pulse Generator block generates square wave
pulses at regular intervals. The block's waveform
parameters, Amplitude, Pulse Width, Period, and
Phase delay, determine the shape of the output
waveform.The Pulse Generator (Thyristor) block
generates two pulse trains. These control a twelve-
pulse thyristor converter made of two three-phase
full-wave thyristor bridges (also called Graetz
bridges). In steady-state condition, each pulse train
consists of six equidistant square pulses with 60
degrees shift between them.

Figure 9: Pulse generator unit

CONCLUSION
The objective of the present work is to investigate
the performance of controlled multi-pulse
converters. These converters are studied in terms of
harmonic spectrum of AC supply current, Total
Harmonic Distortion, Ripple Content in AC mains.
The harmonic reduction for 12 pulse is done. Best
result of ripple factor, a harmonics reduction and
regulated output voltage is obtained using multi
pulse converter. It is concluded therefore that in
general with increase in number of pulses in multi-
pulse case the performance parameters of these
converters are remarkably improved.

REFERENCE

[1] N. Mohan, T. M. Undeland, W. P. Robbins, Power
Electronics: Converters, Applications, and Design, 3rd
Edition, 2002

[2] J. Arrillaga, Y. H. Liu, L. B. Perera, and N.

R. Watson, A current rein- jection scheme that adds
self- commutation and pulse multiplication to the
thyristor converter, IEEE Trans. Power Del., vol. 21,
no. 3, pp. 1593 1599, Jul. 2006.

[3] L. Weilin, Design and Realization of Star
Connected Autotransformer Based 24-Pulse AC-DC
Converter, International Conference on Power System
Technology, 978-1-4244-5940-7 IEEE, 2010.

[4] P. Srivastava, K. Sanjiv, Simulation of

Multi pulse AC-DC Converters for Medium Voltage
ASDs, VSRD International Journal of Electrical,
Electronics & Communications Engineering. Vol. 1,
No.10, pp. 542-554, Dec. 2011.

[5] Kalle Rauma, School of Electrical
Engineering, Aalto University, Electrical
Resonances and Harmonics in a Wind Power Plant
Thesis submitted for examination for the degree of
Master of Science in Technology Espoo, Finland 17th
February 2012.

[5] K.Srinivas, Assistant Professor, JNTUH College of
Engineering, Andhrapradesh, India. Analysis and
Implementation of Multi Pulse Converters for HVDC
System International Journal of Emerging Technology
and Advanced Engineering, (ISSN 2250-2459, Volume
2, Issue 4, April 2012).

[6].Deependra Singh, Prof. Hemant Mahala,
Prof.Paramjeet Kaur, Modeling & Simulationof
Multi-Pulse Converters for Harmonic Reduction
International Journal of Advanced Computer Research
(ISSN).Volume-2 Number-3 Issue-5 September-2012.

[7]Madhuri Saxena, Sanjeev Gupta,
Simulation of Multi pulse Converter for Harmonic
Reduction using Controlled Rectifier International
Journal of Science and Research (IJSR), India Online
ISSN: 2319-7064, Volume 2 Issue 4, April 2013.

[8] Ms.Shruti Gour, Mr.Saurabh Gupta,
Comparative Analysis of Multipulse AC-DC Converter
Using Zig- Zag Transformer IOSR Journal of
Engineering (IOSRJEN) e-ISSN: 2250-3021, p-ISSN:
2278-8719 Vol. 3, Issue 7 July, 2013.


MODELLING OF CUSTOM DEVICES FOR
REDUCING VOLTAGE SAG PROBLEMS
P.Banukutti
1
,A.R.Jothisri
2
, U.Vishnupriya
3
, P.Manikandan
4

Student
1, 2, 3,
Assistant Professor
4

Sree Sowdambika College of Engineering, Aruppukottai, TamilNadu
banu5.eee@gmail.com, jothisree014@gmail.com, vishnupriya772@gmail.com,

ABSTRACT
Power quality of gains their importances with the
introduction of sophisticated electrical gadgets .The
performances of these devices are sensitive to the
quality of input power supply. Various power quality
problems results in failure or mal operation of end
user equipments. One of major problems is voltage
sag. To solve this problem, capacitors and voltage
regulator are conventionally used .These techniques
involve inherent drawback. With the advancement of
power electronic devices these drawbacks overcome
easily .The invention of various custom power
devices such as static compensator (STATCOM)
and DVR and unified power quality conditioner
(UPQC) can be used to mitigate voltage sag. In this
work, it is proposed to mitigate voltage sag and
improve the reactive power support at the user level
by using the custom power device of DVR. Custom
power devices are the most efficient and effective
modern devices used in power distribution network.
By this we can reduce the voltage sag in the power
system.
Keywords: Dynamic Voltage Restorer (DVR),
Power Quality Problem, PI controller, voltage sag,
Voltage Source Converter.
I. INTRODUCTION
In the power sector compatible with the power
quality standards in becoming major issue for the
endeavor power distribution utilities [1]. But now a
day power quality problem is impact of the power
system. Voltage sag is one of the major power
quality problems. A voltage sag is a momentary
decrease in rms ac voltage (0.1-0.9 p.u. of the
nominal voltage), at the power frequency, of duration
from cycles to a few seconds. Voltage sag is an
eccentric issue for system performance. Voltage sag
occurred by using sensitive load, programmable logic
control and variable speed drives in the load side.
Voltage sags are most often caused by fuse, breaker
operation, motor starting and capacitor switching.
[7], [8].
This paper introduced a new approach of a FACTS
device for overcome the Voltage sag problem.
Voltage sags are one of the most occurring power
quality problems. Of course, for an industry an
outage is worse, but voltage dips occur more often
and cause severe problems and economical losses.
The most efficient mitigating device for Voltage sag
has the Dynamic Voltage Restorer (DVR). In order to
properly evaluate the contribution of FACTS devices
to system sag performance two points should be
considered: First, the installation of FACTS device
will influence the voltage sag performance of the
whole network even though the primary reason for its
installation might have been to maintain the voltage
at one particular bus. So from a system point of view,
proper evaluation of the benefits resulting from the
installation of the device could reveal a way to solve
a common problem. Second, due to often prohibitive
costs of these devices the full economic benefits
might be derived only if a larger part of the network
is considered therefore, it is important to take new
and comprehensive approach to assessment of
benefits that FACTS devices could bring to the
system in terms of voltage sag reduction [6]



Fig1.Block diagram of DVR
2. FACTS CONTROLLER
FACTs controller is a power electronic device to be
used for power flow controllability and power
transfer capability. FACTs controller is known as
custom device because it is to improve power flow
controllability and power transfer capability in the
customer side [2].
2.1. VOLTAGE SOURCE CONVERTERS (VSC)
A voltage-source converter is a power electronic
device which can generate a sinusoidal voltage with
any necessary magnitude, frequency and phase angle.
Voltage source converters are widely used in
variable-speed drives, but can also be used to
mitigate voltage dips. The VSC is used to either
totally replace the voltage or to inject the missing
voltage. The missing voltage is the difference
between the nominal voltage and the actual. The
converter is usually based on some kind of energy
storage, which supplies the converter with a DC
voltage. The solid-state electronics in converter is
then switched to get the desired output voltage.
Generally the VSC is not only used for voltage sag
mitigation, but also for other power quality issues,
e.g. flicker, fluctuation and harmonics.

3. SERIES VOLTAGE CONTROLLER
DYNAMIC VOLTAGE RESTORER, (DVR)
DVR is the series voltage control device; the primary
side is connected through the coupling transformer to
power transmission. And secondary side is connected
to the Voltage Source Converter with DC energy
storage. A voltage-source converter is power
electronic devices it can be generate a sinusoidal
voltage with any required magnitude, frequency and
phase angle [3]. The resulting voltages at the load
side are equal to the sum of the source voltage and
injected voltage from the DVR. A DC to AC inverter
regulates this voltage by sinusoidal PWM techniques.
All through normal operating condition, the DVR
injected only a small voltage to compensate for the
voltage drop of the injection transformer and device
losses. However when voltage sag occurs in
transmission system DVR to inject the voltage for
required magnitude and phase angle through injection
transformer. It is linked in series between a power
grid and a load the block diagram of DVR as shown
in fig1.The dc voltage provided by an energy storage
capacitor.

Where,

- Load Voltage.
Vse - DVR voltage.
Vs - Source Voltage.

3. DVR CONTROLLER

Voltage Sag is created by increasing load in the load
terminals as shown in fig.3. The magnitude is
compared with reference voltage (). Pulse width
modulated (PWM) control technique is applied for
inverter switching so as to produce a three phase 50
Hz sinusoidal voltage at the load terminals. [4]
Chopping frequency is in the range of a few KHz
.The MOSFET inverter is controlled with PI
controller in order to maintained in 1 p.u. voltage at
the load terminals i.e. considered as Base voltage
=1p.u.
A proportional-integral (PI) controller [5] (shown in
Fig. 2) drives the plant to be controlled with a
weighted sum of the error (difference between the
actual sensed output and desired set-point) and the
integral of that value. An advantage of a proportional
to plus integral controller is that its integral term
causes the steady-state error to be zero for a step
input. Output of the PI controller block is of the form
of an angle , which introduces additional phase-
lag/lead in the three-phase voltages. The output of
error detector is as following,

........ (2)
Where,

= + (1)


Vref equal to 1 p.u. voltage
Voltage in p.u. at the load terminals

The controller output when compared at PWM signal
Generator Results in the desired firing sequence.

Fig.2. Schematic of a typical PI Controller
The modulated angle is applied to the PWM
generators in phase A as shown in (2). The angles for
phases B and C are shifted by 120
0
and 240
0

respectively as shown in (3) and (4). In this PI
controller only voltage magnitude is taken as a
feedback parameter in the control scheme [4]. The
sinusoidal signal V control is phase-modulated by
means of the angle and the modulated three-phase
voltages are given by

Va = sin (t +) (2)

Vb= sin (t++2/3) (3)

Vc= sin (t ++4/3) (4)

4. PARAMETERS OF DVR TEST SYSTEM
Table 1. System Parameters
Electrical circuit model of DVR test system is shown
in Fig.3. System parameters are listed in Table 1.
Voltage sag is created at load terminals via a three-
phase fault as shown in Fig.3. Load voltage is sensed
and passed through a sequence analyzer. The
Magnitude is compared with reference voltage (Vref).
The testing of system Parameters are lists in Table 1.
MATLAB Simulation diagram of the test system
comprises of 230 kV, 50 Hz generator, feeding
transmission lines through a coupling transformer
connected in Y/, 120/120 kV.

Fig 5.Simulation diagram for DVR

5. SIMULATION RESULTS

Detailed simulations are performed on the DVR test
System using MATLAB/SIMULINK System
performance is analyzed for compensating voltage
sag to give with or without load. Transition time for
the fault is considered from 0.1 sec to 0.2 sec as
shown in Fig. 5. In this cases are discussed below:

Case1: In normal load condition voltage sag is not
present in the transmission network. Transition time
for the fault is considered from 0.1 sec to 0.2 sec as
S.No System
Quantities
Standards
1. Inverter
Specifications
MOSFET based,3 arms
6 Pulse,
Carrier Frequency =1050
Hz,
Sample Time= 5 s
2. Transmission
Line
Parameter
R=0.001 ohms ,L=0.005 H
3. PI Controller KP=0.5
Ki=0.0003
Sample time=10 s
4. Load-1 Active power = 2 Mw
Inductive Reactive Power
=0.2 Mvar
5. Load-2 Active power = 4 Mw
Inductive Reactive Power
=0.2 Mvar


shown in Fig 5.1. And the FFT analysis output as
shown in Fig 5.2.

Fig 5.1 Three phase voltage wave form in Normal
condition

Fig 5.2 FFT analysis in Normal condition
Case2: In adding double load in the transmission
network that condition voltage sag is present without
DVR. Transition time for the fault is considered from
0.1 sec to 0.2 sec as shown in Fig 5.3. And the FFT
analysis output as shown in Fig 5.4.

Fig 5.3 Three phase voltage wave form without DVR

Fig 5.4 FFT analysis without DVR
Case3: In adding double load in the transmission
network that condition voltage sag is present without


DVR. Transition time for the fault is considered from
0.1 sec to 0.2 sec as shown in Fig 5.5.And the FFT
analysis output as shown in Fig 5.6.

Fig 5.5 Three phase voltage waveform with DVR

Fig 5.6 FFT analysis with DVR
6. THD COMPARISON

By increasing the no of cycles but harmonics will get
reduced. Instead of using more number of cycles only
three cycles are used here as following Table 5.1

TABLE 2. THD COMPARISION UNDER
DIFFERENT CYCLE

7. CONCLUSION

In this paper presented the power quality problems
such as voltage sag mitigated by using DVR. DVR is
proposed to eliminate voltage sag Problems. DVR
effectively improves the power quality in
transmission network. It has lower cost, smaller size,
and fast dynamic response to the disturbance. The
objective of this work is to study the performance of
DVR and improve the power quality in transmission
network. THD comparisons of different cycles are
also carried out during normal condition and voltage
condition. So it can be concluded that DVR
effectively improve the power quality in transmission
network.

REFERENCES

S.NO NO OF
CYCLES
THD WITH
OUT DVR
THD WITH
DVR
1. 3 3.12% 0.92%
2. 4 2.75% 0.82%
3 5 2.49% 0.75%


[1] R.Mohan Mathur, Rajiv K.Varma, "Thyristor-
Based FACTS controllers For electrical Transmission
system. New Delhi Widely student EditionIEEE press
on P ower Engineering (2013).

[2] A.Elnady Magdy M.A.salama,fellow, unified
apporach For mitigation Voltage sag and voltage
flicker Using the D-STATCOM. vol.20,no.2, April 2005.

[3] S. V. Ravi Kumar, S. Siva Nagaraju, Simulation
of D-Statcom and DVR In Power system ARPN journal
of Engineering for Applied science vol.2, No.2, June 2007

[4] H.P.Tiwari and Sunil Kumar kuptar DVR
against voltage sag, International journal of innovation,
Management and Technology, vol.1, No.3, Aug 2010.

[5] S.Ezhilarasan, G.Balasubramani, DVR for
voltage sag Mitigation Using pi with fuzzy logic controller
Internal Journal of Engineering Research Application
(IJERA) Vol.3,issue1,January,2013.

[6] Jovica V.Milanovic, fellow, IEEE And
Yanzhang, modeling of facts Devices for voltage sag
mitigation Studies in large power systems IEEE
Transaction power delivery Vol.25, No.4, October 2010

-[7] E. E. El-Araby, N. Yorino and H. Sasaki,A
comprehensive approach FACTs devices optimal
allocation For to mitigate voltage collapse, presented
at the IEEE Power Eng. Soc. Transmission and
Distribution conf. Exhibit: Asia Pacific Yokohama,
Japan, Oct. 6-10-2002, CD-ROM.

[8] M. H. Haque, Compensation of Distribution
voltage sag by DVR And D-STATCOM, presented at
the EEE Porto Power Tech, Porto, Portugal, Sep. 10-13-
2001, CD- ROM.



MICROCONTROLLER BASED ECONOMIC ROOM
ACCESS SYSTEM
1
Bhuvana.K,
2
Jeevitha.D,
3
Umasankari.R,
4
Sasithar.J
1, 2, 3
Dept. of EEE, Ganadipathy Tulsis Jain Engineering College, Kaniyambadi, Vellore

ABSTRACT
Security is gaining awareness and importance in
recent years. And the access control system form
a vital link in the security chain at present there
are many security system available in the
market but the paper proposed here is an
economical electronic system. The consumption
of low operating power, flexible and user
friendly mechanical designs are the merits of
this project the paper presents the technology of
authorized access system by using 89c51
microcontroller and it has an added advantage
of having more than one passwords for entering
into the building.
KEYWORDS- DC Motor, Keypad, LCD
Display, 89c51 Microcontroller, Relay,
Security system
1. INTRODUCTION
Security includes several areas such as personal
security, organizational security and among others.
Security access control is an important aspect of
any system.it is act of ensuring that an
authenticated user accesses only what they are
authorized to and no more. Nearly all application
that deal with financial, privacy, or defence include
some form of access control .Access control is
concerned with determining the allowed activities
of legitimate uses mediating every attempt by a
user to access a resource in the system [1-6].
Nowadays, locks and key are not enough to keep an
environment secure against unwanted or
uncontrolled visitors. To have access mechanical
security system are widely used such system purely
mechanical can be easily defrauded. This paper
presents an access control system that uses keypad
technology.
These functionalities of the design are being able
to:
Give the facility multiple access system an
administrator and 5 users. (user s number can
be extended depending on the size of the used
EEPROM)
The user is able to access only the system
Visualized all functionalities provided using
LCD
2. CIRCUIT DIAGRAM
The system uses a compact circuitry built around
microcontroller ATmel89C51 is low power C-
MOS 8 bit microcontroller it provides following
feature: compatible with MCS-51 product 4k byte
of in system reprogrammable flash memory 32
programmable input output lines working register,
two 16bit timer and counter with compare modes
and internal and external interrupts.
The 89C51 reset pin receive a resister to
ground and an electrolytic capacitors connected to
VCC .at the power up the capacitor discharge ,so
current flows from ground to VCC via the resister


and the capacitor, until it charge the capacitor [7-8].
The CMOS version doesnt need the resistor. If you
want to install reset button, just install the switch
in parallel to the capacitor, so when pressing the
key it will apply VCC to the reset pin also
discharging the capacitor. When reading the code
memory in case of EPROM the 89C51 breaks the
16bit address in twobytes of 8bit each higher order
bits are posted at pore P2 bits while lower order
8bits rae posted at port P0 bits.the 8051 then pulses
up the pin ALE (30)to signal the external circuit
that the address us available at the output of P0 and
P2.
The 8051 pulses down PSEN pin 29 to get the
program byte stored at the EPROM. this PSEN low
level pulse goes directly in to the/ CE. EPROM pin
20 selects the EPROM chip. The output enable(OE
pin22) allows the EPROM to output byte addressed
at pin 11-19. The 8051 reads external code memory
whenever the EA (pin 31)is connected to ground,
even if the 8051 memory has internal
ROM/EPROM. To execute the code stored into the
internal ROM/EPROM the EA pin must be
connected to +5Vdc(high level)
EEPROM: the memory is an electrically erasable
programmable read only memory fabricated with
high endurance single polysilicon CMOS
technology which guarantees an endurance
typically well above one million erase/write cycles
with data .the single supply voltage 4.5v to 5.5v .
The variable resistor connected at LCD pin 3 and
ground, controls LCD display contrast. LCD with
extended temperature range can need a negative
voltage at the VD pin3. When you apply a resistor
or variable resistor to VD a small current flows
through and a voltage develops over a resistor,
normally this voltages small during 0 and 1 volt.
The crystal connected at 89c51 pins 18 &19 need
the capacitor (33pf) connected to ground. Several
89c51 works well without capacitors but some of
them have intermittent no START or STOP
oscillation problem to avoid problems just install a
capacitors.
The 230v,50Hz AC mains step down by
transformer to deliver secondary output of 12v
,500MA.the transformer output is rectified by a full
wave bridge rectifier comprising diodeD1 through
D4 filtered by capacitor and regulated by IC 7805
used to maintain constant output voltage. LED
glows when the power is ON and the resistor act as
current limiter. A numeric keypad for password
entry is connected to the microcontroller. The
keypad is also used for password change and
application of master password when required [9-
11]. Due to the high speed of microcontroller, the
states of different keys is checked in less than
100ms and a key are pressed manually by the users,
this delay of 100 ms is not noticeable. The net
result is that you save I/O pins of the
microcontroller.
Relay is an electrical switch that uses an
electromagnet to move the switch from the OFF
and ON position instead of person moving the
switch. Relay come in different configuration
SPST, SPDT, DPST, DPDT here we are using
SPDT switch. Single pole double through has three
contact common (com) normally open (NO)
normally close (NC).the normally closed contact
will be connected to a common contact when no
power is applied to the coil. The normally open
contact will be open(not connect).when no power is
applied to the coil.
When a persons wants to enters the room, he
enters the password if the password matches
successfully the relay will operate gate is unlocked,
if the password is wrong means the relay will not
operate.
OUTPUT RESULTS:


During execution of the proposed circuit at first it
displays welcome and in further asks the user to
enter the password as shown in fig3.

Fig3.Password Entry screen
Once the user entered the password if matched it
allows the user to enter into the room if not LCD
displays it as Invalid password and it is tested with
the compiler. Those results have been shown in
Fig4. & Fig 5.

Fig4.Entering The Password

Fig 5. Door opening Authenticated

CONCLUSION
This paper has successfully presented a
functional, low cost and low complexity
microcontroller based room access control system.
A real-life equivalent of the prototype can be
developed with minimal development costs and
with relatively low operational costs for
environment where high degrees of security are
required like banks, military research areas, and big
private investment companies. It has the special
feature of keeping more than one entry passwords.
So for more than one reliable authorities can access
the system with their personalized passwords.
REFERENCES
[1]. E. Yavuz, B. Hasan, I. Serkan and K. Duygu. Safe
and Secure PIC Based Remote Control Application
for Intelligent Home. International Journal of
Computer Science and Network Security, Vol. 7,
No. 5, May 20.
[2]. http://research.microsoft.com/enus/
projects/homeos/
[3]. David Ritter, Bernhard Isler, Hans-Joachim Mundt
and Stephen Treado, Access Control In BACnet,
American Society of Heating, Refrigerating and
Air-Conditioning Engineers(ASHRAE), Journal
Vol. 48, Nov. 2006.
[4] Popa, M.; Popa, A.S.; Marcu, M.; A distributed
smart card based access control system, 8
th

International Symposium on Intelligent Systems
and Informatics (SISY), 2010, pp: 341 346.
[5] LCD MODULE 4x20 - 3.73mm, 21 January 2012,
[online]. Available: http://www.lcdmodule.
de/eng/pdf/doma/dip204-4e.pdf
[6] Inderpreet Kaur, Microcontroller Based Home
Automation System With Security, International
Journal of Advanced Computer Science and
Applications (IJACSA), Vol. 1, No. 6, December


2010, pp: 60-65.
[7] Shiwani Saini,C.R.Suri, Design and Development
of Microcontroller Based Auto-Flow Assembly for
Biosensor Application, International Journal of
Computer Applications (0975 8887) Volume 6
No.1, September 2010.
[8] S. A. Hari Prasadi, B. S. Kariyappa, R. Nagaraj, S.
K.Thakur, Micro Controller Based Ac Power
Controller, Wireless Sensor Network, 2009, 2, 61-
121 by Scientific Research, pp:76-81.
[9] Magnetic locks, 24 March 2012, [online] Available:
http://www.doorentryonline.co.uk/acatalog/Magnet
ic_locks.html
[10] White papers: Magnetic locks, 20 March, 2012,
[online]
Available:http://www.sdcsecurity.com/docs/eblasts
/whitepapers_emlo ks.pdf
[11] Magnetic Locks Holding Force Security &
Application,
[online],Available:http://sdcsecurity.wordpress.co
m/2009/04/05/magnetic-locks-holding-
forcesecurity- application/
[12] Bart Huyskens, An Introduction To
Microcontroller Programming V1.0.



Reducing Power in Reconfigurable Processors
Using Dual V
DD

1
S.A.Raja Ram,
2
Mr.D.Jerish Solomon,

1
PG Student, Nehru Institute of Technology, Coimbatore.
2
Assis.Prof.of ECE Department, Nehru Institute of Technology, Coimbatore.

ABSTRACT
Power optimization is very important for
FPGAs in nanometer technologies. The dual V
DD

technique has already been implemented in
reconfigurable processors to improve energy
efficiency. In dual V
DD
technique configurable
power supply is required to obtain a satisfactory
performance and power tradeoff. In this paper,
a flexible or variable dual V
DD
method is used to
reduce the power consumption by varying the
level of lower V
DDL
according to the applications
on a processor. This method finds out the
optimum V
DDL
based on the utilization times of
all arithmetic and logic unit operations. In this
method we use storage elements as latches
instead of registers. This will again reduce some
amount of power. Compared to single V
DD

FPGAs, configurable dual V
DD
FPGAs will
achieve more power reduction.

Index Terms Low power, power gating,
programmable dual V
DD
, reconfigurable
processor (RP), variable dual V
DD
.
I. INTRODUCTION
A Reconfigurable Processor is a microprocessor
with erasable hardware that can rewire itself
dynamically. This allows the chip to adapt
successfully to the programming tasks demanded
by the particular software they are interfacing with
at any given time. Power consumption is an
important factor in embedded system design. Now
a days power consumption becomes more
important for integrated circuit (IC) design. Since
the threshold voltage is restricted by leakage, the
power needed to switch each transistor has not
decreased. FPGAs have a much lower power
efficiency than ASICs since they use more number
of transistors.
Reconfigurable processors are more energy
efficient when compared to general purpose
processors. However its energy efficiency is still lower
than the application -specified IC implementing the
same function [2] since some runtime redundant
circuits are designed to make it flexible. The dual V
DD

technique was already been implemented to increase
the energy efficiency of RP. This technique examine
the slack time between different operations to reduce
power consumption by executing the faster operations
on lower voltage [3], [4]. The supply voltage levels are
fixed, heedless of software. Though, the optimum
level of V
DDL
varies with different applications.

Fig. 1. Architecture of RPU
This paper proposes a power optimization
method called flexible dual V
DD
for the
conventional dual V
DD
RP [3], [4].This method
adapts its V
DDL
for the current application based on
the ALU operations used by it. If the faster
operations are used more oftenly, the optimum
V
DDL
could be lowered. In this varying dual V
DD

method, we use latches as storage elements instead
of the registers which again lead to the power
reduction. In this scheme we apply V
DDH
to logic
on critical paths and V
DDL
to logic on non-critical
paths. A higher supply voltage leads to a higher
performance but larger power.


The rest of this paper is ordered as
follows. Section 2 describes the architecture of the
RPU. Section 3 examines the power and delay of
all its components. Section 4 analyzes the proposed
method in detail. The result of the experiment is
discussed in section 5. Section 6 concludes this
method.
II. ARCHITECTURAL DESCRIPTION
The study of this method is based on the RPU
as shown in fig. 1. Alike to many previous RPs [5],
[6], it contains three main components: an 8 x 8
coarse grained RCA, a 9 k bit data FIFO whose
data width is 256 bits, and a 160 kb configuration
memories whose data width is 1024 bits. The
configuration of the RC is depicted in the right part
of fig.1, containing three-input two-output 16-bit
ALU, the input and output registers and some local
registers.
A. Coarse Grained Reconfigurable Cell:
While the initial systems for reconfigurable
computation featured fine grained FPGAs, it was
soon revealed, that FPGAs stand different
disadvantages for computational tasks. Initially,
due to the bit-level operations, operators for wide
data paths have to be collected of several (bit-level)
processing units. This includes classically a large
routing overhead for the interconnect between
these units and leads to a low silicon area
efficiency of FPGA computing solutions. In
addition, the switched routing wires use more
power than hardwired connections. A second
shortcoming of the fine granularity is the high
volume of configuration data wanted for the large
number of both processing units and routing
switches. This shows the need for a high
configuration memory, with according power
dissipation. The long configuration time, that is
implied by this problem, makes execution models
depending on a steady change of the configuration
impossible.
As a third disadvantage, application
development for FPGAs is very similar to VLSI
design owing to the programmability at logic level.
The mapping of applications from common high-
level languages is difficult compared to the
compilation onto a standard microprocessor, as the
granularity of the target FPGA does not match that
of the operations in the source code. The standard
way of application specification is still a hardware
description language, which requires a hardware
expert. In the following design process, the large
number of processing units leads to a complex
synthesis, which uses up much computation time.
Coarse grained reconfigurable architectures try to
overcome the disadvantages of FPGA-based
computing solutions by providing multiple-bit wide
data paths and complex operators instead of bit-
level configurability. In contrast to FPGAs, the
wide data path allows the efficient implementation
of complex operators in silicon. Thus, the routing
overhead generated by having to compose complex
operators from bit-level processing units is
avoided. Regarding the interconnects between
processing elements, coarse grain architectures also
differ in several ways to FPGAs. The connections
are multiple bits wide, which implies a higher area
usage for a single line. On the other hand, the
number of processing elements is typically several
orders of magnitude lower than in an FPGA. Thus,
much fewer lines are needed, resulting in a globally
lower area usage for routing. The lower number
and higher granularity of communication lines
allows also for communication resources, which
would be quite inefficient for fine grained
architectures. Examples for such resources are
time-multiplexed buses or global buses, which
connect every processing element. In the past
years, several approaches for coarse grained
reconfigurable architectures have been published.
In this chapter, several example architectures will
be presented to give an overview over the
developments in the area of coarse grain
reconfigurable computing.
III. EXPERIMENTAL ANALYSIS
This division describes the features of the RPU
including power and delay distributions. The RPU
is modeled in VHDL. One aim is to find out the
most power efficient circuit parts so that slack time
could be traded for more power reduction. The
application benchmarks include H.264 decoder,
audio video coding standard (AVS) decoder,
MPEG2 decoder, and GPS receiver.

Table I
www.ijrde.com


Normalized delay of ALU with different configurations

Table II
Delays of the different paths in RCA
Table III
Utilization Times of Operation Codes

Table IV
Power analysis of RPU giving out H.264 decoder
configurations

the different paths in RCA

Utilization Times of Operation Codes

H.264 decoder
Table V
Power of ALU and Interconnect of RCA

A. Static Timing Analysis:
Initially a static timing analysis of the ALU
performed. The normalized ALU delays with
respect to different configurations are shown in
table I. The average slack time is about 50% of the
critical operation delay.
Table II shows the static timing analysis of the
RCA. The critical path and non
through different ALU components are listed. The
path delay changes from 0.67 to 7.39 ns and the
ALU delay increases from 0.42 to 5.70 ns The
leading conclusion is that the ALU delay occupies
about 75% of the critical path delay and 64% o
minimal path delay.
B. Power Analysis:
The power of the RPU depends on its
configuration as revealed in table IV. All
configurations given in the table IV are the sub
algorithms of H.264 decoder. The data on the static
row are calculated when the RPU is not working
but its clock is still on. Table V gives the thorough
power consumption of the RCA module,
ALU power and interconnect power are listed
individually. The RCA module contributes about
70% of the RPUs working power and the
sue: pp- 211-216

213 | P a g e

Power of ALU and Interconnect of RCA

Initially a static timing analysis of the ALU is
The normalized ALU delays with
respect to different configurations are shown in
. The average slack time is about 50% of the
Table II shows the static timing analysis of the
non-critical path
through different ALU components are listed. The
path delay changes from 0.67 to 7.39 ns and the
ALU delay increases from 0.42 to 5.70 ns The
leading conclusion is that the ALU delay occupies
about 75% of the critical path delay and 64% of the
The power of the RPU depends on its
configuration as revealed in table IV. All the
configurations given in the table IV are the sub
algorithms of H.264 decoder. The data on the static
U is not working
but its clock is still on. Table V gives the thorough
power consumption of the RCA module, where the
ALU power and interconnect power are listed
The RCA module contributes about
70% of the RPUs working power and the


interconnect part contributes nearly 90% of the
RCAs power. From the above details, interconnect
is the critical part concerning power.
C. Basic Interconnect Structure:
The basic interconnect structure is determined
by the global of the processing elements. This
inturn is often motivated by the targeted
applications for the architecture or by
implementation considerations. Obviously, the type
of the communication architecture has a direct
impact on the complexity of architectures
application mapping. The predominating structures
of the architectures presented here is a two-
dimensional network. In extra architectures, the
processing elements are arranged in one or more
linear arrays. The third interconnect structure found
is a crossbar switch being used to connect
processing elements. This allows basically
orbitrary connections.

IV. FLEXIBLE DUAL V
DD

The analysis of previous section leads to
various outcomes.The RPU normally has large
slack time and it differs with the software.ALU is
the most critical part concerning delay.The
interconnect is the critical part concerning power.

Fig. 2 (a): Flexible dual-V
DD
RCA
A. Reconfiguration Model:
The reconfiguration model determines when a
new reconfiguration is to be loaded in to the
architecture. For architectures containing static
reconfiguration, a configuration is loaded at the
opening of the execution and stays for the period of
the computation phase. When a new arrangement
has to be loaded, the execution must stop. The
dynamic reconfiguration model allows a new
configuration to be loaded while the application is
executing. This includes the case that the execution
relies on steady reconfiguration of the processing
elements.
B. ALU:
The Arithmetic and Logic Unit is the section
of the processor that is implicated with executing
operations of an arithmetic or logical nature. It
works in combination with the register array for
many of these, in specific, the accumulator and flag
registers. The accumulator holds the outcome of
the operations, while the flag register contains a
number of seperate bits that are used to store
information about the last operation carried out by
the ALU. More of these registers can be originate
in the register array section. In the proposed
method we use latches instead of registers.
C. Latch:
Latch is an electronic device that can be worn
to store one bit of information. The D latch is used
to confine, or latch the logic level which is there on
the data line when the clock input is high. If the
data present on the D line changes state though the
clock pulse is high, then the output follows the
input. When the clock input falls to logic 0, the
final state of the D input is fascinated and held in
the latch.
D. Latch Up:
In CMOS fabrication, latch-up is a
malfunction which can occur as a result of
improper design. Latch-up in a CMOS integrated
circuit, causes unintended currents will possibly
resulting with the destruction of the entire circuit,
thus, it must be prevented.
E. Explanation of the Phenomena:
www.ijrde.com


The cross segment of a two
CMOS integrated circuit where the nMOS is on the
left hand area and the pMOS on the right han
As it can be seen as of the figure, we can
about a parasitic pnp transistor from source of the
pMOS to the p-substrate. In addition a parasitic npn
transistor is formed from source of the nMOS, p
substrate and the n-well. These parasitic transistors
and finite resistances of n-well and p-substrate
Fig 2 (b) Latch up phenomenon
As it can be clearly seen from the
equivalent circuit, there is a positive fee
around Q1 and Q2. If a parasitic current flows
through the node X and raise V
x
, Q2 turns on an
I
C2
increases resulting V
Y
decrease. This increases
I
C1
and consequently V
x
increases much more. If
the loop gain is equal to or greater than unity, this
situation continues until an enormous current flow
through the circuit in other words, until the circuit
is latched up.It should be lesser then unity in or
to prevent latch-ups. Consequently, both of process
and design engineers should take steps for latch
prevention. Doping levels, and the other
aspects should be arranged properly in or
have low parasitic resistances and current gain of
bipolar transistors. There are specific
to prevent latch-ups in different technologies. As
its results may be fatal for the circuit, preventing
latch-up in CMOS integrated circuit
essential for a proper operation.
F. Proposed Method:
A variable or flexible V
DD
proposed to reduce power consumption. This is
based on a configurable dual V
DD
technique, which
was implemented for FPGA [7]-[9] and after
of a two-transistor
circuit where the nMOS is on the
the pMOS on the right hand side.
the figure, we can converse
about a parasitic pnp transistor from source of the
a parasitic npn
from source of the nMOS, p-
well. These parasitic transistors
substrate.

Fig 2 (b) Latch up phenomenon
As it can be clearly seen from the
equivalent circuit, there is a positive feedback loop
Q2. If a parasitic current flows
, Q2 turns on and
This increases
increases much more. If
the loop gain is equal to or greater than unity, this
ntinues until an enormous current flow
s, until the circuit
then unity in order
nsequently, both of process
take steps for latch-up
the other design
properly in order to
current gain of
bipolar transistors. There are specific design rules
ifferent technologies. As
its results may be fatal for the circuit, preventing
circuit design is
DD
method is
proposed to reduce power consumption. This is
technique, which
[9] and after that
applied to RP [3], [4], but an adjustable V
used in the place of the fixed V
DDL
that the application dependent optimum V
increase power reduction rate further.
Since ALU is much more power efficient
than ALU, the granularity of dual V
to be the interconnect. The power or
is tens of times larger than that of ALU, so it is
favoured to design configurable dual V
interconnect rather than that of ALU. Two
selecting transistors and two bit configurations are
needed to elect power supply from V
Level shifters are needed at the boundary
the V
DDL
signals are transmitted to the V
domain.
The extra cost of this method is an
adjustable dc to dc converter. The control circuit
and buck converter used in [10]
generate the flexible V
DDL
. The input is given by
the compiler, so the output V
DDL
can be varied by
software control.
G. Variable V
DDL
:

The key point of the projected
variable V
DDL
since the optimum V
with applications. Initially, choose
whose delays under a specified V
DDL
than the target delay. Then, determine
utilization times by a given application by the use
of table III. Finally, the overall section
functioning under this given V
DDL

optimized power consumption can be
accordingly.
V. DISCUSSIONS AND SUMMARY
A. PVT Analysis:
Process voltage temperature (PVT)
variations after fabrication impact the optim
V
DDL
. Considering the impacts on D
are similar, so the optimum V
determined by u(I, V
DDL
).The u(i, V
different process corners and temperatures was
simulated to obtain the corresponding optimum
V
DDL
For GPS application, the PVT variation leads
to a deviation of -0.08- + 0.01 V for the optimum
V
DDL
level. To overcome this problem, a detector
circuitry measuring post silicon delays could be
sue: pp- 211-216

215 | P a g e
applied to RP [3], [4], but an adjustable V
DDL
is
DDL
. The cause is
that the application dependent optimum V
DDL
can
increase power reduction rate further.
Since ALU is much more power efficient
than ALU, the granularity of dual V
DD
is selected
to be the interconnect. The power or delay of ALU
than that of ALU, so it is
red to design configurable dual V
DD
to the
interconnect rather than that of ALU. Two
selecting transistors and two bit configurations are
needed to elect power supply from V
DDH
and V
DDL
.
Level shifters are needed at the boundary by which
signals are transmitted to the V
DDH

The extra cost of this method is an
adjustable dc to dc converter. The control circuit
and buck converter used in [10] are used to
. The input is given by
can be varied by
projected method is a
e the optimum V
DDL
changes
those operations
DDL
are not larger
delay. Then, determine their
on times by a given application by the use
section of the RCs
is obtained. The
optimized power consumption can be determined
DISCUSSIONS AND SUMMARY
Process voltage temperature (PVT)
variations after fabrication impact the optimum
on D
A
, D
I
, and D
C

are similar, so the optimum V
DDL
is mainly
).The u(i, V
DDL
) at
different process corners and temperatures was
simulated to obtain the corresponding optimum
For GPS application, the PVT variation leads
0.01 V for the optimum
. To overcome this problem, a detector
circuitry measuring post silicon delays could be


designed to calibrate the parameters used in our
method, such as u, and also to direct the assignment
of power supplies. However, the detail is out of the
scope of this brief and could be our future topic.
VI. CONCLUSION
This paper has presented the Variable dual
V
DD
method to reduce the power consumption of
RP. This is based on the conventional dual -V
DD

method but has a variable application-dependent
V
DDL
.The main change in this paper is that the
proposed method uses latches instead of the
register, which leads to a power reduction in the
Variable dual V
DD
method. The Reconfigurable
processor can always achieve higher power
optimized performance with this method. This can
be used for the applications of GPS, MPEG2,
H.264, and AVS. The proposed method reduces
power of RPU by about 20%. Compared with the
other techniques, more improvement is achieved in
this technique. The PVT variation causes a slight
deviation in the power,which will be be overcome
in our future work by designing a detector circuitry.

REFERENCES

[1] Jianfeng Zhu, Leibo Liu, Shouyi Yin, and Shaojun
Wei, Low-Power Reconfigurable Processor Utilizing
Variable Dual VDD,IEEE Trans. Circuits and
systems,April 2013.
[2] T. Yamamoto, K. Hironaka, Y. Hayakawa, M.
Kimura, H. Amano, and K. Usami, Dynamic VDD
switching technique and mapping optimization in
dynamically reconfigurable processor for efficient
energy reduction, in Proc. 7th Int. Symp. Reconfig.
Comput.Architect., Tools, Appl., Mar. 2011, pp. 230
241.
[3] C. Tzu-Der, T. Pei-Kuei, L. Pin-Chih, C. Lo-Mei, M.
Tsung-Chuan,C. Yi-Hau, and C. Liang-Gee, A 59.5
mW scalable/multi-view video decoder chip for Quad/3D
full HDTV and video streaming applications, in Proc.
ISSCC Dig. Tech. Papers, Feb. 2010, pp. 330331.
[4] D. Rossi, F. Campi, A. Deledda, S. Spolzino, and S.
Pucillo, A heterogeneous digital signal processor
implementation for dynamically reconfigurable
computing, in Proc. Custom Integr. Circuits Conf., Sep.
2009,pp. 641644.
[5] S. Bijansky and A. Aziz, TuneFPGA: Post-silicon
tuning of dual-Vdd FPGAs, in Proc. Des. Autom. Conf.,
Jun. 2008, pp. 796799.
[6] Y. Lin and L. He, Statistical dual-Vdd assignment
for FPGA interconnect power reduction, in Proc. Des.,
Autom. Test Eur. Conf. Exhib., Apr. 2007,pp. 16.
[7] T. Schweizer, T. Oppold, J. Oliveira Filho, S.
Eisenhardt, K. Blocher, and W. Rosenstiel, Exploiting
slack time in dynamically reconfigurable processor
architectures, in Proc. Int. Conf. Field-Programm.
Technol., Dec. 2007, pp. 381384.
[8] F. Li, Y. Lin, L. He, and J. Cong, Low power FPGA
using pre-defined dual-Vdd/dual-Vt fabrics, in Proc.
ACM Int. Symp. Field-Programm.Gate Arrays, 2004, pp.
4250.
[9] A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir,
M. J.Irwin, and T. Tuan, Reducing leakage energy in
FPGAsusing region-constrained placement: in PTOC.
ACM Intl. Symp. Field-Programmable Gate Arrays,
February 2004.
[10] J. H. Anderson, F. N. Najm, and T. Tuan, Active
leakage power optimization for FPGAs, in Proc. ACM
Intl. Symp. Field-Programmable Cote Arrays, Februray
2004.
[11] F. Li, Y. Lin, L. He, and J. Cong, FPGA power
reduction using configurable dual-Vdd, in Proc. Des.
Autom. Conf., Jul. 2004, pp. 735740.
[12] F. Li, Y. Lin, L. He, and J. Cong, Vdd
programmability to reduce FPGA interconnect power,
in Proc. Int. Conf. Comput.-Aided Des., Nov. 2004,pp.
760765.
[13] H. Singh, M. H. Lee, G. Lu, F. Kurdahi, N.
Bagherzadeh, and E. Chaves,MorphoSys: An integrated
reconfigurable system for data-parallel and computation-
intensive applications, IEEE Trans. Comput., vol. 49,
no. 5,pp. 465481, May 2000.
[14] T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane,
F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda,
T. Sakurai, and T. Furuyama, Variable-supply voltage
scheme for low-power high-speed CMOS digital
design, IEEE J. Solid-State Circuits, vol. 33, no. 3, pp.
454462,Mar. 1998.
[15] E. Kusse and J. Rabaey, "Low-energy embedded
FPGA structures," in ISLPED, pp. 155-160, August
1998.


Microcontroller Based Wheel Run Out Measurement System
for Commercial Vehicles
N.Gayathri
1
, V.Priyanka
2
, Swasini sudarsan
3
, Mr.M.Subramanian
4
1,2,3
Electronics and Instrumentation Engineering, Sri Sairam Engineering College, Chennai, Tamil Nadu
4
Assistant Professor, Dept. of EIE, Sri Sairam Engineering College, Chennai

ABSTRACT
Quality check is a big Challenge, due to high
volume manufacturing. Out of Several Quality
checks, one of the Quality Measurements is Wheel
Run out Measurement. Existing method of
measurement is using displacement strain gauge.
Because of wear and tear of strain gauge, operation
and maintenance expenses per month is high. Our
proposed solution is Micro controller based wheel
run out measurement system. As part of this, a
rectilinear position sensor is fixed at a point on the
wheel around the circumference. The sensed analog
output is proportional to the displacement value.
Microcontroller senses the Displacement value
through ADC and compares with allowed Wheel
Runout value in mm. Microcontroller based system
will pass the wheel which is having allowed runout
value otherwise wheel will be rejected. This system
will ensure proper checking of wheels with required
quality aspects.

Keywords: Hitech-C-compiler, MP lab IDE, PIC
16F886, PICkit 3
I. INTRODUCTION
A. Objective:
Quality check is a big Challenge. Out of
Several Quality checks, one of the Quality Measurement
is Wheel Run out Measurement.
The main objective of wheel run out test is to
check the deformities like
a) welding cracks
b) welding joint unevenness
c) welding abnormalities
B. Current scenario:
Run out tests were performed based on strain
gauge principles of detecting cracks, breaks and
abnormalities. Existing method of measurement is using
displacement strain gauge. Because of wear and tear of
strain gauge, operation and maintenance expenses per
month is high. In order to overcome it, an alternative
solution naming MICROCONTROLLER BASED
WHEEL RUN OUT MEASUREMENT SYSTEM FOR
COMMERCIAL VEHICLES has been introduced. This
system will ensure proper checking of wheels with
required quality aspects [1-3]. The scope of our project
is designing hardware and programming PIC
Microcontroller for Wheel Runout application.
II. DESCRIPTION
A. Existing system
Existing method of measurement is using
displacement strain gauge. Because of wear and tear of
strain gauge, operation and maintenance expenses per
month is high.

Figure.1. Wheel run out test using strain gauge

Optimal replacement of strain gauge due to
wear and tear induced larger cost to the industry. An
intense study was done on the type of sensor to be used
for the process [3-4]. It was decided experimentally to
use rectilinear positional sensor instead of strain gauges.

B. Proposed system


Figure.2. Block diagram for proposed system

III. HARDWARE COMPONENTS

The major hardware components in this system are
a) Rectilinear positional sensor
b) PIC microcontroller
c) LCD display
d) Voltage regulator
e) MAX 232

A. Rectilinear positional sensor (PY-2-F-010-
S01M)
a) 10 to 100 mm stroke
b) Double support of the control rod and return
spring
c) Tip with M2.5 thread and stainless steel ball

Table 1: Technical Data of sensor

d) Independent linearity up to 0.1% and infinite
resolution
e) Working temperature: -30...+100C
f) Displacement speed up to 10 m/s and force
4N
g) Maximum cursor current:- 10mA

h) Case material:- Ionized Aluminium Nylon 66 G
25
i) Control rod material:- Stainless steel material
AISI 303
j) Electrical connections:
PY2 F 3 wire 1m screened cable and PY2 C 5-
pole connector DIN43322 Figure.3. Rectilinear
positional sensor
k) Life duration: > 100x10
6
operations (within
C.E.U.)
l) Suitable for use in explosive environments with
presence of gas (groups IIA, IIB, IIC) and
combustible powders.

B. PIC Microcontroller(PIC 16F886)
PIC is a family of modified Harvard
architecture microcontrollers made by Microchip
Technology, derived from the PIC1650 originally

developed by General Instrument's Microelectronics
Division. The name PIC initially referred to
"Peripheral Interface Controller'". PIC
microcontrollers are electronic circuits that can be
programmed to carry out a vast range of tasks [5-6].
They are found in most electronic devices such as
alarm systems, computer controllers etc. PICs are
popular with both industrial developers and hobbyists
alike due to their low cost, wide availability, large user
base, extensive collection of application notes,
availability of low cost or free development tools, and
serial programming capability.

Figure.4. PIC 16F886-PIN Description

Port A and TRISA Register: Port A is an 8-bit wide,
bidirectional port. Bits of the TRISA control the PORTA
pins. All Port A pins act as digital inputs/outputs.
Port B and TRISB Register: Port B is an 8-bit wide,
bidirectional port. Bits of the TRISB register determine
the function of its pins.
Port C and TRISC Register: Port C is an 8-bit wide,
bidirectional port. Bits of the TRISC Register determine
the function of its pins. Similar to other ports, a logic one
(1) in the TRISC Register configures the appropriate
port pin as an input.

C. LCD Display
A liquid-crystal display (LCD) is a flat panel
display, electronic visual display, or video display that
uses the light modulating properties of liquid crystals.
Liquid crystals do not emit light directly. LCDs are used
in a wide range of applications including computer
monitors, televisions, instrument panels, aircraft cockpit
displays, and signage. They are common in consumer
devices such as video players, gaming
devices, clocks, watches, calculators, and telephones,
and have replaced cathode ray tube (CRT) displays in
most applications. They are available in a wider range of
screen sizes than CRT and plasma displays, and since
they do not use phosphors, they do not suffer image
burn-in. LCDs are, however, susceptible to image
persistence.
Table 2: LCD Pin Description

D. MAX 232
The MAX232 is an IC, first created in 1987
by Maxim Integrated Products, that converts signals
from an RS-232 serial port to signals suitable for use
in TTL compatible digital logic circuits.

Figure.7. MAX 232-PIN Diagram
The intermediate link is provided through
MAX232. It is a dual driver/receiver that includes a
capacitive voltage generator to supply RS232 voltage
levels from a single 5V supply. Each receiver converts
RS232 inputs to 5V TTL/CMOS levels. These receivers
(R1& R2) can accept 30V inputs. The drivers (T1&
T2), also called transmitters, convert the TTL/CMOS
input level into RS232 level.
The transmitters take input from controllers
serial transmission pin and send the output to RS232s
receiver. The receivers, on the other hand, take input
from transmission pin of RS232 serial port and give
www.ijrde.com

serial output to microcontrollers receiver pin. MAX232
needs four external capacitors whose value ranges from
1F to 22F.

E. Voltage Regulator
The 78xx (sometimes L78xx, LM78xx
x...) is a family of self-contained fixed linear voltage
regulator integrated circuits. The 78xx family is
commonly used in electronic circuits requiring a
regulated power supply due to their ease-of-
cost. For ICs within the family, the xx is replaced with
two digits, indicating the output voltage (for example,
the 7805 has a 5 volt output, while the 7812 produces
12 volts). The 78xx lines are positive voltage regulators;
they produce a voltage that is positive relative to a
common ground.

Figure.8. LM7805
Features: LM7805
a) Output Current up to 1A
A. CONNECTIONS OF PIC
Port A
RA0 to RA5, RA6 and RA7 - To LCD display with pull
up resistors and also connected to supply with pull down
resistors.
Port B
RB6 and RB7 - To program pin
RB3- To push button
RB0 - To 3 pin connector
Port C
RC0, RC1 and RC2 - To LCD display
RC4 and RC5 - To LED with pull up resistors
RC6 and RC7 - To MAX232 (for serial
communications)

V. WORKING
A rectilinear positional sensor is fixed at a point
on the wheel around the circumference. This senses the
deformities in the wheel and the sensed analog output is
proportional to the displacement value. Microcontroller
receives the Displacement value through ADC and
compares with allowed Wheel Runout value in mm. The
respective values will be displayed in LCD. The allowed
run out value is set at first using push button.
serial output to microcontrollers receiver pin. MAX232
e value ranges from
LM78xx, MC78x
linear voltage
. The 78xx family is
commonly used in electronic circuits requiring a
-use and low
is replaced with
(for example,
volt output, while the 7812 produces
volts). The 78xx lines are positive voltage regulators;
they produce a voltage that is positive relative to a
b) Output Voltages of 5
c) Thermal Overload Protection
d) Short Circuit Protection
e) Output Transistor Safe Operating Area
Protection

IV. CIRCUIT DIAGRAM AND
CONNECTION
Figure.9. Circuit diagram

To LCD display with pull
up resistors and also connected to supply with pull down
To LED with pull up resistors
To MAX232 (for serial
Other pins
MCLR- To program pin and supply
Vss- To ground
VDD- To program pin
B. OTHER PINS OF LCD
Vss - To ground
VDD - connected to supply
VEE - connected to a variable resistor for lcd contrast
adjustment
Negative (-): BACKLIGHT - connected to ground
Positive (+): BACKLIGHT - connected to supply via a
pull up resistor
A power supply is connected to the voltage re
A rectilinear positional sensor is fixed at a point
on the wheel around the circumference. This senses the
deformities in the wheel and the sensed analog output is
proportional to the displacement value. Microcontroller
ugh ADC and
compares with allowed Wheel Runout value in mm. The
respective values will be displayed in LCD. The allowed
run out value is set at first using push button.
Microcontroller based system will pass the
wheel which is having allowed runout value
the wheel will be rejected. This is indicated using the
LEDs where if green LED glows, the wheel will be
passed and if red LED glows, the wheel will be rejected.
Besides, Wheel runout value can be transferred through
RS232 to the PC for quality audit.

VI. SOFTWARE
pp- 217-221

220 | P a g e
Thermal Overload Protection
Output Transistor Safe Operating Area
DIAGRAM AND

diagram
To program pin and supply
connected to a variable resistor for lcd contrast
connected to ground
connected to supply via a
A power supply is connected to the voltage regulator.
Microcontroller based system will pass the
wheel which is having allowed runout value otherwise
the wheel will be rejected. This is indicated using the
LEDs where if green LED glows, the wheel will be
passed and if red LED glows, the wheel will be rejected.
Besides, Wheel runout value can be transferred through


The software requirement for this system is
EMBEDDED C CODING for programming the PIC
microcontroller. Programming code can be performed
using MP lab IDE (Integrated Development
Environment) with Hitech-C-compiler. PICkit 3 is for
programming on PIC microcontroller.
PICkit is a family of programmers for PIC
microcontrollers made by Microchip Technology. They
are used to program and debug microcontrollers, as well
as program EEPROM. Some models also feature logic
analyzer and serial communications (UART) tool.
Validation will be done in Lab Level for
different wheel models. Based on programming, the
microcontroller based system will pass the wheel which
is having allowed runout value otherwise wheel will be
rejected.

Figure.10. PICkit 3

VII. CONCLUSION

Based on programming, the microcontroller
based system will pass the wheel which is having
allowed runout value otherwise wheel will be rejected.
This system will ensure proper checking of wheels with
required quality aspects. The future extension of this
idea may be done on a larger and more efficient scale by
using three rectilinear positional sensors at three fixed
points that are placed at 120
0
angle on the wheel to be
tested. The entire run out measurement could be
obtained by a single rotation of the wheel about its axis.
This increases the efficiency of the operation largely.

REFERENCES

[1] Jinyi Lee, Myoungki Choi, Jongwoo Jun, Seokjin Kwon,
Joo-Hyung Kim; Jungmin Kim, Minhhuy Le;
Nondestructive Testing of Train Wheels Using Vertical
Magnetization and Differential-Type Hall-Sensor
Array; Instrumentation and Measurement, IEEE
Transactions on (Volume:61 , Issue: 9 ); Sept. 2012;
Pg: 2346 2353.
[2] Ali Asadi Laril, Wheel wear prediction-comparison
between analytical approaches and field tests, Iran
University of Science and Technology, School of
Railway Engineering, Rolling Stock Dept, Tehran
16844, Iran. Proceedings of JRC2006 Joint Rail
Conference April 4-6, 2006, Atlanta, GA,
USA,JRC2006-94054
[3] Rainer Hohmann, Dieter Lomparski, Hans-Joachim
Krause, Marc v. Kreutzbruck, and Willi Becker;
Aircraft Wheel Testing with Remote Eddy Current
Technique using a HTS SQUID Magnetometer, IEEE
TRANSACTIONS ON APPLIED
SUPERCONDUCTIVITY, VOL. 1 I, NO. I, MARCH
2001 I219
[4] Fujioka.T, Kanehara.H; A study on measuring
rail/wheel contact points of running railway
vehicles; Railroad Conference, 1999. Proceedings
of the 1999 ASME/IEEE Joint; Pg: 151-156.
[5] Muhammad Ali Mazidi, Rolin McKinlay, Danny
Causey, "PIC Microcontroller and Embedded
Systems: Using Assembly and C for PIC18.
[6] http://www.enrdd.com/documents/documents/Docu
mentation-
Constructeurs/Werther/Attrezzature/Allineamento/W
A500-WA600/011015_WA500-WA600(047-
056)_MAN_GB.PDF


Geographic Image Retrieval Using Local Invariant
Features with Euclidean Distance
R.Nandhini
1
, T.Joel
2
1,2
Electronics and Communication, R.M.K.Engineering College, Chennai, India

ABSTRACT:-
An image retrieval system is a computer
system for browsing, searching and retrieving
images from a large database of digital images.
A robust natural and geographic image retrieval
using a supervised classifier which concentrates
on extracted features is proposed. Gray level co-
occurrence matrix (GLCM), Scale invariant
feature technique(SIFT) and moment invariant
features are implemented to extract the features
from natural images. Then these features are
passed through SVM classifier. SVM classifies
whether the input is Geographic or natural
image. Based on the SVM result, the retrieval
process is done with Euclidean distance. The
performance comparison is done with standard
features such as colour and texture.

Keywords- GLCM, moment invariant, SIFT,
SVM.

I. INTRODUCTION
Content-based image retrieval is a technique,
which uses visual contents to search images from
large scale image databases according to users
interests and it has been an active and fast
advancing research area since the 1990s[1-7] . A
necessity for developing a successful CBIR system
is the extraction of discriminant features to describe
the images in the database. As such, the
development of feature extraction algorithms has
dominated the literature in this field, where the
ultimate goal is to retrieve visually similar images.
In this paper, retrieval is done for natural
and geographic images using SIFT, GLCM and
moment invariant techniques. Advantages of using
these feature extraction algorithms are better error
tolerance with fewer matches, reliability, efficient
and best image matching task.
II. PROPOSED SYSTEM
A robust natural scene and Geographic
image retrieval using a supervised classifier which
concentrates on extracted features is proposed.
Gray level co-occurrence matrix and invariant
Features are implemented to extract the features
from images. First, the input image undergoes pre-
processing step, in which the noise occurred in it
are removed with the help of median filter. In
second step, features (SIFT, GLCM, invariant) are
extracted from the images. Then these features are
passed through SVM classifier which classifies
whether the input is Geographic image or Natural
image. Based on the SVM result, retrieval process
is done with Euclidean distance. The performance
comparison is done with standard features such as
colour and texture.
Scale-invariant feature transform (SIFT): It is an
algorithm in computer vision to detect and describe
local features in images. For any object in an
image, interesting points on the object can be
extracted to provide a "feature description" of the
object. This description, extracted from a training
image, can then be used to identify the object when
attempting to locate the object in a test image
containing many other objects.
To perform reliable recognition, it is
important that the features extracted from the
training image be detectable even under changes in
image scale, noise and illumination. Such points
usually lie on high-contrast regions of the image,
such as object edges. SIFT descriptors are extracted
from an image in two steps [8-10]. First, a
detection step locates points that are identifiable
from different views. This process ideally locates
the same regions in an object or scene regardless of
viewpoint or illumination. Second, these locations
are described by a descriptor that is distinctive yet
invariant to viewpoint and illumination.

Gray Level Co-occurrence Matrix
(GLCM):
A co-occurrence matrix or co-occurrence
distribution is a matrix or distribution that is
defined over an image to be the distribution of co-
occurring values at a given offset.
Moment Invariant:
Moments are projections of the image
function into a polynomial basis. Invariants are
functional defined on the image space such that,
I(f) = I(D(f)) for all admissible D and I(f
1
), I(f
2
)
different enough for different f
1
, f
2
.The features
drawn by invariants moment technique are used to
evaluate the distributed parameter of a character
image [9-12]. They are measures of the pixel
distribution around the centre of gravity of the
character and allow capturing the global character
shape information.
III. PROBLEM ANALYSIS
Though many feature extraction
techniques are proposed, they have disadvantages
like complexity in probabilistic network, time
consuming in bit mapping and segmentation and
hence this paper is proposed to overcome it.
IV. SYSTEM ARCHITECTURE
In pre-processing method, median filter is
used to remove noise from the input test images.
Then, the pre-processed image undergoes feature
extraction process. The texture features of the
dataset are already calculated. Then, the features of
the input image is also calculated which is then
compared and retrieved using Euclidean distance.
Feature Extraction
SIFT-Detector: The SIFT detection step is
designed to find image regions that are salient not
only spatially but also across different scales.
Candidate locations are initially selected from local
extrema in difference of Gaussian (DoG) filtered
images in scale space. The DoG images are derived
by subtracting two Gaussian blurred images with
different .
D(x, y, ) = L(x, y, k) L(x, y, )

Fig 1 Block diagram for geographic image retrieval
Where L(x, y, ) is the image convolved with a
Gaussian kernel with standard deviation , and k
represents the different sampling intervals in scale
space.
Descriptor: A SIFT descriptor is extracted from
the image patch centered at each interest point. The
size of this patch is determined by the scale of the
corresponding extremum in the DoG scale space.
This makes the descriptor scale invariant.
GLCM-The first step in GLCM is to count all pairs
of pixels in which the first pixel has a value i, and
its matching pair displaced from the first pixel
by d which has a value of j. Then, this count is
entered in the i
th
row and j
th
column of the matrix
P
d
[i,j]. Note that P
d
[i,j] is not symmetric, since the
number of pairs of pixels having gray levels [i,j]
does not necessarily equal the number of pixel pairs
having gray levels [j,i].
Moment invariant: The moment invariants are
evaluated using central moments of the image
function f(x,y) ) up to third order. The image
matrix f(x,y) is processed to obtain the character
with white color on black background. The
expressions given by Equations are used to
evaluate the central invariants moment, which are
used as features. Further, mean and standard
deviation are determined for each feature using
samples [12-14]. To increase the success rate, the
new features need to be extracted based on
perturbation and divisions of the images.

Retrieval: The Euclidean distance or Euclidean
metric is the "ordinary" distance between two
points that one would measure with a ruler, and is
given by the Pythagorean formula. Relevant
Images are retrieved using Euclidean distance.
Texture Features
The below mentioned texture features of
the dataset are calculated and compared against
input image features.

1) Local Homogeneity, Inverse Difference
Moment (IDM) :

IDM= P(i,j)
IDM is also influenced by the homogeneity of
the image. Because of the weighting factor
IDM will get small contributions from
inhomogeneous areas. The result is a low IDM
value for inhomogeneous images, and a
relatively higher value for homogeneous
images.

2) Sum of Squares, Variance

This feature puts relatively high
weights on the elements that differ from the
average values of p[i,j]
3) Cluster Prominence
PROM=
P(i,j)

4) Dissimilarity
D= |i-j|

5) Autocorrelation
Other statistical approaches include an
autocorrelation function, which has been used for
analyzing the regularity and coarseness of texture
by Kaizer. This function evaluates the linear
spatial relationships between primitives. The set
of autocorrelation coefficients shown below are
used as texture features:
C(p,q)=

Where p, q is the positional difference in
the i, j direction, and M, N are image
dimensions.
V. RESULTS AND DISCUSSION

Fig 1(a) and Fig (b)
Fig 1(a) and (b) shows the location of interest
points in the input image using SIFT and the
retrieved image from the dataset.

Fig 2

Fig 2 shows the priority of the input image retrieval
among given dataset.
V. CONCLUSION AND FUTURE
WORK
In this project, a robust natural, Geographic
image retrieval using a supervised classifier which
concentrates on extracted features is developed.
Gray level co-occurrence matrix, moment
invariant features, scale invariant feature
technique are implemented to extract the features
from images. Thus, we found that local invariant
features are more effective than standard features
such as colour and texture for image retrieval of
LULC classes on comparison.

In future, we can apply this technique
for detection and classification. Also, we can
implement some other SIFT techniques for
retrieval process. For further improvement, we can
extend this technique for detecting buildings in
aerial and satellite images.

REFERENCES
[1] Aisen A.M , L. S. Broderick Brodley C.E, C.
Kak, A. Kosak(2010), Assert: A physician-in-
the-loop content-based retrieval system for
HRCT image databases, Comput. Vis. Image
Understand., vol. 75, no. 12, pp. 111132.
[2] Bandon D , A. Geissbuhler , N.
Michoux,(2009), A review of content-based
image retrieval systems in medical applications
clinical benefits and future directions, Int. J.
Med. Informat., vol. 73, no. 1, pp. 123.
[3] Belongie S, Malik J, and Puzicha J (2004),
Shape matching and object recognition using
shape contexts, IEEE Trans. Pattern Anal.
Mach. Intell, vol. 24, no. 4, pp. 509522.
[4] Beaulieu F, S. A. Napel C. Rodriguez, J. Xu
(2009), Rubin, Automated retrieval of ct
images of liver lesions on the basis of image
similarity: Method and preliminary results.,
Radiology, vol. 256, pp. 243252
[5] Brady M and Kadir Z.T (2004), An affine
invariant salient region detector, in Proc. Eur.
Conf. Comput. Vis., pp. 404416.
[6] L hen, D. Foran L. Goodell, O. Tuzel L. Yang
(2009), Pathminer:Aweb-based tool for
computer-assisted diagnostics in pathology,
IEEE Trans. Inf. Technol. Biomed., vol. 13, no.
3, pp. 291299.
[7] Davis C, Klaric M, Scott G and Shyu C.R
(2011), Entropy-balanced bitmap tree for
shape-based object retrieval from large-scale
satellite imagery databases, IEEE Trans.
Geosci. Remote Sens., vol. 49, no. 5a pp.
16031616.
[8] Ebadi H, Mokhtarzade M and Sedaghat (2011),
Uniform robust scale invariant feature
matching for optical remote sensing images,
IEEE Trans. Geosci. Remote Sens., vol. 49, no.
11, pp. 45164527.
[9] Fang T, Xu S and Wang S (2010), Object
classification of aerial images with bag-of-
visual words, IEEE Geosci. Remote Sens.
Lett, vol. 7, no. 2, pp. 366370.
[10] Goncalves J and Goncalves H
(2011),Automatic image registration through
image segmentation and SIFT, IEEE Trans.
Geosci.Remote Sens., vol. 49, no. 7, pp. 2589
2600.
[11] Gool L.J, Moons T and Ungureanu D
(2000),Affine/photometric invariants for
planar intensity patterns, in Proc. Eur. Conf.
Comput. Vis., pp. 642651.
[12] Hongyu Y and Wen C (2004), Remote sensing
imagery retrieval based- on Gabor texture
feature classification, in Proc. Int. Conf. Signal
Process., pp. 733736.
[13] Lindeberg T (1998), Feature detection with
automatic scale selection, Int. J. Comput. Vis.,
vol. 30, no. 2, pp. 79116.
[14] H.Lang, R. Hanka, and H. H. S. Ip(2003),
Histological image retrieval based on
semantic content analysis, IEEE Trans. Inf.
Technol. Biomed., vol. 7, no. 1, pp. 2636.



VIDEO MULTICAST USING LBP AND QDM
IN WIRELESS NETWORK

Ayyappan B
1
Jagan P
2
, Rajasekar K
3
, Thenpandian S
4
1,
Asst Prof,Information Technology,Jeppiaar Engineering College,Chennai,India

2,3,4
information Technology,Jeppiaar Engineering College,Chennai,India

ABSTRACT
Adaptation of transmission bit-rate for
video multicasting is a challenging problem
because of heterogeneous client speed and
variable bit-rates.Prior approach based on leader
based schemes to achieve the video multicasting
for the node that experiences the worst channel
condition .However ,this could affect the other
nodes that can receive a higher throughput. Our
goal is to provide clients heterogeneous visual
quality matching their channel conditions .we
providing differentiated video quality for various
clients to match their heterogeneous channel
conditions and guaranteeing minimum visual
quality for each client. Specifically, our goal is to
develop a software-based rate scheduling protocol
in order to produce the maximal total visual
quality for quality-differentiated video multicast
under the constraint of ensuring at least minimum
visual quality for each member.

Keywords: modulation, multicast, Quality
Differentiated Multicasting(QDM),transmission bit-
rates ,leader based protocol

I. INTRODUCTION
In this paper we have found a way to
transmit the video to different multirate system in a
wireless network connection such that every client node
gets the video streaming with a effective quality
without any data loss using a technology called
QDM(Quality differentiated multicast) and LBP(Leader
Based Protocol) [1].

II. SYSTEM ANALYSIS
Due to the heterogeneity among multicast members,
different multicast recipients may observe dissimilar
link qualities. Recently, several works have focused
on how to allocate bandwidth efficiently for
broadcasting video streams to clients either with
heterogeneous resources, e.g., screen resolution or
decoding capability, or with multiple access
technologies. Our goal is to provide clients
heterogeneous visual quality matching their channel
conditions. Most work on rate selection for wireless
multicast focuses on achieving multicast reliability
by selecting the rate that can deliver data reliably to
the member with the worst channel condition. In the
Leader-Based Protocol (LBP) is the first leader-based
approach proposed to overcome the problem of
feedback collision. It selects the worst node as the
leader to acknowledge multicast packets. Other
members can issue negative acknowledgements to
collide the acknowledgement sent by the leader and,
thus, trigger the sender to retransmit the lost packets.
The goal of LBP is to support reliability by a single
feedback [2].
However, it does not adapt the transmission bit rate
to dynamic channel conditions, but only sends data at
the base rate. Thus, the rate adaptation algorithms,
such as RAM and ARSM, are proposed for the
leader-based multicast protocol. They estimate link
quality of the leader and determine a proper rate that
can better reach the leader. Both of these techniques
let each receiver embed the information about it
receiving SNR value in the CTS frame. The sender
can infer the leaders SNR upon receiving the CTS
frames, and predict a suitable rate accordingly.

A. PROBLEM FORMULATION
However, this approach may not be efficient for
video multicast because it merely selects the rate that
maximizes the throughput of the worst node. In doing


so, it penalizes those nodes who can receive data at a
higher bit rate [3].To avoid this effect, some
multicast rate adaptation schemes select the member
who experiences the worst channel condition as the
leader of the multicast group, and predict a bit
rate that can reach this leader.

III. PROPOSED ARCHITECTURE
In this project, we providing differentiated
video quality for various clients to match their
heterogeneous channel conditions and guaranteeing
minimum visual quality for each client. Specifically,
our goal is to develop a software-based rate
scheduling protocol in order to produce the maximal
total visual quality for quality-differentiated video
multicast under the constraint of ensuring at least
minimum visual quality for each member.
We model the rate scheduling problem as a
variation of the Knapsack problem, and propose a
dynamic programming solution to solve it optimally.
We propose a practical protocol, called Quality-
Differentiated Multicast (QDM), which exploits a
sample-based technique to adapt the transmission bit-
rate of each video frame to variable video bitrates and
client mobility without the need of any preprocess.

Fig 4.1.System Architecture Diagram

A. PEAK SIGNAL-TO-NOISE RATIO
(PSNR)
The different transmission bit-rate for each
video frame according to its importance (defined as
the rate scheduling problem), so that members can
receive differentiated video quality that best takes
advantage of their channel conditions. An intuitive
solution of the rate scheduling problem is to select
the rates that can achieve the maximal peak signal-to-
noise ratio (PSNR) value (a metric standardized by
ITU and used to evaluate video quality.
B. WIRELESS MULTICAST
Most work on rate selection for wireless
multicast focuses on achieving multicast reliability
by selecting the rate that can deliver data reliably to
the member with the worst channel condition. In the
Leader-Based Protocol (LBP) is the first leader-based
approach proposed to overcome the problem of
feedback collision [3-4]. It selects the worst node as
the leader to acknowledge multicast packets. Other
members can issue negative acknowledgements to
collide the acknowledgement sent by the leader and,
thus, trigger the sender to retransmit the lost packets.
The goal of LBP is to support reliability by a single
feedback.

C. QUALITY DIFFERENTIATED MULTICAST
(QDM)
The propose a practical protocol, called
Quality Differentiated Multicast (QDM), which
exploits a sample-based technique to adapt the
transmission bit-rate of each video frame to variable
video bitrates and client mobility without the need of
any preprocess. Thus, it can be applied to real-time
video streaming.

D. RATE SCHEDULING MODEL
A theoretical optimization model, and utilize
a dynamic programming algorithm to compute the
solution using oracle information. This model needs a
high computational complexity and complete
information about the packet loss probability of each
wireless link. Our motivation is to use the model as a
reference to assess the performance of our new
technique, called QDM, introduced in the next


section. We will discuss their performance
comparison.

E. MULTIPLE DESCRIPTIONS CODING
(MDC):

The MDC encodes a media stream into
multiple independent sub streams any part of which
can be decoded independently. Receivers can get
minimum quality by decoding one arbitrary
description, and achieve incremental improvement by
receiving additional descriptions.

F. QDM FRAMEWORK:

The model in the last section is proposed to
find the most efficient solution, which needs
complete information about the loss probability To
cope with the above practical issues, we propose DM,
a practical video multicast framework including three
components: 1) cluster construction: it clusters clients
according to their channel conditions in order to
characterize the heterogeneity of clients; 2) sample-
based rate scheduling: it predicts the rate schedule by
real-time sampling, and, thus, can estimate visual
quality even if information.
V. EXPERIMENTAL RESULTS

Fig V.(a) .Server

Fig V.(b).Proxy

Fig.V.(c) Video Transmission
VI. CONCLUSION & FUTURE WORK

The performance evaluation shows that QDM can
produce a gain of 2-5 dB in terms of the average
video quality as compared to the leader-based
scheme, while also guarantee that each client
perceives at least a minimum video quality. In
addition, the two-state rate-adaptation scheme in
QDM can adapt the rate to network dynamics and
variable video bit rates with a reduced sampling
overhead.
REFERENCES



[1] K.A. Hua and F. Xie, A Dynamic Stream
Merging Technique for Video-on-Demand Services over
Wireless Mesh Access Networks, Proc. IEEE CS
Seventh Ann. Conf. Sensor Mesh and Ad Hoc Comm.
and Networks (SECON), 2010.
[2] A. Kamerman and L. Monteban, WaveLAN-II:
A High-Performance Wireless LAN for the Unlicensed
Band, Bell Labs Technical J., vol. 2, no. 3, pp. 118-133,
1997.
[3] G. Holland, N. Vaidya, and P. Bahl, A Rate-
Adaptive MAC Protocol for Multi-Hop Wireless
Networks, Proc. ACM MobiCom, 2001.
[4] B. Sadeghi, V. Kanodia, A. Sabharwal, and E.
Knightly, OAR: An Opportunistic Auto-Rate Media
Access Protocol for Ad Hoc Networks, Proc. ACM
MobiCom,2002



IMPLEMENTATION OF TEMPERATURE
COMPENSATION TECHNIQUE WITH ULTRASONIC
RANGING FOR OBSTACLE IDENTIFICATION
B.Nalini
1
, B.Nandhini
2
, E.Kavitha
3
, Mrs R.Chandralekha
4
1,2,3
EEE, Veltech multi tech Dr.RR Dr.SR Engg. College, Chennai, India
4
Assistant professor EEE, Veltech multi tech Dr.RR Dr.SR Engg. College, Chennai, India

ABSTRACT
The main aim of the model proposed in this
project is to reduce the error in the distance
measured by ultrasonic sensor using
temperature compensation. With the help of this
we are implementing a system to give alarm
once an obstacle is identified within a specified
distance. The applications may vary according
to the field such as in industries, self-propelling
vehicles, robots or for differently abled person
to detect the obstacle. The model contains an
ultrasonic sensor for distance measurement. A
temperature sensor is also provided for
measuring the temperature of the surrounding
environment. An error is caused in the distance
measured by the ultrasonic sensor due to the
temperature variation. This can be overcome
with the help of the technique of temperature
compensation proposed in this paper. The
sensors are interfaced with a PIC
microcontroller. Based on the calculated
distance, an alarm or LED indication is given
when the obstacle is near. Using ZigBee
transmitter and receiver, the measured values
are sent to a computer. Then a MATLAB based
calculation and analysis is carried out to obtain
the correct distance of the obstacle and to bring
out the difference in the measured value with
compensation and that without temperature
compensation. The main advantage of this
project is its simplicity and feasibility. In future
the analysis can be done for different materials
so that effect of all material can be analysed.
Other factors such as humidity and pressure can
also be included so that the combined
compensation can reduce more error.
Keywords: MATLAB analysis, obstacle,
temperature compensation, ultrasonic, ZigBee.

I. INTRODUCTION
There are various techniques to locate a moving
target in real-time. These can be IR based,
Ultrasonic based or RFID based technology. In [1]
an obstacle detection system using ultrasonic
sensors and USB camera based visual navigation
was considered .In [2] a smart phone based
ultrasonic wireless ranging and collision warning
system was proposed. Many obstacle detection
techniques also use IR sensors. But the sensor
cannot be used in sunlight. Some techniques use
RFID but it is costly. Hence the proposed system is
very effective. In the system proposed we are using
ultrasonic sensor which is more accurate and can be
used outside also.
II.PROPOSED SYSTEM
The general block diagram of the proposed system
is shown in figure 1. Distance is measured with the
help of ultrasonic sensor. Temperature sensor
measures the environment temperature. The
PIC16F887 microcontroller computes the distance
with temperature compensation.
The computer receives serial data (temperature and
distance) from the controller using ZigBee
technology and MATLAB based compensation is
done and displayed. If the distance is below
particular value (say 5 or 10 cm), buzzer alarm is
given to indicate the presence of an obstacle.
A. Ultrasonic sensor:
The audible sound frequency for ultrasonic sound
waves greater than 20kHz.Thus it is greater than
human audible frequency.
With the ultrasonic advance, and the electronic
technology development, especially as high-power
semiconductor device technology matures, the
application of ultrasonic has become increasingly
widespread. Some of the applications are given
below.
Ultrasonic measurement of distance, depth
and thickness
www.ijrde.com


Ultrasonic testing
Ultrasound imaging
Ultrasonic machining, such as polishing,
drilling
Ultrasonic cleaning
Ultrasonic welding

Figure 1: Block diagram of proposed system

The ultrasonic sensor used in this project is HC
SR04. It has four pins: vcc, trig, echo, and ground.
The pin diagram is shown below.
.
Figure 2: Pin diagram of ultrasonic sensor
Electrical Parameters of HC-SR04 Ultrasonic
Module are given the table 1.

Table 1: HC-SR04 electrical parameters
Operating
Voltage
DC 5V
Operating
Current
0.015A
Operating
Frequency
40kHz
Farthest Range 4m
Nearest Range 0.02m
Measuring
Angle
15 degrees
Input trigger 10s TTL pulse
ning, such as polishing,

ure 1: Block diagram of proposed system
The ultrasonic sensor used in this project is HC-
It has four pins: vcc, trig, echo, and ground.

Figure 2: Pin diagram of ultrasonic sensor
SR04 Ultrasonic
SR04 electrical parameters
5V
A
40kHz

15 degrees
s TTL pulse
signal
Output echo
signal
Output TTL level signal
proportional with range
Dimensions 45*20*15 mm

Ultrasonic transmitter emits an ultrasonic wav
one direction, and starts timing when it launched.
Ultrasonic spreads in the air
immediately when it encounters obstacles on the
way. At last, the ultrasonic receiver
when it receives the reflected wave. As U
spread velocity is 340m / s in the air, based on the
timer record t, we can calculate the distance (d
between the obstacle and transmitter, namely:

d =340t / 2

This is called as the time difference distance
measurement principle.

The sound wave spreading velocity for the sensor
used here is 340m/s. The following steps are to be
followed for measuring distance with the help of
ultrasonic sensor. The Trig and Echo port
low when the module initializes. Then at
high level pulse is transmitted to the Trig pin.
the module automatically sends eight 40K square
wave. Then we wait to capture the rising edge
output by echo port at the same time,
opened to start timing. The falling edge output by
echo port is captured, at the same time;
the counter is read. Then the test distance is
calculated as below:

Test distance = (high level time*sound waves
spreading velocity in air)/2.

B. Temperature sensor:
The temperature sensor used in this project
DS18B20. The DS18B20 provides 9
Celsius temperature measurements. The DS18B20
communicates over a 1-Wire bus that by definition
requires only one data line (and ground) for
communication with a central microcontroller. It
has three pins: VDD, DQ, and ground.
diagram is shown in figure 3.
e: pp- 230-234
231 | P a g e
Output TTL level signal
proportional with range
45*20*15 mm
an ultrasonic wave in
timing when it launched.
air and returns
obstacles on the
receiver stops timing
the reflected wave. As Ultrasonic
spread velocity is 340m / s in the air, based on the
calculate the distance (d)
and transmitter, namely:
time difference distance
The sound wave spreading velocity for the sensor
The following steps are to be
followed for measuring distance with the help of
he Trig and Echo port are set as
Then at least 10s
to the Trig pin. Now
ly sends eight 40K square
wait to capture the rising edge
at the same time, the timer is
he falling edge output by
at the same time; the time of
the test distance is
Test distance = (high level time*sound waves
The temperature sensor used in this project is
DS18B20. The DS18B20 provides 9-bit to 12-bit
Celsius temperature measurements. The DS18B20
Wire bus that by definition
requires only one data line (and ground) for
communication with a central microcontroller. It
DD, DQ, and ground. The pin
www.ijrde.com


Figure 3: Pin diagram of temperature sensor
The core functionality of the DS18B20 is its direct
to-digital temperature sensor. The resolution of the
temperature sensor is user-configurable to 9, 1
11, or 12 bits, corresponding to increments of
0.5C, 0.25C, 0.125C, and 0.0625C,
respectively. The default resolution at power
12-bit. The DS18B20 powers up in a low
idle state.
Some of the features of the temperature sensor are:
The operating temperature of the sensor is
-55
0
C to +125
0
C.
It can be powered from Data Line; the
power Supply Range is 3.0V to 5.5V.
It has a 0.5C Accuracy from
+85C.
Resolution of the sensor is user selectable
from 9 to 12 bits.
It converts temperature to 12 b
word in 750ms (max)

C. PIC microcontroller:

The microcontroller used in this project is
PIC16F887.
The PIC16F887 is one of the latest products from
Microchip. It features all the components which
modern microcontrollers normally have. For its low
price, wide range of application, high quality and
easy availability, it is an ideal solution in
applications such as: the control of different
processes in industry, machine control devices,
measurement of different values etc. Som
main features are listed below.

Operating frequency of the controller is 0
20 MHz
It has a precision internal oscillator which
is factory calibrated.
Power supply voltage is 2.0-5.5V.
Figure 3: Pin diagram of temperature sensor
The core functionality of the DS18B20 is its direct-
digital temperature sensor. The resolution of the
configurable to 9, 10,
11, or 12 bits, corresponding to increments of
0.5C, 0.25C, 0.125C, and 0.0625C,
respectively. The default resolution at power-up is
bit. The DS18B20 powers up in a low-power
Some of the features of the temperature sensor are:
operating temperature of the sensor is
It can be powered from Data Line; the
power Supply Range is 3.0V to 5.5V.
It has a 0.5C Accuracy from -10C to
Resolution of the sensor is user selectable
temperature to 12 bits digital
The microcontroller used in this project is
The PIC16F887 is one of the latest products from
Microchip. It features all the components which
mally have. For its low
price, wide range of application, high quality and
easy availability, it is an ideal solution in
applications such as: the control of different
processes in industry, machine control devices,
measurement of different values etc. Some of its
Operating frequency of the controller is 0-
It has a precision internal oscillator which
5.5V.
The power consumption is
4MHz), 11A (2.0 V, 32 K
(stand-by mode).
Power-Saving Sleep Mode is available.
35 input/output pins are available.
D. ZigBee:

ZigBee is based on an IEEE 802.15 standard.
Though low-powered, ZigBee devices can transmit
data over long distances by passing data through
intermediate devices to reach more distant ones.
Because ZigBee nodes can go from sleep to active
mode in 30 ms or less, the latency can be low and
devices can be responsive, particularly compared to
Bluetooth wake-up delays, which are typically
around three seconds. Because ZigBee nodes can
sleep most of the time, average power consumption
can be low, resulting in long battery life.
driver has to be installed in the computer in order to
connect the ZigBee receiver to it.
In this project ZigBee is used to transmit the data
from the various sensors interfaced with the
PIC16F887 microcontroller to the PC in which
MATLAB based calculation and analysis is done.

E. MATLAB based analysis:

A MATLAB based GUI is developed. The actual
distance measured by the ultrasonic sensor and the
temperature measured by the temperature sensor
received through ZigBee are displayed. Then the
compensation is done and the new distance
calculated is also displayed in the GUI. Thus the
amount of error reduction can be analys

F. Implementation:

The sensors are interfaced with the microcontroller.
Then the LED and Buzzer alarm are also interfaced
to the PIC controller. A configuration switch can
also be provided to select the range of proximity of
the obstacle for which the alarm has to be given.
The ZigBee transmitter is also connected to the
microcontroller.
The ZigBee receiver is connected to the computer
through USB port. The required software is
downloaded. MATLAB based GUI is developed
and used for analysis.

e: pp- 230-234
232 | P a g e
The power consumption is 220A (2.0V,
A (2.0 V, 32 KHz) 50nA
Saving Sleep Mode is available.
35 input/output pins are available.
ZigBee is based on an IEEE 802.15 standard.
powered, ZigBee devices can transmit
data over long distances by passing data through
intermediate devices to reach more distant ones.
Because ZigBee nodes can go from sleep to active
mode in 30 ms or less, the latency can be low and
devices can be responsive, particularly compared to
up delays, which are typically
ee seconds. Because ZigBee nodes can
sleep most of the time, average power consumption
can be low, resulting in long battery life. FTDI
driver has to be installed in the computer in order to
d to transmit the data
from the various sensors interfaced with the
PIC16F887 microcontroller to the PC in which
MATLAB based calculation and analysis is done.
A MATLAB based GUI is developed. The actual
the ultrasonic sensor and the
temperature measured by the temperature sensor
received through ZigBee are displayed. Then the
compensation is done and the new distance
calculated is also displayed in the GUI. Thus the
amount of error reduction can be analysed.
The sensors are interfaced with the microcontroller.
Then the LED and Buzzer alarm are also interfaced
to the PIC controller. A configuration switch can
to select the range of proximity of
the alarm has to be given.
The ZigBee transmitter is also connected to the
The ZigBee receiver is connected to the computer
The required software is
MATLAB based GUI is developed


III. TEMPERATURE COMPENSATION

The speed of sound at 0 degree Celsius is
331.46m/s. In dry air at 20 C (68 F), the speed of
sound is 343 metres per second. It is because the
speed of sound waves is affected by various factors
like temperature, pressure and other factors.

A. Speed of sound in ideal gas:
The speed of sound in an ideal gas is independent
of frequency. It is proportional to the square root of
the absolute temperature, but is independent of
pressure or density for a given ideal gas. It is also
independent of pressure in an ideal gas.
B. Speed of sound in real gas:
The speed of sound does vary slightly with
frequency in a real gas. Sound speed in air varies
slightly with pressure. In addition, for different
gases, the speed of sound is inversely proportional
to the mean molecular weight of the gas [4].
Thus various factors affect the speed of sound
waves. In this paper we are trying to reduce the
effect of temperature.

C. Distance calculation:
Generally the distance is measured by the
ultrasonic sensor is given as:

= /2
C is the speed of sound waves. t is the time
interval between the transmission and reception of
the ultrasonic waves. It is known as the round trip
delay. Hence to find the distance of the obstacle
half the value of t is taken.
Now since the value of C is dependent on
temperature, the value of the distance measured by
the ultrasonic sensor is also affected.
The formula without temperature compensation is:

Dcm=34000*
(t*10
-6
)
2

Here since the round trip delay is in s, it is
converted to seconds and the distance in
centimetres is obtained from the above equation.
It is observed that the speed increases by 0.607 m/s
for an increase of 10 degree Celsius in air
temperature and also decrease for decrease in
temperature [1]. The reported distance will be
comparably less in hot weather and large in cold
weather. To overcome this problem we are using
temperature compensation. The speed of ultrasonic
waves in air is 340m/s. Thus the new formula is
obtained with the help of this information.

The formula with temperature compensation is:
Dcm=(34000+60.7T)*
(t*10
-6
)
2

Where t = round trip delay from ultrasonic sensor
and T= temperature of the surrounding.
So this formula is used to obtain the corrected
distance based on which the obstacle will be
detected and if found to be very near, an alarm will
be raised.

IV. APPLICATIONS
This system can be used in automatic robots, self-
propelling vehicles in automated production
factories etc. This distance measurement and
obstacle detection system can be used in places
where accurate distance measurement is required.
This system if reduced in size can also be
implemented for helping blind people.
V. CONCLUSION

The accuracy of the distance measurement is thus
improved by using this module along with
temperature compensation. This project effectively
reduces the error in the distance measured due to
the effect of temperature. In future various other
factors influencing the distance measurement can
be taken into account. The proposed method is
highly effective and efficient.

REFERENCES

[1] Rahul Kumar Rastogi, Rajesh Mehra Efficient
Error Reduction in Ultrasonic Distance
Measurement Using Temperature compensation.
[2] Amit Kumar, Rusha Patra, M. Manjunatha, J.
Mukhopadhyay and A. K. Majumdar, IIT,
Kharagpur An Electronic Travel Aid for
Navigation of Visually Impaired Persons
International Conference on Communication
Systems and Networks (COMSNETS), PP-1-5,
IEEE 2011.
[3] Bruno Ando, and Salvatore Graziani,
Multisensor Strategies to Assist Blind People: A


Clear-Path Indicator, Transactions on
Instrumentation and Measurement, Vol. 58, Issue
no. 8, PP- 2488-2494, IEEE.
[4] http://en.wikipedia.org/wiki/Speed_of_sound.
[5]http://www.elecfreaks.com/store/download/prod
uct/Sensor/HC-SR04/HC-
SR04_Ultrasonic_Module_Guide.pdf



Hardware mapping for Graphics Geometric Intersections

R.Karthika
1
,K.Kayalvizhi
1
,P.Meera
1
and Dr.M.P.Chitra
2

1
student, Electronics and communication, Panimalar Institute Of Technology, Chennai-123,
2
Professor and head, Electronics and communication, Panimalar Institute of Technology, Chennai-123.

ABSTRACT
Most consumer electronic devices employ graphic
applications which vector graphics equations to model
various object shapes. These mathematical representations
of data are computationally intense giving ample scope for
hardware oriented accelerating ways. This paper explains
the hardware mapping of ray tracing algorithm which is
used for three dimension object rendering. First, the
matlab simulation model for various object rendering is
demonstrated. Based on this model, architecture is
proposed using fast arithmetic units like divider,
multipliers and square root. The proposed computational
element computes the box-cube intersections. The
synthesis result shows that it can run at 20 MHz
frequency.
Keywords Vector graphics, Ray Tracing, rendering,
data path.

I.INTRODUCTION

Computer graphics are graphics created using
computers and the representation of image data by a computer
with the help of graphics hardware and software. It is used to
understand and interpretation of data in an easier manner.
Vector graphics is used to create more complex image. If a
vector graphic image is made very big on the monitor, it will
still be as good as its regular size.
3D graphics is the three dimensional representation
of data. Some of the algorithm used in 3D graphics are ray
tracing, cone tracing, beam tracing, path tracing, photon
mapping, scan-line renderer. Ray tracing is the one of the
method to render the 3D image. It is the most straightforward
method compared to other algorithms [7], [1]. There are many
techniques to improve the performance of 3D graphics. In this,
graphics accelerator is one of the techniques. It is hardware
used to perform functions faster than the software. In shading,
secondary and tertiary reflections are not considered. It will
consider only primary reflection.

II.RAY TRACING

Ray tracing is a technique for generating an image by
tracing the path of light through pixels in an image plane. This
technique is capable of producing a very high degree of
photorealism. There are two types of ray tracing are forward
and reverse ray tracing. In forward ray tracing, it traces the
light path from light source to object and from object to
viewer. Many photons will come from the light source to find
only one photon that would strike the viewer. This is the main
drawback of the forward ray tracing. To overcome this
drawback, reverse ray tracing is used. In reverse ray tracing
[8], it traces light from viewer to object and from object to
light source. If the ray hits an object from viewer, it is used to
find how much light it receives by throwing another ray from
object to light source.

Figure 1: Image plane Formation

Ray tracing includes three steps of process to trace the image.
i) Intersection tests
ii) Grid traversal
iii) Shading

In intersection tests, each ray is tested for intersection
against the surface in the rays current pixel in the grid.
Intersection testing is done with ray tracing algorithm. If the
intersection is found within the pixel, the surface index and
information about the point of intersection are stored alone to
be used in future for tracing image in the final process of
algorithm. In grid traversal, if an intersection is not found in
the previous process the ray will be traversed through the grid
Viewer origin
(x0, y0, z0)
Image plane
Object
X axis
Y axis
Z axis
Max, Min
bound

to the next pixel which intersects in the grid. If an intersection
has been found, no tracing will be done either a new ray will
be created with its beginning point in the pixel. This created
ray is named as shadow. If there is an intersection, then the
pixel is shaded using the point of intersection, position of light
and material, color and normal of the hit surface.

(a) (b) (c) (d) (e)
Figure 2: Various Graphics Geometric in 3D with varied orientation (a) and (b) representing Cube, (c) and (d) representing Sphere, (e)
Representing Tetrahedron

The following pseudo code techniques the computation of
every pixel value of the image plane is taken

For every pixel value {
Generate Viewing Rays r(x, y, and z)
Calculate the intersection I(x0, y0, z0)
Determine suitable shading f(x, y, z)
Find the Pixel value}

Figure 3: Viewing Rays
To view the ray direction,

/| | (1)
Where, X = ray direction, R = image center,
S = focal point, r (t) = viewing ray can be represented as

(2)

RAY-SPHERE INTERSECTION

To find the point on the ray,
(3)
To find the point on sphere,

. (4)
Substitute the equation (3) in (4)

. (5)
To find the solution for the above equation, use quadratic
solution. The suitable coefficients shall decide the point of
intersection of generated rays and the object surface using
equation (6).
The equation is in the form of
0. (6)
Where

, 2. ,

Let
4
If d < 0 no solution
Otherwise
_ / 2 , Check t_ 0

RAY-BOX INTERSECTION

Equation (7), (8) (9) (10) explains the method of
intersection finding for axis aligned cube - box which involves
solving simultaneous equations as shown in figure 4.

To find where the ray intersects with this line is
(7)
Re-ordering the above expression
/.. (8)
If the value of t is negative then box is behind the ray.
Similarly, the ray intersects the box plane parallel to the y and
z axis.
0 0/... (8)

0 0 0/.. (10)

Figure 4: Ray-Box Intersection

The results of the matlab model constructed for sphere,
cubical and tetrahedron intersection is shown in the figure (2).


The point of origin (camera viewing) and light throwing
direction, focal length, focal point, material properties,
viewing direction are considered parameter. To keep it simple,
the considered material surface is opaque so the reflection and
refraction phenomenon and multiple reflections are avoided.
The model object rendering for various orientation is also
illustrated. The basic unidirectional lighting and shading [6]
for the rendered object is considered.

III. DATA PATH ARCHTIECTURE

As computational 3D geometry its origin, the vector
graphics equation dictates these tasks are highly
computationally intensive. The hardware mapped to these
corresponding iterations is the suitable solution to these
demands [2]. The data path synthesis is alone considered from
the entire architecture.
However, at the coarse level of this architecture include
adders, subtractor, multipliers, dividers, square roots only. The
efficient methods of these individual units combined with
proper data driven arrangement will make the computational
overhead at ease. The increased pipelined registers in between
these hardware units can effect easy processing with little
compromise on area utilized by these registers. This data path
is explained here is novel architecture of one computational
element, basic unit of computation. The architecture reuse is
made in use through this method as this repeatedly accessed
for every pixel value in the image plane.
The computational element takes the coordinates of the
origin view point and the image plane points to calculate the
viewing ray direction. Having direction computed the ray
extension R (t) is done for varying values of t. Next, to find
the intersection with specific geometry i.e. cube or box like
structure is taken as consideration. The Vmin and Vmax
bound limits the cube with axis aligned as {Xmin, Xmax}
{Ymin, Ymax} and {Zmin, Zmax}.
Figure 6 shows the architecture of a computational element
which is the basis for computing value of a pixel in the image
plane. First the input co ordinates (x1, y1, z1) with the
considered origin (x0, y0, z0) the unit direction vector is
calculated for ray generation. After generation, the intersection
for cube-box object is by solving the equation using the
suitable integer value. The arithmetic multiplier employs
modified booth algorithm which computed is n/2 iteration
limit. The arithmetic divider unit has restoring method of
division. The hardware unit for square root gives only integer
results with little compromise on accuracy.

In box intersection the respective axis intercept with
magnitude value is computed and compared with the each
other to calculate the intersection points. The minimum and
maximum value of those intercept within the bound Vmin and

Vmax values are inferred to confirm the intersection with the
rendered object boundary.

X1-X0

Y1-Y0 Z1-Z0
(.)
2
(.)
2
(.)
2
(+)/ (.)
*
+ y=x0+ t*r
x
min
-x
0

x
max
-x
0
y
min
-y
0
y
max
-y
0

z
min
-z
0

z
max
-z
0
xmin
ymin
zmin

Any
integer t
xmax
ymax
zmax
Ra Ry Rz
X0
x0 z0 y0
t0z>t0y t1x>t1y
> t
0z,
t
1z

t0x
t1x
t0y
t1y
t0z
t1z
t
min
t
max
t
0x
>t
1y

or
t
0y
>t
1y
No intersection

t
max
t
min
Yes
Creating
ray trace
Intersection
mapping to
cube-box
structure
no


Figure 5: Hardware architecture of ray generation and
Cube-box Intersection
www.ijrde.com

IV. RESULTS AND DISCUSSION

The proposed architecture RTL level net list
inferred is shown in figure6. The results shows
with the critical path delay fixing the maxim
operating frequency up to 20
arithmetic unit with inherent pixel level parallelism
can be achieved with array of
elements. This computation with respect to a single
pixel is what that is iteratively repeated for
entire pixels in the image plane.
this architecture with parallel mapping pixel will
enable it for other geometric i
Using the sc105u technology, this architecture use
the clock frequency of 20
is 7000. It uses some of the gates are AN2T0,
AO1A0, FA2A0, HA1A0, IVIN0, etc.

REFERENCES

[1]Efficient Vector Graphics Rasterization Accelerator
Using Optimized Scan-line Buffer
vol.21, No.7, July 2013

[2]Ray Tracing On Graphics Hardware
Hachisuka, University of California, San Diego.

[3]Ray Tracing On Programmable
by Timothy, T.J. Purcell, I. Buck
P.Hanrahan Stanford University.
Trans.Graph.21,3,703-712,2002

[4]A 2.05 Gvertices/S 151 mw
3D Graphics Vertex And Pixel Shading
in IEEE journal of solid-state circuits,vol.48,No.1,Jan
2013.
ISSN: 2279-0500


Figure 6: Synthesized Structure Of Computational Element
architecture RTL level net list
inferred is shown in figure6. The results shows
with the critical path delay fixing the maximum
operating frequency up to 20 MHz. The faster
with inherent pixel level parallelism
can be achieved with array of such computational
This computation with respect to a single
pixel is what that is iteratively repeated for the
in the image plane. The extension of
with parallel mapping pixel will
other geometric intersections too.
Using the sc105u technology, this architecture use
MHz and the total gates
. It uses some of the gates are AN2T0,
AO1A0, FA2A0, HA1A0, IVIN0, etc.
Efficient Vector Graphics Rasterization Accelerator
line Buffer in IEEE Transaction
Graphics Hardware by Toshiya
Hachisuka, University of California, San Diego.
Programmable Graphics Hardware
I. Buck William R.Mark,
Hanrahan Stanford University.ACM
,2002.
w Lighting Accelerator For
Pixel Shading In 32 Nm CMOS
state circuits,vol.48,No.1,Jan

[5]3D Graphics Acceleration Development
VLSI and Computer Grap

[6]An Improved Illumination Model
by Tuner Whitted, Bell laboratories, Holmdel, New
Jersey.

[7]Hardware
Y.O.Kim, H.J.Woo and C.H.Kim U.S.Patent 0 045 683
Feb 25 2010.

[8]Parker.S, Martin.W, Sloan.P, Shriley.P,
Hansen.C.1999.
Symposium on Ineractive 3D Graphics,

[9]B.G.Nam et al.,
Rendering Engine With Lighting Acceleration For
Handheld Multimedia Systems
Trans.Consum.Electron., vol.51,no.3, pp.1020
Aug 2005.

[10]Karlsson.F and Ljungstedt.C.J.2004.
Fully Implemented On Programmable Graphics
Hardware. Masters thesis, Chalmers University Of
Technology.

[11]Wald.I, Slusallek.P, Benthin.C, and Wagner.M.2001.
Interactive Rendering With Coherent Ray
Computer Graphics Forum 20,3,

[12]Deering, Michael and S.Nelson, Leo:
Cost Effective
SIGGARAPH,

[13]B.T.Phong,
Pictures, Commun. ACM,
1975.

MEPED) 2014 239 | P a g e

Figure 6: Synthesized Structure Of Computational Element

3D Graphics Acceleration Development by centre for
VLSI and Computer Graphics, University of Sussex, UK.
An Improved Illumination Model For Shaded Display
by Tuner Whitted, Bell laboratories, Holmdel, New
Hardware Type Vector Graphics Accelerator by
Y.O.Kim, H.J.Woo and C.H.Kim U.S.Patent 0 045 683
Feb 25 2010.
[8]Parker.S, Martin.W, Sloan.P, Shriley.P, Smits Band
Hansen.C.1999. Interactive Ray Tracing. In 1999 ACM
Symposium on Ineractive 3D Graphics, 119-12.
9]B.G.Nam et al.,Development Of 3D Graphics
Rendering Engine With Lighting Acceleration For
Handheld Multimedia Systems, IEEE
Trans.Consum.Electron., vol.51,no.3, pp.1020-1027,
]Karlsson.F and Ljungstedt.C.J.2004.Ray Tracing
Fully Implemented On Programmable Graphics
. Masters thesis, Chalmers University Of
Technology.
Wald.I, Slusallek.P, Benthin.C, and Wagner.M.2001.
Interactive Rendering With Coherent Ray Tracing.
Computer Graphics Forum 20,3, 153-164.
[12]Deering, Michael and S.Nelson, Leo: A System For
Cost Effective 3D Shaded Graphics. Proceedings of
SIGGARAPH, 1993, pp.101-108.
[13]B.T.Phong, Illumination For Computer Generated
, Commun. ACM, vol.18, no.6.pp, 311-317, Jun
9
P a g e


Performance Analysis for the Automatic Detection and
Grading of Macular Edema Stages
M.Ramya
1
, S.Vijayprasath
2
1
M.E Communication Systems, M.Kumarasamy College of Engineering, Tamilnadu, India
2
Assistant Professor, M.Kumarasamy College of Engineering, Tamilnadu, India

ABSTRACT
Recently, we have many researches on the fundus
image for the detection of abnormality. Diabetic
retinopathy is the damage of retina caused by
complication of diabetes which results complete
vision loss. Macula is responsible for our pinpoint
vision. Diabetic macular edema is the major
problem for the diabetic patients. Several
techniques have been reported about an automated
solution for the diabetic macular edema detection.
In this paper, we propose a new method for the
detection and severity classification of abnormality.
Proposed method has five steps which comprises of
localization and masking of optic disk and macula,
motion pattern generation, feature selection,
exudate detection by PCA DD, feature extraction
of possible exudate region for classification using
Naive Bayes Classifier. The normal retinal images
in the MESSIDOR database are taken for training
and testing. By finding the exudate, the
performance of the proposed methodology
provides better accuracy classification compare to
the existing method. In addition, the severity for
the abnormal images is graded as three stages.
Experimental result shows the superior nature of
proposed method in terms of performance
measures.

Keywords: Diabetic macular edema, Diabetic
retinopathy, Fundus, Hard exudates, Retina
I. INTRODUCTION
Retinopathy is the group of noninflammatory eye
disease. Diabetic retinopathy (DR) is a disorder of the
eyes which occurs in patients having diabetes. Early
detection and treatment is essential to prevent the DR
from its severe stage. Hypoalbuminemia is often
found in diabetic patients, as a major retinal disease
and subsequent loss of protein in the proteinuria.The
decreased plasma protein deliberation decreases the
intravascular oncotic pressure. This in turn results in
net fluid movement into the retinal tissues. The person
who has diabetics with longer year there is a chances
of developing diabetic retinopathy. This systemic
disease can degenerate DME and their treatment and
control can help to resolve DME. The patients with
retinopathy on premature stage, have no symptoms,
but at the mature stage, symptoms such as cloudy
vision or blind spots may develop in [1]-[3].
Eventually it will develop blindness if it is untreated.
Complete eye exam is the only way to know whether
the person have diabetic retinopathy or not. Macula is
found at the centre of the retina where the incoming
rays of lights are focused. The macula is very
important and it is responsible for what we see straight
in front of us, the vision needed for full activities and
for our ability to see colour.

(a) (b)
Figure 1: (a) A Normal retina, (b) A retina showing
signs of diabetic retinopathy
Macular edema is often complication of diabetic
retinopathy. The fluid and protein deposits collect on
or under the macula of the eye, cause it to thicken the
macula portion. Fig. 1 differentiates 1(a) the normal
retinal image and 1(b) abnormal retinal image by


showing signs of diabetic retinopathy in the fundus
system. The symptom of DME was based on the HE
location with respect to the macula region. Hard
exudates have been used to grade the risk of macular
edema. In the retina, the yellow spots near the macula
are called hard exudates. The substances like lipid
break-down from the blood vessels. Usually Diabetic
macular edema (DME) can be evaluated directly or
indirectly. The manual examination (direct) is by
using Stereoscopy or optical computed tomography
images [6]. And in the other way of indirect
examination is done by the presence of hard exudates
in the retina. This indirect way is taken into an account
for the automatic assessment of the disease and the
severity level measurement in [7], [8], and [9]. The
remainder part of this paper prepared as follows. The
section II gives the literature review for the
abnormality detection. In section III, gives the brief
explanation with different algorithms and classifiers
for the processing steps. Finally, the paper is
concluded in section IV.
II. PAST DETECTION METHOD
Many techniques have been proposed for the detection
of abnormality in colour fundus images. Different
filters and classifiers have been used for the automatic
detection of exudates. These techniques help the
doctor to diagnose the disease as earlier as possible.
A. Case for automatic detection:
Silberman et al. [1] briefly discuss about a case for
automatic detection of diabetic retinopathy. In
addition it also discuss about the potential force on
early detection of DR. For the preprocessing the
global colour-balancing operation is performed. For
the SIFT feature extraction the segmentation mask is
created during preprocessing because the optic disk
and the exudates have the same intensity. They mask
the optic disk and subsequently mask the non-retinal
background component in the feature extraction.
Finally the images were trained using 2000 negative
and 1309 positive patches by the Gaussian SVM
classifier [10]. The classification score is greater than
93%. From the SIFT feature extraction of 1000
images, the SVM classifier detect that 87 images
having exudates.
B. CAD Scheme:
Hatanaka et al. [2] determine the both Hemorrhages
and exudate in ocular images. The detection of
Hemorrhages and exudates is done by the length-to-
width ratio analysis. It avoids the fluorescein
angiograms. In the detection process the blood vessels
were eliminated by examining the structure of blood
vessels. In this, the vessels in the centrelines are
extracted and eliminated to avoid the incorrectly
detected vessels. Finally, the funicular shapes were
eliminated to enhance the detection of hemorrhage. By
evaluating the lengthto-with ratio [11], the remaining
false positives are eliminated accurately. Normally the
ratio value was small when the candidate is incorrectly
detected as vessels. The detection of exudates is same
as the hemorrhage detection. Since the exudates are
segmented by thresholding technique. The only
difference is that the false positives are eliminated by
the contrast. For 109 fundus images, the detection of
exudates results with a sensitivity of 77% when the
specificity was 83%.
C. Computation intelligence based approach:
Osareh et al. [3] combines the computational
intelligence and pattern recognition with machine
learning techniques to analyse the diabetic
retinopathy. Two steps have been performed for the
pre-processing. In the first step, the colour retinal
images are normalized by using histogram
specification [12]. In the second step the local contrast
enhancement is performed to increase the contrast
level of exudates in [13]. The segmentation of retinal
image is done by using two-stage colour segmentation
algorithm based on Gaussian-smoothed histogram
analysis and FCMs clustering [14]. After segmentation
the feature is extracted by using Gabor filters based on
iris recognition. For selecting the best subset from the
input images, the genetic-based algorithm (GA) is
used for the result of better classification. The Neural
network classifier classifies the segmented regions
[15]. Over 150 images this scheme achieves
sensitivity of 96% and specificity of 94.6%.
D. Model based approach:
Li et al. [4] make use of the prior knowledge of the
retinal images. For the detection purpose first the optic
disk is localized by PCA which make use of the top-
down strategy for extract the common characteristics
among the training images. Boundary of the optic disk
is detected by Modified ASM. Then the fovea is
estimated at the centre of candidate region. A polar
coordinate system centred on the fovea is selected in
this work. The radii of the three fovea-centred circles
from the innermost to the outermost correspond to
(1/3) DD, 1DD and 2DD respectively. Finally the


exudates are detected by region growing [17]. In this
the retinal image is subdivided into 64 subimages.
Exudate detection is performed in each subimage. The
resultant sensitivity and specificity is 100% and 71%
respectively.
III. PROPOSED DETECTION METHOD
In the proposed work, the HE detection and severity
classification is done by using Naive Bayes classifier.
The proposed method has two divisions. In the first
division the exudate detection is done by using single
class classifier called Principle Component analysis
data description (PCA DD) which is one of the
existing methods. In the second division the exudate
detected lesions in the process of PCA DD are taken
as input for the clear classification of exudates and
nonexudates using Naive Bayes classifier. The reason
for migrating to second division is because of
incorrect exudate detection. Before exudate detection
some steps of operation is done on images, which is
same for both divisions. The operations on the images
are explained in step by step manner given below with
flow diagram. Here the operations need not have
preprocessing operation because the images were
taken in the database. The database images have high
resolution, high contrast and no noise. So there is no
need of preprocessing. The preprocessing is taken into
an account only for enhancing the image and prior to
computational processing. It involves removing low-
frequency surroundings noise, normalizing the
strength of the individual unit of an image and
removing reflections. The detection and severity
classification steps are shown in Fig. 2. For both
classifiers the processing steps is same. The only
difference is in the detection process.

Figure 2: Flow diagram for the detection and assessment of
DME
A. Locating and masking of optic disk and macular
region:
The images in the database are in the form of RGB
colour combination. In the RGB colour images, only
the green channel is selected for input images. The
selection of green channel as
=

()
(1)
The green channel interest denoted as I gives a clear
contrast and high intensity compared to Red and Blue
colour component. The green channel interest I forms
the input for all upcoming processing. Next the Optic
disk and macular region were detected by the intensity
variation in the pixels. The optic disc is noticeable and
brightest region, where the macular region is the
darkest region in the fundus image. The macula is the
central region of the given input image. Their
centroids are detected using [19] and superimpose
those centroid locations on the input image. The large
and bright region is located as optic disc that consist
of pixels with the highest gray levels in [20] and [21].
In the fundus image the large lesions are similar to
optic disc lead to false detection. The optic disc is
detected and masked using [22]. Subsequently the
macular region also masked same as optic disc. The
detection and masking is shown in Fig.3.
Performance Comparison
Severity Classification
Nave Bayes PCA
Detection based
Feature Selection
Motion Pattern Generation
Locating and masking of OD
and macula
Green channel
Retinal images from database


(a) (b)
Figure 3: Result of macula and OD detection (a)
Detection of OD and macula (b) Mask of OD in rectangle
and macula in circle

B. Motion pattern Generation:
The given image is transformed to an intermediate
representation called motion pattern that spatially look
up the HE presence regardless of their size. This is
followed by foundation of global features on motion
pattern for detection of HE. The images are rotated by
angle degrees in a counterclockwise direction around
its center point to induce the motion pattern. The
rotation step is -1 and maximum angle is -90.
Motion pattern I
MP
is obtained by using the union
operation as the coalescing function f. Let the given
input image I is denoted as ()
. A motion pattern I
MP

for I is derived as follows:

()
() (2)

where vector r denote the pixel location. G
N
is a
transformation representing the induced motion. Let N
be the transformed images generated by G
N
combined
using f to coalesce the sampled intensities at each
pixel location in (2). G
N
(I) is expressed as follows:
G
N
(I) = {R
n
(I)} (3)

where R is a rotation matrix. The rotation angle
n
=
n
0
with n=0,1,....N;
0
denotes the rotation step. For
the discriminability between normal and abnormal
retinal image the mean and maximum were consider
in this work. These are defined as follows:

()
(()
) (4)

(())
()

(5)

From the above two equations the mean tries to
achieve the averaging effect observed in motion blur
and the maximum tries to exploit the fact that HE
usually appear brighter than any other structures in the
background at the same radial distance. Here the
Shannons entropy is calculated for the motion pattern
I
MP
is defined as H(Y) at every point Y in the
magnitude of imageI
. The entropy is computed

over a local neighbourhood of Y to create an
entropy map. The total entropy is computed by
summing the entropy at every point Y as follows:
H
= H(I
(Y)) (6)
The discriminability d of normal and abnormal retinal
images is the difference between the entropy values
for normal and abnormal images
d = H

HMPnormal (7)
C. Feature selection:
In model construction, feature selection is the process
of selecting a subset of relevant features. Motion
pattern is well defined by using descriptor derived
from the Radon space. The radon transform method is
used for the feature selection in [9]. This provides the
rotation pattern for the mean values of the given
image. Then these mean vectors are passed to the
radon transform method to extract the rotation pattern
estimation and in the next step we extract the feature
values of the image. The radon function computes the
line integrals from multiple sources along parallel
paths in a certain direction. A projection of a two-
dimensional function f(x, y) is a set of line integrals.
The beams are spaced 1 pixel unit apart. To represent
an image, the radon function takes multiple parallel-
beam projections of the image from different angles
by rotating the source around the center of the image.
Since the transformation transform two dimensional
images with lines into a domain of possible line
parameters, where each line in the image will give a
peak positioned at the corresponding line parameters.
The radon transform of f(x, y) is computed as
P
(r) = f(x, y)(r xcos
y sin)dxdy (8)


where r is the distance from a line to the origin and
is the angle formed by the distance vector. First a
vector response for every angle is obtained by
projecting the image I
MP
and then concatenates the
responses P
for different orientations to derive the

desired feature vector. The motion pattern I
MP

enhances the spatial extent of any HE that may be
present. Due to the intensity variation of HE the
normal retina feature vector have uniform values and
the abnormal retina feature vector have several peaks
in its profile. Thus the feature vectors are used for
learning the subspace corresponding to normal
images.
D. Detection of macular edema:
For the abnormality detection two classifiers are used
in this classification work: Principle component
Analysis Data Description (PCA DD) and Naive
Bayes Classifier.
1) PCA DD: By learning normal cases, the detection
of macular edema is achieved using this type of
classification. A classification boundary is formed in
the feature space around the subspace corresponding
to normal cases. Then the new image is projected to
this feature space for the classification. If that new
image is lies within this boundary, then it is classified
as normal otherwise it is abnormal. In the PCD DD the
linear subspace is defined for the normal images. The
subspace is described by the Eigen values
corresponding to the covariance matrix of the
training set. The new case is again reconstructed as
(I
MP
)
proj
by projecting that new case to the subspace.
Based on the reconstruction error the new image is
classified to be normal. The feature vectors (I
MP
)
were projected on to six dimensions to compute the
reconstruction error. For the classification, the
reconstruction error is computed as
(
) = ((
) (
(9)

In data description of classification between normal
and abnormal images, the threshold ranging from 0 to
1 was applied on the parameter (
). In Fig.4
shows the result of PCA DD. Fig.4 (a) is the detected
lesions and Fig.4 (b) is the detected exudates of colour
fundus image.

(a) (b)
Figure 1: Result of PCA DD (a) Detected lesions (b)
Detected exudate

By using this PCA DD method we met some problems
in the detection. Those are the exudate detection gives
more false positive values, smaller exudates detection
is less, raw data is not the best form for running a PCA
and normalization needs to be applied to the data
before running PCA.
2) Nave Bayes Classifier: It involves feature
extraction and classification. Naive Bayes classifier is
a simple probabilistic classifier based on applying
Bayes theorem with strong independence
assumptions. An advantage of naive Bayes is that it
only requires a small amount of training data to
estimate the parameters (means and variances of the
variables) necessary for classification [18]. Because
independent variables are assumed, only the variances
of the variables for each class need to be
determined and not the entire covariance matrix.
In the feature extraction step, the detected lesion
region from the PCA DD is considered as possible
exudate region which is taken as input. To increase the
possibility of detecting smaller exudates, the threshold
value for filtering is kept low by design. Pixels not
lying in the exudate category are detached in
classification phase. The appearance of exudates can
be viewed as bright yellow spots which can have
different sizes and shapes having strong and sharp
edges. If there are n possible regions for image x, in
which presence of exudates can be viewed, the set of
exudates can be represented as follows X = v1; v2; v3;


_ _ _; vn. This whole set has to be processed for
detecting each exudate and non-exudate region. Every
potential candidate exudate is considered as a sample
vector input for the classification algorithm. The
classification algorithm uses certain features for
making the decisions. The feature vector includes of
area, compactness, mean intensity, mean HSV values,
mean gradient magnitude, energy, entropy and third
moment.
In the lesion identifying process, we have used the low
value of threshold by choice so that we can get most
out of the image in forms of possible exudates. The
unsure detections are eliminated in the phase of
classification. In the proposed scheme, we have used
Naive Bayes classifier [5]. Two classes are used for
classification those are R
1
= Exudate region and R
2
=
Non exudate region. The final decision of classifying
regions is made by using a supervised classification
method. The input data set is divided into subsets for
training. The classifier is trained using the earlier
created sample dataset. Bayes decision rule is used to
obtain a decision rule based on estimation from the
training set. Bayes decision rule is stated as [5].

Choose R
1
if; p (v|R
1
) P (R
1
) > p (v|R
2
) P (R
2
)
Otherwise Choose R
2
(1)

Here p (v
j
|R
i
) can be defined as the class conditional
probability Density Function and P (R
i
) is the prior
probability of class R
i
which is calculated as the ratio
of class R
i
samples in the training set.
E. Severity case of macular edema:
Considering 1 optic disk diameter from the center, is
the key interest to detect the risk of severity. The
classification is divided into three types of cases.
Those are normal case, moderate case and severe case.
If there is no HE present in the fundus image, that
image is classified as normal image otherwise it is
classified as affected image. The location of HE is not
inside macula, hence it is stated as a moderate case.
On the other hand the HE is within the macula, hence
the case is deemed severe. The severity classification
is characterized using rotational asymmetry metric by
studying the rotational symmetry of macular edema
[9].
IV. EXPERIMENTS AND RESULTS
A. Retinal images from database:
The image database is a collection of images. The
databases are publicly available with high contrast
compressed (jpeg) images [23]. The images from
these databases are taken for the evaluation purpose.
For the assessment of macular edema the training and
testing is performed on the MESSIDOR database.
MESSIDOR database consists of retinal images which
has macula as a centered on that fundus images. Over
200 images were taken for normal and abnormal
classification.

B. Detection results:
For the detection of macular edema and severity
classification the performance comparison parameters
are as follows: Sensitivity, Specificity, Precision, and
Accuracy. All the parameters are calculated by using
confusion matrix. The confusion matrix have the
following meaning in the context of our study: TP is
defined as sick people correctly diagnosed as sick and
FP is defined as Healthy people incorrectly identified
as sick. Then TN is defined as Healthy people
correctly identified as healthy and FN is defined as
Sick people incorrectly identified as healthy.
Sensitivity measures the proportion of actual positives
which are correctly identified as such that is the
proportion of a positive test, given that the patient is
ill. This can be written as Sensitivity = TP/(TP+FN).
Then Specificity measures the proportion of negatives
which are correctly identified as such that is the
proportion of negative test, that the patient is well. It
can also be written as, Specificity = TN/(TN+FP). The
Precision is the proportion of the predicted positive
cases that were correct, as calculated using the
equation: TP/(TP+FP). Finally, the Accuracy is the
proportion of the total number of predictions that were
correct. It is determined using the equation:
Accuracy(AC) = (TP+TN)/(TP+FP+FN+TN).

In Table I shows the calculation result for the
performance parameter. Table II shows the severity
classification for all three type of cases. Here the
threshold value is in percentage (p) as 10% for the S
value for normals and for the moderate case 30%.

Table 1: Performance classification for normal and
abnormal cases in MESSIDOR database
Parameters PCA DD Nave Bayes classifier
Sensitivity (%) 100 100


Specificity (%) 92 94
Precision (%) 80 84
Accuracy (%) 94 95

Table 2: Performance classification for normal and
abnormal cases in MESSIDOR database

Parameters PCA
DD
Nave Bayes
classifier
Overall
Accuracy (%)
92 95
Normal
Accuracy (%)
89.83 94.91
Moderate
Accuracy (%)
94.73 94.73
Severe
Accuracy (%)
95.45 95.45
V. CONCLUSION
In this paper, we examine towards the development of
an existing automated methods for the detection and
severity classification of diabetic retinopathy. Diabetic
retinopathy is the new cause of blindness at the age
from 20 to 74. The macular edema disease affects 10
percentages of all patients who had diabetics for 10
years or more. This paper also describes the automatic
assessment technique for the diabetic retinopathy with
new method, which helps the diabetics to diagnosis
the disease at the early stage for the prevention from
vision loss. An aggregate performance of 92%
specificity with 100% sensitivity is observed for PCA
DD. For the Nave Bayes classification 94%
specificity with 100% sensitivity is observed. Then the
accuracy for the detection is 94% and 95% for PCA
DD and Nave Bayes classifier respectively. The
Overall Accuracy for severity classification forPCA
DD is 92% and for Nave Bayes is 95%. The proposed
method reduces the effort of building CAD scheme by
removing the need for annotated abnormal images.
Moreover there is no need for either preprocessing the
original images or postprocessing the results, to
handle the false alarms. Even though the proposed
method is quite complicated but the detection is
accurate. In future, by using this motion pattern
generation and radon transformation we can apply for
the abnormal indicators such as microaneurysms,
hemorrhages, and cotton wool spots for the better
performance.
REFERENCES
[1] R. F. N. Silberman, K. Ahlrich, and L. Subramanian,
Case for automated detection of diabetic
retinopathy, Proc. AAAI Artif. Intell. Development
(AI-D10), pp. 8590, Mar. 2010.
[2] Y.Hatanaka, T. Nakagawa, Y. Hayashi, Y. Mizukusa,
A. Fujita, M.Kakogawa, K. K.M. D. , T. Hara, and H.
Fujita, Cad scheme to detect hemorrhages and
exudates in ocular fundus images, in Proc. SPIE
Med. Imag. 2007: Comput.-Aided Diagn., Mar. 2007,
vol. 6514, pp. 2M12M8.
[3] A.Osareh, B. Shadgar, and R. Markham, A
computational-intelli-gence-based approach for
detection of exudates in diabetic retinopathy images,
IEEE Trans. Inf. Technol. Biomed., vol. 13, no. 4, pp.
535545, Jul. 2009.
[4] H. Li and O. Chutatape, A model-based approach for
automated feature extraction in fundus images, in
Proc. 9th IEEE Int. Conf. Comput. Vis., Oct. 2003,
vol. 1, pp. 394399.
[5] G. H. John and P. Langley, Estimating Continuous
Distributions in Bayesian Classifiers. Proceedings of
the Eleventh Conference on Uncertainty in Artificial
Intelligence,1995. pp. 338-345.
[6] M. R. Hee, C. A. Puliafito, C. Wong, J. S. Duker, E.
Reichel, B. Rutledge, J. S. Schuman, E. A.
Swanson, and J. G. Fujimoto, Quantitative
assessment of macular edema with optical coherence
tomography, Arch. Ophthalmol., vol. 113, no. 8, pp.
10191029, Aug. 1995.
[7] C. P. Wilkinson, F. L. Ferris, R. E. Klein, P. P. Lee,
C. D. Agardh, M. Davis, D. Dills, A. Kampik, R.
Pararajasegaram, and J. T. Verdaguer, Proposed
international clinical diabetic retinopathy and diabetic
macular edema disease severity scales, Am. Acad.
Ophthalmol., vol. 110, no. 9, pp. 16771682, Sep.
2003.
[8] NIH. 2009. Facts about diabetic retinopathy disease
http://www.nei.nih.gov/health/diabetic/retinopathy.asp
[9] K. Sai Deepak and Jayanthi Sivasamy, Automatic
Assessment of Macular Edema From Color Retinal
Images, IEEE Transactions on Biomedical
Engineering, vol. 31, no. 3, pp. 766-776, Mar 2012.
[10] Zhang, X., and Chutatape, O. 2005. Top-down and
bottom-up strategies in lesion detection of background
diabetic retinopathy.In CVPR 05: Proceedings of the
2005 IEEE Computer Society Conference on
Computer Vision and Pattern Recognition (CVPR05)


- Volume 2, 422428. Washington, DC, USA: IEEE
Computer Society.
[11] O. R. Mitchell, C. R. Myers and W. Boyne, A max
min measure forimage texture analysis, IEEE
Transactions on Computers, C-2 (4), 408414, 1977.
[12] R. Gonzalez and R. Woods, Digital Image Processing.
Reading, MA: Addison-Wesley, 1992.
[13] C. Sinthanayothin, Image analysis for automatic
diagnosis of diabetic Retinopathy, Ph.D. dissertation,
Kings College of London, London,U.K., 1999.
[14] Y. Lim and S. Lee, On the color image segmentation
algorithm based on the thresholding and the fuzzy c-
means techniques, Pattern Recogn., vol. 23, no. 9, pp.
935952, 1990.
[15] C. Bishop, Neural Networks for Pattern Recognition.
London, U.K.: Oxford Univ. Press, 1995.
[16] L Vincent, Morphological grayscale reconstruction in
image analysis: applications and efficient algorithms,
IEEE Journal of Image Processing, vol. 2, no. 2, pp.
176201, 1993.
[17] R A Kirsch, Computer determination of the
constituent structure of biological images.,
Computers and Biomedical Research, vol. 4, no. 3, pp.
315328, Jun 1971.
[18] R. O. Duda, P. E. Hart, and D. G. Stork, Pattern
Classifcation. New York: Wiley, 2001.
[19] J. Singh, G. D. Joshi, and J. Sivaswamy, Appearance-
based object detection in colour retinal images, in
Proc. Int. Conf. Image Process., 2008, pp. 14321435.
[20] S. Tamura, Y. Okamoto, and K. Yanashima, Zero-
crossing interval correction in tracking eye-fundus
blood vessels, Pattern Recogn., vol. 21, no. 3, pp.
227233, 1988.
[21] Z. Liu, O. Chutatape, and S. M. Krishnan, Automatic
image analysis of fundus photograph, Proc. 19th
Annu. Int. Conf. IEEE Engineering in Medicine and
Biology Society, vol. 2, pp. 524525, 1997.
[22] G. D. Joshi, J. Sivaswamy, K. Karan, and S. R.
Krishnadas, Optic disk and cup boundary detection
using regional information, in Proc. Int. Conf. Image
Process., 2010, pp. 948951.
[23] MESSIDOR,Jun.[Online],Available:http://messidor.cr
ihan.fr/index-en php.

ACKNOWLEDGEMENT
We would like to thank the person for providing the
MESSIDOR dataset: Mr.XiweiZHANG, PhD student,
Centre for Mathematical Morphology Mines ParisTech.


CONGESTION CONTROL AND RATE BASED
SCHEDULING ALGORITHM FOR MULTIHOP
WIRELESS NETWORKS WITH ORDER OPTIMAL PER
FLOW DELAY
S.SHAHANA
1
,
Ms.K.L.NISHA
2
1,2
Department of ECE, Arunachala college of engineering for women,Nagercoil,India

ABSTRACT
Quantifying the end-to-end delay performance in
multihop wireless networks is a well-known
challenging problem. This project uses a window
based flow control and rate based scheduling
algorithm for multihop wireless networks with
fixed-route flows operated under a general
interference model with interference degree. The
proposed algorithm not only achieves a provable
throughput guarantee but also leads to explicit
upper bounds on the end-to-end delay of every
flow. The end-to-end delay and throughput
bounds are in simple and closed forms, and they
explicitly quantify the tradeoff between
throughput and delay of every flow. The proposed
algorithm is fully distributed and requires a low
per-node complexity that does not increase with
the network size. Hence, it can be easily
implemented in practice.

Keywords: multihop wireless networks , rate
based scheduling, throughput, window based flow
control
I.INTRODUCTION
The joint congestion control and scheduling
problem in multihop wireless networks has been
extensively studied in the literature. Often, each user
is associated with a non decreasing and concave
utility function of its rate, and a cross-layer utility
maximization important as well because, practical
congestion control protocols need to set
retransmission timeout values based on the packet
delay, and such parameters could significantly impact
the speed of recovery when packet loss occurs [1-6].
Packet delay is also important for multimedia traffic,
some of which have been carried on congestion-
controlled sessions.There are two major issues on the
delay-performance of the back-pressure algorithm.
First, for long flows, the end-to-end delay may grow
quadratically with the number of hops. Under the
back-pressure algorithm, if a link schedules the long
flow, the queue difference of the long flow must be
larger than the queue length q of the competing short
flow. Therefore, when the joint congestion and
scheduling algorithm converges, the queue length of
the long flow at each hop must be around H
q
,(H-
1)q,..,q and the total end-to-end backlog is of order
O(H
2
) [7-9]. By Littles law, the end-to-end delay
will also be of order O(H
2
). Note that a packet needs
at least H time-slots to reach the destination. Hence,
the optimal order should have been O(H). This
implies that the back-pressure algorithm may have
significantly larger end-to-end delay for long flows.
Second, under the back-pressure algorithm, it is
difficult to control the end-to-end delay of each flow.
The main parameter to tune a joint congestion control
and scheduling algorithm based on the back-pressure
algorithm is the step size in the queue update. A
larger step size may lead to smaller queue length.
However, a smaller step size is needed to ensure that
the joint congestion control and scheduling algorithm
converges to close-to-optimal system throughput.
Although one may use the step sizes to tune the
throughputdelay tradeoff, a change of the step size
on one node will likely affect all flows passing


through the node. Hence, it is difficult to tune the
throughputdelay tradeoff on a per-flow basis [9-15].

This project provides a new class of joint congestion
control and scheduling algorithms that can achieve
both provable throughput and provable per- flow
delay. Consider flows in a multihop network shown
in fig.1.1operating under a general interference
model with the interference degree , and each flow
is given a fixed route with H
m
hops.

Fig 1. Multihop network
A.COMPONENTS:
Algorithm consists of three main components:
window-based flow control, virtual-rate computation,
and scheduling. The main ideas of the proposed
algorithm, is to improve the end-to-end delay are as
follows. First, by using window-based flow control, it
can tightly control the number of packets inside the
network. Second, by using a rate-based scheduling
algorithm with the computed virtual rate as input to
schedule packets and do not need to wait for the
packets to accumulate before making scheduling
decisions. However, the key difficulty in analyzing
the end-to-end throughput and delay under this
algorithm is that the services at different links are
correlated. Hence, a Markov chain analysis will no
longer provide a closed-form solution. Specifically,
for any ,
m
(0,1) by appropriately choosing the
number of backoff mini-slots for the scheduling
algorithm and the window size of flow m, algorithm
can guarantee that each flow m will achieve a
throughput where the total utility of the virtual rate
allocation vector is no smaller than the total utility of
any rate h,hvector within /, where is the
capacity region. Further-more, the end-to-end
expected delay of flow m can be upper-bounded by
H
m
. Therefore, with a reasonable choice of the
parameters of the algorithm, and this scheme can
utilize a provable fraction of the total system utility
with per- flow expected delay that increases line arly
with the number of hops.
Since a flow- packet requires at least H
m
time-slots to
reach the destination, the order of the per-flow delay
upper bound is optimal with respect to the number of
hops. This proposed algorithm is fully distributed and
can be easily implemented in practice. Furthermore,
the delaythroughput tradeoff of each flow can be
individually controlled [16-18]. This is the first fully
distributed cross-layer control solution that can both
guarantee order-optimal per- flow delay and a
minimum throughput utilization close to1/ of the
system capacity under a general interference
model.Recently, there have been a number of papers
that quantify the delay performance of wireless
networks with or without congestion control. The
authors proposed methods to reduce the delay of the
back-pressure algorithm [19]. The algorithm
proposed by the authors is a shadow back-pressure
algorithm, which maintains a single first-in first-out
(FIFO) queue at each link and uses multiple shadow
queues to schedule the transmissions. This method
decouples the control information from the real
queues and hence reduces the delay. In simulation,
this algorithm seems to achieve linear delay after the
algorithm con-verges. However, at the transient
period, the real queues will still follow the shadow
queues, which leads to a large queue backlog.
B. NETWORKING
A computer network, or simply a network, is a
collection of computers and other hardware
interconnected by communication channels that
allow sharing of resources and information. Where at
least one process in one device is able to send/receive
data to/from at least one process residing in a remote
device, then the two devices are said to be in a
network. Simply, more than one computer
interconnected through a communication medium for


information interchange is called a computer
network.
Networks may be classified according to a
wide variety of characteristics, such as the medium
used to transport the data, communications
protocol used, scale, topology, benefit, and
organizational scope. Communication protocols
define the rules and data formats for exchanging
information in a computer network, and provide the
basis for network programming. Well-known
communications protocols include Ethernet, a
hardware and link layer standard that is ubiquitous
in local area networks, and the Internet protocol suite,
which defines a set of protocols for internetworking,
i.e. for data communication between multiple
networks, as well as host-to-host data transfer, and
application-specific data transmission formats.
A communication protocol is a set of rules
for exchanging information over a network. It is
typically a protocol stack , which is a "stack" of
protocols. This stack is used between the wireless
router and the home user's personal computer when
the user is surfing the web. Communication protocols
have various properties, such as whether they are
connectionoriented or connectionless, whether they
use circuit mode or packet switching, or whether they
use hierarchical or flat addressing.
C.NETWORK PROGRAMMING
Computernetwork programming involves writing
computer programs that communicate with each
other across a computer network. Different programs
must be written for the client process, which initiates
the communication, and for the server process, which
waits for the communication to be initiated. Both
endpoints of the communication flow are
implemented as network sockets; hence network
programming is basically socket programming.

D.MULTI HOP NETWORKING
Multi-hop or ad hoc, wireless networks use two or
more wireless hops to convey information from a
source to a destination. There are two distinct
applications of multi-hop communication, with
common features, but different applications.
MOBILE AD HOC NETWORKS (MANETS): A
mobile ad hoc network consists of a group of mobile
nodes that communicate without requiring a fixed
wireless infrastructure. In contrast to conventional
cellular systems, there is no master-slave relationship
between nodes such as base station to mobile users in
ad hoc networks. Communication between nodes is
performed by direct connection or through multiple
hop relays. Mobile ad hoc networks have several
practical applications including battlefield
communication, emergency first response, and
public safety systems. Despite extensive research in
networking, many challenges remain in the study of
mobile ad hoc networks including development of
multiple access protocols that exploit advanced
physical layer technologies like MIMO, OFDM, and
interference cancellation, analysis of the fundamental
limits of mobile ad hoc network capacity, practical
characterization of achievable throughputs taking into
account network overheads.Multi-hop cellular
networks: Cellular systems conventionally employ
single hops between mobile units and the base
station. As cellular systems evolve from voice centric
to data centric communication, edge-of-cell
throughput is becoming a significant concern. This
problem is accentuated in systems with higher carrier
frequencies (more path loss) and larger bandwidth
(larger noise power). A promising solution to the
problem of improving coverage and throughput is the
use of relays. Several different relay technologies are
under intensive investigation including fixed relays
(powered infrastructure equipment that is not
connected to the network backbone), mobile relays
(other users opportunistically agree to relay each
others' packets), as well as mobile fixed relays (fixed
relays that are mounted on buses or trains and thus
moving). There has been extensive research on multi-
hop cellular networks the last few years under the
guise of relay networks or cooperative diversity. The
use of relays, though, impacts almost every aspect of
cellular system design and optimization including:
scheduling, handoff, adaptive modulation, ARQ, and
interference management.
II.ALGORITHMS


A. JOINT CONGESTION CONTROL AND
SCHEDULING ALGORITHM
There are many approaches available in the literature
to solve, and most of them do not consider delay
performance. A typical optimal solution can be
obtained by a duality approach that results into the
back-pressure algorithm and a congestion-control
component at the source node. Furthermore, a
considerable amount of effort has focused on
developing low-complexity and distributed
scheduling algorithms that can replace the centralized
back-pressure algorithm and yet still achieve
provably good throughput performance. Like the
back-pressure algorithm, these low-complexity
scheduling algorithms are usually also queue-length-
based. The drawback of these approaches, however,
is that the end-to-end delay of the resulting queue-
length-based scheduling algorithm is very difficult to
quantify, under certain cases the back-pressure
algorithm can have poor delay performance. This
paper uses a window-based flow control algorithm
and a rate-based scheduling algorithm that are very
different from the back-pressure algorithm. The
solution strategy is to first approximately solve and
compute the decision vector [r
m
]. However, the
decision variables are not directly used as the rates to
inject flow- packets. For this reason, these variables
r
m
are referred as virtual rates. These virtual rates
are the control variables in a new class of rate-based
scheduling algorithms. The actual end-to-end
throughput under this algorithm will be denoted as
R
m
. For each flow, this new joint congestion control
and scheduling algorithm will guarantee both
provable throughput and provably low delay. Also,
they are fully distributed and easy to implement in
real systems.
B.VIRTUAL-RATE COMPUTATION
The equations are solved. Since the true capacity
region is of a complex form, instead of solving
directly, precise the relationship between
optimization problems
0 ,

Note that the eqn is very similar to the standard
convex-optimization problem in wire line network
with linear constraints. Therefore, it is easy to apply
the approaches. Instead of elaborating on all the
possible approaches to solve problem, it is possible to
present one well-known distributed solution.
Specifically, associate a Lagrange multiplier (the dual
variable) to each constraint.
C.virtual-Rate Computation Algorithm:
At each time t:
1) The source node of flow m updates r
m
by equation
r
m
(t)=

2) Each link updates the dual variables by equation
(t+1)=
k
(t) +
k

m
r
m
1
The variables r
m
are virtual rates, and they
are not directly used to inject flow-m packets under
proposed algorithm.The virtual rates used by the real
injection rates due to the following reasons. First,
optimization problems are formulated as if the rates
are immediately passed to all links at the same time.
In reality, a packet must traverse the links in a hop-
by-hop fashion. In order to control the end-to-end
delay, an additional flow-control algorithm is needed
to regulate this hop-by-hop packet flow. Second, the
low-complexity virtual-rate computation algorithm
did not produce the schedule for link transmission.
The scheduling algorithm is needed to compute the
schedule that can support the virtual rate vector [r
m
].
The end-to-end delay of the back-pressure
algorithm is difficult to quantify and may be poor.
Hence, in the sequel, will use very different
scheduling and flow-control components, for which
quantify both the throughput and the end-to-end
delay on a per- flow basis.
D. SCHEDULING ALGORITHM
The scheduling algorithm, which is a
modification of the low-complexity distributed
scheduling algorithm. Each time-slot consists of an


initial scheduling slot, which is further divided into F
mini-slots. The links that are to be scheduled are
selected in the scheduling slot, and the selected links
transmit their packets in the rest of the time-slot.
RATE-BASEDSCHEDULING ALGORITHM
At each time-slot t:
1) Each link L first computes Power
2) In the scheduling slot, each link then randomly
picks a backoff mini-slot (B)
3) When the backoff timer for a link expires in the
scheduling slot, it begins transmission unless it has
already heard a transmission from one of its
interfering links. If two or more links that interfere
begin transmissions simultaneously, a collision
occurs, and both transmissions fail.
4) When a link begins transmission, it will randomly
choose a passing flow m to serve with probability.
Note that this scheduling algorithm only uses virtual
rates to compute P
L
, which is different from the
queue-length-based algorithm. For simplicity, the
performance analysis will be based on this scheduling
algorithm.
WINDOW-BASED FLOW CONTROL
It is the process of managing the rate of data
transmission between two nodes to prevent a fast
sender from overwhelming a slow receiver. It
provides a mechanism for the receiver to control the
transmission speed, so that the receiving node is not
overwhelmed with data from transmitting node. Flow
control should be distinguished from congestion
control, which is used for controlling the flow of data
when congestion has actually occurred. Flow control
mechanisms can be classified by whether or not the
receiving node sends feedback to the sending
node.Flow control is important because it is possible
for a sending computer to transmit information at a
faster rate than the destination computer can receive
and process it. This can happen if the receiving
computers have a heavy traffic load in comparison to
the sending computer, or if the receiving computer
has less processing power than the sending computer.
F.WINDOW-BASEDFLOW CONTROL
ALGORITHM
It is the congestion control component. For each
flow, maintain a window W
m
at the source node, and
inject new packets to the queue at the source node
when the total number of packets for this flow inside
the network is smaller than the window size. This can
be achieved by letting the destination node send an
acknowledgement (ACK) back to the source node
whenever it receives a packet. There are two
advantages for this approach. First, for each flow,
tightly control the maximum number of packets in
each intermediate node along the route. This will
prevent buffer over flows, which is an important
issue as addressed. Second, each flows tradeoff
between throughput and delay can be individually
controlled by the window size.There is a feedback
channel from the destination node to the source node
at each time-slot. Through this feedback channel, the
destination node can send the ACK to the source
node, and the source node can then decide if it is
possible to inject an-other packet at the next time-
slot. In reality, in order to reach the source node, each
ACK will also go through the entire route in a hop-
by-hop fashion in the reverse direction. And this can
be achieved by piggybacking the ACK after each
packet transmission. This method can be analyzed
with the same approach presented, and this extra
ACK delay does not change the delay order of our
result.
RESULTS
A. CONGESTION FREE ROUTING


Fig 1.2 CONGESTION FREE ROUTING
The fig 1.2 shows congestion free routing. Networks
used here is multihop. No of nodes used in the fig is
50. The source node is shown as green and
destination node is shown as red. Initial routing is
shown as black and congestion free routing is shown
as red.
B. END TO END DELAY

Fig 1.3 end to end delay
The fig 1.3 shows the end to end delay performance.
The graph is drawn between X and Y axis. Only with
the help of proper transmissions and reception the
delay can be avoided.
C. OUTPUT OF ENERGY

Fig 1.4 Energy
D. RATE BASED SCHEDULING

Fig 1.5 Throughput
The fig 1.5 shows rate based scheduling method.
From the figure it is possible to compare the
throughput between existing methods and proposed
method. From the fig it can be inferred that , by
comparing with existing method, the proposed
method achieves better throughput.
III. CONCLUSIONS AND FUTURE WORK
The proposed system produces the
congestion free output, throughput and end to end
delay. With the help of rate based scheduling
algorithm throughput can be achieved.
In the future work, the Fuzzy Weighted
Scheduling Algorithm will be applied to improve the
performance and reduce power consumption.


REFERENCES
[1] L.Georgiadis, M.J. Neely, and L.Tassiulas, Resource
allocation and cross-layer control in wireless
networks, Found. Trends Netw., vol. 1,no. 1, pp. 1144,
2006.
[2] S. H. Low and D. E. Lapsley, Optimization flow
controlI: Basic algorithm and convergence, IEEE/ACM
Trans. Netw., vol. 7, no. 6,pp. 861874, Dec. 1999.
[3] S. Shakkottai and R. Srikant, Network optimization
and control,Found. Trends Netw., vol. 2, no. 3, pp. 271
379, 2007.
[4] X.Lin, N.B. Shroff, and R. Srikant, A tutorial on cross-
layer optimization in the wireless networks, IEEE J. Sel.
Areas Commun., vol. 24, no. 8, pp. 14521463,Aug. 2006.
[5] M. Shaked and J. G. Shanthikumar, Stochastic Orders
and Their Applications.New York: Academic, 1994.
[6] E.Modiano, D.Shah, and G Zussman,Maximizing
throughput in wireless networks via gossiping, in Proc.
ACM SIGMETRICS, 2006, pp. 2738.
[7] S. Sanghavi, L. Bui, and R. Srikant, Distributed link
scheduling with the constant overhead, in Proc. ACM
SIGMETRICS, 2007, pp. 313324.
[8] X. Lin and N. B. Shroff, The impact of imperfect
scheduling on cross-layer congestion control in wireless
networks, IEEE/ACM Trans. Netw., vol. 14, no. 2, pp.
302315, Apr. 2006.
[9] C. Joo, X. Lin, and N. B. Shroff, Understanding the
capacity region of the greedy maximal scheduling
algorithm in multi-hop wireless networks,IEEE/ACM
Trans. Netw., vol. 17, no. 4, pp. 11321145, Aug2009.
[10] L. Bui, R. Srikant, and A. L. Stolyar, Novel
architectures and algorithms for delay reduction in back-
pressure scheduling and routing,in Proc. IEEE INFOCOM
Mini-Conf., 2009, pp. 29362940.
[11] L. Huang and M. J. Neely, Delay reduction via
Lagrange multipliers in stochastic network optimization,
in Proc. WiOpt, 2009, pp. 110.
[12] L. B. Le, E. Modiano, and N. B. Shroff, Optimal
control of wireless networks with the finite buffers, in
Proc. IEEE INFOCOM, 2010, pp. 19.
[13] L. Huang and M. J. Neely, Delay efficient scheduling
via redundant constraints in multihop networks, in Proc.
WiOpt, 2010, pp. 142151.
[14] P. Jayachandran and M. Andrews, Minimizing end-
to-end delay in wireless networks using a coordinated EDF
schedule, in Proc. IEEEINFOCOM, 2010, pp. 19.
[15] M. Xie and M. Haenggi, Towards an end-to-end
delay analysis of wireless multihop nettworks, Ad Hoc
Netw., vol. 7, pp. 849861, Jul. 2009.
[16] S. Jagabathula and D. Shah, Optimal delay
scheduling in networks with arbitrary constraints, in Proc.
ACM SIGMETRICS, Jun. 2008,pp. 395406.
[17] B. Hajek and G. Sasaki, Link scheduling in
polynomial time, IEEETrans. Inf. Theory, vol. 34, no. 5,
pp. 910917, Sep. 1988.
[18] S. Sarkar and L. Tassiulas, End-to-end bandwidth
guarantees through fair local spectrum share in wireless ad-
hoc networks, in Proc. IEEE CDC, Maui, HI, Dec. 2003,
vol. 1, pp. 564569.
[8] F. P. Kelly, A. Maulloo, and D. Tan, Rate control in
communicationnetworks: Shadow prices, proportional
fairness and stability, J. Oper.Res. Soc., vol. 49, pp. 237
252, 1998.
[19] A. L. Stolyar, Large number of queues in tandem:
Scaling properties under back-pressure algorithm, Bell
Labs Tech. Memo, Oct. 2009.


Fuzzy Logic based Boiler drum Level Control and Protection
system

P.Meenu
1
,G.Priya
2
1,2
ARM College of Engineering and Technology, Maraimalai Nagar, Chennai.

ABSTRACT
A boiler system is an integral component of a
thermal power plant and control of water level
in the drum of boiler system is a critical
operational. The drum water level is the main
index in the running for circulating fluidized
bed (CFB) boiler, it indirectly reflects the
balance relation between boiler load and
water supply. If the water level is too low then
it will result in boiler drum
explosion.However, If the water level is too
high, it will affect the separator of steam water
and cause damage to the turbine. Therefore,
drum water level is too high or too low, which
will all result in the serious consequences, and
we must take a strict control. A 3 element
proportional integral derivative(PID) control
is a popular conventional approach. This
scheme works satisfactorily in the absence of any
process disturbance. when there are significant
process disturbances, the 3-element PID control
scheme does not perform well because of lack of
knowledge of proper controller gains to cope with
such disturbances. Inevitably over time and use,
PID controllers get detuned. This project presents
a model free approach ,that the performance of
existing PID control scheme is observed and
collected data is used to gain knowledge about the
process. based on this process knowledge, an
intelligent control technique, fuzzy logic
control(FLC) is developed. This project shows that
FLC gives better performance in rejecting process
disturbance when compared to 3 element PID
control scheme.

Keywords- Boiler drum , level control, PID
Controller, Fuzzy logic, Better performance

EXISTING METHOD
In existing scenario to measure the boiler drum level
more than two level transmitters are used and the
changeover or selection of transmitters to be done by
manual by the operator present. On failure of a
transmitter which is already being selected may
generate alarm and force the level control loop into
manual mode [1-5]. On alert operator should study the
condition and to take immediate step to maintain the
boiler drum level which many times not possible to
maintain the during the transfer period and carrying
boiler trip on drum level very low or very high
protection.In the existing system PI controller is used
to control the drum level in the boiler. The controller
requires proper tuning. It is possible only to tune the
controller which is suitable for the normal variations
in the system [6-8]. If any major disturbance occurs
the controller may not act faster to recover the normal
status. If the controller is tuned to act faster in the
emergency condition hence, it may leads to more
fluctuations under normal operations.

Block diagram of PID controller

Figure:1 PID Controller

Drawbacks
In the PI band control over shoot oscillation
will be more.
Time taken to reach the steady state is more.
Gain and efficiency is low.
Level control is maintained approximately.

PROPOSED SYSTEM
In this project initially it is a certain that the boiler
drum level measured throw various sources/ various
transmitters is converted into digital by analog to
digital converter ADC 0809 and fed to the computer
through printer port with the aid of printer port
interface circuit.


1) Fuzzy logic based drum level transmitter selection:
It is considered three level transmitters available for
measuring drum level and out of which any one
transmitter is selected in the software by using fuzzy
techniques such as maxima, minima, average, mid-
value etc. In this mid value technique is used to select
a level transmitter one which is considered as suitable
for control operation.

2) Required control operation to operate level control
value using fuzzy techniques:

The selected transmitter value which shows the
present level and is compared with the desired level
set point. An error is signal is arrived and hence it is
referred with the fuzzy table. From the the fuzzy table
suitable assigned fuzzy variables are processed to get
the output demand. The new demand signal is fed to
the digital to analog converter DAC 0832, where it is
converted into analog signal which is amplified by
op-amp 741 and fed to display unit and also to the
voltage to pneumatic pressure converter. Voltage to
pneumatic pressure converter produces signal outlet
air which is proportional to the voltage at its input [9-
10].
The deviation derived by the software may be positive
or negative which decides the output demand whether
to increase or decrease.A required level set point
desired to be fed by the operator else default value
stored in the software will be selected to maintain the
drum level.

3) Fuzzy controller and its tuning:
Soft based Fuzzy control logic is developed which has
got fire tuning of controls and perfect control output.
Fuzzy constants to be declared in the software may be
manipulated by manual to get fine control system.

Features
It is proposed to implement fuzzy based
controller for the above boiler diagram
process.
Fuzzy uses adaptive logic control.
Overshoot is reduced.
Accurate level control is maintained.
Steady state is reached in short span.
Process speed is very high

Comparison of PID and Fuzzy:

Figure:2 Comparison between PID & Fuzzy

BASIC FUZZY LOGIC

Fuzzy Logic
Fuzzy logic is other class of artificial intelligence, but
its history and applications are more recent than those
of expert system. Human thinking doesnt always
follow crisp YES/NO logic, but is often vague,
qualitative, uncertain, imprecise or fuzzy in
nature.Knowledge-based or rule-based systems, If-
Then rules

Fuzzy set
A fuzzy set can be defined mathematically by
assigning to each possible individual in the universe
of discourse, a value representing its grade of
membership in the fuzzy set. This grand corresponds
to the degree to which that individual is similar or
compatible with the concept representing by the fuzzy
set. In other words, fuzzy sets support a flexible
sensing of membership of elements to a set.
Fuzzy set A, is said to be subset of B if
A(x) B(x)
E.g. B=far & A=very far
A(x) 2B(x)
Crisp set
Conventional or crisp set are binary. An element
either belongs to set or doesnt.
{TRUE, FALSE} {1, 0}

Membership function
Thus linguistic variables are defined as fuzzy sets of
fuzzy subsets. A membership function is a curve that
defines how the values of a fuzzy variable in a certain
region are mapped to a member ship value (degree
of membership) between 0 and 1. the fuzzy sets can


have more sub divisions such as very very low, very
low, low, medium, high, very high, very very high
etc.,

Hardware Description
There are certain hardware required for
implementation of our project work. Hardware
components that are used such as differential pressure
transmitter, relay, pneumatic valve actuator, boiler
drum, ADC, interface, programmed computer, DAC,
power supply unit, valve driving circuit.

BLOCK DIAGRAM

Figure:3 Block Diagram of FLBBDLC
Circuit Diagram

Figure:4 Circuit Diagram of FLBBDLC

HARDWARE MODULARE

Power supply
It is the power source unit, it can be produce
5V and 12V ranges. This power supply units are
Step down transformer
Rectifier
Filter
Voltage regulator
Step down Transformer
When AC 230V 50Hz supply is applied to the primary
winding of the transformer. It can be step down into
230V to 18V ranges. The output voltage will be
pickup by the secondary winding of the transformer.
This step down voltage will be applied to rectifier
section.

Rectifier
This is the full wave bridge type rectifier. Bridge is
constructed by four diodes. It is used to convert from


AC form into DC form. This Dc output is given to
filter section.

Filter
This is the capacitive type filter. It can be filter AC
ripples in output DC voltage. It can be avoid AC
ripples.

Voltage Regulator
The voltage regulators place an important role in our
power supply. Here positive voltage regulators are
used in the power supply. It can be able to produce
fixed voltage outputs.

Differential Pressure Transmitter
DPT is the level measuring sensor as well as
transducer, Its look like monometer. Its compared
between actual value and reference value, because
generate the electrical signal.Calculation of DPT
L
T
= L
AC
-L
Re
-HP
Where
L
T
= Total level of the Boiler
L
AC
= Actual level of the Boiler
L
RE
= Reference level of the boiler
HP = Head Pressure

Analog To Digital Convertor
It is the major part of control scheme. Here this
convertor can be convert analog quantity into digital
quantity signals. ADC 0809 has 8 channels of analog
inputs. This ADC function block is shown in the
figure.

Optocoupler
One of the simples optoisolated output circuit for
parallel port is the following 4N33 based circuit.

Figure:5 Optocoupler
The 4N33 optocouplet device has a Darlington output
transistor that is capable of driving up to 30 mA of
load safely. The maximum voltage on the output side
is 30V. The input to output isolation can handle up to
1500V voltage. You connect the input side to the
parallel port output pin you want to use for the
controlling. Then you connect the input - side to
parallel port ground pin. You can expect to get
something like 10 mA of drive capacity on output
(maybe more if you are lucky to have a coupler with
high CTR and parallel port with high output current).
The circuit can be built also using 4N32 optocoupler
that is very similar to 4N33.
Relay Unit
The circuit can handle relays which take currents up to
100 mA and operate at 12V or less. The circuit need
external power supply which has the output voltage
which is right for controlling the relay (5..24V
depending on relay). The transistor does the switching
of current and the diode prevent spikes from the relay
coil form damaging your computer (if you leave the
diode out, then the transistor and your computer can
be damaged). The circuit can be also used for
controlling other small loads like powerful LEDS,
lamps and small DC motors. Keep in mind that those
devices you plan to control directly from the transistor
must take less than 100 mA current.
WARNING: Check and double check the circuit
before connecting it to your PC. Using wrong type or
damaged components can cause you parallel port get
damaged.

Feed Water Control Valve
Pneumatic Actuator is Control to Feed Water Control
Valve. The Valve Operating range is 5 to 25psi. It is a
diaphragm type valve .

FUZZY SIMULATION

It is essentially to know the difference between the
fuzzy set and crisp set. The set of the universe X can
accommodate the degree of membership is termed as
Fuzzy Set. For example, Is the boy intelligent? For
the answer need not be Yes or No. It may consists of
variety of Linguistics variables.

Simulation Block of Fuzzy Scheme


Figure :6 Functional Block of Fuzzy System
Error Signal
The error signal which compares the reference or set
point input signal with feedback or measured signal
due to which it produces error. The error signal is used
to correct the deviation of the output with respect to
desired value.

Fuzzification
The process or plant or sensor normalized out. It is in
the form of crisp. The crisp values are that can be
converted into fuzzy value by the use of fuzzification
part. Here Intution method is used.

Linguistics Variables:
Linguistics Variables are take as many region or
condition. The rule base table show bellow.

Fuzzy rule based table
Table:I Fuzzy rule based table

Linguistics
Variables
Extremely high
Very very high
High
Medium
Low
Very low
Very very low
Extremely low

Defuzzification
The output is product by the fuzzy logic controller. It
is in the form of fuzzy value. The fuzzy Valves are
that can be converted into crisp value by the
Defuzzification block. Here Centroid method is
used.

SOFTWARE DESCRIPTION

Software Module
Fuzzy System is simulated by C Graphics
platform and Rule Base is Programmed in Software
language. This is work in DOS Mode (Operating
System not needed).

Minimum System Requirements
1G Hz Processor(Intel or AMD)
128MB RAM
16xSpeed CD-Drive
Parallel Port
15inch Monitor

Visual View of FLBBDLC

Figure:7 Visual View of FLBBDLC

RESULT
Boiler Drum level is obtained in our project is based
on reference value of set point and One of set point
value given below. The drum level output wave is
shown in the figure.


SET POINT IS -20
Figure:8 Output Response of Drum Level

In our project the level is maintained by the set point
and level is controlled with out any oscillation or
overshoot
Hardware Module

Figure :9 Fuzzy logic based boiler drum level control

Model of the Boiler Drum

Figure:10 Boiler Drum

REFERENCES

1) Amdani.E.H. (1977). Application of fuzzy logic to
approximate reasoning using linguistic synthesis,
7UDQVDFWLRQV RQ &RPSXWHUV
&___(12): 11821191.
2) Adaptive fuzzy control of drum level in a boiler
system by Vanlandingham H.F,Tripathi N.D,
copyright @ 2008 IEEE.
3) Astrom, K., Hang, C., Persson, P. and Ho,W.
(1992). Towards intelligent PID control,
$XWRPDW_LFD __(1): 19.
4) Astrom, K. J. and Hgglund, T. (1995). 3,'
&RQWUROOHUV _ 7KHRU\_ 'HVLJQ_ DQG
7XQLQJ, seconded, Instrument Society
ofAmerica, 67Alexander Drive, PO Box 12277,
Research TrianglePark, North Carolina 27709,
USA.
5) Boiler Control july28, 2005, Eurotherm IDC.
6) Drum level boiler control
Jan03,2006,EurotharmIDC.
7) Franksen, O. I. (1978). Group representation of
finite polyvalent logic, LQ A. Niemi (ed.), 3UR_
FHHGLQJV _WK 7ULHQQLDO: RUOG
&RQJUHVV, International federation of automat
Paragon, Helsinki.
8) Jantzen, J. (1995). Array approach to fuzzy logic,
)X]]\ 6HWV DQG 6\VWHPV __: 359
370.Kaufmann, A. (1975). , QWURGXFWLRQ
WR WKH WKHRU\ RI IX]]\ VHWV, Academic
Press, New York.
9) Jantzen, J. (1998). Design of fuzzy controllers,
RQOLQH GHVLJQ_, Technical University of
Denmark: Dept. of Automation,
http://www.iau.dtu.dk/ jj / pubs. Lecture notes, 27
p.
10) Kiszka. J.B, Kochanska,M.E. and Sliwinska.D.S.
(1985). The influence of some fuzzy implication
operators on the accuracy of a fuzzy model,) X]]\
6HWVDQG 6\VWHPV __: (Part1)111128; (Part
2) 223 240



Temperature rise estimation in a 420 kV GIS bus bar
considering skin and proximity effects
1
Bavisha T,
1
Usa S,
2
Ucchintala Ravindra,
3
Santosh Kumar A

1
Department of Electrical and Electronics Engineering, College of Engineering Guindy, Chennai, India.
2,3
Alstom T&D India Ltd., Padappai, Chennai 620006,India

ABSTRACT
Gas Insulated Switchgear should carry high
current permanently. The high current creates
ohmic losses in the current carrying parts. The
heat from the losses increases the temperature of
the current carrying parts due to which their
resistance increases. This will result in a thermal
runaway condition resulting in failure of GIS.
Hence the temperature rise on the current
carrying parts should not exceed a maximum limit
which is defined by standards. Thus the current
carrying capacity is limited by the maximum
operating temperature. Moreover the capital cost
of GIS depends upon the current carrying
capacity. Hence it is necessary to predict the
temperature rise accurately. In this paper, the
temperature rise in a 420 kV GIS bus bar is
estimated using a theoretical model. The
theoretical model is in line with the publication of
CIGRE working group 21.12 which is meant for
the calculation of continuous current rating in
compressed gas insulated cables. However a
different principle and pattern that suits GIS bus
duct is adapted. The temperature rise estimated
using the theoretical model shows good agreement
when compared with the measured temperature
rise.
Keywords: bus bar, power loss, proximity, skin
effect, temperature.
I. INTRODUCTION
Gas Insulated Substation (GIS) is an
electrical substation in which the live parts are
contained in an external metal enclosure with sulfur
hexafluoride (SF6) gas as the insulating medium. It
occupies only 10% of the space required by a
conventional Air Insulated Substation (AIS).This
ratio reduces further as voltage level increases. Other
advantages include improved operator safety and
higher reliability during operation.
In gas insulated switchgear, the current
carrying conductor is enclosed in concentric metallic
enclosure intended to contain the pressurized
insulating gas. The cross sectional view of conductor
and enclosure is shown in Fig 1.An alternating
current flowing through the conductor produces an
alternating magnetic field. The magnetic field
generated by the conductor induces a current in the
external earthed enclosure. These currents produce
joules heating loss which in turn increases the
temperature of both conductor and enclosure. The
skin and proximity effects increase the losses further.
The temperature rise on the current carrying parts
should not exceed a maximum value, beyond which
thermal runaway occurs resulting in the failure of
GIS. Thus the current carrying capacity is limited by
the maximum operating temperature. Hence the
knowledge of temperature profile is important to
understand the performance of GIS and to improve its
design.

Fig 1.Bus bar conductor and enclosure
Due to the advances in computer technology and the
evolution of finite element (FE) model, the FE
technique which solves electromagnetic and thermal


fields has been used for such problems [4],[5],[6].The
difficulty in this technique lies in determining the
convection heat transfer coefficient at the solid-gas
interface. The heat transfer coefficient depends upon
the geometry, temperature and material property. A
coupled finite element and analytical technique has
been used which involves the calculation of heat
transfer coefficient by iterative analytical technique
[2],[3].Uncoupled field analysis where two fields are
solved separately, could not take into account of the
interrelationship between the two field parameters
like temperature dependent resistivity. Therefore
fully coupled field analysis that repeatedly solves the
two fields has been used. But this technique is time
consuming [4].
In this paper a theoretical model to estimate
the temperature rise in a 420 kV GIS bus bar is
developed. The publication of CIGRE working group
[1] is meant for the calculation of continuous current
rating in a single core compressed gas insulated
cables. Since the gas insulated cables and GIS bus
duct are similar in construction, a theoretical model
in line with the CIGRE document is developed to
estimate the temperature rise. However the principle
and pattern that suits GIS bus duct is adapted. The
theoretical model mainly concerns the skin effect,
proximity effect, thermal resistance of gas insulation
and thermal resistance of surrounding ambient. The
accuracy of the developed theoretical model is
verified by comparing with the measured
temperature.
II. ALTERNATING CURRENT RESISTANCE
The alternating current resistance per unit length of
the conductor or outer enclosure is given by

(1)
is the alternating current resistance of the
conductor tube at its maximum operating
temperature, is the direct current resistance of tube
at 20 , y is the coefficient of skin effect, is the
temperature coefficient of electrical resistivity at
20 per 1K temperature difference, is the
maximum operating temperature of the conductor or
the enclosure.
III. SKIN-PROXIMITY EFFECT
Skin and proximity effects are the major source of
losses in transformer and inductor designs, as well as
in AC power distribution systems composed of
separate, round conductors. They cause a non
uniform current distribution with an increase in loss.
A. Skin Effect
The skin effect corresponds to the uneven distribution
of the time-varying current in a conductor. The AC
distribution causes the conductor resistance to exceed
its DC value and produces higher losses. Fig.2 shows
the non uniform current distribution pattern on the
current carrying conductor due to skin effect

Fig.2 Non uniform current distribution due to skin effect
The skin depth equation is given as

(2)
f is the frequency (Hz), is the absolute permeability
(H/m), is the conductivity (S/m).



B. Proximity effect:
The AC current flowing in two round, parallel
conductors is not distributed uniformly around the
conductors. The magnetic fields from each conductor
affect the current flow in the other, resulting in a non-
uniform current distribution, which in turn, increases
the apparent resistance of the conductors. This is
called proximity effect.

Fig 3a.
Conductors carrying
current in
same direction
Fig 3b. Conductors
carrying current in
opposite direction
Fig 3a,3b .Illustrates the non uniform current distribution
when two current carrying conductors are in proximity.
C. Coefficient of skin proximity effect:
The coefficient of skin and proximity effect for the
inner conductor is given by
(3)
The coefficient of skin and proximity effect for the
outer tube is given by

(4)
is the thickness of inner tube , is the thickness
of outer tube, is the external diameter of inner
tube, is the external diameter of outer tube,
, are parameters that depend
upon the value of z. The parameter z is given by
(5)
is the electrical resistivity at direct current and
maximum operating temperature.
IV. PERMISSIBLE CURRENT
The permissible current is calculated from
the formulae based on the publication of CIGRE
working group 21.12.However the parameters that do
not apply to the GIS are not considered.
(6)
is the current in one conductor(inner tube), is
the alternating current resistance of inner tube at its
maximum operating temperature, is the thermal
resistance of the insulation, is the thermal
resistance of the surrounding ambient, is the
permissible temperature rise of inner tube above
ambient, is the loss factor due to losses in the outer
tube (enclosure).
V. HEAT TRANSFER MECHANISM
Heat transfer takes place by conduction,
convection and radiation. The current carrying
conductor creates power loss in the form of heat. The
generated heat is transferred from the conductor to
the enclosure by convection and radiation. Moreover
the induced current flowing through the enclosure
creates heat. This heat is transferred to the outer
atmosphere via convection and radiation.
VI. THERMAL RESISTANCE
Thermal resistance is a heat property and is
a measurement of a temperature difference by which
an object or material resists a heat flow.
A. Thermal resistance between conductor and
enclosure
Heat losses transmitted from the conductor by
radiation are


=
(7)
Heat losses transmitted from the conductor by
convection are

8)
Thermal resistance between conductor and enclosure
= (9)
is the internal diameter of the outer tube, is
the maximum operating temperature of inner tube,
is the maximum operating temperature of outer tube,
is the temperature of the ambient air, is the
emissivity coefficient of the inner tube, is the
emissivity coefficient of the inner surface of outer
tube, is the gas pressure. is equal to 11.3 if sf6
gas is used as insulating gas whereas it is equal to
5.83 if nitrogen is used as insulating gas.
B. Thermal resistance of enclosure
Heat losses transmitted from the enclosure by
radiation are

(10)
Heat losses transmitted from the enclosure by
convection are

(11)
Thermal resistance of enclosure is

= (12)
is the external diameter, is the temperature
of the outer enclosure, is the emissivity
coefficient of the outer surface, e is the factor
permitting to take into account of proximity
effect of adjacent conductor by means of the
formula
(13)
is the external diameter of enclosure and s is the
axial separation of conductors.
VII. METHODOLOGY
Initial temperature of both conductor and
enclosure was assumed. Maximum allowed
temperature rise is taken as initial temperature. As
per standard IEC 62271-1 the maximum allowed
temperature is 65C for the conductor and 40C for
the enclosure for 40C ambient temperature. Heating
losses, permissible current and ac resistance are
calculated. The losses are substituted in the energy
balance equation in each iteration. The temperature
corresponding to the heating losses that satisfies
energy balance equation is the maximum temperature
rise. This methodology is implemented in the form a
simulation program.

Start
Initialize Tc
Initialize Te
Energy balance equation
Pc
= +
Decrement Te
Calculate alternating
resistance, current and heat
losses


Tc is the temperature of the conductor, Te is the
temperature of the enclosure, Ta is the ambient
temperature.
VIII. ENERGY BALANCING EQUATION
The energy balance equation is given by
Pc = + (14)
Pc + Pe = (15)
Pc is the power loss in the conductor and Pe is the
power loss in the enclosure.
IX. VALIDATION OF METHODOLOGY
The temperature rise in a 420 kV gas insulated bus
bar is estimated using the proposed method. Fig 4
shows the cross-sectional view of 420 kV single core
three phase GIS bus bar model.

Fig.4.cross sectional view 0f 420 kV GIS
The conductor and enclosure are made of Aluminum
alloy. Table I shows the specification of the 420kV
bus bar.
Table I. Specification of 420 kV GIS bus bar
Parameter Conductor Enclosure
Maximum allowed
temperature rise C)
65 40
Ambient temperature
(C)
30
Frequency (Hz) 50
Rated current(A) 4000
To check correctness of the used methodology the
calculated temperature rise is compared with the
measured temperature rise. The measured
temperature rise is the maximum temperature rise
measured during the temperature rise type test.
(CERDA test report n7599).
Table II shows the comparison of calculated and
measured temperature rise.
Componen
t
Analytical
Temperatur
e
Measured
Temperatur
e
Percentag
e
Deviation
Conducto
r
84 (C) 79.68 (C) 5.42%
Enclosure 53 (C) 53.3 (C) 0.005%
Table II. Comparison of calculated and measured
temperature rise
The table III shows the comparison of temperature
rise calculated temperature rise without considering
skin-proximity effect with measured temperature rise.
Table III. Comparison of temperature rise calculated
temperature rise without considering skin-proximity effect
with measured temperature rise.
Component
Analytical
Temperatu
re
Measured
Temperatur
e
Percentag
e
Deviation
Conductor 86 (C) 79.68 (C) 7.93%
Enclosure 55 (C) 53.3 (C) 3.18%

X. CONCLUSION
Temperature rise in a gas insulated bus bar
is a critical design parameter. A theoretical model in
line with the publication of CIGRE working group
Te > Ta
Decrement Tc
Tc > Ta
End
yes
yes


21.12 to estimate the temperature rise in a 420 kV
GIS bus bar is developed. The temperature rise
estimated using the theoretical model shows good
agreement when compared with the measured
temperature rise. The results are found to be more
accurate since the skin and proximity effects are
considered.
REFERENCES

[1] CIGRE Working group 21.12., Calculation of
the continuous rating, compressed gas insulated
cables in still air with no radiation, Electra No
100,pp. 65-76, 1985.

[2] S. W. Kim, H. H. Kim, and S. C. Hahn, Coupled
finite-element analytic technique for prediction of
temperature rise in power apparatus, IEEE
Trans. on Magnetics., vol.38, no.2, pp. 921-924,
2002.

[3] J.K.Kim, S.C.Hahn, K.Y.Park, H.K.Kim,
Y.H.Oh, Temperature Rise Prediction of EHV
GIS Bus Bar by Coupled Magneto-thermal Finite
Element Method, IEEE Trans. Magnetics, Vol.
41, No. 5,pp. 1636-1639, May 2005.588

[4] J.H. Yoon, H.S. Ahn, J. Choi, I.S. Oh, An
Estimation Technology of Temperature Rise in
GIS Bus Bar using Three-Dimensional Coupled-
Field Multiphysics, Proceedings of the IEEE
ISEI, 2008, 432-436

[5] Y. Li, S.L. Ho, N. Wang, and J. Guo
,Calculations of Electromagnetic Field and
Thermal Problem in an Isolated Phase Bus by
Using FE Model IEEE 2008 .

[6] Kim, H.K.; Oh, Y.H.; Lee, S.H ," Prediction of
temperature rise in gas insulated bus bar using
multi-physics analysis, IEEE Transmission &
Distribution Conference & Exposition: Asia and
Pacific, 2009.

[7] B. Novk, L. Koller, Steady-state Heating of
Gas Insulated Busbars ,IEEE 2008

[8] K. Itaka, T. Araki, and T. Hara, Heat transfer
characteristics of gas spacer cables, IEEE Trans.
P.A. , vol. 97, Sept./Oct. 1978



Secure Ranking Prediction Based On Qos in Cloud Services

1
P. Jenefer Liban,
2
R. Arun Sendrayan,
3
B.Ayyappan
1,2
Dept of Information technology, Jeppiaar Engineering College, Chennai, India
3
Asst.Prof/ Dept. of Information technology, Jeppiaar Engineering College, Chennai, India

ABSTRACT
Cloud computing is one of the current research
area. So many organizations started to offer the
cloud services and it is very difficult for the
customers to choose the best one. QoS rankings
provide valuable information to select from a set of
equivalent services. This method provides ranking
based on past users experience. Two QoS ranking
prediction algorithms are used to predict the QoS
rankings. In the proposed work the feedback
method is used to predict the ranking based on the
likes given by the end users. The user can also able
to send suggestions through comments along with
the feedback to improve the quality of the services
by the provider. It also contains a security
implication using elliptical curve cryptography to
encrypt and Decrypt the feedback in order to
prevent it from the hackers. An accurate ranking
prediction can be done using our feedback method.

Keywords: Qos, Feedback, Security, cloud service,
rank prediction

1. INTRODUCTION

The cloud involves a large number of
computer systems connected through a real-time
communication network such as the Internet. It also
refers to network-based services which are provided by
real server hardware, which is in fact served by a
virtual hardware, simulated by software that runs on
one or more real machines [1-3]. The name actually
comes from the common use of a cloud-shaped symbol
as a perception for the complex infrastructure it
contains in system diagrams. Cloud computing
providers generally offer their services as several
fundamental models such as an infrastructure as a
service (IaaS), platform as a service (PaaS), and
software as a service (SaaS) [4].Here IaaS is the most
basic one and each higher model succeeds from the
details of the lower ones. Client-side cloud service
performance is influenced by the unpredictable Internet
connections of the user. Therefore, different cloud
applications may receive various levels of quality for
the same cloud service. Also, the QoS ranking of cloud
services for a user cannot be transferred directly to
another user, because the locations of the cloud
applications are different. Personalized cloud service
QoS ranking is thus required for different cloud
application and also which should depend on the
feedback given by the user [5-7].
2. USER FEEDBACK

Feedback from customers is one of the best
way to help growing and expanding the products and
services. Obtaining feedback from the customers and
applying it efficiently into the business can make a lot
of difference. It can also help you in recovering from
flaws in our business. For predicting and portraying the
ranking for the cloud services feedback from the end
users will be collected along with their suggestions for
such services to Rank the Quality of the Service. So a
request is send to the users to get the feedback,
suggestions on their usage of services. The service with
a large number of positive feedbacks tops the list. The
service with the lowest ranking has the option to
improve their service based on the suggestions given
by the active users. The feedback for every service
used is then send to the cloud service provider by the
user. The feedback is based on the likes and comments.
The cloud service with maximum number of likes will
be at the top of the ranking. When a user request for
the particular service the services are listed in the
ascending order of predicted rank.
www.ijrde.com


3. SECURITY USING ECC ALGORITHM

Elliptic curve cryptography (ECC) is a public
key cryptography based on the algebraic structure of
elliptic curves over fields. Public-key cryptography is
actually based on the intractability of certain
mathematical problems. Early public-key systems are
secure by assuming that it is difficult to factor a large
integer composed of two or more large prime factors.
For elliptic curve based protocols, finding the discrete
logarithm of such random elliptic curve element with
respect to publicly known base point is a challenge.
Security depends on the mathematical function and
whose inverse is impossible to calculate the feedback
sent from the users system is thus secured using ECC
algorithm. This ensures that no hacker will disrupt the
feedback from the authenticated users. Elliptic Curve
Cryptography (ECC) will be used for secure
transmission of feedbacks and suggestions which
ensures its security from data change.
Fig.1 User Feedback System

4. PROPOSED ARCHITECTURE

In our proposed work the feedback
system is used to predict the ranking which is based on
the likes of the end users. The user can also able to
send their suggestions along with the feedback to
improve the Quality of the Services (QoS). We also
provide a good security using elliptical curve
cryptography to encrypt and decrypt the feedback and
comments given by the user in order to prevent the
Hackers take the advantage. Here the ranking is done
Power and Energy Development (MEPED) 2014
C ALGORITHM
Elliptic curve cryptography (ECC) is a public-
key cryptography based on the algebraic structure of
key cryptography is
actually based on the intractability of certain
key systems are
ecure by assuming that it is difficult to factor a large
integer composed of two or more large prime factors.
For elliptic curve based protocols, finding the discrete
logarithm of such random elliptic curve element with
t is a challenge.
Security depends on the mathematical function and
whose inverse is impossible to calculate the feedback
sent from the users system is thus secured using ECC
algorithm. This ensures that no hacker will disrupt the
icated users. Elliptic Curve
Cryptography (ECC) will be used for secure
transmission of feedbacks and suggestions which
ensures its security from data change.

Fig.1 User Feedback System
4. PROPOSED ARCHITECTURE
In our proposed work the feedback and suggestion
system is used to predict the ranking which is based on
the likes of the end users. The user can also able to
send their suggestions along with the feedback to
improve the Quality of the Services (QoS). We also
elliptical curve
cryptography to encrypt and decrypt the feedback and
comments given by the user in order to prevent the
Hackers take the advantage. Here the ranking is done
according to the previous user likes and comments.
Ranking is thus predicted by th
QoS and hence the quality could be increased by the
service providers accordingly. Elliptic Curve
Cryptography (ECC) is used to ensure security for
feedback

Fig.2 Secure Feedback Architecture
5. CONCLUSION
The ranking accuracy can be improved by getting the
feedback from the end users in the form of likes and
comment. The users can also able to send their suggestions
along with the feedback to improve the Quality of Service
(QoS). Based on the feedback of privileged users the
ranking prediction is done for the set of functionally
equivalent services. The important enhancement we have
done in this work is providing a good security to the
feedback system. We provide a security mechanism for the
system to protect it from the hackers who
change the comments and feedback which will results in a
false rating of the services. In future, enhancement can be
made to increase the speed of ranking prediction. Along
with likes and comments dislikes can also be added to
moderate the service rating.
REFERENCES

[1] M. Deshpande and G. Karypis, Item
Recommendation, ACM Trans. Information System, vol.22,
no. 1, pp. 143-17

[2]QOS ranking prediction for cloud services Zibinzheng,
member, IEEE, Xinmiaowu, yileizhang, student Member,
IEEE, MichaelR.Lyu, Fellow, IEEE, and Jianmin wang.
268 | P a g e
according to the previous user likes and comments.
Ranking is thus predicted by the user suggestions on
QoS and hence the quality could be increased by the
service providers accordingly. Elliptic Curve
Cryptography (ECC) is used to ensure security for

Fig.2 Secure Feedback Architecture
be improved by getting the
feedback from the end users in the form of likes and
comment. The users can also able to send their suggestions
along with the feedback to improve the Quality of Service
(QoS). Based on the feedback of privileged users the
g prediction is done for the set of functionally
equivalent services. The important enhancement we have
done in this work is providing a good security to the
feedback system. We provide a security mechanism for the
system to protect it from the hackers who may tend to
change the comments and feedback which will results in a
false rating of the services. In future, enhancement can be
made to increase the speed of ranking prediction. Along
with likes and comments dislikes can also be added to
[1] M. Deshpande and G. Karypis, Item-Based Top-n
Recommendation, ACM Trans. Information System, vol.22,
[2]QOS ranking prediction for cloud services Zibinzheng,
member, IEEE, Xinmiaowu, yileizhang, student Member,
IEEE, MichaelR.Lyu, Fellow, IEEE, and Jianmin wang.


[3] K.J. arvelin and J. Kekalainen, Cumulated Gain- Based
Evaluation of IR Techniques, ACM Trans. Information
Systems, vol. 20, no. 4, pp. 422-446, 2002.

[4] P.A. Bonatti and P. Festa, On Optimal Service
Selection, Proc. 14th Intl Conf. World Wide Web (WWW
05), pp. 530-538, 2005.

[5] J.S. Breese, D. Heckerman, and C. Kadie, Empirical
Analysis of Predictive Algorithms for Collaborative
Filtering, Proc. 14th Ann. Conf. Uncertainty in Artificial
Intelligence (UAI 98), pp. 43-52, 1998.

[6] R. Burke, Hybrid Recommender Systems: Survey
and Experiments, User Modeling and User-Adapted
Interaction, vol. 12, no. 4, pp. 331-370, 2002.

[7] W.W. Cohen, R.E. Schapire, and Y. Singer, Learning to
order things, J. Artificial Intelligent Research, vol. 10, no. 1,
pp. 243-270, 1999.

.



Design of Wind Driven PMSG Based Z-Source Inverter
fed Three Phase load for Stand-Alone Applications

G.Arthiraja
1
, M. Ammal Dhanalakshmi
2
, Dr. M. Sasikumar
3
1,2
PG Scholar,
3
Professor,Head of the Department EEE
Jeppiaar Engineering College, Chennai.

AbstractThis paper presents the development of design,
modeling and simulation for variable speed wind turbine
coupled PMSG based ZSI are simulated through
computer software tool using MATLAB/SIMULINK. A
variable wind speed turbine coupled Permanent Magnet
Synchronous Generator with power electronics interface
is modeled for dynamic simulation analysis. The
MATLAB/SIMULINK is provided to implements the
wind driven PMSG based ZSI for stand-alone application
components models and equations. Controllable
Impedance source inverter strategies are intended for
capturing the maximum power under variable speed
operation and maintaining reactive power generation at a
pre-determined level for constant power factor control or
voltage regulation control. Control schemes for both wind
turbine and Permanent Magnet Synchronous Generator
are constructed by user-define function provided in the
simulation. Simulation case studies provide the variable
speed wind Permanent Magnet Synchronous Generator
dynamic performance for changes in different wind speed.
This control scheme of this model can be employed to
regulate the real power, reactive power, generated voltage
and generated speed at different wind speed in the power
system. Simulation results of this model can be validate
the real power, reactive power, generated voltage and
generated speed at different wind speeds in the power
system. Its simulations results are presented.

Index TermsWind turbine, variable speed, Permanent
Magnet Synchronous Generator, Impedance source
inverter, Power electronics interface, Reactive power
control.
I. INTRODUCTION
Wind energy generation equipment is most
often installed in remote, rural areas. Wind energy has
been the subject of much recent research and
development. In order to maximize the wind energy
capture, many new wind farms will employ variable
speed wind turbine. PMSG (Permanent Magnet
Synchronous Generator) is one of the components of
Variable speed wind turbine system. PMSG offers
several advantages when compared with fixed speed
generators including speed control. Many works have
been proposed for studying the behavior of PMSG
based wind turbine system connected to the load. Most
existing models widely use PWM technique for three
phase PWM inverter and the output of the inverter is
fed to load here Induction motor is acting as a load.
Wind electrical power system are recently getting lot of
attention, because they are cost competitive,
environmental clean and safe renewable power sources,
as compared fossil fuel and nuclear power generation
capability of design, modeling, simulating and
analyzing the dynamic performance of a variable speed
wind energy conversion system using
MATLAB/SIMULINK. The modeled system includes a
fixed-pitch type wind blades, a direct-drive Permanent
Magnet Synchronous Generator without a gear-box,
and a controllable power electronics system, which
consists of a six-diode rectifier and three phase inverter.
The entire schematic diagram of the modeled wind
generation is shown in Fig. 1. Models of the elements
and the system control scheme are proposed in the form
of mathematical equations and graphical control blocks
and implemented in MATLAB/SIMULINK [2]. The
simulation results demonstrate the modeling work
provide a reliable and useful simulation tool for
evaluating the dynamic performance of a variable speed
wind turbine integrated into power system.

Fig. 1 Schematic representation of modeled VSWT coupled
Permanent Magnet Permanent Magnet Synchronous Generator.



II. MATLAB/SIMULINK BASED
MODELING

The variable speed wind turbine model consists of the
following components.
- Wind model
- Wind turbine and control
- Permanent Magnet Synchronous Generator
- Rectifier and inverter

Fig. 2 Components of a VSWT coupled Permanent Magnet
Synchronous Generator MATLAB/SIMULINK simulation model.

Fig.2 depicts the component blocks Components of a
VSWT coupled Permanent Magnet Synchronous
Generator Matlab/Simulink simulation model. For
modeling the shaft and Permanent Magnet Synchronous
Generator, models provided by the Matlab/Simulink are
used, and models of the wind speed, the wind turbine,
power electronics block and the control block are built
into the Matlab/Simulink.

A. Wind Model
A wind model selected for this study is a four-
component Mode l [3], and can be described by
equation (1).

VWIND = VBASE + VGUST + VRAMP + VNOISE (1)
Where,
VBASE = base wind speed [m/s]
VGUST = gust wind component [m/s]
VRAMP = ramp wind component [m/s]
VNOISE = noise wind component [m/s]
The base component is a constant speed and wind gust
component can be usually expressed as a sine or cosine
wave function [4]. In this simulation, wind speed can be
representing the constant block in Matlab/Simulink.

B. Wind Turbine

The wind turbine is described by the following equation
(2), (3) and (4)

(2)

(3)

(4)

Where = tip speed ratio
M = blade angular speed [mechanical rad/s]
R = blade radius [m]
VWIND = wind speed [m/s]
PM = mechanical power from wind blades [kW]
l = air density [kg/m3]
CP = power coefficient
TM = mechanical torque from wind blades [N-m]

The mechanical torque obtained from equation (4)
enters into the input torque to the Permanent Magnet
Synchronous Generator, and is driving the generator. CP
may be expressed as a function of the tip speed ratio
(TSR) given by equation (2) [5].

(5)

Where is the blade pitch angle. For a fixed pitch
type the value of is set to a constant value.

C. Permanent Magnet Synchronous Generator

The Matlab/Simulink provides a fully developed
synchronous Permanent Magnet Synchronous
Generator model, which is based on generalized
machine theory [2] and with this model both sub-
transient and transient behavior can be examined. It is
considered that the Permanent Magnet Synchronous
Generator is equipped with an exciter identical to IEEE
type 1 model [6]. The exciter plays a role of meeting
the dc link voltage requirement. Since the Permanent
Magnet Synchronous Generator is a direct drive type
with low speed and a high number of poles, the wind
turbine and the generator are rotating at the same
mechanical speed via the same shaft. Therefore, shaft
dynamics can be characterized by a swing equation on a
single mass rotating shown in equation (6). The shaft


dynamics and the rotating mass can be represented by
multi-mass torsional shaft model of Matlab/Simulink,
which can be easily interfaced with the synchronous
machine model
(6)

Where
JM = a single rotating inertia [kg-m2]
TE = electric torque produced by generator [N-m]
D = damping [J-s/rad]

In variable speed operation, the rotating speed of the
wind generator is not consistent with the electrical
synchronous speed of the electric network and
generally much slower than the speed. The electrical
base frequency of the machine in the built-in models
must be set to a value corresponding to the rated
mechanical speed of the wind turbine specified by a
manufacturer or a designer. Equation (7) and (8) give
the value for the electrical base speed of the
synchronous machine w
B..

(7)

(8)

Where
f
B
= electrical base frequency of the generator [Hz]
P = number of poles
RPM
TUR
= mechanical rated speed of the turbine [rpm]

D. Power Electronics Control

Several types of power electronics interfaces have been
investigated [7]. In this study, system is interfaced with
a six diode rectifier and three phase Impedance source
inverter which is less expensive than others and
commonly put into industrial use, has been modeled for
AC-DCAC conversion. . Fig. 3 shows a rectifier
model and inverter model. The six diodes rectifier
converts ac power generated by the wind generator into
dc power in an uncontrollable way and it is given to
Impedance source inverter it convert into ac and
inverter output is given to voltage load system.

Fig. 3 Rectifier and inverter model.

The ZSI is a voltage harmonic source in the point view
of ac system and a harmonic filter need be placed
appropriately to reduce the voltage harmonics it
generates [8]. A L-C harmonic filter consisting of a
series interconnection inductor and a parallel capacitor
is located at the ZSI terminal. Fig. 4 shows a rectifier
and ZSI system model that has been implemented in
Matlab/Simulink. The six diodes rectifier converts ac
power generated by the wind generator into dc power in
an uncontrollable way and so control has to be
implemented by the power electronics inverter.
Current-controlled ZSIs can generate an ac current
which follows a desired reference waveform so can
transfer the captured real power along with controllable
reactive power. For the modeling study, DQ control
method that is widely used for ZSI current control is
employed. Variables in the ABC three phase
coordinates may be transformed into those in the d-q
reference frame rotating at synchronous speed by the
rotational d-q transformation matrix [2]. In the three-
phase balanced system, the instantaneous active and
reactive power outputs, P and Q, of the wind turbine are
described by equation (9).

(9)

Where
VD = d-axis voltage at the wind turbine
VQ = q-axis voltage at the wind turbine
ID = d-axis current at the wind turbine
IQ = q-axis current at the wind turbine.

Here, VQ is identical to the magnitude of the
instantaneous voltage at the wind generation system


and VD is zero in the rotating d-q coordinates, so the
equation (9) may be contracted into simpler equation
(10).

(10)

where |VO| is the instantaneous voltage magnitude of
the wind turbine system. Since the voltage remains at a
level of the load AC voltage and the voltage variation is
very small compared to changes in the magnitude of IQ
and ID, P and Q are mainly subject to the d-axis current
and q-axis current respectively. Fig. 4 illustrates DQ
control decouples real and reactive components and
enables real power and reactive power to be separately
controlled by specifying the respective reference values
of PREF and QREF for the both power outputs and
independently adjusting the magnitude of the d-axis
current IQ and that of the q-axis current ID. The
reference values PREF and QREF of the wind
generation are specified by what ZSIs control
strategies are taken for real and reactive power output.
The firing signals are generated by the sine pulse width
modulation (SPWM) technique. The desired current
vector IABC_REF and the actual output current vector
IABC_WT of the wind system are compared and

Fig. 4 Current control scheme of a Impedance source inverter

The error signal vector IERR is compared with a
triangle waveform vector to create the switching
signals.

E. Capturing the maximum power

The maximum aerodynamic power available from wind
energy can be described by equation (11) . This simply
means that the maximum power may be achieved by
varying the turbine speed with varying wind speed such
that at all times it is on the track of the maximum power
curve [1], [9]. One way of enabling the maximum
power capture is to specify the reference value of real
power for the inverter control as the available
maximum power multiplied by the inverter efficiency,
as shown in equation (12).

(11)

(12)

Where CP
MAX
= the maximum power coefficient
OPT = value of where CP
MAX
= CP ( OPT)
= electrical loss in generator and inverter

F. Reactive Power Control

Various control modes can be used for determining the
amount of reactive compensation to provide. Possible
control modes include power factor, K
var
, current and
voltage. Constant power factor mode and voltage
regulation mode are implemented in this analysis. In
constant power factor control (PFC) mode, the
reference value of the reactive power of the wind
turbine, QREF, may be specified by equation (13).

(13)

Where PF is power factor and PREF is the reference
value of real power output of the VSWT.

In voltage regulation (VR) mode, reactive
power compensation is controlled in such a manner that
the voltage magnitude of the VSWT-connected bus
being kept constant at a specified level. The reference
magnitude of the voltage to be regulated must be set as
the nominal voltage of the AC load where the wind
turbine is considered as being interconnected. Whether
the mode controls constant power factor or voltage, the
reactive power capability of a VSWT is limited. Such a
limitation is required to be considered in the modeling


study. The reactive capability limits of the wind turbine
used in this study are determined by MVA rating of the
inverter which may be described by equation (14).

(14)
Where QLIMITS, PINV and SINV
are the reactive power limits,
thereal power output and MVA rating of the inverter
respectively.

III. MATLAB/SIMULINK STUDIES OF
PROPOSED SYSTEM

Fig. 5 Matlab/Simulink model of VSWT coupled Permanent Magnet
Synchronous Generator interfaced with power electronics

The proposed model is implemented into
Matlab/Simulink computer software tool and simulated
for analyzing the dynamic behaviors of a wind turbine
with varying wind conditions. Fig. 5 shows a VSWT
based PMSG model implemented in Matlab/Simulink.
It indicates wind turbine model, Permanent Magnet
Synchronous Generator model, power electronics
model with power load system and control blocks. The
generated voltage of the Permanent Magnet
Synchronous Generator is step up the voltage using step
up transformer (0.6kv/2.5k). The step up voltage is
given to the power electronics interface of the load
system which consists of rectifier and inverter. The
inverter output is again step up to 130kv using step up
transformer. The detailed explanation of each
component of the proposed system was already
discussed in section II.

Fig.6.Simulink Model of PMSG based Three phase ZSI fed Induction
motor load.
The above simulink model describes that the
generated voltage is fed with the impedance source
network and the inverter output voltage is given to the
three phase induction motor. Here the impedance
source inverter does both buck and boost operation. The
inductor and capacitances design is chosen depend
upon the application. The induction motor rotor speed
and torque is observed.

IV. SIMULATION RESULTS ANALYSIS OF
VSWT BASED PMSG.

The rating capacity is chosen to be 1.5 MVA and real
power 1.5 MW. The rated speed of the rotor is chosen
to be 40 rpm. The rated wind speed is 8 m/s. the cut-in
and cut-out speeds are 4 m/s and 16 m/s respectively.
The switching frequency of the load interface inverter is
1.040 kHz. The capacitor value of load interface
rectifier is 2500uF and d.c link voltage is 2.5 kv. The
generated voltage of Permanent Magnet Synchronous
Generator is 0.6kv. The transformer rating of load
connected side is 2.5k/130kv. The p.u voltage
magnitude of primary of the transformer is 0.99 p.u.
The maximum value of Cp is 1.2. the proposed system
operate the unity power factor control.
powergui
Continuous
p5
Out1
c2
c1
v
+
-
Volt1
v
+
-
Subsystem
Conn1
Conn2
Scope 6
Scope 2
Scope 11
Scope 10
RMS 5
signal rms
RMS
signal rms
P6
P5
P4
P3
P2
M7
g D
S
M6
g D
S
M5
g D
S
M4
g D
S
M3
g D
S
M1
g D
S
L2
L1
Gain
-K-
Display 8
Display
Asynchronous Machine
SI Units
Tm
m
A
B
C
<El ectromagnetic torque Te (N*m)>
<Rotor speed (wm)>


Fig.7.Simulation results of VSWT based PMSG generator voltage.

Fig.8. Simulation results of VSWT based PMSG generated three
phase current

Fig.9. Simulation results of VSWT based PMSG generated three
phase voltage.

Fig.10.Simulation results of VSWT based PMSG generated speed.

V. SIMULATION RESULTS ANALYSIS OF
ZSI FED INDUCTION MOTOR LOAD

The Impedance source inverters (ZSI) are used to
regulate the speed of three-phase squirrel cage motors
by changes the frequency and the voltage and consist of
input rectifier, DC link and output converter. They are
available for low voltage range and medium voltage
range. The value of inductance L
1
and L
2
is chosen
depend upon the application. In this project the value is
chosen for inductor is L
1
= L
2
= 2MH and the value for
capacitor C
1
= C
2
= 2200f. the operating frequency is
10Khz. The parameters of three phase induction motor
load are 5HP horse power, voltage is 420V, current is
8Amps, frequency is 60Hz and rotor type is squirrel
cage.

Fig.11. simulation results of three phase ZSI output
Voltage.
The fig.11. shows the three phase ZSI output voltage of
the three phase impedance source inverter fed
induction motor. The output voltage value is 380V AC
(peak voltage). The fig.12. shows the simulation results


of speed of Induction motor. The rotating speed of
induction motor is 1500RPM which is achieved by the
output voltage of an impedance source inverter. The
fig.13. shows the simulation results of generated torque
of an Induction motor. The generated electromagnetic
torque for three phase impedance source inverter fed
induction motor achieved is 40 Tm. The fig.14. shows
the simulation results of switching pulses of ZSI. The
value of pulse amplitude is 1V and the value of pulse
width is 33.3% of period, and the time period is 0.02
sec.

Fig.12.simulation results of speed of Induction motor.

Fig.13. simulation results of generated torque of an Induction motor.

Fig.14. simulation results of switching pulses of ZSI.
VI. CONCLUSIONS

A dynamic model of a variable speed wind generation
with power electronic interface was proposed for
computer software tool simulation study and
implemented in Matlab/Simulink. Component models
of a VSWT and its control scheme have been built by
using matlab function block and control block provided
in the software. A wind model was integrated into the
modeling to see the wind impact. Dynamic responses of
the wind turbine to varying wind speeds and under
different reactive control schemes were simulated and
analyzed based on the modeled system. In the view
point of electric utilities, load interface of intermittent
generation sources such as wind turbines has been a
challenge that can cause lower power quality in power
systems. So comprehensive impact studies are
absolutely necessary before wind turbines being added
to real networks. Also, users who intend to install wind
turbines in networks must ensure their systems meet the
requirements for load connection. Therefore, the work
done in this study provides a reliable tool for evaluating
the performance of variable speed wind turbines and
their impacts on power networks in terms of dynamic
behaviors as a preliminary analysis for their actual
integrations and operations.

VII. REFERNCES

[1] Seyed Mohammad Dehghan,MustafaMohamadian,
and AliYazdianVarjani, A new variable speed wind
energy conversion system Using permanent magnet
synchoronus generator and Z-source inverter. IEEE
transactions on energy conversion, vol.24,no.3.
September 2009.


[2] E. Spooner and A. C. Williamson, Direct coupled
permanent magnet generators for wind turbine
applications, Inst. Elect. Eng. Proc., Elect. Power
Appl., vol. 143, no. 1, pp. 18,1996.
[3] N. Yamamura, M. Ishida, and T. Hori, A simple
wind power generating system with permanent magnet
type synchronous generator, in Proc.IEEE Int. Conf.
Power Electron. Drive Syst., 1999, vol. 2, pp. 849854.
[4] S. H. Song, S. Kang, and N. K. Hahm,
Implementation and control of grid connected AC
DCAC power converter for variable speed wind
energy conversion system, Appl. Power Electron.
Conf. Expo., vol. 1, pp. 154158, 2003.
[5] A. M. Knight and G. E. Peters, Simple wind
energy controller for an expanded operating range,
IEEE Trans. Energy Convers., vol. 20, no. 2, pp. 459
466, Jun. 2005.
[6] T. Tafticht, et al, Output power maximization of a
permanent magnet synchronous generator based
standalone wind turbine, in Proc. IEEE ISIE 2006,
Montreal, QC, Canada, pp. 24122416.
[7]M. Chinchilla, S. Arnaltes, and J. C. Burgos,
Control of permanent magnet generators applied to
variable-speed wind-energy systems connected to the
grid, IEEE Trans. Energy Convers., vol. 21, no. 1, pp.
130135, Mar. 2006.
[8]F. Z. Peng, Z-source inverter, IEEE Trans. Ind.
Appl., vol. 39, no. 2,pp. 504510, Mar./Apr. 2003.
[9]F. Z. Peng, M. Shen, and Z. Qian, Maximum boost
control of the Z-source inverter, IEEE Trans. Power
[10]F. Z. Peng, A. Joseph, J.Wang, andM. Shen, Z-
source inverter for motor drives, IEEE Trans. Power
[11]P. C. Loh, D. M. Vilathgamuwa, C. J. Gajanayake,
Y. R. Lim, and C. W. Teo, Transient modeling and
analysis of pulse-width modulated Z-source inverter,
507, Mar. 2007.



PV Based Bidirectional Soft-Switching DC/DC Converter
with Auxiliary Switch Control for Battery Recharging

Neenu Therese Antony
1
, S. Shantha Sharmila
2
, B. Karthika
3
, N. Tejesvi
4
,
Dr. M. Sasikumar
5

1,2,3,4
PG Scholar,
5

ABSTRACT
This paper presents a PV based bidirectional
dc/dc converter with auxiliary switch control
which performs soft switching, which have been
used for battery recharging applications. In
conventional method topologies applied with
soft-switching technique, not only the resonant
components but also additional power switching
devices are required which will results in
additional switching losses and conduction
losses. In the proposed converter topology, soft
switching can be applied to the conventional
bidirectional dcdc converter through adding
auxiliary circuit to the converters and which is
operated at buck and boost mode. Through the
buck and boost mode analysis, soft switching
technique of zero voltage switching and zero
current switching are explained. The aim of this
paper is to introduce a high efficiency PV based
bidirectional dc/dc converter for the battery
charge and discharge system. The proposed
bidirectional converter is modeled and verified
through simulation by using MAT LAB
/SIMULINK.

Keywords - Bidirectional dc/dc converter,
photovoltaic (PV), regenerative braking,
resonant converter, soft switching.

I. INTRODUCTION

The bidirectional dc-dc converter along
with energy storage has become a promising option
for many power related systems, including hybrid
vehicle [1], fuel cell vehicle, renewable energy
system and so forth. It not only reduces the cost
and improves efficiency, but also improves the
performance of the system.
In the electric vehicle applications, an auxiliary
energy storage battery absorbs the regenerated
energy fed back by the electric machine. In
addition, bidirectional dc-dc converter shown in
Figure 1.1 is also required to draw power from the
auxiliary battery to boost the high-voltage bus
during vehicle starting, accelerate and hill climbing
[1]. With its ability to reverse the direction of the
current flow, and thereby power, the bidirectional
dc-dc converters are being increasingly used to
achieve power transfer between two dc power
sources in either direction.
The photovoltaic (PV) module-integrated
converter (MIC) system is the key technology for
the future distributed production of electricity using
solar energy [2][3]. The PV MIC system offers
plug and play concept, greatly optimizing the
energy yield from the PV module [3]. Each PV
module has its own power conversion system,
generating the maximum power from the PV
module [4]. To make the PV MIC system
commercially viable, a low-cost and high-
efficiency power conversion scheme should be
developed. The PV module voltage has a low-
voltage characteristic [5]. In order to deliver
electric power into the grid, the low PV module
voltage should be converted into a high dc voltage
[6]. The electricity available at the output of the PV
module may directly give to the light loads. In
some applications requires additional converters to
process the electricity from the module. To regulate
the current and voltage at the load, also to track the
maximum power, these converters are used. Thus, a
dcdc converter with a high-voltage gain is needed.
The regenerative braking is a process to
create their own power for battery recharging in
hybrids and all-electric vehicles. In the motion
control industry, regenerative braking refers to
charge a battery by using back emf voltage of the
motor. In this operational mode motor acts as a
generator . Since it is opposite to the normal mode.
So, instead of wasting the back emf power into heat
heat loss, it can be used to recharge the battery by a
bidirectional converter.
In this paper, a resonant bidirectional
buckboost converter topology applied with soft-
switching technique of zero voltage switching
(ZVS) and zero current switching is proposed. The
supply is given from a pv panel. In the new
proposed topology, the fundamental operation
equals the conventional bidirectional buckboost
converter [14][15]. The resonance of the proposed


converter is caused by the resonant capacitor and
inductor of the auxiliary circuit and the auxiliary
switch is operated in boost mode and buck mode.

Fig. 1. Proposed bidirectional soft-switching dc/dc
converter.

The aim of this paper is to introduce the auxiliary
switch turn-on time control for the bidirectional
dc/dc converter in a battery charging and
discharging system supplied by a solar source.

II. CONVERTER OPERATION
A. Proposed Converter Configuration
Fig.1 shows the proposed pv based
bidirectional soft-switching dc/dc converter. The
circuit consists of conventional buck-boost circuit
and an auxiliary circuit powered by a photovoltaic
module. This proposed converter is formed by
adding one resonant inductor, two resonant
capacitors, and two switches to the conventional
bidirectional converter circuit. Before turning ON
the main switch, the resonant inductor L
r
in the
auxiliary circuit is energized with the voltage
difference V
high
Vl
ow
.There by soft-switching
operation is obtained. The voltage across Lr is
maintained with V
high
V
low
by operating the upper
converter in continuous conduction mode, before
the main switch is turned ON.
B. Operation Mode
The circuit consists of two operational modes.
They are Boost mode and Buck mode operations.
Each operation mode topology is divided into
seven operating intervals.

Boost mode of operation:
When the power transferred from the low
voltage side to high voltage side it behaves as a
boost converter. To avoid the inrush current, the
output voltage is always higher than the input
supply voltage. In boost mode, voltage increases
rapidly and current decreases slowly. In this mode,
S1 and Sa1 are the main and auxiliary switches .
.Before starting conduction, all the switches are off
and the resonant inductor current (I
Lr
) is increses
and transferred to the output voltage through the
body diode of S2. The auxiliary switch S
a1
is turned
on under ZCT condition and main switch S
1
turned
on under ZVT condition.
Buck mode of operation:
When the power flows from high-voltage
side to low voltage side it behave like step down
converter .To avoid the inrush current input supply
voltage higher than the output voltage. Here S2and
Sa2are the main and auxiliary switches. During
buck mode voltage decreases and current increases
and power remain constant. Buck mode of
operation is otherwise called as step up mode of
operation. Before starting conduction, all the
switches are off. However, switches S2 and
auxiliary switch Sa2 are active in buck mode
operation. Both switches are turned on under ZVT
and ZCT conditions. Like boost mode operational
characteristics are same and buck mode operates in
complement with the boost mode.
The boost and buck mode operations are simulated
by MATLAB.
C. Soft-Switching Principles:
To improve the efficiency of the converter resonant
and soft-switching is implemented in the power
stage. Switching transition occurs under favourable
conditions device voltage or current is zero. Soft
switch auxiliary circuit is composed of a switch and
capacitor. Zero voltage switching means, under
turn on condition the switch voltage brought to zero
before gate voltage is applied. Under turn off
condition a parallel capacitor act as a loss-less
snubber, thats why turn off condition are called as
low loss transition. Zero current switching means,
under turn off condition the switch current brought
to zero before the gate voltage is removed. So turns
on conditions are called as zero loss transition.

III. MODELING OF PHOTOVOLTAIC
ARRAY SYSTEM
The equivalent of PV cell is shown in Figure 2.


Figure 2:Equivalent circuit of PV cell

The PV panel is modeled as an equivalent current
source. From the MATLAB Simulink ibrary the
mathematical model for the various equations
describing the PV panel characteristics are
modeled. The below figure 6 shows the equivalent
circuit model of the PV panel. This simulation is
done for standard test condition (STC) when
temperature is 25o C and Irradiation is 1000 W/m2
.

Figure3: Equivalent circuit of solar PV using MATLAB

Figure4: Maximum current (Im) of Solar PV using
MATLAB

Figure5: Current generated by the incident light(Ipv)

Figure6: Reverse saturation current (Io) using MATLAB

IV. SIMULATION AND RESULTS

With the above pv modelling, the output of the pv
panel is given to the bidirectional dc-dc converter
which is simulated in MATLAB 7.10.The output
obtained from the pv module is shown in figure7.

Figure7: Output of th pv module.
The output of the open loop boost operation
supplied from solar cell is given below in figure8.

Figure8: Output voltage in boost mode operation



The output of the open loop buck operation is given
below in figure 9.

Figure9: Output voltage in buck mode operation

The modelling of the bidirectional converter with
battery driving RLE load is given in the figure.
Figure 9 shows the bidirectional operation mode
with closed loop control.

Fig.10. Simulink model of bidirectional converter

The battery used in the simulation is
Nickel-Cadmium with maximum capacity of
22.727Ah, nominal voltage 85V, fully charged
voltage 97.2548V and nominal discharge current
4A. PID controller is used to control the overall
circuit.
Figure10 shows the output voltage
obtained from the bidirectional converter.

Fig.11. Output voltage of the bidirectional converter

For a certain period bidirectional converter
operates in boost mode and after that period
converter operated in buck mode. At the boost
mode operation converter boosts the voltage and
driving the load. In boost mode of operation, output
voltage is 225V and current obtained is 17A. In the
regenerative mode of the system, converter is
operated in buck mode. So the regenerative energy
become stored in the battery. At the buck mode
operation the voltage obtained is 115V and the
current obtained is -25A.

Fig.12. Output current of the bidirectional converter

The output current waveform of the
bidirectional dc/dc converter operating in boost and
buck mode is shown in figure11.

V. CONCLUSION
In this paper, pv based soft switching
converter with auxiliary switch control for battery
charge and discharge system is proposed. The
supply to the bidirectional dc-dc converter is given
from a pv module. In the intelligent control
techniques for the tracking of MPP were
investigated in order to improve the efficiency of
PV systems, under different temperature and
irradiance conditions. The design and simulation of
a fuzzy logic based MPPT controller was proposed
using MATLAB. The soft-switching condition for
all semiconductor elements is achieved only by
adding two auxiliary switches and resonant
parameters for full duty cycle range. The switches


are turned ON and OFF under zero-voltage and
zero-current conditions by adding the LC resonant
circuit to the conventional bidirectional converter.
The proposed converter reduces the switching
power losses, increasing power efficiency and the
topology is analysed using MATLAB/SIMULINK.

REFERENCES

[1]J.-S. Lai and D. J. Nelson, Energy management
power converters in hybrid electric
and fuel cell vehicles, in Proc. IEEE Ind. Electron.,
Taipei, Taiwan, Volume 95,
Issue 4, April 2007, pp. 766 777.
[2] E. Serban and H. Serban, A control strategy for a
distributed power generation microgrid application with
voltage- and current- controlled source converter, IEEE
Trans. Power Electron., vol. 25, no. 12, pp. 2981 2992,
Dec. 2010.
[3] L. Quan and P. Wolfs, A review of the single phase
photovoltaic module integrated converter topologies with
three different DC link configurations, IEEE Trans.
Power Electron., vol. 23, no. 3, pp. 13201333, May
2008.
[4] L. Zhang, K. Sun,Y. Xing, L. Feng, andH.Ge, A
modular grid-connected photovoltaic generation system
based on DC bus, IEEE Trans. Power Electron., vol. 26,
no. 2, pp. 523531, Feb. 2011.
[5] Y. Fang and X. Ma, A novel PVmicroinverter with
coupled inductors and double-boost topology, IEEE
Dec. 2010.
[6] W. Yu, J. S. Lai, H. Qian, and C. Hutchens, High-
efficiency MOSFET inverter with H6-type configuration
for photovoltaic nonisolatedAC-module applications,
1260, Apr. 2011.
[7] M. Cacciato, A. Consoli, R. Attanasio, and F.
Gennaro, Soft-switching converter with HF
transformer for grid-connected photovoltaic systems,
1686, May 2010.
[8] C. Rodriguez and G. A. J. Amaratunga, Long-
lifetime power inverter for photovoltaic AC modules,
2601, Jul. 2008.
[9] S. Bin and L. Zhengyu, An interleaved totem-pole
boost bridgeless rectifier with reduced reverse-recovery
problems for power factor correction, IEEE Trans.
Power Electron., vol. 25, no. 6, pp. 14061415, Jun.
2010.
[10] Z. Liang, R. Guo, J. Li, and A. Q. Huang, A high-
efficiency PV moduleintegrated DC/DC converter for PV
energy harvest in FREEDM systems, IEEE Trans.
Power Electron., vol. 26, no. 3, pp. 897909, Mar. 2011
[11]Z. Salameh and Daniel Taylor, Step-up maximum
power point tracker for photovoltaic arrays, Solar
Energy, Vol. 44, n 1, 1990, pp. 57-61.
[12] W. Y. Choi, J. S. Yoo, and J. Y. Choi, High
efficiency dcdc converter with high step-up gain for low
PV voltage sources, in Proc. IEEE ECCE Asia, Jeju,
Korea, May 30/Jun. 3, 2011, pp. 11611163.
[13] M. Barai, S. Sengupta, and J. Biswas, Digital
controller for DVS-enabled dcdc converter, IEEE
Trans. Power Electron., vol. 25, no. 3, pp. 557 573,
Mar. 2010.
[14] H.-C. Choi and H.-B. Shin, A new soft-switched
PWM boost converter with a lossless auxiliary circuit,
Int. J. Electron., vol. 93, no. 12, pp. 805817, Nov. 2011.
[15] I. H. Lee, J. G. Kim, J. H. Kim, C. Y.Won, andY. C.
Jung, Soft switching bidirectional DC-DC converter to
reduce switching losses, in Proc. IEEE Int. Conf. Electr.
Mach. Syst., Aug. 2011, pp. 16.



PV based DCDC Converter with High Efficient and Fast
Dynamic Response for Stand Alone Applications

S.Shantha Sharmila
1
, Neenu Therese Antony
2
,B.karthika
3
,N.Tejesvi
4
, Dr.M.Sasikumar
5

1,2,3,4
PG Scholar,
5

Abstract
This paper proposes a high-efficiency dcdc
converter with fast dynamic response for low-
voltage photovoltaic (PV) sources. The voltage
stress of power switches is reduced at low voltage
side. Zero-current turn-off of output diodes is
achieved at high-voltage side. Power efficiency is
improved by reducing switching power losses. A
modified proportional and integral controller is
also suggested to achieve fast output voltage
control. The dynamic response of the proposed
converter is improved. The performance of the
proposed converter is verified based on an
experimental prototype for a 200-W PV module.

Keywords- DCDC converter, dynamic response,
photovoltaic (PV), power efficiency

I. INTRODUCTION
The photovoltaic (PV) module-integrated converter
(MIC) system is the key technology for the future
distributed production of electricity using solar
energy [1][3]. The PV MIC system offers plug and
play concept, greatly optimizing the energy yield
from the PV module [3]. Each PV module has its own
power conversion system, generating the maximum
power from the PV module [4]. To make the PV MIC
system commercially viable, a low-cost and high-
efficiency power conversion scheme should be
developed. The PV module voltage has a low-voltage
characteristic [5]. In order to deliver electric power
into the grid, the low PV module voltage should be
converted into a high dc voltage [6]. Thus, a dcdc
converter with a high-voltage gain is needed. The
active-bridge dcdc converter has been used for low-
voltage PV sources [7], [8]. The power switches at
low-voltage side are turned ON at zero voltage.
However, the output diode at high-voltage side has
high switching power losses due to its reverse-
recovery current [9]. The half-bridge dcdc converter
has been presented to reduce switching power losses
at high voltage side [10]. The output diodes are
turned OFF at zero current by using the voltage
doubler rectifier. However, an additional half-wave
rectifier is needed, which increases switching power
losses. Alternatively, the active-clamped dcdc
converter has been used for low-voltage PV sources ,
[12]. It uses the active-clamping circuit and the
resonant voltage doubler rectifier. However, the
active-clamping circuit increases the voltage stress of
power switches at low-voltage side, causing high
switching power losses. Additionally, thermal
management problems should be considered for a
practical design of the PV MIC system. Considering
the dynamic response of the converter, bandwidth
limitations of conventional controllers have forced
power electronics engineers to increase switching
frequency or increase output capacitor [13]. Such
hardware modification results in lower efficiency and
higher component cost. However, by improving the
controllers dynamic response, the transient
performance of the converter can be improved.
Therefore, it is not only necessary but also practical
to improve both power efficiency and dynamic
response of the dcdc converter for low voltage PV
sources.
This paper proposes a high-efficiency dcdc
converter with fast dynamic response for low-voltage
PV sources. An improved active-clamped dcdc
converter is presented by using a dual active-
clamping circuit. The voltage stress of power
switches can be reduced at low-voltage side. Also, a
modified proportional and integral (PI) controller is
suggested for fast output voltage control. The
transient performance of the proposed converter is

improved. All control functions are implemented in
software with a single-chip microcontroller. The
proposed converter is realized with minimal hardware
with a low cost. The operation of the proposed
converter is described. The control strategy is
presented, including the fast output voltage control
and its digital implementation. The performance of
the proposed converter is verified using a 200-W
experimental prototype. The experimental results
confirm that a high efficiency of 97.9% is achieved at
60-V input voltage for 200-W output power with an
improved dynamic performance.

II. CONVERTER OPERATION

Fig. 1 shows the circuit diagram of the proposed dc
dc converter. The converter consists of main switches
(S1 , S4 ), the dual active-clamping circuit (S2 , S3 ,
Cc ), the transformer T, and the resonant voltage
doubler rectifier (Llk , Cr , Do 1 , Do 2 ). The main
switches (S1 , S4 ) and auxiliary switches (S2 , S3 )
operate complementarily with a short dead time. All
switches are the metaloxidesemiconductor field-
effect transistors. They are considered ideal switches
except their body diodes DS 1 DS 4 and output
capacitors CS 1CS 4 . Ci is the input capacitor. Cc is
the clamping capacitor. Co is the output capacitor.
The capacitors Ci , Cc , and Co are large enough so
that their voltages Vi , Vc , and Vo are considered
constant, respectively. The transformer T has the
magnetizing inductor Lm and leakage inductor L
lk

with the turns ratio of 1:N, where N=N
s
/N
p
. L
lk
is
assumed to be much smaller than Lm. The capacitor
Cr is the resonant capacitor. Cr resonates with the
leakage inductor Llk . Thus, the resonant capacitor
voltage Vr is not considered constant for one
switching period.

Fig 1: Circuit diagram of proposed converter

Fig. 2 shows the switching waveforms of the
proposed converter during one switching period Ts
(=1/fs ). Fig. 2(a) shows the switching waveforms at
the primary side. Fig. 2(b) shows the switching
waveforms at the secondary side. The proposed
converter has six switching modes during Ts . The
duty ratio D is based on the on-time of the main
switches. Fig. 3 shows theswitching modes of the
proposed converter during Ts . Beforet = t
0
, S
2
and
S
3
have been turned OFF. The voltages VS
1
and VS
4
have been zero when the primary current ip flows
through the body diodes DS 1 and DS 4 .
There is a wide range of operating conditions that can
be used for fuel cells. The range of operating
conditions and the optimal conditions are summarized
in Table . The fuel cell performance is determined by
the pressure, temperature, and humidity based upon
the application requirements, and can often be
improved (depending upon fuel cell type) by
increasing the temperature, pressure, humidity and
optimizing other important fuel cell variables. The
ability to increase these variables is application
dependent, since system issues, weight and cost play
important factors when optimizing certain
parameters.

(a)


(b)
Fig 2:Switching waveforms of the proposed converter

III. CONTROL STRATEGY

The output voltage Vo is controlled with the duty
ratio D. When S
1
and S4 are turned ON (Mode1 and
Mode2), the magnetizing current iL
m
increases
linearly. The input energy is stored in the
magnetizing inductor Lm. The following voltage
relation is obtained as
Vi Lm diLm /dt = 0.

Fig 3: Switching modes of proposed converter

The suggested voltage control is digitally
implemented by using a single-chip microcontroller
dsPIC30F3011 (Mircochip) [14]. The microcontroller
provides a function of 16-bit fixedpoint arithmetic,
including a significant support for DSP. It has various
peripherals directed toward a single-chip solution for
digital control of power electronic converters. It also
has a flash ROM, allowing it to be reprogrammed for
software updates. These advantages result in
increased integration and reduced system cost
capacitor voltage Vc : 50 V/division; switch voltage
VS
2
: 50 V/division; switch voltage VS
2
:
50V/division, 10 s/division. (a)Waveforms at 50-V
input voltage for 200-W output power. (b)Waveforms
at 60-V input voltage for 200-W output power. the
suggested controller. The program structure can be
divided into initialization, control, and pulsewidth
modulation (PWM) generation. At the beginning of
the main program, the system registers and control
parameters are initialized. The control routine is
activated every 100-s period by the timer interrupt.
The input voltage Vi and output voltage Vo are
measured by the voltage sensing amplifiers. They are
sensed through the 10-bit A/D converter in the
microcontroller. After the input and output voltages
are read, the duty ratio D is obtained by calculating
Dn and Dc . The PWM duty generation is performed
every 20-s period by using the PWM interrupt. The
motor control PWM module in the dsPIC30F3011
generates the complementary duty signals for the
power switches [14].

IV. CIRCUIT DIAGRAM FOR DC DC
BOOST CONVERTER

The maximum available power will be extracted by
the operation of PV generator at its MPP, by the role
of the MPPT. The fig 4 shows the general block
diagram for a MPPT solar PV system, using a general
DC/DC converter [11]. This one is connected to the
PV generator, a battery and a load profile (such as a
resistance, DC/DC motor). The main objective of this
MPPT technique is to obtain the maximum power
from the PV generator.

www.ijrde.com

Fig 4:Circuit diagram for boost converter

The operation of boost converter can be divided into
two modes. Mode 1 begins, the MOSFET M
switched on at t=0 and hence the input current rises,
flows through inductor L and MOSFET M
begins when the MOSFET M
1
is switched off at t=t
and hence the current flowing through the MOSFET
would now flow through inductor L, capacitor C,
and Diode D
m
. The inductor current falls until
MOSFET M
1
is turned on again in the next cycle.
The load which receives the energy from the inductor
L

V MODELING OF PHOTOVOLTAIC
ARRAY SYSTEM

The equivalent of PV cell is shown in Figure 5.

Fig 5:Equivalent circuit of PV cell

source. From the MATLAB Simulink library the
describing the PV panel characteristics are modeled.
The below figure 6 shows the equivalent circuit
model of the PV panel. This simulation is done for
standard test condition (STC) when temperature is
25
o
C and Irradiation is 1000 W/m
2
.



4:Circuit diagram for boost converter
The operation of boost converter can be divided into
two modes. Mode 1 begins, the MOSFET M
1
is
switched on at t=0 and hence the input current rises,
flows through inductor L and MOSFET M
1
. Mode 2
is switched off at t=t
1

and hence the current flowing through the MOSFET
would now flow through inductor L, capacitor C, load
. The inductor current falls until
is turned on again in the next cycle.
The load which receives the energy from the inductor
MODELING OF PHOTOVOLTAIC
equivalent of PV cell is shown in Figure 5.

5:Equivalent circuit of PV cell
source. From the MATLAB Simulink library the
describing the PV panel characteristics are modeled.
The below figure 6 shows the equivalent circuit
panel. This simulation is done for
standard test condition (STC) when temperature is

Fig6:Equivalent circuit of solar PV using MATLAB

Fig7:Maximum current (Im) of Solar PV using MATLAB

Fig8: Current generated by the incident light(I

Fig9: Reverse saturation current (Io) using MATLAB

VI. SIMULATION AND RESULTS

The simulation is done using the Matlab Coding for
the fuel system for Grid connection in MATLAB
7.10.In R load condition the output voltage is 360V
which shown in fig 10
286 | P a g e

6:Equivalent circuit of solar PV using MATLAB

7:Maximum current (Im) of Solar PV using MATLAB

8: Current generated by the incident light(I
pv
)

9: Reverse saturation current (Io) using MATLAB
VI. SIMULATION AND RESULTS
The simulation is done using the Matlab Coding for
the fuel system for Grid connection in MATLAB
the output voltage is 360V


Fig10 Voltage waveform for R load

In motor load the armature current is 2A,shown in
fig11

Fig11:Armature current for motor load

The speed of the motor attained 140 rad/sec,which
was shown in fig 12

Fig12: Speed of the motor

The torque attained for motor load is shown in fig 13

Fig13: Torque for motor load

VII.CONCLUSION

This paper has proposed a high-efficiency dcdc
converter with fast dynamic response for low-voltage
PV sources. The operation of the proposed converter
has been described. The control strategy has been
presented, including the fast output voltage control
and its digital implementation. The proposed
converter reduces the switching power losses,
increasing power efficiency. In the intelligent control
techniques for the tracking of MPP were investigated
in order to improve the efficiency of PV systems,
under different temperature and irradiance conditions.
The design and simulation of a fuzzy logic based
MPPT controller was proposed using MATLAB. The
proposed method has very good performances, fast
responses with no overshoot and less fluctuation in
the steady state, for rapid irradiance and temperature
variations. By using this PWM technique the
harmonics will be reduced. These controllers are able
to maintain very rapidly and the operating point of
the PV systems at the maximum power point hence
improving the amount of energy effectively extracted
from the PV modules, i.e. increasing the efficiency of
the PV system.

VIII. REFERENCES

[1] F. Blaabjerg, Z. Chen, and S. B. Kjaer, Power electronics as
efficient interface in dispersed power generation systems, IEEE
Trans. Power Electron., vol. 19, no. 5, pp. 11841194, Sep. 2004
.
[2] E. Serban and H. Serban, A control strategy for a distributed
power generation microgrid application with voltage- and current-
controlled source converter, IEEE Trans. Power Electron., vol.
25, no. 12, pp. 2981 2992, Dec. 2010.

[3] L. Quan and P. Wolfs, A review of the single phase
photovoltaic module integrated converter topologies with three


different DC link configurations, IEEE Trans. Power Electron.,
vol. 23, no. 3, pp. 13201333, May 2008.

[4] L. Zhang, K. Sun,Y. Xing, L. Feng, andH.Ge, A modular grid-
connected photovoltaic generation system based on DC bus, IEEE
Trans. Power Electron., vol. 26, no. 2, pp. 523531, Feb. 2011
.
[5] Y. Fang and X. Ma, A novel PVmicroinverter with coupled
inductors and double-boost topology, IEEE Trans. Power
Electron., vol. 25, no. 12, pp. 31393147, Dec. 2010.

[6] W. Yu, J. S. Lai, H. Qian, and C. Hutchens, High-efficiency
MOSFET inverter with H6-type configuration for photovoltaic
nonisolatedAC-module applications, IEEE Trans. Power
Electron., vol. 26, no. 4, pp. 12531260, Apr. 2011.
[7] M. Cacciato, A. Consoli, R. Attanasio, and F. Gennaro, Soft-
switching converter with HF transformer for grid-connected
photovoltaic systems, IEEE Trans. Ind. Electron., vol. 57, no. 5,
pp. 16781686, May 2010.

[8] C. Rodriguez and G. A. J. Amaratunga, Long-lifetime power
inverter for photovoltaic AC modules, IEEE Trans. Ind. Electron.,
vol. 55, no. 7, pp. 25932601, Jul. 2008.

[9] S. Bin and L. Zhengyu, An interleaved totem-pole boost
bridgeless rectifier with reduced reverse-recovery problems for
power factor correction, IEEE Trans. Power Electron., vol. 25,
no. 6, pp. 14061415, Jun. 2010.

[10] Z. Liang, R. Guo, J. Li, and A. Q. Huang, A high-efficiency
PV moduleintegrated DC/DC converter for PV energy harvest in
FREEDM systems, IEEE Trans. Power Electron., vol. 26, no. 3,
pp. 897909, Mar. 2011

[11]Z. Salameh and Daniel Taylor, Step-up maximum power point
tracker for photovoltaic arrays, Solar Energy, Vol. 44, n 1,
1990, pp. 57-61.

[12] W. Y. Choi, J. S. Yoo, and J. Y. Choi, High efficiency dcdc
converter with high step-up gain for low PV voltage sources, in
Proc. IEEE ECCE Asia, Jeju, Korea, May 30/Jun. 3, 2011, pp.
11611163
.
[13] M. Barai, S. Sengupta, and J. Biswas, Digital controller for
DVS-enabled dcdc converter, IEEE Trans. Power Electron., vol.
25, no. 3, pp. 557 573, Mar. 2010.



Analysis of Various Sinusoidal Pulse Width Modulation Techniques
for a Five Level H6 Bridge Inverter
N.Tejesvi
1
, N. Sujitha
2
, R. Hemantha kumar
3
and Dr.M. Sasikumar
4
1,2,3
PG Scholar,
4

Abstract
This paper deals with the novel five level H6 bridge inverter with
various sinusoidal pulse width modulation techniques. The
proposed inverter includes the full bridge topology with two
additional power switches and two diodes connected to the
midpoint of the DC link. The midpoint voltage is balanced using
the various sinusoidal pulse width modulation techniques. Thus
the two added levels are obtained by the discharge of the two
capacitors from the DC link. Simulation study of the inverter
employing alternative phase opposition disposition and third
harmonic injection sinusoidal pulse width modulation technique
has been done using MATLAB/SIMULINK .
Index termsFive level H6 bridge inverter, alternative phase
opposition disposition (APOD), third harmonic injection.
I. INTRODUCTION
This paper concerns about the implementation of multilevel
topologies for single phase converters. By the use of these
multilevel inverter harmonic level of the system can be
reduced to a considerable amount, as a result of which efficient
output can be derived with the help of smaller and cheaper
filters itself[1][2]. This also helps in the improvement of
output waveform and reduction of electromagnetic interference
(EMI) [3].
The basic idea of the multilevel inverter is that to provide
the intermediate voltage levels between the reference potential
and the dc link voltage [4]. In half bridge neutral point
clamped inverter the additional levels are provided by
clamping the series of dc link capacitors or the flying
capacitors and the balancing system is required such as an
external circuit [5] or modified PWM strategies [6],[7].
Cascaded full bridge inverter needs several dc sources such
as PV strings [8]. Using the transformers, inverter can also use
the single dc supply [9]. Cascaded full bridge inverter employs
different PWM techniques [10] such as APOD, SPWM, SVM
[11], [12]
In hybrid topologies, a novel NPC full bridge is presented
[13] with NPC three level leg (four switches) and the other leg
with two devices switches at low frequency. A similar
approach was presented in [14], where four low frequency
devices (instead of the two employed in [13]) were employed
in a full-bridge configuration.
A different topology was proposed in [15] where only six
devices are needed and the positive rail of full bridge can be
connected to dc link or the mid point of dc link capacitors thus
the maximum number of conducting devices is three.
This paper proposes a five level output by the help of a full
bridge inverter along with two diodes and two power switches
connected to the midpoint of the DC link. The midpoint
voltage control and unity power factor of the circuit is obtained
by implementing various sinusoidal pulse width modulation
techniques like alternative phase opposition disposition
(APOD) and third harmonic injection. The most efficient
method is derived out from the analysis of above mentioned
techniques.
II. FIVE LEVEL H6 BRIDGE INVERTER
This H6 bridge inverter is mainly designed and
implemented inorder to maintain constant output voltage
incase of transformerless inverter for photovoltaic applications.
The output voltage of the five level inverter can be written as
V
out
= mV
dc
Various pulse width modulation stratagies are applied
according to the modulation index value. Four zones of
operation are identified in this circuit. The output voltage of
the power converter differs for each mode of operation.
A. Circuit Diagram


Fig. 1. Circuit diagram of Five level Inverter
The circuit consist of a voltage source V
dc
, two capacitors,
power switches, diodes and four transistors with a R load. The
midpoint voltage control between these capacitors will be
achieved with the help of PWM strategies. The output voltage
level +V
MP
is obtained by the discharge of the lower side
capacitor C
LS
and the V
MP
is obtained by the discharge of the
higher side capacitor C
HS
. Transistors T1, T4 are in ON
condition during the positive semiperiod whereas the
transistors T3, T2 are in ON condition during the negative
semiperiod.
B. Modes Of Operation
Mode 1:
During the operation of Mode1 transistors T1, T4 and T6
will be in ON condition whereas the transistors T2, T3 and T5
will be in off condition. The turn ON of transistor T6 varies the
output voltage value between +V
MP
and 0V. The output
voltage +V
MP
is obtained with the help of the lower side
capacitor C
LS
and the NULL voltage is obtained during the
freewheeling operation of diodes D1 and D2. The current flow
for the Mode 1 operation is as shown in figure 2.

Fig. 2. Five level P WM strategy for mode 1. (a) Active phase.
(b) Freewheeling phase.
Mode 2:
During Mode2 operation transistors T1, T4 and T5 will be
in ON condition. During this mode of operation the output
voltage varies from +V
dc
to +V
MP
. V
dc
is obtained during the
active phase whereas +V
MP
is obtained during the freewheeling
phase. The current flow of this mode of operation is as shown
in figure 3.

Fig. 3. Five-level PWM strategy for Zone 2 (a) Active phase (b)
Freewheeling phase.
Mode 3 and Mode 4:
The operation of mode 3 and mode 4 are similar to that of
mode 1 and mode 2 except that they work for the negative
semiperiod. Here the transistors T2 and T3 will be in ON
condition for both modes of operation whereas T6 will be ON
during mode 3 and T5 will be ON during mode 4 operation.
C. Midpoint Voltage Control
During symmetrical conditions midpoint voltage drift does
not arise but during asymmetrical conditions the midpoint
voltage drift arises. The lower side and the higher side
capacitors are used to balance this drift. The midpoint voltage
control is explained with the help of the figure 4. The HS
capacitor and the LS capacitor helps in providing constant
output voltage V
MP
to the full bridge converter. The output
voltage level +V
MP
is obtained by the discharge of C
LS
and
V
MP
is obtained by the discharge of the higher side capacitor
C
HS
.THE two configurations shown in figure 4 helps out to
balance the charge of the two capacitors. Figure 5 is taken for
the analysis of midpoint voltage control. Here V
dc
is kept
constant and the capacitors are considered to be equal.
That is
C
HS
=C
LS
=C
www.ijrde.com

Fig. 4. T5 and T6 configurations providing the same v
the full- bridge rails. In (a), the HS capacitor is discha
the LS capacitor is discharging.
Fig. 5. DC capacitor circuit employed for the analytical analysis of
the MVC.
From figure 5 it is evident that
D(V
MP
/dt) = -I
MP
/2C
This means that I
MP
affects the midpoint voltage. While
considering mode1 operation during the active phase the
midpoint current I
MP
will be equal to that of the load current
while the load current will be zero during the freewheeling
operation. Now considering the mode 2 operation, the
midpoint current I
MP
is zero during the active phase
midpoint current I
MP
equals the load current during the
freewheeling operation. Thus the midpoint voltage control is
achieved.
III. SINUSOIDAL PULSE WIDTH MODULATION
TECHNIQUES
The comparison of various sinusoidal pulse width
modulation techniques like alternative phase opposition
disposition method (APOD) and third harmonic injection are
explained below.
A. Alternative phase opposition disposition
ISSN: 2279-0500 Special Issue: pp
Methods Enriching Power and Energy Development (MEPED) 2014 291

voltage V
MP
to
discharging, and in (b),

for the analytical analysis of
int voltage. While
during the active phase the
will be equal to that of the load current
while the load current will be zero during the freewheeling
operation. Now considering the mode 2 operation, the
is zero during the active phase while the
equals the load current during the
freewheeling operation. Thus the midpoint voltage control is
SINUSOIDAL PULSE WIDTH MODULATION
The comparison of various sinusoidal pulse width
ike alternative phase opposition
and third harmonic injection are
For a m-level inverter the APOD technique requires m
carrier signals which has to be phase disposed from each other
by an angle of 180 degree. Four carrier signals are required for
bipolar mode of operation, two signals which are phase
displaced by 180 degree are used for upper half and two for the
lower half. The unipolar carrier signal arrangement
alternative phase opposition disposition technique is given in
figure 6.
Fig. 6. APOD signal
Each carrier wave generated have the same frequency and
amplitude. Based on the inverter level the amplitude of the
modulation signal is modified.
B. Third Harmonic Injection
The third harmonic injection signal arr
shown in figure 7.
pp- 289-296
291 | P a g e
level inverter the APOD technique requires m-1
carrier signals which has to be phase disposed from each other
by an angle of 180 degree. Four carrier signals are required for
bipolar mode of operation, two signals which are phase
are used for upper half and two for the
lower half. The unipolar carrier signal arrangement for
alternative phase opposition disposition technique is given in

APOD signal
Each carrier wave generated have the same frequency and
e. Based on the inverter level the amplitude of the
The third harmonic injection signal arrangement is as
www.ijrde.com

Fig. 7. Third harmonic injection signal arrangement
Sinusoidal PWM technique is considered to be the simplest
modulation scheme but the drawback is that it cannot
completely utilize the Dc supply voltage. To overcome this
problem the Third Harmonic Injection pulse width modulation
technique is introduced. By using this method the inverter
performance can be improved. Here in this method a triple
frequency term
y = sin+Asin3
is added with the fundamental component. From the figure it is
evident that due to the third harmonic injection to the peak
magnitude of the modulation wave, the effect of reducing the
peak value of output waveform without changing the
fundamental amplitude is achieved. By this method the
amplitude of the modulating waveform can be increased, as a
result of which the full output voltage can be utilized. There
will be 15.5% increase in the amplitude of the fundamental
phase voltage due to the third harmonic injection.
C. Single Carrier Sinusoidal Pulse Width Modulation
Technique
This technique is implemented when there is usage of multiple
sinusoidal modulating signals and a single carrier signal. These

Third harmonic injection signal arrangement
Sinusoidal PWM technique is considered to be the simplest
drawback is that it cannot
completely utilize the Dc supply voltage. To overcome this
problem the Third Harmonic Injection pulse width modulation
y using this method the inverter
performance can be improved. Here in this method a triple
added with the fundamental component. From the figure it is
evident that due to the third harmonic injection to the peak
magnitude of the modulation wave, the effect of reducing the
peak value of output waveform without changing the
is achieved. By this method the
amplitude of the modulating waveform can be increased, as a
result of which the full output voltage can be utilized. There
will be 15.5% increase in the amplitude of the fundamental
n.
Sinusoidal Pulse Width Modulation
This technique is implemented when there is usage of multiple
sinusoidal modulating signals and a single carrier signal. These
sinusoidal signals must have the same fundamental frequenc
f
0
and amplitude Am. The pulses are generated based on the
intersection between the sinusoidal signals and the carrier
signal. The single carrier sinusoidal pulse width modulation
technique arrangement is shown in figure 8

Fig 8 Single carrier SPWM signal
SIMULATION RESULTS
The five level H6 bridge inverter operation and its various
results at R load are studied and discussed below. The
representation of APOD pulse generation

(a)
pp- 289-296
292 | P a g e
sinusoidal signals must have the same fundamental frequency
and amplitude Am. The pulses are generated based on the
intersection between the sinusoidal signals and the carrier
signal. The single carrier sinusoidal pulse width modulation
arrangement is shown in figure 8.
SPWM signal
The five level H6 bridge inverter operation and its various
studied and discussed below. The simulink
generation is shown in Figure.9



(b)
Fig. 9: APOD signal (a) simulink representation (b) generated pulses.
The simulink representation of third harmonic injection
strategy is shown in figure 10 and that of SCSPWM is shown
in figure 11.

(a)

(b)
Fig. 10. Third Harmonic injection (a) simulink representation
(b) generated pulses

(a)

(b)
Fig. 11. Single Carrier Sinusoidal Pulse Width Modulation Technique
(a) simulink representation (b) generated pulses

Block diagram representation of five level H6 bridge inverter
is shown in figure 12.

Fig 12. Simulink for five level H6 bridge inverter
The switching sequence waveform of each switch T1 through
T6 using APOD is shown in Figure 13(a) the switching
sequence waveform using third harmonic injection is shown in
figure 13(b) and that of SCSPWM is shown in figure 13(c).

(a)


(b)

( c )
Fig .13. Switching pulses (a) using APOD (b) using third harmonic
injection (c) using SCSPWM technique.
The input voltage applied is 400V and the load resistance is
10ohms. The obtained output voltage of the proposed five
level H6 bridge inverter is shown in figure 14.

Fig 14. Output voltage waveform of five level H6 bridge inverter
The total harmonic distortion THD using APOD for the
output voltage is about 15.52% and it is 1.23% for third
harmonic injection. The harmonic spectrum in the modulation
region M=0.95 is shown in figure 15.

(a)

(b)

(C)
Fig 15.Harmonic spectrum of output voltage (a) using APOD (b)
using third harmonic injection (c) using SCSPWM.


IV. CONCLUSION
The five level H6 bridge inverter is simulated in
MATLAB- Simulink environment using three different pulse
width modulation techniques such as alternative phase
opposition disposition, third harmonic injection and single
carrier sinusoidal PWM techniques. The effective midpoint
voltage control (MVC) provides two more voltage levels in the
output which decreases the switching losses and EMI. The
harmonic performance of the proposed inverter is analyzed and
it seems to be effective with the single carrier pulse width
modulation technique. This topology can be varied to allow the
four quadrant operations.
REFERENCES
[1] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro,
Multilevel voltage-source-converter topologies for industrial
medium-voltage drives, IEEE Trans. Ind. Electron., vol. 54,
no. 6, pp. 29302945, Dec.2007.
[2] J. Rodrguez, J. S. Lai, and F. Z. Peng, Multilevel inverters: A
survey of topologies, controls and applications, IEEE Trans.
Ind. Electron., vol. 49, no. 4, pp. 724738, Aug. 2002.
[3] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. Franquelo,
B. Wu, J. Rodriguez, M. Pandrez, and J. Leon, Recent
advances and industrial applications of multilevel converters,
IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 25532580, Aug.
2010.
[4] J.-S. Lai and F. Z. Peng, Multilevel convertersA new breed
of power converters, IEEE Trans. Ind. Appl., vol. 32, no. 3, pp.
509517, May 1996.
[5] Shukla, A. Ghosh, and A. Joshi, Control schemes for dc
capacitor voltages equalization in diode-clamped multilevel
inverter-based dstatcom, IEEE Trans. Power Del., vol. 23, no.
2, pp. 11391149, Apr. 2008.
[6] Bendre, G. Venkataramanan, D. Rosene, and V. Srinivasan,
Modeling and design of a neutral-point voltage regulator for a
three-level diode clamped inverter using multiple-carrier
modulation, IEEE Trans. Ind. Electron., vol. 53, no. 3, pp.
718726, Jun. 2006.
[7] L. Zhang and S. Watkins, Capacitor voltage balancing in
multilevel flying capacitor inverters by rule-based switching
pattern selection, Elect. Power Appl., vol. 1, no. 3, pp. 339
347, May 2007.
[8] Villanueva, P. Correa, J. Rodriguez, and M. Pacas, Control of
a single-phase cascaded h-bridge multilevel inverter for grid-
connected photovoltaic systems, IEEE Trans. Ind. Electron.,
vol. 56, no. 11, pp. 43994406, Nov. 2009.
[9] S. G. Song, F.S. Kang, and S.-J. Park, Cascaded multilevel
inverter employing three-phase transformers and single dc
input, IEEE Trans. Ind. Electron., vol. 56, no. 6, pp. 2005
2014, Jun. 2009.
[10] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. Pandrez,
A survey on cascaded multilevel inverters, IEEE Trans. Ind.
[11] Y. Liang and C. Nwankpa, A new type of statcom based on
cascading voltage-source inverters with phase-shifted unipolar
SPWM, IEEE Trans. Ind. Appl., vol. 35, no. 5, pp. 11181123,
Sep. 1999.
[12] N. Sujitha, S.Satish kumar, M.Sasikumar Simulation Analysis
of Hybrid Alternative Phase Apposition Disposition PWM
Scheme for Cascaded Multilevel Inverters, IJSER Volume 3,
Issue 10, October 2012.
[13] Y. Zhang and L. Sun, An efficient control strategy for a five-
level inverter comprising flying-capacitor asymmetric H-
bridge, IEEE Trans. Ind. Electron., vol. 58, no. 9, pp. 4000
4009, Sep. 2011.
[14] Ruiz-Caballero, R. Ramos-Astudillo, S. Mussa, and M.
Heldwein, Symmetrical hybrid multilevel dcac converters
with reduced number of insulated DC supplies, IEEE Trans.
Ind. Electron., vol. 57, no. 7, pp. 23072314, Jul. 2010.
[15] F.-P. Zeng, G.-H. Tan, J.-Z. Wang, and Y.-C. Ji, Novel single-
phase fivelevel voltage-source inverter for the shunt active
power filter, Power Electron., vol. 3, no. 4, pp. 480489, Jul.
2010.
[16] Giampaolo Buticchi, Emilio Lorenzani, and Giovanni
Franceschini, A Five-Level Single-Phase Grid-Connected
Converter for Renewable Distributed Systems, IEEE Trans.
Ind. Electron., vol. 60, no. 3, pp. 906918, Jul. 2013.



A Novel Error Detect and Data Recovery Architecture for
Video Compression Application
Balanivetha.K
1
, Judy Jonila.J
2
, Santhana Priyank Costa.B
3
,

Palaniammal.G
4
UG Scholar, Jeppiaar Engineering College, Chennai

ABSTRACT
In this paper, necessary modules have been
inserted to make architecture to insert to motion
estimation. The main aim is focusing on video
coding error detection. It implements a data
recovery with an in built block. An error in the
processing element can be recovered effectively
by this proposed FDDR design which has
significant importance in motion estimation. By
this proposed structure testing of compression
output of motion estimation with a residue and
quotient code generator.
Keywords: Compression of video applications,
Data recovery architecture, Error detector
FDDR design.
1. INTRODUCTION
METHODOLOGIES:
Coding approaches such as parity code, Berger
code, and residue code have been considered for
design applications to detect circuit errors. Residue
code is generally separable arithmetic codes by
estimating a residue for data and appending it to
data. Error detection logic for operations is
typically derived by a separate residue code,
making the detection logic is simple and easily
implemented. For instance, assume that N denotes
an integer, N1 and N2 represent data words, and m
refers to the modulus. A separate residue code of
interest is one in which N is coded as a pair. N m is
the residue N of m modulo. Error detection logic
for operations is typically derived using a separate
residue code such that detection logic is simply and
easily implemented. However, only a bit error can
be detected based on the residue code. [2] The
processing element is the key component of motion
estimation which finds difference between the pixel
values. Additionally, an error cannot be recovered
effectively by using the residue codes Therefore,
this work presents a quotient code, which is derived
from the residue code, to assist the residue code in
detecting multiple errors and recovering errors.

2. PIXEL VALUES

Fig 1: Pixel values
3. NUMERIC CALCULATION
The processing element finds the difference
between the current and the reference pixels.
Consider the first pixel values, 128 and 1. The
output from processing element is 128-1=127.
Calculation of residue and quotient is done with a
modulus values. The modulus chosen is
M=2^6-1=63. RQ values are calculated with
M=63.

4. MAIN MODULE
PROCESSING ELEMENT
RQ CODE GENERATION
TEST CODE GENERATION
ERROR DETECTION CIRCUIT
DATA RECOVERY CIRCUIT



Fig 2: Specific PEi testing processes of the EDDR
architecture
4.1. MODULE DESCRIPTION
4.1.1. PROCESSING ELEMENT
A ME (Motion Estimation) consists of many PEs
incorporated in a 1-D or 2-D array for video
encoding applications. A PE generally consists of
subtraction of the current pixel (Cur pixel) and
reference pixel (Ref_pixel) for video encoding
applications. Notably, some registers and latches
may exist in ME to complete the data shift and
storage. The PEs are essential building blocks and
are connected regularly to construct a ME.
Generally, PEs are surrounded by sets of subtractor
that determine how data flows through them. The
testing assignment of processing element can be
easily achieved by using the fault model, cell fault
model (CFM). Using CFM has received
considerable interest due to accelerated growth in
the use of high-level synthesis, as well as the
parallel increase in complexity and density of
integration circuits (ICs). Using CFM makes the
tests independent of the adopted synthesis tool and
vendor library. Arithmetic modules, are carried out
in the primary element, due to their regularity, are
designed in an extremely dense configuration. A
ME generally consists of PEs with a size of 4 x 4.
However, accelerating the computation speed
depends on a large PE array, especially in high-
resolution devices with a large search range such as
HDTV. Additionally, the visual quality and peak
signal-to-noise ratio (PSNR) at a given bit rate are
influenced if an error occurred in ME process. A
testable design is thus increasingly important to
ensure the reliability of numerous PEs in a ME.
Moreover, although the advance of VLSI
technologies facilitate the integration of a large
number of PEs of a ME into a chip, the logic-per-
pin ratio is subsequently increased, thus decreasing
significantly the efficiency of logic testing on the
chip. As a commercial chip, it is absolutely
necessary for the ME to introduce design for
testability (DFT). Motion estimation is the process
of determining motion vectors that describe the
transformation from one 2D image to another;
usually from adjacent frames in a video sequence.
It is an ill-posed problem as the motion is in three
dimensions but the images are a projection of the
3D scene onto a 2D plane.[4] The motion vectors
may relate to the whole image (global motion
estimation) or specific parts, such as rectangular
blocks, arbitrary shaped patches or even per pixel.
The motion vectors may be represented by a
translational model or many other models that can
approximate the motion of a real video camera,
such as rotation and translation in all three
dimensions and zoom. Closely related to motion
estimation is optical flow, where the vectors
correspond to the perceived movement of pixels. In
motion estimation an exact 1:1 correspondence of
pixel positions is not a requirement. Applying the
motion vectors to an image to synthesize the
transformation to the next image is called motion
compensation. The combination of motion
estimation and motion compensation is a key part
of video compression as used by MPEG 1, 2 and 4
as well as many other video codecs.

4.1.2. RQ CODE GENERATION
Coding approaches such as parity code, Berger
code, and residue code have been considered for
design applications to detect circuit errors. Residue
code is generally separable arithmetic codes by
estimating a residue for data and appending it to
data. Error detection logic for operations is
typically derived by a separate residue code,
making the detection logic is simple and easily
implemented. The basic problem we have to
resolve is that memory and communications
technology isn't totally reliable; we have to expect


and be ready to deal with errors in the hardware. In
Hamming codes changing just one more bit can
result in another valid string, which means we can't
know which bit was wrong: so we can detect an
error but not correct it.
4.2. SUBMODULES
COMPARATOR
PRIORITY ENCODER
MULTIPLEXER
SUBTRACTOR
QUASI BLOCK
4.2.1. COMPARATOR
A digital comparator or magnitude comparator is a
hardware electronic device that takes two numbers
as input in binary form and determines whether one
number is greater than, less than or equal to the
other number. Comparators are used in a central
processing units (CPU) and microcontrollers.
Examples of digital comparator include the CMOS
4063 and 4585 and the TTL 7485 and 74682-'89.
The analog equivalent of digital comparator is the
voltage comparator. Many microcontrollers have
analog comparators on some of their inputs that can
be read or trigger an interrupt. A digital comparator
is an electronic circuit or device capable of
accepting two binary signals and performing tests
on those signals to determine their equivalence to
each other. The simplest form of a digital
comparator compares two binary signals, known in
computer processing as bits, and uses a series of
logical gates to determine if the two bits are equal
or if one is greater than the other based on binary
logic in which each signal is given the value of
either zero or one. The comparator can only handle
binary data, meaning that whatever the input
mechanism is, the signal coming into the circuit
can only have two states, which commonly are
referred to as zero and one. When a bit is compared
to another bit, it can be tested in one of three ways
by the digital comparator. The first is equivalency,
meaning the result of comparing one bit to another
will result in a positive, or true, result if both of the
bits equal one or if both of the bits equal zero.
Individual bits also can be checked to see if one is
greater than or less than another. For a sequence of
bits, however, comparisons to determine which set
has a higher or lower value need to check each bit
to see which set has a more highly placed most
significant bit, because this determines the actual
numerical value of the bit set. A digital comparator
also can be used in conjunction with a number of
other devices to act as a monitor in an industrial
setting to see accurate digital information about the
state of a machine.
This is useful if we want to compare two variables
and want to produce an output when any of the
above three conditions are achieved.
TABLE 1: 1-bit comparator

PRIORITY ENCODER
Here we applied input width is 5 bit and output
width is 3 bit by using priority encoder. A priority
encoder is a circuit or algorithm that compresses
multiple binary inputs into a smaller number of
outputs. The output of a priority encoder is the
binary representation of the ordinal number starting
from zero of the most significant input bit. They are
often used to control interrupt requests by acting on
the highest priority request. If two or more inputs
are given at the same time, the input having the
highest priority will take precedence. An example
of a single bit 4 to 2 encoder is shown, where
highest-priority inputs are to the left and "x"
indicates an irrelevant value - i.e. any input value
there yields the same output since it is superseded
by higher-priority input. The output V indicates if
the input is valid. Priority encoders can be easily
connected in arrays to make larger encoders, such
as one 16-to-4 encoder made from six 4-to-2
priority encoders. Four 4-to-2 encoders having the
signal source connected to their inputs, and the two
remaining encoders take the output of the first four


as input. The priority encoder is an improvement
on simple encoder circuit in terms of all handling
possible input configurations. The output from the
priority encoder is used to output the residue and
quotient values.
4.2.2. MULTIPLEXER
This module will generate reminder code according
to selection line. We applied three input signal as
mux_in and m. We obtain the output specific signal
from given input signal. If a greater than B is equal
to 1 will get mux_in signal. If A lesser than B we
get m signal. Otherwise we get 0(8 bit signal). A
data selector, more commonly called a Multiplexer,
shortened to "Mux" or "MPX", are combinational
logic switching devices that operate like a very fast
acting multiple position rotary switch. They
connect or control, multiple input lines called
"channels" consisting of either 2, 4, 8 or 16
individual inputs, one at a time to an output. Then
the job of a multiplexer is to allow multiple signals
to share a single common output. For example, a
single 8-channel multiplexer would connect one of
its eight inputs to the single data output.
Multiplexers are used as one method of reducing
the number of logic gates required in a circuit or
when a single data line is required to carry two or
more different digital signals.
4.2.3. SUBTRACTOR
Here we calculate the difference between input
signal and specific constant value with help of
subtraction. This model converts two rotations A
and B into their difference A-B. This is useful for
various applications. For instance, when you build
a treaded vehicle such as a construction bulldozer,
you'd like one motor to control total motion, and
the other the turning. This construction does that:
connect the treads to the (A+B) and (A-B) axles,
and the motors to A and B. Now motor A makes
the vehicle go forward or backward, and B turns it
left or right. Of course you can also run them
simultaneously. The great advantage is that you can
now guarantee that the two sides of the treaded
vehicle run at the same speed that does not happen
with 2 motors, they always have a slight power
difference. So it is more likely that it goes straight
when you want it to. The subtractor used here is to
represent division operation required to obtain
quotient and residue values. Non restoring division
methodologies is implemented in this system.
4.2.4. QUASI BLOCK
This block will generate quotient value according
to given input. Here we applied 3 bit input then
generate 8 bit signal as output. This 8-bit signal is
coded as the quotient value. The output of the
priority encoder is applied to the quasi block. The
priority encoder generates a 3-bit value which is
mapped to produce the quotient value from the
quasi block.

Fig 3: Block diagram of RQCG
4.2.5. TEST CODE GENERATOR
TCG design is based on the ability of the RQCG
circuit to generate corresponding test codes in order
to detect errors and recover data. TCG is an
important component of the proposed EDDR
architecture. The specific PEi in estimates the
absolute difference between the Cur_pixel of the
search area and the Ref_pixel of the current macro
black. The output of TCG generates residue and
quotient for the particular pixel values. It consists
of 5 RQCG block and comparator, single
accumulator block and subtractor.

4.2.6. COMPARATOR
In this module compare the both pixel values
(current frame and reference frame) finally we will
get the two output signal. When a bit is compared
to another bit, it can be tested in one of three ways


by the comparator. The first is equivalency,
meaning the result of comparing one bit to another
will result in a positive, or true, result if both of the
bits equal one or if both of the bits equal zero. The
pixel value that is large is checked and utilized for
code generation.
4.2.7. ADDER
Here we taken two 3 bit input and we will get 8bit
output as sum by adder In this module describe
about full adder operation. Here we get quotient
code from sum value. The limitation of a half-adder
is that it cannot accept a carry-in bit. The carry-in
bit represents the carry-out of the previous low-
order bit position. Thus a half-adder can be used
only for the two least significant digits when
adding two multibit binary numbers, since there
can be no possibility of a propagated carry to this
stage. In multibit addition, a carry bit from a
previous stage must be taken into account, which
gives rise to the necessity for designing a full
adder. A full adder can accept two operands bits, ai
and bi, and a carry-in bit ci from previous stage; it
produces a sum bit si and a carry-out bit c0. sum bit
si is 1 if there is an odd number of 1s at the inputs
of the full adder, whereas the carry-out c0 is 1 if
there are two or more 1s at the inputs. The sum
and carry out bits will be 0 otherwise. In ripple
carry adder, the carry signals must ripple through
all the full adders before the outputs stabilize to the
correct values; hence such an adder is often called a
ripple adder.
4.2.8. ACCUMULATOR

In this module consists of flip-flop which act as a
accumulator. We can store a bit of data. Flip-flop"
is the common name given to two-state devices
which offer basic memory for operations. Flip-
flops are heavily used for digital data storage and
transfer and are commonly used in banks called
"registers" for the storage of binary numerical data.
There are some circuits that are not quite as straight
forward as the gate circuits we have discussed in
earlier lessons. However, you still need to learn
about circuits that can store and remember
information. They're the kind of circuits that are
used in computers to store program information.

4.2.9. ERROR DETECTION CIRCIUT

In this module indicates that the operations of error
detection in a specific PEi is achieved by using
EDC, which is utilized to compare the outputs
between TCG and in rder to determine whether
errors have occurred. The EDC output is then used
to generate a 0/1 signal to indicate that the tested
PEi is error-free/errancy. Using XOR operation can
be identify the error if any variation in terms of
residue and quotient value. Because a fault only
affects the logic in the fan-out cone from the fault
site, the good circuit and faulty circuits typically
only differ in a small region. Concurrent fault
simulation exploits this fact and simulates only the
differential parts of the whole circuit. Concurrent
fault simulation is essentially an event-driven
simulation with the fault-free circuit and faulty
circuits simulated altogether. In concurrent fault
simulation, every gate has a concurrent fault list,
which consists of a set of bad gates. A bad gate of
gate x represents an imaginary copy of gate x in the
presence of a fault. Every bad gate contains a fault
index and the associated gate I/O values in the
presence of the corresponding fault. Initially, the
concurrent fault list of gate x contains local faults
of gate x. The local faults of gate x are faults on the
inputs or outputs of gate x.[2] As the simulation
proceeds, the concurrent fault list contains not only
local faults but also faults propagated from
previous stages. Local faults of gate x remain in the
concurrent fault list of gate x until they are
detected. As we move to the nanometer age, we
have begun to see nanometer designs that contain
hundreds of millions of transistors.

4.2.10. DATA RECOVERY CIRCUIT

In this module will be generate error free output by
quotient multiply with constant value (64) and add
with reminder code. During data recovery, the
circuit DRC plays a significant role in recovering
RQ code from TCG. Notably, the proposed EDDR
design executes the error detection and data
recovery operations simultaneously. Additionally,
error-free data from the tested PEi or data recovery
that results from DRC is selected by a multiplexer
(MUX) to pass to the next specific PEi+1for
subsequent testing.
The temporal domain techniques that we have
considered rely on information in the previous


frame to perform the reconstruction. However, if
the previous frame is heavily damaged, the
prediction of the next frame may also be affected.
For this reason, we must consider making the
prediction before the errors have occurred.
Obviously, if one frame has been heavily damaged,
but the frame before that has not been damaged, it
makes senses to investigate how the motion vectors
can be extrapolated to obtain a reasonable
prediction from a past reference frame. If the BER
is high and/or the burst length is long, the impact of
a damaged frame can propagate, hence the problem
is more global and seems to require a more
advanced solution, i.e., one which considers the
impact over multiple frames. In the following, we
propose an approach that considers making
predictions from a past reference frame, which has
not been damaged.[1] In method which
reconstructs the frame with the aid of neighbor
motion vector is successfully applied to motion
estimation. Thus, an error signal 1 is generated
from EDC and sent to mux in order to select the
recovery results from DRC.

Fig 4: Processing Element

Fig 5: RQ code generation

Fig 6: Test code generation

Fig 7: Error detection circuit

Fig 8: Data recovery block

www.ijrde.com


Fig 9: Top Module
6. DEVICE UTILIZATION SUMMARY
TABLE 2: Device Utilization Summary

7. CONCLUSION
This work presents EDDR architecture for
detecting the errors and recovering the data of PEs
in motion estimation. Experimental results indicate
that the proposed EDDR architecture can
effectively detect errors and recover data in PEs of
a ME with reasonable area overhead and only a
slight time penalty. Existing system realizes only
residue codes for difference of the pixels. The
proposed system is based on the Residue and
Quotient code, a RQCG-based TCG design
developed to generate the corresponding test codes
to detect errors and recover data. The reliability
issues of the particular design are improved greatly
by detection of errors in the processing element and
the throughput of the system is also increase
to recovery of data from the quotient code and
residue code generated from the test code
generator.

DEVICE UTILIZATION SUMMARY
2: Device Utilization Summary

This work presents EDDR architecture for
detecting the errors and recovering the data of PEs
in motion estimation. Experimental results indicate
that the proposed EDDR architecture can
and recover data in PEs of
a ME with reasonable area overhead and only a
slight time penalty. Existing system realizes only
residue codes for difference of the pixels. The
proposed system is based on the Residue and
based TCG design is
developed to generate the corresponding test codes
to detect errors and recover data. The reliability
issues of the particular design are improved greatly
by detection of errors in the processing element and
the throughput of the system is also increased due
to recovery of data from the quotient code and
residue code generated from the test code
REFERENCE
[1] C. Y. Chen, S. Y. Chien, Y. W. Huang, T. C. Chen,
T. C. Wang, and L. G. Chen, (Mar. 2006)
architecture design of variable block
estimation for H.264/AVC, IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 53, no. 3, pp. 578593.
[2] C. L. Hsu, C. H. Cheng, and Y. Liu, (Feb. 2010)
Built-in self-detection/correction architecture for
motion estimation computing arrays, IEEE Trans. Vary
Large Scale Integr. (VLSI) Systs., vol. 18, no. 2, pp.
319324.
[3] C. H. Cheng, Y. Liu, and C. L. Hsu, (2009)
cost BISDC design for motion estimation computing
array, in Proc. IEEE Circuits Syst. Int. Conf., , pp. 1
[4] D. Li, M. Hu, and O. A. Mohamed, (Jun. 2004)
Built-in self-test design of motion estimation computing
array, in Proc. IEEE Northeast Workshop Circuits
Syst., pp. 349352.
[5] Y. S. Huang, C. J. Yang, and C. L. Hsu, (Dec. 2009)
C-testable motion estimation design for video coding
systems, J. Electron. Sci. Technol., vol. 7, no. 4, pp.
370374.

sue: pp- 297-303
303 | P a g e
C. Y. Chen, S. Y. Chien, Y. W. Huang, T. C. Chen,
T. C. Wang, and L. G. Chen, (Mar. 2006) Analysis and
block-size motion
, IEEE Trans. Circuits Syst. I,
593.
[2] C. L. Hsu, C. H. Cheng, and Y. Liu, (Feb. 2010)
detection/correction architecture for
, IEEE Trans. Vary
Large Scale Integr. (VLSI) Systs., vol. 18, no. 2, pp.
[3] C. H. Cheng, Y. Liu, and C. L. Hsu, (2009) Low-
cost BISDC design for motion estimation computing
, in Proc. IEEE Circuits Syst. Int. Conf., , pp. 14.
M. Hu, and O. A. Mohamed, (Jun. 2004)
test design of motion estimation computing
, in Proc. IEEE Northeast Workshop Circuits
[5] Y. S. Huang, C. J. Yang, and C. L. Hsu, (Dec. 2009)
ign for video coding
l., vol. 7, no. 4, pp.


A Zigzag Transformer Based Three Phase Ups System with
SPWM Controller Operating Under Highly Non Linear Loads
Mekala.S
1
, Nandhini.C
2
, Pavithra.S
3
1,2,3
Electrical and Electronics Engineering, Jeppiaar Engineering College, Chennai, India,

ABSTRACT
This Paper presents the usage of zigzag transformer
with sinusoidal pulse width modulation controller
operating under highly non linear loads. The increased
use of rectifier loads draws highly non linear currents
and UPS outputs get distorted. The distortion causes
generation of low dc output voltage resulting in
malfunction of the critical load or UPS system,
increased power losses, heavy current flow. The
voltage drop across the inductive elements of the LC
filter is the main cause of the distortion. The inverter
is highly responsible for generating sinusoidal voltages
using pulse width modulation controller in the UPS
system. In order to remove the switching frequency
harmonics which are generated from PWM operation
of the inverter, inductive elements has to be removed.
To overcome the problem an optimum filter with
small inductance value is designed; even then the
distortion is not completely eliminated. So, a proper
inverter controller has to be designed to control signal
which has the ability to carry information to produce
sine voltage. Better efficiency, fast transient response,
distortion gets reduced even under highly non linear
loads.
1. INTRODUCTION
In military, medical equipment and in information
technologies the increased usage of rectifiers in the UPS
system distort the UPS output because the high power
single phase rectifier loads draw highly non linear current
which cause generation of low dc output voltage. This
distortion result in high current flow, malfunction of UPS
system, increased power loss. The voltage drop across the
inductive element is the main reason for the distortion.
The switching frequency harmonics in the current
waveform is generated by PWM operation of the UPS
system which can be reduced by the removal of inductive
element [1-3]. Even under the usage of small inductive
value, the distortion cannot be completely reduced. So the
proper controller has to design which can carry signals for
generating of sine voltages. Fast dynamics response, low
THD can be obtained.
2. CIRCUIT DESCRIPTION
2.1. EXISTING MODEL
2.1.1. BLOCK DIAGRAM

Fig.1 Block diagram of FIXED PWM system
2.1.2. EXPLANATION
The existing system consists of ac source, filter unit,
rectifier, and inverter and control units. Filter removes the
harmonics generated by the natural ac source. Rectifier
unit is used to convert the ac into dc.
Disadvantages:
Total harmonic distortion will be more in the
output.
Circuits become bulky.
Generate harmonic distortion in the output
voltages.
Switching losses will be more in the output.

2.2. PROPOSED MODEL
2.2.1. EXPLANATION


The block diagram consists of ac source, filter unit,
rectifier, and inverter and control units. Filter removes the
harmonics generated by the natural ac source. Rectifier
unit is used to convert the ac into dc.
2.2.2. BLOCK DIAGRAM

Fig. 2 Block diagram of SPWM system

The stationary or synchronous-frame space-vector PWM
(SVPWM)-based controllers are the primary choice of
many researchers and the applications currently used in
industry, however, the classical sinusoidal PWM (SPWM)
method is still preferred by many manufacturers because
of its implementation simplicity, easy tuning even under
load, flexibility, and most importantly the advantages of
controlling each phase independently. The independent
regulation of each phase provides easy balancing of three-
phase voltages which makes heavily unbalanced loading
possible. Also, it avoids problems such as transformer
saturation [4-5]. Although the classical SPWM method is
quite effective in controlling the RMS magnitude of the
UPS output voltages, it is not good enough in
compensating the harmonics and the distortion caused
specifically by the nonlinear loads.
2.2.3. Advantages
The optimization may include obtaining the
lowest THD or the best tracking of the RMS
value or the fastest Dynamic response.
The easy tuning of the proposed method under
load is verified during the experimental studies.
The scalability that It means that the controller is
easy to design and tunable for any power level.
Total harmonic distortion (THD) has been
improved.

3. MODES OF OPREATION

180 Degree Conduction
For this mode of operation, each device conducts 180
degrees. The sequence of firing is: 123, 234, 345, 456,
561, and 612. The gating signals are shifted from each
other by 60 degrees.

Fig. 3 Waveform for 180 deg. Conduction



Fig. 4 waveform of 180 deg. Conduction.
4.1. EXISTING SIMULATION CIRCUIT

Fig. 5 Fixed PWM simulation circuit

Fig. 6 Voltage waveform



Fig. 7 Current waveform

Fig. 7 THD in voltage

4.2. PROPOSED SIMULATION CIRCUIT

Fig. 8 SPWM simulation circuit



Fig. 9 Voltage waveform

Fig. 10 Current waveform

Fig. 11 THD in voltage
5. TABULATION
TABLE 1 Results of a zigzag transformer under non-linear load
PARAMETER
FIXED PWM
RESULT
SINUSOIDAL
PWM RESULT
VOLTAGE 76.4 127.3
CURRENT 0.288 0.15
THD IN
VOLTAGE
1.18% 0.89%

6. CONCLUSION
Our paper concludes about the design and performance of
SPWM controller for three-phase UPS systems operating
under highly nonlinear loads with zigzag transformer.
Although the fixed PWM method is very successful in
controlling the RMS magnitude of the UPS output
voltages, it cannot effectively compensate for the
harmonics and the distortion caused by the nonlinear
currents drawn by the rectifier loads. Therefore, the
modified controller is designed which has the capacity to
carry signals for the generation of sine voltages. This
brings the effective control RMS magnitude of the UPS
output voltages and also effective reduction of harmonics
and distortions. The fastest transient response is achieved
by the use of SPWM controller in the UPS system. It adds
inner loops to the closed loop Control system effectively
that enables successful reduction of harmonics and
compensation of distortion at the voltages. A THD equal


to 0.89% at the output voltage is achieved even under the
worst nonlinear load.
REFERENCE
[1]. Abdel-Rahim.N.M and Quaicoe.J.E., Analysis and design
of a multiple feedback loop control strategy for single-phase
voltage-source UPS inverters, IEEE Trans. Power
Electron., vol. 11, no. 4, pp. 532541, Jul.
[2]. Borup.U, Enjeti.P.N, and Blaabjerg.F, A new space-vector-
based control Method for UPS systems powering nonlinear
and unbalanced loads,IEEE Trans. Industry Appl., vol. 37,
no. 6, pp. 18641870, Nov./Dec.
[3]. Botteron.F, Pinheiro.H,and Grundling.H.A., Digital
Voltage and current controllers for three-phase PWM
inverter for UPS Applications, in Proc. 36th Annu. Meeting
IEEE Ind. Appl., Chicago, IL,Sep./Oct. 2001, vol. 4, pp.
26672674.
[4]. Botteron.F and Pinheiro.H, A three-phase UPS that
complies with the standard IEC 62040-3, IEEE Trans. Ind.
Electron., vol. 54, no. 4, pp. 21202136, Aug. 2007.
[5]. Jiang.S, Cao.D, Li.Y, Liu.J, and Peng.F.Z, Low THD, fast
transient, and cost-effective synchronous-frame repetitive
controller for three-phase UPS inverters, IEEE Trans.
Power Electron., vol. 27, no. 6, pp. 2294 3005,2012.


An Intelligent Parking and Navigation System Using
Radio Frequency Identification
A.Sharat Jaffry
1
, M.Somsundarm
2
, S.Shiv Prashad
3
, S.K. Binu Siva Singh
4
Electronics and Communication Engineering, Jeppiaar Engineering College, Chennai, India,

ABSTRACT
An Embedded system is a special purpose
computer controlled electro-mechanical system in
which the computer is completely encapsulated by
the device it controls. An embedded system has
specific requirements and performs pre-defined
tasks, unlike a general-purpose personal
computer. An embedded system is a computer-
controlled system. The core of any embedded
system is a microprocessor, programmed to
perform a few tasks (often just one task). This is to
be compared to other computer systems with
general purpose hardware and externally loaded
software loaded software. Embedded systems are
often designed for mass production. Embedded
systems are computer systems in the widest sense.
They include all computers. Most commercial
embedded systems are designed to do some task at
a low cost. Most, but not all have real- time system
constraints that must be met. They may need to be
very fast for some functions, but most other
functions will probably not need speed. These
systems meet their real- time constraints with a
combination of special purpose hardware and
software tailored to the system requirements. It is
difficult to characterize embedded systems by
speed or cost, but for high volume systems, cost
usually dominates the system design. Often many
parts of an embedded system need low
performance compared to the primary mission of
the system. This allows an embedded system to be
intentionally simplified to lower costs compared to
a general- purpose computer accomplishing the
same task, by using a CPU that is just good
enough for these secondary functions. Embedded
systems reside in machines that are expected to
run continuously for years without errors.
Therefore the software is usually developed and
tested more carefully than software for Personal
computers. Many embedded systems avoid
mechanical moving parts such as Disk drives,
switches or buttons because these are unreliable
compared to solid- state parts such as Flash
memory. In addition, the embedded systems may
be outside the reach of humans, so the embedded
system must be able to restart itself even if
catastrophic data corruption has taken place. This
is usually accomplished with a standard electronic
part called a watchdog timer that resets the
computer unless the software periodically resets
the timer.
I. INTRODUCTION
Embedded Systems are divided into four major
categories:
Autonomous
Real- Time
Networked and
Mobile
AUTONOMOUS:
Autonomous Systems function in standalone mode.
Many embedded systems used for process control in
manufacturing units and automobiles fall under this
category. In process control systems the inputs
originated from transducers that convert a physical
quantity, such as temperature into an electrical signal.
The systems output controls the device[1-5]. In
standalone systems, the deadlines or response times
are not critical. An air-conditioner can be set to turn
on when the temperature reaches a certain level,
measuring instruments and CD players are examples
of Autonomous Systems.
REAL-TIME:
Real-Time embedded systems are required to carry
out specific tasks in a specified amount of time.


These systems are extensively used to carry out time-
critical task in process- control. For instance, a boiler
plant must open the valves if the pressure exceeds a
particular threshold. If the job is not carried out in the
stipulated time, a catastrophe may result.
NETWORKED:
Networked embedded systems monitors plant
parameters, such as temperature, pressure and
humidity will send the data over the network to a
centralized system for online monitoring [6-8]. A
networked-enabled web camera monitoring the plant
floor transmits its video output to a remote
controlling organization.
MOBILE:
Mobile gadgets need to store databases locally in
their memory. These gadgets have powerful
computing and communication capabilities to
perform Real-Time as well as non-Real-Time tasks
and handle multimedia applications. The gadgets
embedded powerful processor and OS, and a lot of
memory with minimal power consumption.
HARDWARE AND SOFTWARE
In an embedded system, assigning functions to
hardware and software is a vital consideration.
Hardware implementation has the advantages that the
task execution is faster than in software
implementation. On the flip side, the hardware chip
occupies space, cost money, and consumes power.
Good software design in embedded systems stems
from a good understanding of the hardware behind it.
Processor
Memory
Peripherals
PROCESSOR
Each design is unique in embedded system. But to
make the system intelligent we use processors and
the kind of processors used in are quite varied. A
plethora of processors are available to cater to
different applications. 8- Bit, 16- bit, and 32- bit
processors are available with different processing
powers and memory addressing capabilities. A list of
some of the common processor families are: Intel
8051/80188/x86 family, Motorola 68k family, Zilog
Z8 family and the PowerPC family. Application
functionality processing speed and memory
capability dictate processor selection.
a) 8- Bit Processors: Application involving
Minimal Processing and I/O functions such as
digital watches, refrigerators, air- conditioners
and VCRs use an 8- bit Microcontrollers.
The Hardware Cost is Minimal since an 8- bit
microcontroller has On- Chip Memory
and Serial Interface and so on. The System
become Portable in turns of size and is usually
popular for consumer electronics. Like a digital
watch incorporating an 8- bit controller uses a set
of buttons for input and an LCD for output.
b) 16-/32-/64- bit Processors: Application involving
More Processing and I/O Functions such as
Process Control Systems, Telecom Switches,
Routers and Protocols Converters use 16-/32- bit
Processor with more computing and
communication capabilities.
Industrial and Single- Board computers
incorporated in Industrial Automation Processes,
Video Game Players and Graphic Accelerators
need 64- bit Processor.
MEMORY
An Embedded System also needs Memory for two
Purposes:
To store its program and
To store its data
Unlike normal desktops, in which programs and data
are stored at same place, embedded systems store
data and programs in different memories. This is
simply because the embedded system doesnt have a


hard drive and the program must be stored in
memory, even when the power is turned off
System space: The Motorola 68k family reserves the
first 1024 memory locations for exception vector
tables. This system can support upto 256 vectors.
Code space: Above the system space code space
stores the instructions.
Data space: Above code space ROM data space
stores the constant values such as error messages and
string literals.
I/O space: Devices reside in I/O space area.
PERIPHERALS
Any additional requirement in an embedded system is
dependent on the equipment it is controlling. Very
often these systems have a Standard Serial Port,
Network Interfaces, Input/output (I/O) interface or
hardware to interact with sensors and activators on
the Equipment.
II. PROPOSED SYSTEM
RFID Enabled Automated Parking Access Control
Systems. RFID parking access control system that
can be implemented quickly and simply. This parking
solution is ideal for apartments and condos, gated
communities, business parking lots and garages,
university parking areas and recreation operations
from hotels to RV camps.

Fig. 1 Parking Lot Vehicle Management System
RFID parking solution enables you to operate an
unattended parking barrier with controlled parking
access privileges. By using RFID technology you can
issue parking passes, either windshield type tags are
RFID cards that are specific to the user. Once the
new car with the tag enters the barrier, the controller
checks the free parking slot. The free/occupied
parking slot is identified using IR Transmitter and
Receiver [8-11]. These passes can be controlled to
determine the type and time of access permitted and
can be activated and deactivated remotely by the
operator. While exit the same tag is shown and the
parking amount will be displayed in the LCD.

Fig. 2 Block diagram
III. HARDWARE SPECIFICATIONS
AT89S52 MICROCONTROLLER
The AT89S52 is a low-power, high-performance
CMOS 8-bit microcontroller with 8K bytes of in-
system programmable Flash memory. The device is
manufactured using Atmels high-density nonvolatile
memory technology and is compatible with the
Indus-try-standard 80C51 instruction set and pin out.
MEMORY ORGANIZATION
As you can see, all the operations within the
microcontroller are performed at high speed and quite
simply, but the microcontroller itself would not be so


useful if there are not special circuits which make it
complete. In continuation, we are going to call your
attention to them.
READ ONLY MEMORY (ROM)
Read Only Memory (ROM) is a type of memory used
to permanently save the program being executed. The
size of the program that can be written depends on
the size of this memory. ROM can be built in the
microcontroller or added as an external chip, which
depends on the type of the microcontroller. Both
options have some disadvantages. If ROM is added
as an external chip, the microcontroller is cheaper
and the program can be considerably longer. At the
same time, a number of available pins is reduced as
the microcontroller uses its own input/output ports
for connection to the chip. The internal ROM is
usually smaller and more expensive, but leaves more
pins available for connecting to peripheral
environment. The size of ROM ranges from 512B to
64KB
RANDOM ACCESS MEMORY (RAM)
Random Access Memory (RAM) is a type of
memory used for temporary storing data and
intermediate results created and used during the
operation of the microcontrollers. The content of this
memory is cleared once the power supply is off. For
example, if the program performs an addition, it is
necessary to have a register standing for what in
everyday life is called the sum . For that purpose,
one of the registers in RAM is called the "sum" and
used for storing results of addition. The size of RAM
goes up to a few KBs. Electrically Erasable
Programmable ROM (EEPROM). The EEPROM is a
special type of memory not contained in all
microcontrollers. Its contents may be changed during
program execution (similar to RAM ), but remains
permanently saved even after the loss of power
(similar to ROM)It is often used to store values,
created and used during operation (such as calibration
values, codes, values to count up to etc.), which must
be saved after turning the power supply off. A
disadvantage of this memory is that the process of
programming is relatively slow. It is measured in
milliseconds.
SPECIAL FUNCTION REGISTERS (SFR)
Special function registers are part of RAM memory.
Their purpose is predefined by the manufacturer and
cannot be changed therefore. Since their bits are
physically connected to particular circuits within the
microcontroller, such as A/D converter, serial
communication module etc., any change of their state
directly affects the operation of the microcontroller or
some of the circuits. For example, writing zero or one
to the SFR controlling an input/output port causes the
appropriate port pin to be configured as input or
output. In other words, each bit of this register
controls the function of one single pin.
PROGRAM COUNTER
Program Counter is an engine running the program
and points to the memory address containing the next
instruction to execute. After each instruction
execution, the value of the counter is incremented by
1. For this reason, the program executes only one
instruction at a time just as it is written.
Howeverthe value of the program counter can be
changed at any moment, which causes a jump to a
new memory location. This is how subroutines and
branch instructions are executed. After jumping, the
counter resumes even and monotonous automatic
counting +1, +1, +1
CENTRAL PROCESSOR UNIT (CPU)
As its name suggests, this is a unit which monitors
and controls all processes within the microcontroller
and the user cannot affect its work. It consists of
several smaller subunits, of which the most important
are:
Instruction decoder is a part of the electronics which
recognizes program instructions and runs other
circuits on the basis of that. The abilities of this
circuit are expressed in the "instruction set" which is
different for each microcontroller family.


Arithmetical Logical Unit (ALU) performs all
mathematical and logical operations upon data.
Accumulator is an SFR closely related to the
operation of ALU. It is a kind of working desk used
for storing all data upon which some operations
should be executed (addition, shift etc.).
It also stores the results ready for use in further
processing. One of the SFRs, called the Status
Register, is closely related to the accumulator,
showing at any given time the "status" of a number
stored in the accumulator (the number is greater or
less than zero etc.). A bit is just a word invented to
confuse novices at electronics. Joking aside, this
word in practice indicates whether the voltage is
present on a conductor or not. If it is present, the
appropriate pin is set to logic one (1), i.e. the bits
value is 1.
Otherwise, if the voltage is 0 V, the appropriate pin is
cleared (0), i.e. the bits value is 0. It is more
complicated in theory where a bit is referred to as a
binary digit, but even in this case, its value can be
either 0 or 1.
INPUT/OUTPUT PORTS (I/O PORTS)
In order to make the microcontroller useful, it is
necessary to connect it to peripheral devices. Each
microcontroller has one or more registers (called a
port) connected to the microcontroller pins.
Why do we call them input/output ports? Because it
is possible to change a pin function according to the
user's needs. These registers are the only registers in
the microcontroller the state of which can be checked
by voltmeter.
OSCILLATOR
Even pulses generated by the oscillator enable
harmonic and synchronous operation of all circuits
within the microcontroller. It is usually configured as
to use quartz-crystal or ceramics resonator for
frequency stabilization. It can also operate without
elements for frequency stabilization (like RC
oscillator). It is important to say that program
instructions are not executed at the rate imposed by
the oscillator itself, but several times slower.
It happens because each instruction is executed in
several steps. For some microcontrollers, the same
number of cycles is needed to execute any
instruction, while it's different for other
microcontrollers. Accordingly, if the system uses
quartz crystal with a frequency of 20MHz, the
execution time of an instruction is not expected 50nS,
but 200, 400 or even 800 nS, depending on the type
of the microcontroller.
TIMERS/COUNTERS
Most programs use these miniature electronic
"stopwatches" in their operation. These are
commonly 8- or 16-bit SFRs the contents of which is
automatically incremented by each coming pulse.
Once the register is completely loaded, an interrupt is
generated!
If these registers use an internal quartz oscillator as a
clock source, then it is possible to measure the time
between two events (if the register value is T1 at the
moment measurement has started, and T2 at the
moment it has finished, then the elapsed time is equal
to the result of subtraction T2-T1 ).
If the registers use pulses coming from external
source, then such a timer is turned into a counter.
Automotive electronics are a demanding application,
encompassing a wide range of products, from body
electronics, engine components, and access systems
to lighting and entertainment components.
They must support small designs and offer a high
level of integration, to fit the limited space available
in automotive environments. To meet the diverse
needs of a variety of automotive applications,
developers need solutions that offer:


1. Compliance with strict automotive
qualification demands, including industry
standards and automotive-qualified fabs.
2. Flexible interface options for a variety of
HMI capabilities.
3. Standards-based connectivity for intelligent
networked solutions.
4. Protection and compatibility for high-
voltage products, including robust
electromagnetic compatibility (EMC);
electrostatic discharge (ESD) protection; and
OEM approvals.
5. Resistance to high temperatures for trouble-
free operation in automotive environments.
6. Maximum safety for automobile access.
7. Low power consumption for maximum
efficiency.
Building Automation: Today's intelligent home and
building automation solutions offer new levels of
comfort, security, and efficiency. To develop the
sophisticated solutions that meet the needs that
consumers demand, designers need standards-based,
flexible technology that can provide:
1. Innovative touch control to enable a variety
of home devices, including remote controls,
control panels, or thermostats.
2. Power efficiency to meet the needs of
today's green applications.
3. Compatibility with standards-based
technology to bring innovative solutions to
market, fast.
4. Support for wireless networking to enable
home connectivity.
5. Robust security through hardware
authentication and secure communication,
which is essential for highly networked
devices.
Home Appliances: More than ever, consumers have
high expectations for home appliances. They demand
sophisticated, feature-rich products that are reliable
and easy to use. To meet these needs, developers of
white goods need technology that provides:
1. Advanced motor control features for safe,
quiet operation.
2. Green, power-efficient technology, as well
as energy measurement and control through
connectivity with smart metering networks.
3. Advanced human machine interface (HMI)
support through touchscreen technology for
a rich, easy user experience.
4. Flexible, compatible connectivity to
integrate devices with the outside world.
5. Standards-based certification to enable
reliable, high-quality solutions.
Industrial Automation: As industrial environments
become more advanced and connected, automation
technology is developing at a rapid pace. To deliver
the communication features and intelligence required
at the plant floor and beyond, developers need
solutions that can provide:
1. High performance together with power
efficiency.
2. Rugged environmental design to resist
water, dust, moisture, and extreme
temperatures.
3. Advanced, yet cost effective Human
Machine Interface (HMI) features.
4. Support for high-speed wired and wireless
communication.
5. Dedicated features for functional safety
implementation.
Lighting: Fluorescent and LED lights use 50 to 80
percent less energy than their incandescent
counterparts. No wonder U.S. and European
governments are pushing vendors for lighting
solutions that rely on high frequency electronic
ballasts. Successful ballast design depends on a few
key tradeoffs:
1. Balancing ease of use against design
complexity and cost.
2. Balancing voltage and current control
against design complexity and board space.
3. Balancing functionality against low power
consumption.
Metering: The market for energy, water, and gas
metering systems is rapidly changing, driven by new
environmental and conservation concerns and


regulations. Traditional standalone meters are now
being replaced by complex networked systems that
utilize a variety of communication methods. To meet
the needs of this evolving Smart Grid, metering
developers need solutions that can provide intelligent
support for application and communication stacks
robust security functionality:
1. Remote upgrades in the field.
2. Support for communications protocols for
home connectivity.
RFID READER & IR SENSORS
Radio Frequency Identification (RFID) is a system
that facilitates the tracking of objects, primarily for
inventory tracking, via a three part technology
comprised of a reader, a transceiver with decoder and
a transponder (RF tag). RFID is a wireless system
that works in conjunction with an organizations
information technology infrastructure to improve
business processes such as inventory management
and efficiency in supply chain management. The
development of RFID was spurred by the need to
enhance tracking and access applications in the
1980s in manufacturing and other hostile
environments. This no contact means of gathering
and tracking information proved to be resilient. RFID
is now an established part of specific business
processes in a variety of markets. The reader emits a
radio signal that activates the tag and reads and writes
data to it. As products are shipped, received or stored,
the information (encoded on a bar code like tag) can
be read and received by the reader, which is attached
to a computer. RFID has been integrated into the
EPC globalM network and uses the EPC (Electronic
Product Code). The EPC is a unique number that
identifies a specific item in the supply chain. The
EPC is stored on a RFID tag, which combines a
silicon chip and a reader. Once the EPC is retrieved
from the tag, it can be associated with dynamic data
such as the origin of an item

IV. IR SENSOR
OVERVIEW OF THE IR SENSOR
This sensor can be used for most indoor applications
where no important ambient light is present. For
simplicity, this sensor doesn't provide ambient light
immunity, but a more complicated, ambient light
ignoring sensor should be discussed in a coming
article. However, this sensor can be used to measure
the speed of object moving at a very high speed, like
in industry or in tachometers. In such applications,
ambient light ignoring sensor, which rely on sending
40 KHz pulsed signals cannot be used because there
are time gaps between the pulses where the sensor is
'blind'.
The solution proposed doesn't contain any special
components, like photo-diodes, photo-transistors, or
IR receiver ICs, only a couple if IR LEDs, an Op
amp, a transistor and a couple of resistors. In need, as
the title says, a standard IR led is used for the
purpose of detection. Due to that fact, the circuit is
extremely simple, and any novice electronics
hobbyist can easily understand and build it.
OBJECT DETECTION USING IR LIGHT
It is the same principle in ALL Infra-Red proximity
sensors. The basic idea is to send infra-red light
through IR-LEDs, which is then reflected by any
object in front of the sensor.
Then all you have to do is to pick-up the reflected IR
light. For detecting the reflected IR light, we are
going to use a very original technique: we are going
to use another IR-LED, to detect the IR light that was
emitted from another led of the exact same type. This
is an electrical property of Light Emitting Diodes
(LEDs) which is the fact that a led produce a voltage
difference across its leads when it is subjected to
light. As if it was a photo-cell, but with much lower
output current. In other words, the voltage generated
by the LEDs can't be - in any way - used to generate
electrical power from light, It can barely be detected.
Thats why as you will notice in the schematic, we
are going to use a Op-Amp (operational Amplifier) to
www.ijrde.com


accurately detect very small voltage changes.
Fig. 3 Object Detection Using IR
Fig. 4 IR sensor
The IR Sensor-Single is a general purpose proximity
sensor. Here we use it for collision detection. The
module consists of a IR emitter and IR receiver pair.
The high precision IR receiver always detects a IR
signal. The module consists of 358 comparator IC.
The output of sensor is high whenever it IR
frequency and low otherwise. The on
indicator helps user to check status of the sensor
without using any additional hardware. The power
consumption of this module is low. It gives a digital
output.
Functional description
The output voltage is generated by a thermopile,
formed by a series connection of thermo junctions
deposited on a silicon substrate. The hot junctions are
thermally isolated from the cold junctions on the
substrate by etching an extremely thin membrane. A
black absorbing layer on the hot junctions transform
the incoming radiation into heat. A voltage
proportional to the radiation is generated by the
thermoelectric effect.
ISSN: 2279-0500 Special Is
accurately detect very small voltage changes.

Single is a general purpose proximity
sensor. Here we use it for collision detection. The
module consists of a IR emitter and IR receiver pair.
The high precision IR receiver always detects a IR
ignal. The module consists of 358 comparator IC.
The output of sensor is high whenever it IR
frequency and low otherwise. The on-board LED
indicator helps user to check status of the sensor
without using any additional hardware. The power
is module is low. It gives a digital
The output voltage is generated by a thermopile,
thermo junctions
deposited on a silicon substrate. The hot junctions are
d junctions on the
substrate by etching an extremely thin membrane. A
black absorbing layer on the hot junctions transform
the incoming radiation into heat. A voltage
proportional to the radiation is generated by the
The used thermopiles are processed on 400 mm
silicon substrates using BiSb and NiCr for the thermo
junctions. For different radiation spectra various
filters are available to get the optimal solution. Easy
and accurate measuring of the sensor temperature can
be done with a built-in temperature sensor (only for
type SMTIR9902).
Product description
The Smartec infrared sensors SMTIR99XX are
sophisticated full silicon infrared sensors and
comprise of so called thermopiles. Thermopiles are
based on the Seebeck effect, which
standard for conventional thermocouples. The
application of thin film technology allows the
production of miniaturized and low cost sensor
elements. For specific applications there is a version
with a small openings angle (7).
The sensors can be used in measuring the radiation
temperature without any contact. For different
radiation temperature ranges various filters are
available. The sensor type SMTIR9902 contains a
temperature sensor for measuring the temperature of
the sensor itself. The temperature range of the sensor
element is between -40 to 100 C. The sensor is
available in a standard TO-05 encapsulation and is
equipped with a 5.5 micrometer filter. For small field
of view there is an infrared sensor available with a
silicon lens.
V. CONCLUSION
The problems that existed in the previous models
were rectified using this proposed model. Various
drawback such as excessive time consumption, cost
effectiveness, reduced efficiency because of the use
of man power and Security issues were elimina
in the model.

REFERENCES
sue: pp- 310-318
317 | P a g e
iles are processed on 400 mm
silicon substrates using BiSb and NiCr for the thermo
junctions. For different radiation spectra various
filters are available to get the optimal solution. Easy
and accurate measuring of the sensor temperature can
in temperature sensor (only for
The Smartec infrared sensors SMTIR99XX are
sophisticated full silicon infrared sensors and
comprise of so called thermopiles. Thermopiles are
based on the Seebeck effect, which is a long time
standard for conventional thermocouples. The
application of thin film technology allows the
production of miniaturized and low cost sensor
elements. For specific applications there is a version

an be used in measuring the radiation
temperature without any contact. For different
radiation temperature ranges various filters are
available. The sensor type SMTIR9902 contains a
temperature sensor for measuring the temperature of
temperature range of the sensor-
40 to 100 C. The sensor is
05 encapsulation and is
equipped with a 5.5 micrometer filter. For small field
of view there is an infrared sensor available with a
The problems that existed in the previous models
were rectified using this proposed model. Various
drawback such as excessive time consumption, cost
reduced efficiency because of the use
of man power and Security issues were eliminated as


[1] S. He and M. Torkelson, Design and implementation
of a 1024-point pipeline FFT processor, in Proc. IEEE
Custom Integrated Circuits Conf., May 1998, pp. 131134.
[2] M. A. Sanchez, M. Garrido, M. L. Lopez, and J.
Grajal, ImplementingFFT- based digital channelized
receivers on FPGA platforms, IEEE Trans. Aerosp.
Electron. Syst., vol. 44, no. 4, pp. 15671585, Oct. 2008.
[3] A. Cortes, I. Velez, and J. F. Sevillano, Radix rk
FFTs: Matricial representation and SDC/SDF pipeline
implementation, IEEE Trans. Signal Process., vol. 57, no.
7, pp. 28242839, Jul. 2009.
[4] E. H. Wold and A. M. Despain, Pipeline and parallel-
pipeline FFT processors for VLSI implementations, IEEE
Trans. Comput., no. 5, pp. 414426, May 1984.
[5] S.-N. Tang, J.-W. Tsai, and T.-Y. Chang, A 2.4-GS/s
FFT processor for OFDM-based WPAN applications,
IEEE Trans. Circuits Syst. I, vol. 57, no. 6, pp. 451455,
Jun. 2010.
[6] H. Liu and H. Lee, A high performance four-parallel
128/64-point radix-24 FFT/IFFT processor for MIMO-
OFDM systems, in Proc. IEEE Asia Pacific Conf. Circuits
Syst., 2008, pp. 834837.
[7] L. Liu, J. Ren, X. Wang, and F. Ye, Design of low-
power, 1GS/s throughput FFT processor for MIMO-OFDM
UWB communication system, in Proc. IEEE Int. Symp.
Circuits Syst., May 2007, pp. 25942597.
[8] N. Li and N. P. van der Meijs, A radix 22 based
parallel pipeline FFT processor for MB-OFDM UWB
system, in Proc. IEEE Int. SOC Conf., 2009, pp. 383386.
[9] S.-I. Cho, K.-M. Kang, and S.-S. Choi, Implementation
of 128-point fast Fourier transform processor for UWB
systems, in Proc. Int. Wireless Comm. Mobile Comp.
Conf., 2008, pp. 210213.
[10] C. Cheng and K. K. Parhi, High-throughput VLSI
architecture for FFT computation, IEEE Trans. Circuits
Syst. II, vol. 54, no. 10, pp. 863867, Oct. 2007.
[11] J. A. Johnston, Parallel pipeline fast Fourier
transformer, in IEE Proc. F Comm. Radar Signal Process.,
vol. 130, no. 6, Oct. 1983, pp. 564572.


Automated Peripheral Neuropathy Assessment of
Diabetic Patients using Optical Imaging and
Binary Processing Techniques
Suman, K
1
, Mohan Kumar
2
, G.M. Andrew
3
, Jerome
4
Electronics and Communication Engineering, Jeppiaar Engineering College, Chennai, India,

ABSTRACT
Plantar sensory neuropathy (PSN) affects a
large proportion of individuals suffering from
type 2 diabetes. In order to avoid ulceration or
other damage to patients' feet regular testing
and assessment of PSN needs to be undertaken.
Currently, the standard test involves a trained
podiatrist visiting the patient and testing their
feet manually with a simple hand-held nylon
monofilament probe. This process is time
consuming, requires special training and is
prone to errors. Moreover, the number of PSN
sufferers is increasing and has already reached
such numbers as to make manual testing
unfeasible. Hence, our research team is
currently developing an automated PSN testing
device that will ultimately be capable of reliably
testing a patient at home, providing direct
feedback while registering and communicating
this information to a local health care practice.
An initial investigation is presented into a novel
approach to automatically identify the areas of
interest on a given patient's foot via optical
image processing. That is to say, we present a
method to reliably select suitable test points on
the plantar surface that correspond to those
chosen by a trained podiatrist. Once these
points have been ascertained they will be sent to
a microcontroller based robotic mechanism
that subsequently tests the plantar surface with
a monofilament probe. The robotic actuator
will apply the probe to the pressure points of
plantar surface a required number of times. On
each application the patients' response, or lack
of, will be recorded to identify the insensitive
region of the plantar surface. The system will
effectively automate the traditional Semmes-
Weinstein monofilament examination (SWME).
A CUI will be developed to show the statistics
about patient sensory neuropathy.
I. INTRODUCTION
Diabetes Mellitus is a chronic illness currently
affecting upwards of 8% of the developed world,
with growing numbers in developing countries
such as China and India.
In Europe alone there are roughly 27 million
registered diabetics, the majority of these
individuals (>80%) present Type 2 diabetes.
Around half of these are aged 60 and over. The
management of diabetes and its complications
reportedly required close to 10% of the total
budget of the UK National Health Service (NHS)
in 2011 alone. Diabetic peripheral neuropathy is a
common complication of diabetes mellitus,
typically around 60% of all Type 2 diabetics will
develop this condition within 10 years of being
first diagnosed. The condition tends to affect the
peripheral extremities of the body, often starting
with numbness of the toes and then the soles of the
feet. This peripheral sensory neuropathy is
commonly regarded as a key factor in the
development of ulceration in the feet. If not
carefully monitored and treated, lower limb
amputation is commonly indicated [1]. Sufferers
lose mobility and this degenerative process has a
dramatic impact on their quality of life. Healthy
feet are clearly fundamental in enabling the elderly
to maintain an active and healthy lifestyle and
reduce their risk of falling.
Currently accepted techniques for the assessment
of peripheral neuropathy such as the vibration and
neurometer methods to identity insensitive regions
on the plantar surface of the patient are considered
quite rudimentary. Research has shown that the
inability to detect a 109 force (i.e. 98mN) applied
to key weight bearing points indicates a degree of
neuropathy which is consistent with increased risk
of ulceration. Currently, in order to test this, an
extruded homopolymer, known as the Semmes-
Weinstein Monofilament (SWM) is applied to the


patient's foot at various pressure points by a
trained clinician. The monofilament is designed to
bend by lOmm when 109 (98mN) of force is
applied. At this point the patient is required to
acknowledge whether they can or cannot feel the
probe on the area in question and the process is
repeated for a number of sites on both feet. This
technique is considered cumbersome, labour
intensive, repeatability is difficult to maintain and
prone to experimenter bias [4].
Furthermore, the resources required simply to test
current sufferers outstrips that which is available
from national health providers. Therefore, there is
a clear and present need to expedite and simplify
the testing procedure.
Innovative analytical methods using image
processing and computer-assisted diagnosis are
rapidly growing in areas of medical applications.
The aim of this study is to investigate a novel
approach to fabricate an automated system to test
for sensory neuropathy of the plantar surface.
Diabetic feet develop calluses that can become
ulcerated. It has been shown that higher foot
pressure is the major cause of developing calluses,
so in regards of diabetic foot ulcers, measuring the
foot pressure points on plantar surface is of prime
importance.
The authors propose to develop an automated
device to replace the need for a trained specialist
to attend in person. Such a device could be
deployed in the home enabling users to test
themselves much more regularly and, crucially, in
a more reliable and rigorous manner. The
proposed device would give direct feedback to
users after testing and communicate results
directly to health care trusts and doctors' surgeries
as desired. It would empower patients to manage
their own care under guidance and in this way,
significantly reduce the risk of ulceration and loss
of limbs, having a dramatic effect on the quality of
life of many elderly diabetes sufferers. This will
also enable the creation of a database containing
patient foot images, mapping a patient's
progression to help practitioners better understand
their individual care requirements and helping
research.
II. METHODOLOGY
A unique approach to automate the Semmes-
Weinstein Monofilament Examination (SWME) is
proposed by exploiting optical detection and
binary image processing. Overall the system is
shown in Figure 1. Here a perforated glass sheet
rests on a scanner structure with a built in
mechanically driven probe element. First, the
optical scanner section is used to obtain the image
of the plantar surface of the patient. The glass
sheet serves two purposes (a) it has a removable
thin film to provide hygienic patient foot support
and (b) holes within the sheet permit a probe to
pass through so that the accepted 109 (98mN) of
force can be applied. In order to reduce the system
complexity holes on the sheet are equidistant in
both the horizontal (x) and vertical (y) domains
The image is scanned at a resolution of 300 dpi to
aid the visualization of the patients' pressure
points. The orientation of these pressure points is
then determined in both x and y dimensions by a
novel image processing technique. The
localization information is then sent to a micro-
controller which uses two stepper motor driven
linear rails to position the force sensing probe at
the relevant test location. A third linear actuator
then applies the probe at the appropriate speed
consistent with the SWME test, until 98mN of
force is applied. The position of the probe is
dictated by the results of the novel image
processing algorithm. An example of a test image
is shown in Figure 2 and will be discussed
subsequently. To complete the SWME, the probe
is relocated to four or five tests site for each foot
and the patient's response is duly noted with a
simple hand-held button. The image processing
development from the initial foot image algorithm
development consists of a number of discrete
repeated steps:
1. Obtain an image in RGB color space
2. Convert the image into HSV (Gray color)
color space
3. Threshold the grayscale image at a
specific level according to a human
plantar color range
4. Dilate, Erode and Smooth the image to
remove noise
5. Draw contours of resulting binary image
www.ijrde.com


6. Calculate the central point of specific
contours (polygon) in terms of
coordinates
7. Send these points to micro-controller
8. Activate the servo and the probe
accordingly.
The image shown in Figure 2 is taken as the basic
starting point. The software for image processing
was developed in C using the opencv library. The
image in Figure 2 is converted into a black and
white, binary (threshold) image.
Using various image processing functions the
image can be specified into explicit color ranges.
These functions can be used to clarify if the pixels
in an image fall within a particular specified range.
Each pixel of the source image (such as that shown
in Figure 2) is compared with that particular
specified range. If the pixel's value in source image
is outside of the specified range, (here the specified
further analysis on generic color space is
to account for different patient ethnicities. Once a
binary image is obtained, edge detection becomes
less complex. From here the foot area and
subsequently the pressure point coordinates are
calculated. Functions are used to detect foot edges
and compute contours [7]. The authors used a two-
dimensional dynamic array (vector) of type Points
to store these contours. Another function draws a
polygon around these contours. Finally, a function
bounds each polygon in a rectangle by calculating
the extreme contour points. When a foot is pressed
against a surface in the normal manner some parts
of plantar surface i.e. toe, metatarsal and heel are in
greater contact with the said surface and experience
more pressure than other parts of the foot [8]. In
this study the investigators are interested in plantar
areas that are in contact with the surface, since the
pressure points lie in those areas, as can be seen
from the foot scan shown in Figure 2. Figure 3b
shows the resulting polygons bounded by
Calculate the central point of specific
contours (polygon) in terms of
controller
Activate the servo and the probe
The image shown in Figure 2 is taken as the basic
image processing
was developed in C using the opencv library. The
image in Figure 2 is converted into a black and
sing various image processing functions the
ns can be used to clarify if the pixels
of the specified range, (here the specified
l of the source image (such as that shown
analysis on generic color space is ongoing
nt for different patient ethnicities. Once a
binary image is obtained, edge detection becomes
less complex. From here the foot area and
subsequently the pressure point coordinates are
calculated. Functions are used to detect foot edges
[7]. The authors used a two-
dimensional dynamic array (vector) of type Points
to store these contours. Another function draws a
polygon around these contours. Finally, a function
bounds each polygon in a rectangle by calculating
s. When a foot is pressed
against a surface in the normal manner some parts
of plantar surface i.e. toe, metatarsal and heel are in
greater contact with the said surface and experience
more pressure than other parts of the foot [8]. In
tigators are interested in plantar
areas that are in contact with the surface, since the
pressure points lie in those areas, as can be seen
from the foot scan shown in Figure 2. Figure 3b
shows the resulting polygons bounded by
rectangles and can be identified by their sizes,
namely toe (hallux), metatarsal head and heel
(condyle) polygons. The pressure points are now
easily recognizable. From here we decide where to
apply the probe. The work [9], has shown how we
can obtain the central point of each polygo
the following equations:
1 N-l
Cx =
6A
(Xi +Xi+1)(X)';+1 -Xi+l1';) . . . . . . . . .
. . . . (1)
1 N-l
Cy = 6A L(1'; +1';+l)(Xi1';+l -Xi+l1';) . . . . . . . . . .
. . . . . . (2)
1=0
In image processing techniques the ongm (0, 0) of
an image is set at the top left comer of the image
and the bottom right pixels give maximum width
and height values.
Specific points must now be chosen at different
locations on these polygons to represent the probe
contact pressure points. The resulting poly
irregularly shaped, thus polygon centroid equations
(1) and (2) are utilized to detect
polygon. From here circles of equal radii are
produced in order to specify the probe point as
shown in Figure 3b.
The center of the toe polygon (
calculated using above equations (1) and (2). For
the metatarsal head areas we chose three areas
based on the information provided by health
experts. This leads to three circles, but this number
can be increased or decreased depending on
requirements. Equations (1) and (2) only provide
the center of the polygon that will give one circle in
the middle.
For the right most circle on the metatarsal pressure
point zone we take the largest x coordinate (to get
the right most point) of the polygon pro
arc on the right most part of the metatarsal pressure
point area. The left circle is found in the same
manner but using the smallest x coordinate.
sue: pp- 319-323
321 | P a g e
fied by their sizes,
namely toe (hallux), metatarsal head and heel
(condyle) polygons. The pressure points are now
easily recognizable. From here we decide where to
apply the probe. The work [9], has shown how we
can obtain the central point of each polygon using
Xi+l1';) . . . . . . . . .
Xi+l1';) . . . . . . . . . .
In image processing techniques the ongm (0, 0) of
image is set at the top left comer of the image
and the bottom right pixels give maximum width
Specific points must now be chosen at different
locations on these polygons to represent the probe
contact pressure points. The resulting polygons are
irregularly shaped, thus polygon centroid equations
(1) and (2) are utilized to detect center of each
polygon. From here circles of equal radii are
produced in order to specify the probe point as
of the toe polygon (contours) is
calculated using above equations (1) and (2). For
the metatarsal head areas we chose three areas
based on the information provided by health
experts. This leads to three circles, but this number
can be increased or decreased depending on
rements. Equations (1) and (2) only provide
of the polygon that will give one circle in
For the right most circle on the metatarsal pressure
point zone we take the largest x coordinate (to get
the right most point) of the polygon providing an
arc on the right most part of the metatarsal pressure
point area. The left circle is found in the same
manner but using the smallest x coordinate.


The heel polygon (contours) requires a circle
positioned at the edge of the heel color contrast
shown in the Figure 4. As contours are stored in
two dimensional vector points, the above location
can be identified by finding the largest height (y
coordinate) values in these contours. The largest
height value of contours should logically always be
located at the edge of the heel. This is currently
under further investigation. Once the circles are
determined, it must be ensured that they align fully
with an entire hole on the perforated sheet to enable
appropriate probe pressure application and to avoid
probe damage. Although the probe pressure points
have been determined, it does not mean a probe
point will align appropriately with the center of
these circles as is evident from Figure 5. In order to
ensure that a probe point is found accurately within
the pressure circle, the ensuing method is applied.
a) The first top left hole on the perforated
sheet is taken as the reference point as
shown in the Figure 6. This will remain as
the reference point for all subsequent
processing and images are aligned to
match this reference. The top left hole
from a fixed image is now known as "ref
coordinates" and for the presented image
has fixed coordinates (156, 107).
Furthermore the generated pressure point
circle has a center C with coordinates (X
c
,
Y
d
as shown in Figure 7. Since all the
holes are equidistantly separated (row 88
pixels) and columns (178 pixels),
excluding at the moment bowing from
heavy feet (currently being analyzed), the
position of all holes is identifiable.
b) From here we then find the closest
complete hole inside the generated circle
on the perforated sheet nearest to the
center of the pressure point circle C.
The process of selecting appropriate holes on the
perforated sheet for the probe is the same for all
circles. Consider the selection of the closest hole to
the center of pressure point circle at toe.
III. CONCLUSION
A novel approach towards automation of plantar
surface sensory neuropathy is proposed. In this
approach a scanner is used to obtain the patients
plantar surface image. Then via developed image
processing, and now working on its generalization,
the orientations of pressure points are identified.
This information is then sent to a robotic arm
holding a monofilament probe. The robotic arm
will be used to conduct the Semmes-Weinstein
Monofilament Examination (SWME) procedure as
it is conducted in hospital or health care center
manually. The patient's feedback will be recorded
to identify the insensate area of plantar surface.
REFERENCES
1. R. S. Saurin and K. M. Patil. "Processing of
foot pressure images and display of an
advanced clinical parameter PR in Diabetic
Neuropathy", Proceedings of the 2nd
International IEEE EMBS Conference on
Neural Engineering. pp. v, 2005.
2. G. David, N. Singh, Armstrong, A Benjamina,
Lipsky. (2005 Jan). "Preventing Foot Ulcers
in Patients With Diabetes" The Journal of the
American Medical Assoication Available:
http://jama.jamanetwork.com/article.
aspx?articleid=200119[Accessed 4/08/2012].
3. A. Nather, S.H. Neo, B.C. Siok, C.F. Stanley.
Liew, Y.S. Eileen, L.L. Jocelyn L.L. Chew
(2008). Assessment of sensory neuropathy in
diabetic patients without diabetic foot
problems, Journal of Diabetes and Its
Complications, pp. 126-127.

4. B. Geofrey. "Mechanical sensory threshold
testing using nylon monofilaments: The pain
field's "Tin Standard"". Department of
Anesthesia and Critical Care, Beth Israel
Deaconess Medical Center and Harvard
Medical School., pp 13-17, 2006.
5. E.L Thomas, I. R. Barry and V. Aristidis
"Foot Pressure Abnormalities in the Diabetic
Foot" in The Diabetic Foot, 2nd. ed., Humana
Press. 2006, ch. 9, pp. 171.
6. J. M. B. Andrew, "The Pathway to Ulceration:
Aetiopathogenesis" , The Foot in Diabetes,
3rd. ed., WILEY, pp. 25.


7. G. Bradski and A. Kaebler, "Learning opencv
computer vision with opencv library,"
Newgen Publishing and Data Services, 2008.
8. S. Lin, H. Tao, W. Yangyong, L. Qiao, D.F.
David and T. Xiaoming. "In-Shoe Plantar
Pressure Measurement and Analysis System
Based on Fabric Pressure Sensing Array"
IEEE Transactions on information technology
in biomedicine, Vol. 14, No. 3, pp. 769,2010.
9. Paul Bourke (1988) [WWW] "Calculating the
area and centroid of a polygon" Available
from: ttp://paulbourke.net/geometry/polyarea/



Correlation Based Feature Extraction for Power Quality
Disturbance Classification
Saranya.V
1
, Sriranjane.S.S
2
, Vanitha.C
3

1
Electrical and Electronics Engineering, Jeppiaar Engineering College, Chennai, India
2
3

ABSTRACT
This paper proposes a method for classification of
power quality disturbance based on correlation
technique and features selection is done by using
rough set theory. The disturbances classified are
sag, swell, harmonics and comparisons are made
with normal voltage. The developed scheme can
efficiently sense the power quality disturbances by
the features extracted from the cross-correlogram
of power quality disturbance waveforms.
Classification of these disturbances is highly
essential with advancements in the field of
electronics. Power quality is one of the major
problems in transmission and distribution
network. Especially, with the introduction of
highly sophisticated devices, which are very
sensitive to the quality of power supply. Studies of
power quality phenomena have emerged as an
important subject in recent years. To improve the
quality of the power signals it is important to
sense and classify various Power Quality (PQ)
disturbances. The analysis by classification of the
power quality disturbances helps in
understanding the history of disturbances. This
data could be further used for achieving higher
levels of power quality. The simulation results
validate the accuracy and efficiency of the
proposed method. The stand-alone module is
developed on a PIC18F series microcontroller.
The analysis is carried out in real-time which is
implemented by a hardware model.
Keywords: Correlation Technique,
Microcontroller, Power Quality, Rough Set
Theory, Stand-Alone Module
I. INTRODUCTION
A properly installed and configured monitoring
system is a valuable asset to almost all types of
consumers. All consumers have different variety of
considerations and concerns where energy usage is
involved. This is mainly due to the diversity of load
types and requirements. Studies of power quality
phenomena have emerged as an important subject in
recent years. To improve the quality of the power
signals it is important to sense and classify various
Power Quality (PQ) disturbances [1-3]. In an
electrical network the power signals are contaminated
with different types of power quality disturbances
like sag, swell, transients, harmonics etc. Power
quality problems are voltage sag, swell, unbalance
etc. These disturbances are injected into the line due
to electrical hazard like short circuit of a live part,
switching of heavy load etc. Moreover, lightning
strikes etc. introduce the transients in the power
signal. In addition to these, usage of nonlinear
electronic loads, solid state converters also introduce
the notches, harmonics and transients in the power
signals [4-6]. If these disturbances are not corrected
properly they can cause failure or malfunction of
different equipment connected to the user end. This
paper presents the scheme of Rough Set based
optimal or, minimal set of feature selection and
classification of power quality disturbances that can
be implemented in a general purpose microcontroller.
The problem in hand is addressed in two different
stages. The first one is to extract several features
from the recorded signal and in the second stage
optimal number of these features are selected and
classified using suitable classification algorithm.
Correlation based method is used for feature
extraction because of its low computational burden,
which is desirable for microcontroller based system,
as it has limited space in program memory. Also
another advantage of the correlation method is that it
reduces the effect of uncorrelated noise present in the


signal while extracting the features. Moreover, the
real-time applications demand less computational
time for instantaneous response [6-7]. Hence, this
correlation based technique is used successfully for
feature extraction of different types of signals with
reasonable accuracy.
1. HARDWARE STRUCTURE OF THE
DEVELOPED MODULE
The standalone system for power quality monitoring
is developed as a compact module with its heart
being a PIC18F series microcontroller, which has a
16-bit data bus having a modified Harvard
architecture with an enhanced instruction set. The
whole system is designed on the basis of a single
analog input channel and is suitable for automatic
long-duration power quality monitoring. The system
is flexible and the operations are controlled through
software. This would allow future up gradations and
modifications without the necessity of making major
changes in hardware of the module. The system has a
provision to be connected to a computer through the
RS232 link. This allows communications between a
PC and the developed PQ monitoring system for the
purpose of post processing of any relevant data, if
required. The schematic of the PQ monitoring unit is
shown.
The main component of the data acquisition system is
the PIC18F series microcontroller. It has got 44 K
words of program memory and 8 K of data memory.
It is chosen for this application because of its low-
power consumption, comparatively low-cost and
inbuilt 10-bit A/D converter facilitating direct analog
inputs to be fed at its pin. This ADC works according
to the principle of Successive Approximation (SAR)
conversion with Conversion speeds of up to 500
kSps. To ensure optimum circuit design and
minimum power consumption, the ports of the
microcontroller are used effectively. The scaled
voltage from the operational amplifier (IC1) is fed to
the port B pin (RB0/AN0) that is configured to accept
analog input. The parallel master port (PMP) of the
microcontroller is programmed as data line output to
a 162 alpha-numeric backlit LCD.. The display is
configured to show the status of the input power
quality, i.e. sag swell etc.
[1]
. The photograph of
developed PQ monitoring module is shown in Fig. 2.
For the purpose of implementation of classifying the
PQ disturbances in the hardware, an autotransformer
is used for varying the supply voltage.
www.ijrde.com


Fig.1: Schematic of Hardware Structure
Autotransformers are often used to step up or step
down voltages. The autotransformer is used in this
hardware for the introduction of sag or swell in the
circuit. The optocoupler circuit provides for electrical
isolation in the hardware prototype. In this a bulb is
used as the load. Programming making use of the
correlation technique is implemented in the
microcontroller. In case of power quality events like
sag, swell or harmonics the load is tripped and the
occurrence of the event is displayed on the LCD. In
case of normal voltage the load is not tripped and the
equipment are protected from the power quality
events. This this is a stand-alone module that could
be implemented and used on a real time basis
are often used to step up or step
down voltages. The autotransformer is used in this
for the introduction of sag or swell in the
The optocoupler circuit provides for electrical
isolation in the hardware prototype. In this a bulb is
used as the load. Programming making use of the
correlation technique is implemented in the
microcontroller. In case of power quality events like
ell or harmonics the load is tripped and the
occurrence of the event is displayed on the LCD. In
case of normal voltage the load is not tripped and the
equipment are protected from the power quality
module that could
a real time basis.
Fig. 2: Stand Alone PQ Monitoring Module
2. CORRELATION BASED FEATURE
EXTRACTION
Correlation is a Digital Signal Processing method
involving mathematical operation that closely
resembles convolution. There are two different
methods in correlation: cross
autocorrelation. In cross-correlation, two different
signals were compared to measure the degree to
which the two signals are similar. Autocorrelation is
the cross-correlation of a signal with itself. Features
based on cross correlation method give better
sue: pp- 324-331
326 | P a g e

Fig. 2: Stand Alone PQ Monitoring Module
CORRELATION BASED FEATURE
Correlation is a Digital Signal Processing method
involving mathematical operation that closely
resembles convolution. There are two different
methods in correlation: cross-correlation and
correlation, two different
ompared to measure the degree to
which the two signals are similar. Autocorrelation is
correlation of a signal with itself. Features
based on cross correlation method give better
www.ijrde.com


performance as compared to that of autocorrelation
based features.
A part from being a simple algorithm to be
implemented in a general microcontroller, another
advantage of using cross correlation technique is that,
it can minimize the effect of random uncorrelated
noise present in the signal. It means that, if two
signals are contaminated with random uncorrelated
noise, then the effect of that noise will not be
reflected in the cross correlogram of these two
signals as cross correlation coefficient value for
random uncorrelated noise are very small. Hence we
make use of cross-correlation method.
Fig. 3: Block Diagram of Proposed Scheme
3.1. FLOWCHART FOR PROPOSED SCHEME
The flowchart explaining the process flow of the
project is as shown below. Initially the program is
started. After starting, two inputs X and Y are
obtained from the rough set theory and the analog to
digital converter. Using these inputs the correlation
coefficient is obtained. The correlation between two
variables is the degree to which there is a 'linear
relationship' between them. Correlation is usually
expressed as a 'coefficient' which measures the
strength of that linear relationship between the
variables. The method used here is the
product moment coefficient for the calculation for
correlation coefficient. The correlation coefficient
can vary between -1 and1.
performance as compared to that of autocorrelation
A part from being a simple algorithm to be
implemented in a general microcontroller, another
advantage of using cross correlation technique is that,
it can minimize the effect of random uncorrelated
noise present in the signal. It means that, if two
ls are contaminated with random uncorrelated
noise, then the effect of that noise will not be
reflected in the cross correlogram of these two
signals as cross correlation coefficient value for
random uncorrelated noise are very small. Hence we

Fig. 3: Block Diagram of Proposed Scheme
FLOWCHART FOR PROPOSED SCHEME
The flowchart explaining the process flow of the
project is as shown below. Initially the program is
started. After starting, two inputs X and Y are
obtained from the rough set theory and the analog to
digital converter. Using these inputs the correlation
correlation between two
variables is the degree to which there is a 'linear
relationship' between them. Correlation is usually
expressed as a 'coefficient' which measures the
strength of that linear relationship between the
iables. The method used here is the Pearson
product moment coefficient for the calculation for
The correlation coefficient
Fig. 4: Flowchart of Proposed Scheme
The classification of the power quality events done is
simulated by means of the Proteus software. Using
this software the power quality events like sag, swell,
harmonics are displayed.
for TExt Easy to USe) is a fully functional,
procedural programming language created in 1998 by
Simone Zanella. Proteus incorporates many functions
derived from several other languages: C, BASIC,
Assembly, Clipper/dBase; it is especially versatile in
dealing with strings, having hundreds of dedicated
functions; this makes it one of the richest languages
for text manipulation. Language
[7]
The simulations are obtained for the following cases:
1. Normal Voltage
2. Swell Voltage
3. Sag Voltage
4. Normal Voltage with harmonics
5. Swell Voltage with harmonics
6. Sag Voltage with harmonics
The simulation results are shown in the following
diagrams. The virtual terminal shows whether the
sue: pp- 324-331
327 | P a g e

Fig. 4: Flowchart of Proposed Scheme
SIMULATION RESULTS
the power quality events done is
simulated by means of the Proteus software. Using
this software the power quality events like sag, swell,
Proteus (PROcessor
) is a fully functional,
procedural programming language created in 1998 by
Simone Zanella. Proteus incorporates many functions
derived from several other languages: C, BASIC,
/dBase; it is especially versatile in
dealing with strings, having hundreds of dedicated
ne of the richest languages
[7]
.
The simulations are obtained for the following cases:
4. Normal Voltage with harmonics

The simulation results are shown in the following
diagrams. The virtual terminal shows whether the
www.ijrde.com


normal mode or harmonics mode is selected and also
whether sag, swell or normal voltage is present.
TABLE 1: Parameters of PQ Events
S.NO TYPE OF
WAVEFORM
VOLTAGE
VALUE
(V)
Fig 5: Simulation for Normal Voltage Waveform
Fig. 6: Simulation for Swell Voltage Waveform
normal mode or harmonics mode is selected and also
whether sag, swell or normal voltage is present.
VOLTAGE pu
VALUE
1. NORMAL 230
2. SAG 180
3. SWELL 260
Fig 5: Simulation for Normal Voltage Waveform
Fig. 6: Simulation for Swell Voltage Waveform
sue: pp- 324-331
328 | P a g e
1
0.78
1.13

www.ijrde.com


Fig. 7: Simulation for Sag Voltage Waveform
Fig. 8: Simulation of Normal Voltage Waveform with Harmonics
Fig. 9: Simulation of Swell Voltage Waveform with Harmonics
Fig. 7: Simulation for Sag Voltage Waveform
Simulation of Normal Voltage Waveform with Harmonics
Fig. 9: Simulation of Swell Voltage Waveform with Harmonics
sue: pp- 324-331
329 | P a g e

www.ijrde.com


Fig. 10: Simulation of Sag Voltage Waveform with Harmonics
4. CONCLUSION
A novel approach based on Rough set theory for
power quality disturbance sensing is implemented in
a general purpose microcontroller. Cross
technique is used in this project as feature extraction
tool because it minimizes the effect of random n
present in the signal and also offers low
computational burden. Results show that the
developed module can be used effectively to sense
power quality disturbances for applications with
reasonable accuracy. The proposed system was
implemented by using simulation and hardware.Thus,
using the method of cross-correlation and rough set
theory the power quality disturbances like sag, swell,
harmonics were extracted from the input signal.
Correspondingly the load was tripped in case of a
power quality event. In case normal voltage is present
the loads are unaffected. Therefore we can ensure
that the equipment used in the system is protected
from the events of sag, swell and harmonics. The
future scope of the project might be extended for the
classification of other power quality disturbances like
flickering, Momentary interruption and impulsive
transients. Further, the scope could be extended
towards the mitigation of the classified power quality
disturbances.
REFERENCES
[1]. Sovan Dalai, Biswendu Chatterjee,
Debangshu Dey, Sivaji Chakravorti,
Rough-Set-Based Feature Selection and
Classification for Power Quality Sensing
Fig. 10: Simulation of Sag Voltage Waveform with Harmonics
A novel approach based on Rough set theory for
power quality disturbance sensing is implemented in
a general purpose microcontroller. Cross-correlation
technique is used in this project as feature extraction
tool because it minimizes the effect of random noise
present in the signal and also offers low
computational burden. Results show that the
developed module can be used effectively to sense
power quality disturbances for applications with
reasonable accuracy. The proposed system was
simulation and hardware.Thus,
correlation and rough set
theory the power quality disturbances like sag, swell,
harmonics were extracted from the input signal.
Correspondingly the load was tripped in case of a
In case normal voltage is present
the loads are unaffected. Therefore we can ensure
that the equipment used in the system is protected
harmonics. The
future scope of the project might be extended for the
other power quality disturbances like
flickering, Momentary interruption and impulsive
, the scope could be extended
towards the mitigation of the classified power quality
Sovan Dalai, Biswendu Chatterjee,
Debangshu Dey, Sivaji Chakravorti,
Based Feature Selection and
Classification for Power Quality Sensing
Device Employing Correlation Techniques
IEEE Sensors Journal, vol. 13, no. 2,
february 2013
[2]. M. A. S. Masoum, S. Jamali, and N.
Ghaffarzadeh, Detection and classification
of power quality disturbances using discrete
wavelet transform and wavelet networks
IET Sci. Meas. Technol.
193205, Jul. 2010
[3]. B. Biswal, P. K. Dash, and B. K. Panigrahi,
Power quality disturbance class
using fuzzy C-means algorithm and adaptive
particle swarm optimization
Ind. Electron., vol. 56, no. 1, pp.212
Jan. 2009.
[4]. D. Dey, B. Chatterjee, S. Chakravorti,
Munshi, Rough-granular
impulse fault classification of transformers
using crosswavelet transform
Dielectr. Electr. Insul., vol. 15, no. 15,
12971304, Oct. 2008.
[5]. W. Tong, X. Song, J. Lin, and Z. Zhao,
Detection and classification of
quality disturbances
packet decomposition and
machines, in Proc. 8th Int. Conf. Signal
Process., 2006, pp. 14.
[6]. M. R. Frankowiak, R. I. Grosvenor, and P.
W. Prickett, A Petri
distributed monitoring system using PIC
microcontrollers, Microsyst.
pp. 189196, Jun. 2005.
sue: pp- 324-331
330 | P a g e

Device Employing Correlation Techniques
IEEE Sensors Journal, vol. 13, no. 2,
M. A. S. Masoum, S. Jamali, and N.
Detection and classification
of power quality disturbances using discrete
wavelet transform and wavelet networks,
IET Sci. Meas. Technol., vol. 4, no. 4, pp.
B. Biswal, P. K. Dash, and B. K. Panigrahi,
Power quality disturbance classification
means algorithm and adaptive
particle swarm optimization, IEEE Trans.
, vol. 56, no. 1, pp.212220,
D. Dey, B. Chatterjee, S. Chakravorti, and S.
granular approach for
impulse fault classification of transformers
transform, IEEE Trans.
, vol. 15, no. 15, pp.
W. Tong, X. Song, J. Lin, and Z. Zhao,
Detection and classification of power
quality disturbances based on wavelet
packet decomposition and support vector
Proc. 8th Int. Conf. Signal

M. R. Frankowiak, R. I. Grosvenor, and P.
A Petri-net based based
distributed monitoring system using PIC
Microsyst., vol. 29, no. 5,



[7]. http://en.wikipedia.org/wiki/Proteus_(progr
amming_language)


Design and Implementation of Satellite Image
Enhancement Using DTC Wavelet Transform
T. Betsy Saral
1
, A. Christina Shamili
2
, T.Rithu
3,
P.Mahalakshmi
4
Electronics and Communication Engineering in Jeppiaar Engineering College, Chennai, India

ABSTRACT
Resolution enhancement
3
(RE) loses high
frequency contents and hence blurring occurs.
Thus, dual-tree complex wavelet-transform
2

(DT-CWT) is proposed for RE of the satellite
images. The transform decomposes the input
image into high-frequency sub-bands which are
then interpolated with the low resolution (LR)
input image using Lanczos interpolator and
filtered using an NLM filter. The inverse DT-
CWT combines the filtered sub-bands and the
input image. This results in a resolution
enhanced image. Various analyses reveal that
the proposed technique is superior to the
conventional and state-of-the-art RE techniques.
1. INTRODUCTION
The DT-CWT is a new implementation of discrete
wavelet-transform
6
(DWT) which is used in various
image and signal processing applications. The
transform has a dual tree of wavelet filters which is
used to obtain the real and imaginary parts of
complex wavelet coefficients [1-4]. Thus, the
redundancy is limited. The transform also provides
approximate shift-invariant and directionally
selective filters. The properties like perfect
reconstruction and computational efficiency are
preserved. The DT-CWT has certain properties:
Approximate shift-invariance
2

Good directional selectivity in 2-
dimensions
Perfect reconstruction using linear-phase
filters
Limited redundancy independent of the
number of scales
Efficient order-N computation
The utilization of remote sensing data is limited by
resolution. Spatial as well as spectral RE is
desirable. Commonly used interpolation techniques
used are nearest neighbour, bilinear, bicubic and
Lanczos. The Lanczos interpolation has an
increased ability to detect edges and linear features.
It compromises the reduction of aliasing, sharpness
and ringing.
The LR satellite input image is converted into high
resolution (HR) using the proposed DT-CWT
technique.
The DT-CWT has two real DWTs which gives the
real and imaginary parts of the transform. The two
different sets of filters used in the transform satisfy
the PR conditions and are jointly designed to obtain
an approximately analytic transform. The low-pass
/ high-pass filter pair is denoted as h
0
(n), h
1
(n) for
upper FB and g
0
(n), g
1
(n) for lower FB. The two
wavelets associated with each of the two
transforms are denoted as ! (t)=! h (t)+j! g (t).
Equivalently, it is denoted as ! g (t) ! H {! H (t)}.
Interpolation constructs new data points within the
range of a discrete set of known data points. The
Lanczos algorithm devised by Cornelius Lanczos is
an iterative way of adapting power methods to find
the Eigen values and vectors of a square matrix or
decomposing the singular value of a rectangular
matrix. It is mainly used to decompose very large
sparse matrices.
The Lanczos algorithm is similar to Arnoldis
algorithm. The matrix A is transformed into a tri-
diagonal matrix T
mm
in the m
th
step of the
algorithm. T
mm
is similar to A, when m is equal to
the dimension of A.
The tri-diagonal and symmetric matrix is calculated
as: T
mm
=V
m
*AV. The diagonal elements are
denoted by
j
=t
jj
and the off-diagonal elements by
j
=t
j-1, j
. Due to symmetry, t
j-1, j
=t
j, j-1
.



Fig. 1 Block diagram


Fig. 2 Diagram of the proposed work
After calculating T
mm
, its eigen values
i
(m)
and
their corresponding eigen vectors u
i
(m)
are solved
[5-6]. The Eigen values are proved to be the
approximate eigen values of the original matrix A.
The Lanczos algorithm has the following functions
when implemented practically:
Prevents the loss of orthogonality
Recovers the orthogonality after the
generation of basis
Removes the spurious Eigen values after
identifying the good and spurious ones.

The non-local means (NLM) filtering is a de-
noising method which is contrast to image de-
noising technique. In this method, any noisy pixel
located in the centre of an image patch is de-noised
by building relevant patches with similar structure
located anywhere in the image. The accuracy level
is same as that of state-of-the-art methods and
exceeds them in certain types of images as when
applied to images with significant texture patterns.
Various applications of this technique are as
follows:
Improves de-noising for ultra-sound
images
Provides better de-noising results for
computed tomography images
De-noises MRI images
The NLM
5
has a high computational cost and many
techniques are developed to reduce this cost such as
with reduced similarity neighbourhoods, pre-
selecting similar patches, for textual pattern and
with Probabilistic Early Termination.
The NLM technique is compared with few other
de-noising techniques like Gaussian, Bilateral and
Wavelet. The compared filtering results are:
Wavelet filtering and NLM preserves the
image edges during noise filtering

NLM filter preserves edges and filters
better background noise than the other
techniques.
For a discrete noisy image = { (i) | i I}, the
estimated value for a pixel i is calculated as a
weighted average of all the pixels in the image:
NL [] (i)= | (i, j) (j) |
j I

The similarity between two pixels i and j is
measured as a decreasing function of the weighted
Euclidean distance, || (
i
) - (
j
) ||
2
2, a
. The
equality obtained by the Euclidean distance is:
E || (
i
) (
j
) ||
2
2, a
= || (
i
) - (
j
)
2
2, a
|| + 2
2

This equality indicates the robustness of the
algorithm due to the conservation of the order of
similarity between pixels using the Euclidean
distance.
The NLM compares the grey level in a single point
as well as the geometrical configuration in a whole
neighbourhood. This shows an increased robust
when compared to neighbourhood filters.
The human eye alone can decide whether the image
quality has been improved by the de-noising
method. The analyses are simulated by adding a
Gaussian white noise having a standard deviation
to the true image. The main objective is to compare
the visual quality of the restored images, non-
presence of artifacts and the correct reconstruction
of edges and texture.
Natural images have enough redundancy to be
restored by NLM. They allow us to find many
similar configurations far away from pixels.
Flat zones have a huge number of similar
configurations lying inside the same object
Straight or curved edges possess a
complete line of pixels with similar
configurations
Blurred or degraded structures of the
restored images coincide with some
structures of its method noise
After filtering is done, they are interpolated with
the same factor. The interpolated sub-bands are
then combined using Inverse DT-CWT to obtain a
super-resolved high resolution image.
TABLE 1 Comparison of existing and proposed
techniques for the Washington DC image

Fig. 3. Input Image

Fig. 4 Output image


Fig. 5.Difference image
3. CONCLUSION
The proposed technique makes use of DWT and
decomposes an input image into different sub-
bands. Then the high frequency sub-bands are
interpolated. The interpolated high frequency sub-
band coefficients are corrected by the high
frequency sub-bands obtained from Stationary
Wavelet Transform
6
(SWT) of the input image.
Here, the original image is interpolated half that of
the high frequency sub-bands. Then, all these
images are combined by Inverse DWT
1
to generate
a super-resolved
4
image. This technique has been
tested on certain well-known benchmark images
whose PSNR
3
and visual results reveal that the
proposed technique is superior to the other
conventional and state-of-art image resolution
techniques.
REFERENCES
[1]. IEEE TRANSACTION ON IMAGE
PROCESSING VOL NO.5, MAY 2011,
Image Resolution Enhancement by using
Discrete and Stationary Wavelet
Decomposition, Hasan Demirel and
Gholamreza Anbarjafari .
[2]. Signal Processing Group, Department of
Engineering University of Cambridge,
Cambridge CB2 IPZ, UK, The Dual Tree
Complex Wavelet Transform: A new technique
for Shift variance and Directional filters, Nick
Kingsbury.
[3]. School of Electrical Engineering and Computer
Science, Korea Advanced Institute of Science
and Technology, Daejeon, Korea, Image
Resolution Enhancement using Inter sub-band
correlation in Wavelet domain, Yinji Piao,
Bhong Shin, Hyun Wook Park.
[4]. IEEE GEOSCIENCE AND REMOTE
SENSING LETTERS VOL.5,NO.4,OCT 2008,
On the Super-resolution of Microwave
Scanning Radiometer measurements, Attilio
Gambardella, member, IEEE and Maurizio
Migliaccio, Senior member, IEEE.
[5]. IEEE SIGNAL PROCESSING
LETTERS,VOL.9,NO.3,MARCH 2002, A
Universal Image Quality Index, Zhou Wang,
Student Member, IEEE, and Alan C. Bovik,
Fellow, IEEE.
[6]. IEEE GEOSCIENCE AND REMOTE
SENSING LETTERS VOL.10,NO.3, MAY
2013, Satellite Image Resolution
Enhancement using Dual Tree Complex
Wavelet Transform and Non local means,
Muhammad Zafar Iqbal, Abdul
Ghafoor,andAdil Masood Siddiqui .



Design and Implementation of Smart Motion Sensing
System Using Fps
V.Christy Hancy Rani
1
, G.Sharmila
2
, A.Surya
3
, B.V.Kavetha
4
Electronics and Communication, Jeppiaar Engineering College, Chennai, India
ABSTRACT
Diabetic Neuropathy is a serious medical
disorder and can be prevented by the early
detection of abnormal pressure patterns under
the foot. Although equipment to measure foot
pressure distribution is available in India and
elsewhere, these are still not readily accessible
for a large segment of the population, are too
expensive to own, and are too bulky to be
portable. The foot pressure monitors are also
not readily available in less developed countries
which are home to many communities with a
high prevalence of diabetes. The project is to
design and build a low-cost foot pressure and
foot movement analysis and blood flow
stimulation system, embedded within smart
footwear which a patient can wear at any place
to monitor his or her foot pressure distribution
to identify and diagnose foot neuropathy as
early as possible. A complete experimentation is
developed to test the performance of the new
proposal when dealing with datasets of 20
different people, comprising a detailed analysis
of results, which shows the advantages of our
proposal in comparison with some other
classical and computational intelligence
techniques. The nal goal is to obtain a specic
model for each persons gait in such a way that
it can generalize well with different gaits of the
same person.
INTRODUCTION
Diabetes is one of the major causes of illness and
premature death worldwide. Diabetes causes
neurovascular complications, which result in the
development of high pressure areas in the feet and
hands [1-2]. Diabetic neuropathy causes nerve
damage which can ultimately lead to amputation or
ulceration. The vascular and neural diseases are
closely related and intertwined. Blood vessels
depend on normal nerve function, and nerves
depend on adequate blood flow. A person with
diabetic neural dysfunction would also have Micro
vascular dysfunction. Recent advances in the scope
of wearable devices and networks make body area
sensor networks (BASNs) an extremely attractive
tool to the elds of mobile and tele-health, owing
to the range of medical applications they can serve
and the diagnostic richness of patient data they can
offer. This project not only enables early detection
but also provides treatment and prevention of
Diabetic Neuropathy which is a serious medical
disorder [3-5]. As a remedy, sending imperceptible
vibrations through the feet of diabetics and stroke
patients significantly improves the damaged nerves
and stimulates blood flow, according to a study
conducted by a biomedical engineering university
in America. The goal of this paper is to present an
innovative technology based on wearable sensors
on-shoe and processing algorithm, which provides
the advantage of being practical to use in home or
clinics without any discomfort for the subject.
www.ijrde.com


BLOCK DIAGRAM

Fig. 1 Handheld Monitoring Unit

Micro SD
Memory Card
Buzzer
GPIO
UART-1
IEEE 802.15.4
Transceiver
FlexiForce Sensor - 1
IEEE 802.15.4
Transceiver
SPI-1

Micro SD
Memory Card
Color TFT LCD
SPI-1
GPIO
SPI-2
Touchscreen
Controller
FlexiForce Sensor
ADC
ADC
ADC
IC
sue: pp- 337-341
338 | P a g e

Color TFT LCD
Display
Touchscreen
MEMS
Accelerometer


Fig. 2 Smart Footwear Unit
DESCRIPTION
In this system, the foot pressure distribution is
measured by a set FlexiForcepressure sensors
located on the insole of the shoe. These sensors are
based on force-sensing resistors, whose resistance
varies inversely with the applied force. The
footwear unit measures the pressure sensor outputs
and transmits the information using IEEE 802.15.4
wireless transceiver to the handheld monitoring
unit. The handheld touchscreen unit communicates
wirelessly with the foot attached unit and collects
real-time data, stores it in the memory card for
analysis by a doctor at a later time. The monitoring
device is equipped with a 65K Color Touchscreen
TFT Display that receives the wireless data and
displays the foot pressure information on color bar
graph as well as store that data in the memory card.
The device also monitors the user foot movement
using a 3-axis MEMS Accelerometer and actively
looks for situations leading to foot injuries.
Once the system detects an anomaly in the user's
foot pressure distribution or foot motion, it issues
an alert to the handheld touchscreen device. To
improve the blood flow the smart footwear has a
set of miniature Vibrating Motors that stimulate the
nerves by vibrating in different amplitude that can
be configured individually, started and stopped by
the user using the handheld touchscreen unit. The
smart footwear will collect data from foot pressure
sensors and foot motion sensor and periodically
transfer this data to the handheld unit where it will
be stored in a 2GB Micro SD memory card for
future reference or for an analysis by a doctor.
Both the footwear unit and the handheld display
unit use LPC1313, a 32-bit ARM Cortex-M3
Microcontroller from NxP Semiconductors. Apart
from the application software and the device driver
firmware the microcontroller also runs software
such as a Graphics Library, a FAT-32 File System
and an IEEE 802.15.4 Wireless Networking
Protocol Stack.
PWM
Motor Drive
Controller
Vibrating Motor - 3
Vibrating Motor - 2 Vibrating Motor - 1


EXISTING SYSTEM
In this Smart motion sensing system the use of
sensors are large and it is very costly to afford.Each
sensor has its own peculiar value and use .All
existing systems are replaced by their proposed
system due to technology development and
individuals usage.

PROPOSED SYSTEM
This project not only enables early detection but
also provides treatment and prevention of Diabetic
Neuropathy which is a serious medical disorder.
Equipment to measure foot pressure distribution is
either too expensive to own or too bulky to be
portable. The system design in the project is such
that the sensors and actuators can be fitted within
the shoe unit and the monitoring unit a simple
handheld device allowing overcoming the previous
drawback.Thus the project will be cheaper and
readily available in all countries which are not
developed. Large external memory allows the
system to continuously store data from the smart
shoe even for several weeks. Advanced Color
Graphical User Interface with the help of a TFT
LCD and Touchscreen Panel.Next generation ARM
Cortex-M3 architecture is the chosen hardware
platform, ideal when low power and high
performance is needed.
RESULTS AND DISCUSSION
This project not only enables early detection but
also provides treatment and prevention of Diabetic
Neuropathy which is a serious medical
disorder.Equipment to measure foot pressure
distribution is either too expensive to own or too
bulky to be portable. The system design in the
project is such that the sensors and actuators can be
fitted within the shoe unit and the monitoring unit a
simple handheld device allowing to overcome the
previous drawback.Advanced Color Graphical User
Interface with the help of a TFT LCD and
Touchscreen Panel.Large external memory allows
the system to continuously store data from the
smart shoe even for several weeks.
Next generation ARM Cortex-M3 architecture is
the chosen hardware platform, ideal when low
power and high performance is needed.Thus the
project will be cheaper and readily available in less
developed countries which are home to many
communities with a high prevalence of diabetes.

Fig. 3 Handheld Monitoring Unit

Fig. 4 Smart Footware Unit
CONCLUSION
This paper presents a wearable shoe-based device
and related pattern recognition methodology. The
design of the wearable platform allows integration
into a single sensor location, which requires
minimal additional effort for everyday use. The
proposed methodology requires only minimal
processing of the sensor data. Combining pressure
and acceleration modalities in the device also
allows for a signicant reduction in the sampling
frequency, thus conserving battery power. The
proposed methodology demonstrated excellent
recognition accuracy, especially compared to
devices that have used only a single location on the
body. The population-average accuracy of
individual models is very close to that of a group


model, thus allowing for accurate recognition
without individual calibration. Use of a single shoe
instead of two resulted in a tolerable reduction in
accuracy.
Finally, the experiments have shown that
comparable recognition accuracy can be achieved
with a minimal set of sensors composed of one
acceleration and one pressure sensor. Overall, the
low intrusiveness and high accuracy of the
proposed device should enable long-term studies of
human mobility and energy expenditure in free-
living conditions given further improvement and
durability of the shoe sensor design.
REFERENCE
[1]. P. R. Cavanagh and S. A. Bus, Off-
loading the diabetic foot for ulcer
prevention and healing, JAPMA, vol.
100, no. 5, pp. [360368], Sep.2010.
[2]. J. B. Wendt and M. Potkonjak, Medical
diagnostic-based sensor selection, in
Proc. IEEE Sensors, pp. [15071510],
Oct.2011.
[3]. S. Popovic et al., A reliable gyroscope-
based gait-phase detection sensor
embedded in a shoe insole, IEEE Sensors
J., vol. 4, no. 2, pp. [268274], Apr. 2004.
[4]. J. Parkka, M. Ermes, P. Korpipaa, J.
Mantyjarvi, J. Peltola, and I. Korhonen,
Activity classication using realistic data
from wearable sensors, IEEE Trans. Inf.
Technol. Biomed., vol. 10, no. 1, pp.
[119128], Jan.2006.
[5]. U.Maurer, A.Smailagic,
D.P.Siewiorek,and M.Deisher,Activity
recognition and monitoring using multiple
sensors on different body positions, in
Proc. IEEE Comput. Soc. Int. Workshop
Wearable Implantable Body Sens. Netw.
pp. [113116], 2006.



Fast DCT Computation Using Cordic Algorithm for
Image Processing Application
Kalaiyarasi .K
1
, Deepika .S
2
, Naga Abinaya .G
3
,

R. Jhansi Rani
4

ABSTRACT
This letter proposes the fast DCT computation
using CORDIC algorithm for image processing
application. The proposed algorithm has some
of the advantages such as lower computational
complexity, highly scalable, reliable, high speed,
lesser area, low power consumption compared
to existing algorithm. Similar to the Cooley-
Turkey Fast Fourier Transformation (FFT)
algorithm, the proposed algorithm can
generate the next higher order DCT from two
identical lower order DCTs. Based on the
proposed algorithm, signal flows of DCTs and
inverse DCTs are developed and deduced using
orthogonal property. In addition this letter
provides easy way to implement this algorithm
in image processing application.
1. INTRODUCTION
For a long time the field of Digital Signal
Processing has been dominated by
Microprocessors. This is mainly because they
provide designers with the advantages of single
cycle multiply-accumulate instruction as well as
special addressing modes. Although these
processors are cheap and flexible they are
relatively slow when it comes to performing
certain demanding signal processing tasks e.g.
Image Compression, Digital Communication and
Video Processing [5]. Of late, rapid advancements
have been made in the field of VLSI and IC
design. As a result special purpose processors
with custom-architectures have come up. Higher
speeds can be achieved by these customized
hardware solutions at competitive costs. To add to
this, various simple and hardware-efficient
algorithms exist which map well onto these chips
and can be used to enhance speed and flexibility
while performing the desired signal processing
tasks. One such simple and hardware-efficient
algorithm is CORDIC, an acronym for Coordinate
Rotation Digital Computer, proposed by Jack E
Volder. CORDIC uses only Shift-and-Add
arithmetic with table Look-Up to implement
different functions. Since it uses only shift-add
arithmetic, VLSI implementation of such an
algorithm is easily achievable.
DCT was proposed by Ahmed [3]. This algorithm
has diverse applications and is widely used for
Image compression. Implementing DCT using
CORDIC algorithm reduces the number of
computations during processing, increases the
accuracy of reconstruction of the image, and
reduces the chip area of implementation of a
processor built for this purpose. This reduces the
overall power consumption. FPGA provides the
hardware environment in which dedicated
processors can be tested for their functionality.
They perform various high-speed operations that
cannot be realized by a simple microprocessor.
The primary advantage that FPGA offers is On-
site programmability. Thus, it forms the ideal
platform to implement and test the functionality of
a dedicated processor designed using CORDIC
algorithm. [2].
2. PROPOSED CORDIC BASED DCT
AND IDCT ALGORITHM
In existing system, For an 8-point signal, x(n) , the
DCT is defined as:
=
,
= , , , . ,


Neglecting the post-scaling factor without loss of
generality, the main operation of an N-point DCT
denoted as can be written as:
=
+
, = , ,

For an 8-point signal, x (n) , the IDCT is defined
as:
=
,
= , , , . ,
2.1. CORDIC BASED ALGORITHM

Fig 1: Signal flow of an N-point fast discrete cosine
transformation (DCT)

Fig 2: Signal flow of a 2-point fast discrete cosine

Fig 3: Signal flow of a 4-point fast discrete cosine



Fig 4: Signal flow of a 8-point fast discrete cosine transformation (DCT)
2.2. DCT SIGNAL FLOW
The general signal flow graph for the proposed
fast DCT algorithm is shown in the fig.1.while the
signal flow graphs of 2-point,4-point,8-point DCT
are respectively shown in the fig 2-4.where the
angles in the circles are used to represent the
CORDICs with this rotation angles. The inputs are
given in bit reverse order and the outputs are in
natural order.
2.3. IDCT SIGNAL FLOW
The signal flow graph of 8-point IDCT is shown
in the fig.4.The inputs are given in natural order
and the outputs are in bit reverse order.
Hardware complexity: The CORDIC-based
algorithm is highly suitable for VLSI
implementation, since it is built using shifters and
adders only. Liang et al. [4] propose lifting
scheme-based fast multiplier less approximation
of the DCT using only binary shift and addition
operations.

Fig 5: Signal flow of a 8-point inverse discrete cosine
transformation (IDCT)



3. RESULTS AND DISCUSSION
Fig 6: Simulated output of 8-point DCT

Fig 7: Simulated output of 8-point IDCT
www.ijrde.com


4. SIMULATION USING XILINX 13.2
4.1. EXISTING
Table 1 Existing system
4.2. PROPOSED
Table 2 Proposed system
5. CONCLUSION
We propose a novel CORDIC-based radix
DCT and IDCT algorithm. This algorithm can
identical lower-orders DCTs. Compared to
existing DCT and IDCT algorithms, our proposed
algorithm has several distinct advantages, such as
low computational complexity, and being highly
scalable, modular, regular, and able to admit
efficient pipelined implementation. Compared to
Existing algorithm, proposed algorithm requires
less time to compute DCT and IDCT. It can be
implemented in image processing applications.
The pixel values of the image is obtained by usin
MATLAB software. The pixel values of the image
is given as the input for DCT and its output is
given to the IDCT input it gives the pixel values
ISSN: 2279-0500 Special

XILINX 13.2
based radix-2 fast
DCT and IDCT algorithm. This algorithm can
orders DCTs. Compared to
existing DCT and IDCT algorithms, our proposed
algorithm has several distinct advantages, such as
low computational complexity, and being highly
, and able to admit
efficient pipelined implementation. Compared to
Existing algorithm, proposed algorithm requires
less time to compute DCT and IDCT. It can be
implemented in image processing applications.
The pixel values of the image is obtained by using
MATLAB software. The pixel values of the image
is given as the input for DCT and its output is
the pixel values
as the output [5]. Furthermore, the proposed
algorithm also provides an easy way to implement
a reconfigurable or unified architecture for
point DCTs and IDCTs. Future work is to
compute the 16-point DCT and IDCT.
REFERENCES
[1]. E. Feig and S.Winograd, (Sep.1992)
algorithms for the discrete cosine
transform, IEEE Trans. Signal Process., vol.
40, no. 9, pp. 21742193.
[2]. L. Xiao and H. Huang, (Aug. 2012)
CORDIC based unified architecture for DCT
and IDCT, in 2012 Int. Conf.
Optoelectronics and Microelectronics (
pp. 496500.
l Issue: pp- 342-347
346 | P a g e

Furthermore, the proposed
algorithm also provides an easy way to implement
architecture for 16-
point DCTs and IDCTs. Future work is to
point DCT and IDCT.
E. Feig and S.Winograd, (Sep.1992) Fast
rithms for the discrete cosine
, IEEE Trans. Signal Process., vol.
L. Xiao and H. Huang, (Aug. 2012) A novel
CORDIC based unified architecture for DCT
, in 2012 Int. Conf.
Optoelectronics and Microelectronics (ICOM),


[3]. N. Ahmed, T. Natarajan, and K. R.
Rao,( 1974) Discrete cosine transform,
IEEE Trans. Comput.,vol. C-23, pp. 9094.
[4]. J. Liang and T. D. Tran, (2001) Fast
multiplierless approximations of the DCT
with the lifting scheme, IEEE Trans. Signal
Process., vol. 49, no. 12, pp. 30323044.
[5]. C. W. Kok, ( Mar. 1997) Fast algorithm for
computing discrete cosine transform,IEEE
Trans. Signal Process., vol. 45, no. 3, pp.
757760.

www.ijrde.com

Fibre Enclosed Induction Machine
Vishnu P
1
, Pradeep Kumar R
1
Electrical and Electronics Engineering, Jeppiaar Engineering College, Chennai,
1
1
ABSTRACT
At present researches going on to improve the
efficiency of the electrical machines. Efficiency
of the electrical machines is mainly depends on
two losses, one is fixed loss and another one is
variable losses. Fixed losses are further
classified hysteresis loss and eddy current loss.
Hysteresis loss mainly occurs due to the flux
leakage in the rotating machines. To reducing
the flux leakage by the help of non
material, we can reduce the hysteresis loss and
improve the efficiency of the machine. The
protective enclosures are designed by using cast
iron. It quickly absorbs temperature, it consist
more weight and cast iron have high conducting
medium so it needs proper grounding. Because
of these reasons we decided to design an
induction motor with fibre mounted protective
enclosure without using cast iron. Fibre material
cant have a conducting medium. So there is no
need for grounding and everybody should
handle the machine without panic. Fibre
mounted protective enclosure will reduce
voltage drop, temperature, weight, as well as the
cost of the induction machine and the fibre
material cant affect from corrosion and it will
protect from high wind, driving sleet, rain and
snow fall. Combinations or concentrations of the
attack elements will quickly destroy vital motor
parts, such as insulation and bearings. The
objectives are to protect the internal motor
parts, to do it economically and also keep the
inside of the motor cool.
1. INTRODUCTION
I. Maximizing motor efficiency is
equivalent to minimizing motor losses
and there are several methods of
decreasing the energy consumption in
electrical machines, for example:
reorganizing the production lines, using
adjustable ac-drives choosing the motor
Fibre Enclosed Induction Machine
, Pradeep Kumar R
2
, Tamilarasan M
3

trical and Electronics Engineering, Jeppiaar Engineering College, Chennai, India,

At present researches going on to improve the
efficiency of the electrical machines. Efficiency
of the electrical machines is mainly depends on
fixed loss and another one is
variable losses. Fixed losses are further
classified hysteresis loss and eddy current loss.
Hysteresis loss mainly occurs due to the flux
leakage in the rotating machines. To reducing
the flux leakage by the help of non-magnetic
material, we can reduce the hysteresis loss and
improve the efficiency of the machine. The
protective enclosures are designed by using cast
iron. It quickly absorbs temperature, it consist
more weight and cast iron have high conducting
s proper grounding. Because
of these reasons we decided to design an
induction motor with fibre mounted protective
enclosure without using cast iron. Fibre material
cant have a conducting medium. So there is no
grounding and everybody should
le the machine without panic. Fibre
mounted protective enclosure will reduce
voltage drop, temperature, weight, as well as the
cost of the induction machine and the fibre
material cant affect from corrosion and it will
et, rain and
snow fall. Combinations or concentrations of the
attack elements will quickly destroy vital motor
parts, such as insulation and bearings. The
objectives are to protect the internal motor
parts, to do it economically and also keep the
Maximizing motor efficiency is
equivalent to minimizing motor losses
and there are several methods of
decreasing the energy consumption in
electrical machines, for example:
reorganizing the production lines, using
drives choosing the motor
size correctly and decreasing the losses of
machines [1-4].
II. The analysis method for the flux leakage
and reversal magnetization of a rotating
machine considering the air gap and
material to be mounted. The decreased
losses in industry also lead to lower
power transmission losses, reduction in
the need for cooling and lower power
reservation costs.
III. The purpose of generating the magnetic
flux which is used to produce the relative
motion to the rotor. But the stator flux
mostly attracted by the enclosure, because
the machine was mounted by using the
magnetic material.
IV. So by replacing the enclosure by non
magnetic material, the flux leakage has
been controlled in the machine and the
efficiency of the machine should be
increased gradually.
2. DESCRIPTION
Figure 1 Hardware setup
The basic components of the fibre enclosed
induction machine are namely the fibre enclosure,
the stator, the rotor, the bearings and the capacitor.
348 | P a g e
India,
India,
India,
size correctly and decreasing the losses of
The analysis method for the flux leakage
and reversal magnetization of a rotating
machine considering the air gap and
material to be mounted. The decreased
osses in industry also lead to lower
power transmission losses, reduction in
the need for cooling and lower power
The purpose of generating the magnetic
flux which is used to produce the relative
motion to the rotor. But the stator flux
mostly attracted by the enclosure, because
the machine was mounted by using the
So by replacing the enclosure by non-
magnetic material, the flux leakage has
been controlled in the machine and the
efficiency of the machine should be
The basic components of the fibre enclosed
induction machine are namely the fibre enclosure,
the stator, the rotor, the bearings and the capacitor.
www.ijrde.com

The stator consists of thin, stacked laminations that
are wound with insulated wire. The core contains
hundreds of these laminations and the stator
mounted in fibre housing [5-7]. The solid state
rotor placed on the stator core with standard air
gap. The bearings are placed on the housing for
efficient rotation and to avoid the mechanical stress
of the rotor [7-9]. The capacitor connected to the
starting winding because the induction motor
doesnt have self-starting, so the capacitor is used
to starting the motor.
Figure 2 Stator core and the Rotor with Beari
Figure 2 Stator core and the Rotor with Bearings
A rotor basically acts just like a magnet. When the
supply is switched ON, the current flows through
the stator winding and creates an electromagnetic
field that rotor cuts across the rotor bars. This
induces current in the rotor bars, which create an
The stator consists of thin, stacked laminations that
re wound with insulated wire. The core contains
hundreds of these laminations and the stator
. The solid state
rotor placed on the stator core with standard air
gap. The bearings are placed on the housing for
n and to avoid the mechanical stress
. The capacitor connected to the
starting winding because the induction motor
starting, so the capacitor is used


A rotor basically acts just like a magnet. When the
supply is switched ON, the current flows through
the stator winding and creates an electromagnetic
field that rotor cuts across the rotor bars. This
induces current in the rotor bars, which create an
electromagnetic field around the rotor and
polarization of the rotor.
2.1. MATERIALS OF THE FIBRE
ENCLOSURE
Fibre glass
Polyvinyl resin
Polyurethane resin
Catalyst
Dryer
2.2. DIMENSIONS OF THE FIBRE
ENCLOSURE
2.2.1. STATOR HOUSING
Inner diameter 106.67mm.
Thickness 7mm.
Length 126mm.
2.2.2. BEARING SLOTS
Diameter 31mm.
Length 19.5mm.
Thickness 9mm.
2.2.3. ENCLOSURE BASE
Angle 60
0

Length 126mm.
Thickness 10mm.
3. STANDARD CALCULATIONS OF
HARDWARE SETUP
Hysteresis Loss for Induction Mo
Kh * Bg
2
* f
Kh = hysteresis magnetic co efficient value of cast iron
(27.63 to 40.2)
B
g
= flux density of centre of the pole
F = frequency in Hz
= 40.2 * (0.498)
2
* 50
= 0.498Kw = 49.8Watts
Hysteresis Loss for Induction Motor with
Fibre Enclosure
Kh = hysteresis co efficient value of fibre (0)
=0*(0.498)
2
*50 = 0 watts
Pin = 0.75Kw
Pout = 0.45Kw
Losses = 0.30Kw
Efficiency = Pout/Pin
= 0.45 / 0.75 = 0.6 = 60%
349 | P a g e
electromagnetic field around the rotor and
MATERIALS OF THE FIBRE
DIMENSIONS OF THE FIBRE

Inner diameter 106.67mm.
STANDARD CALCULATIONS OF
Hysteresis Loss for Induction Motor
Kh = hysteresis magnetic co efficient value of cast iron
Hysteresis Loss for Induction Motor with
= hysteresis co efficient value of fibre (0)
www.ijrde.com


4. IM vs. FEIM
TABLE 1 comparison between IM vs. FEIM
INDUCTION
MACHINE
IM WITH FIBRE
ENCLOSURE
INPUT: 230volts
3.2Amps
50Hz
1440 RPM
0.75 Kw
INPUT: 230volts
3.2Amps
50Hz
1440 RPM (theoretical)
0.75 Kw
OUTPUT:
0.37 Kw
LOSSES:
0.38 Kw
EFFICIENCY:
49%
OUTPUT:
0.45 Kw
LOSSES:
0.30 Kw
EFFICIENCY:
60%
5. CIRCLE DIAGRAM
From equivalent circuit of an induction motor, the
motor can be treated as series R=L circuit where
the element resistance of the circuit is variable
which varies as slip S. thus for variable load
condition, the resistance changes and hence the
current drawn by the motor also changes. Th
diagram of such a current phasor is circular in
nature and hence called circle diagram.
Figure 3 Experimental setup
5.1. NO LOAD TEST
TABLE no 2 No load test
V
oc
In Volts I
oc
in Amps W
oc
230 0.4 80
5.2. BLOCKED ROTOR TEST
TABLE no 3 Blocked rotor test
FEIM
IM WITH FIBRE
ENCLOSURE
INPUT: 230volts
3.2Amps
50Hz
1440 RPM (theoretical)
0.75 Kw
OUTPUT:
0.45 Kw
LOSSES:
0.30 Kw
EFFICIENCY:
60%
duction motor, the
motor can be treated as series R=L circuit where
the element resistance of the circuit is variable
which varies as slip S. thus for variable load
condition, the resistance changes and hence the
current drawn by the motor also changes. The locus
diagram of such a current phasor is circular in
nature and hence called circle diagram.

oc
in Watts

V
sc
In Volts I
sc
In Amps W
oc
In Watts
160 1.66 180
Cos
oc
= W
o
/ (V
o
* I
o
) = 80 / (230 * 0.4) = 0.869
oc
= 29.65
Active component of no load current
I
c
= I
o
* cos
o
= 0.4 * 0.869 = 0.3476
Magnetizing component of no load current
I
m
= I
o
* cos
o
= 0.4 * 0.494 = 0.1978
No load branch resistance
R
o
= V
o
/ I
c
= 230 / 0.3476 = 661.68
No load branch reactance
X
o
= V
o
/ I
m
= 230 / 0.1978 = 1162.79
Short circuit power factor
Cos
sc
= W
sc
/ (V
sc
* I
sc
) = 180 / (160 * 1.66) = 0.677
sc
= 47.390
Equivalent impedance referred to stator
Z
1e
= V
sc
/ I
sc
= 93.37
Equivalent impedance referred to rotor
R
1e
= Z
1e
2
- R
1e
2
= 66.716
Short circuit current at normal voltage
I
SN
= [V
l
/ V
sc
] * I
sc
= [230 / 155] * 1.66 = 2.46
Short circuit input power at normal voltage
W
sn
= [I
sn
/ I
sc
]
2
* W
sc
= [2.46 / 1.66] * 180 = 266.74
Power scale = W
sn
/ l (AD) = 266.74 / 6.2 = 43.02
= 53
0
C [as per graph]
Full load line current= l (OP) = 5.8 * 0.2 = 1.16amps
Total motor input = PT * Power scale = 168.089 watts
Fixed loss = ST * PS = 40.02watts
Rotor cupper loss = QR * PS = 24.012 watts
Stator cupper loss = SR * PS = 48.024 watts
Total losses = QT * PS = 116.056 watts
Rotor output = PQ * PS = 72.036 watts
Rotor input = PR * QR = 112.06 watts
Slip S = QR / PR = 0.2
Power factor = PT / OP = 4.2 / 5.2 = 0.809
= Cos (0.809) = 0.999 lagg
Efficiency = Rotor output / Rotor input = 72.036 / 112.06
= 0.6428 = 64.28%
Starting torque = 97.56 Syn.watts
Full load torque = 140.07 Syn.watts
350 | P a g e
In Watts
) = 80 / (230 * 0.4) = 0.869
Magnetizing component of no load current
) = 180 / (160 * 1.66) = 0.677
Equivalent impedance referred to stator

= [230 / 155] * 1.66 = 2.46
al voltage
= [2.46 / 1.66] * 180 = 266.74
/ l (AD) = 266.74 / 6.2 = 43.02
Full load line current= l (OP) = 5.8 * 0.2 = 1.16amps
Total motor input = PT * Power scale = 168.089 watts
Rotor cupper loss = QR * PS = 24.012 watts
Stator cupper loss = SR * PS = 48.024 watts
Total losses = QT * PS = 116.056 watts

factor = PT / OP = 4.2 / 5.2 = 0.809
Efficiency = Rotor output / Rotor input = 72.036 / 112.06



Figure 4 Circle Diagram
6. CONCLUSION
The fibre enclosure is totally differing from the cast
iron or other type of enclosure. The fibre enclosure
is the new arrival for electrical appliances and it
has many advantages over other type of enclosures.
First time the enclosure which is helps to increasing
the efficiency of the machine and it consumes less
weight, low cost, corrosion avoidance, non-
conducting material etc. The electrical machine has
been mounted by the fibre enclosures which is
reducing the losses and increase the efficiency of
the machine. This enclosure can be used in mining
operations, pumping, deserts, oil and gas industries,
cement industries, textile industries etc.,
REFERENCES
[1] 2002 National Electric Code, 2002, National Fire
Protection Association, Quincy, Massachusetts.
[2] API Standard 541, 1993, Form-Wound Squirrel
Cage Induction Motors 250 Horsepower and
larger, American Petroleum Institute, Washington,
D.C.
[3] Institute of Electrical Electronic Engineers Standard
112-1996, 1996, Test Procedure for Poly phase
Induction Motors and Generators, Washington,
D.C.
[4] NEMA Standard Publication MG-1, 1993, Motors
and Generators, National Electrical manufactures
Association, Washington D.C.
[5] Del Toro, V., 1968, Electromechanical Devices for
Energy Conversion and Control Systems,
Englewood Cliffs, New Jersey: Prentice- Hall.
[6] Proper motor lubrication, December 1987,
Engineers Digest, Rockwell Automation, Reliance
Electric White Paper, Document B-5021.
[7] Traister, J.E., 1984, Handbook of Electric motors:
Use and repair, Englewood Cliffs, New Jersey:
prentice-Hall.
[8] Westinghouse, 1974, Westinghouse Electrical
Maintenance Hints, Trafford, Pennsylvania:
Westinghouse Electric Corporation.
[9] What Do All Those Things on an AC Motor
Nameplate Mean? May 1993,Power
Transmission Design, Rockwell Automation,
Reliance Electric white Paper, Document B-7095-1.

www.ijrde.com

FPGA Based Flexible
S.Ramesh
1
, M.Dinesh
Electrical and Electronics Engineering, Jeppiaar Engineering College,
ABSTRACT
This project deals a method of generating non
orthogonal Frequency Division Multiplexed
signals, where the spacing between sub
can be controlled externally without the need for
re-synthesis. The internal data-
associated algorithms are constructed so as to
react to changes which dictate the
aforementioned spacing, and as such represents
a dynamic transmission platform for the future
research work. In order to achieve the
orthogonal spacing a Spectrally Efficient
Frequency Division Multiplexed (SEFDM)
signal generation method is adopted. In this
work the hardware implementation is
performed using field programmable gate array
(FPGA). It is of interest to have the abili
modify the aforementioned sub
separation, to achieve functionality. SEFDM
signal sources are required so as to evaluate
FPGA implementations of non
detection techniques, which are speci
SEFDM. The implementation is purposely
targeted at a general case where, within
available resource limits, the values by which
the non-orthogonality is derived are not bound.
1. INTRODUCTION
SEFDM signals may be defined as a general class
of multicarrier signals, where the sub
frequency separation results in a non-orthogonal set
of modulated carriers. Such signals have been of

Based Flexible SEFDM Transmitter Architecture
, M.Dinesh
2
, K.David Simon
3
, I.Roshan Antony Nevis

This project deals a method of generating non-
orthogonal Frequency Division Multiplexed
signals, where the spacing between sub-carriers
can be controlled externally without the need for
-paths and
associated algorithms are constructed so as to
react to changes which dictate the
aforementioned spacing, and as such represents
a dynamic transmission platform for the future
research work. In order to achieve the non-
orthogonal spacing a Spectrally Efficient
Frequency Division Multiplexed (SEFDM)
signal generation method is adopted. In this
work the hardware implementation is
performed using field programmable gate array
(FPGA). It is of interest to have the ability to
modify the aforementioned sub-carrier
separation, to achieve functionality. SEFDM
signal sources are required so as to evaluate
FPGA implementations of non-orthogonal
detection techniques, which are specic to
SEFDM. The implementation is purposely
argeted at a general case where, within
available resource limits, the values by which
orthogonality is derived are not bound.
SEFDM signals may be defined as a general class
of multicarrier signals, where the sub-carrier
orthogonal set
of modulated carriers. Such signals have been of
interest recently as means to create communication
systems offering bandwidth saving
Mathematically, these signals may be generated by
modifying typical Orthogonal Frequency Division
Multiplexed (OFDM) signal generation methods
(using the Inverse Discrete Fourier Transform
(IDFT)). The output signal samples
functions of two parameters; the number of sub
carriers, N, and the relative frequency separation of
the sub-carriers, which also defines the bandwidth
saving relative to OFDM. For implementation
purposes is taken as the ratio of two integers b
c. As such, X[K] may be represented as
Where S0, S1 are the input symbols.. The SEFDM
system will consist of c, N-length Inverse Discrete
Fourier Transform (IDFT) blocks. N source data
symbols are padded with zeros or repositioned, as a
function of a modulo operation in base of b, to
form a new matrix of size
implementation in an FPGA of an IDFT is resource
intensive and it is standard practice to use Inverse
Fast Fourier Transforms (IFFT) where possible. N
is therefore restricted to values falling at 2L, where
L is an integer greater than one. The general
functional block diagram of SEDFM with above
mentioned functions is shown.
sue: pp- 352-358
352 | P a g e
Transmitter Architecture
I.Roshan Antony Nevis
4
Chennai, India
interest recently as means to create communication
offering bandwidth saving [1-3].
Mathematically, these signals may be generated by
modifying typical Orthogonal Frequency Division
Multiplexed (OFDM) signal generation methods
(using the Inverse Discrete Fourier Transform
(IDFT)). The output signal samples, X[K], are
functions of two parameters; the number of sub-
carriers, N, and the relative frequency separation of
carriers, which also defines the bandwidth
saving relative to OFDM. For implementation
purposes is taken as the ratio of two integers b and
c. As such, X[K] may be represented as:

S0, S1 are the input symbols.. The SEFDM
length Inverse Discrete
Fourier Transform (IDFT) blocks. N source data
symbols are padded with zeros or repositioned, as a
a modulo operation in base of b, to
form a new matrix of size Cn [4]. The
implementation in an FPGA of an IDFT is resource
intensive and it is standard practice to use Inverse
Fast Fourier Transforms (IFFT) where possible. N
values falling at 2L, where
L is an integer greater than one. The general
functional block diagram of SEDFM with above


Fig 1.Block Diagram of SEFDM transmitter operation
2. CIRCUIT DIAGRAM OF PROPOSED
FLEXIBLE CORDIC SEFDM
TRANSMITTER ARCHITECTURE
SEFDM is the general method of producing non-
orthogonal sub carrier signals where the spacing
between them can be adjusted externally using two
parameters b and c without the need of re-
synthesis. This can be implemented by two
different modulo implementation methods: i)
Modulo Arithmetic Method ii) Modulo Index
Method.
In modulo index method we are using a comparator
to check the equality of the values from the counter
and incremented values of input b rather than using
a division operation in modulo divisor method to
produce the IFFT outputs [5-6]. Among the two
implementation methods, the index modulo
implementation method is quiet efficient than the
modulo division implementation.
It can be seen that a modest reduction in resources,
results in a dramatically decreased clock period.
This is due to the removal of the divider circuits
load on the clock. The reduction in latency is due to
the methodology itself; division in FPGAs is
implemented as long division, which requires w
clock cycles per division, where w is defined as the
number of bits used to represent data symbols. The
index method has no such divider, and therefore
offers the advantage of a 90% reduction in clock
cycles.
As per methodology, the outputs of the IFFT
blocks should be phase rotated with some values
and their outputs are added up to produce our final
desired SEFDM signal
In the existing system, the outputs of the IFFT
blocks are phased rotated using the predetermined
values that are stored in the RAM. The outputs of
the vectoring blocks are added up to produce the
SEFDM signals. The disadvantages of this system
is that RAM occupies more space and the vectoring
cant be done with different values to obtain
different types of output SEFDM signals. Though
in need, all the values in RAM should be changed
every time with new values to produce different
values of vectoring and on the output. In our
proposed system, which is illustrated in the fig 2
the RAM has been replaced by the CORDIC
algorithm implementation block.



Fig 2.Block diagram of the proposed flexible CORDIC SEFDM transmitter
This will helps us to produce different values for
vectoring very easily just by changing the angle of
rotation. This further implies that different values
for vectoring can produce different phase rotated
SEFDM signals. We need not have to change the
values quiet often as incase of the existing system.
The advantage of using CORDIC algorithm is that
just by changing the value of rotating angles
different values of real and imaginary values are
generated that can be given as the input of
multipliers that perform the vectoring of IFFT
outputs. Finally, these signals are added up then to
produce the final output of SEFDM signal.
3. VLSI TECHNOLOGY
A field-programmable gate array (FPGA) is
an integrated circuit designed to be configured by a
customer or a designer after manufacturinghence
"field-programmable". The FPGA configuration is
generally specified using a hardware description
language (HDL), similar to that used for
an application-specific integrated circuit (ASIC)
(circuit diagrams were previously used to specify
the configuration, as they were for ASICs, but this
is increasingly rare).
FPGAs contain programmable logic components
called "logic blocks", and a hierarchy of
reconfigurable interconnects that allow the blocks
to be "wired together somewhat like many
(changeable) logic gates that can be inter-wired in
(many) different configurations. Logic blocks can
be configured to perform complex combinational
functions, or merely simple logic
gates like AND and XOR. In most FPGAs, the
logic blocks also include memory elements, which
may be simple flip-flops or more complete blocks
of memory. Here in our project, we use virtex
family of FPGA
The Virtex series of FPGAs have integrated
features that include FIFO and ECC logic, DSP
blocks, PCI-Express controllers, Ethernet MAC
blocks, and high-speed transceivers. In addition to
FPGA logic, the Virtex series includes embedded
CORDIC ALGORITHM
IMPLEMENTATION
IFFT IFFT
En En

a
a
a
b b
b
d d
d
Data from Modulo
Operation
+ ++ +
Output to DAC

fixed function hardware for commonly used
functions such as multipliers, memories, serial
transceivers and microprocessor cores. These
capabilities are used in applications such as wired
and wireless infrastructure equipment, advanced
medical equipment, test and measurement, and
defense systems
The Virtex-5 LX and the LXT are intended for
logic-intensive applications, and the Virtex-5 SXT
is for DSP applications. With the Virtex-5, Xilinx
changed the logic fabric from four-input LUTs to
six-input LUTs. With the increasing complexity of
combinational logic functions required by SoC
designs, the percentage of combinational paths
requiring multiple four-input LUTs had become a
performance and routing bottleneck. The new six-
input LUT represented a tradeoff between better
handling of increasingly complex combinational
functions, at the expense of a reduction in the
absolute number of LUTs per device. The Virtex-5
series is a 65 nm design fabricated in 1.0 V, triple-
oxide process technology.
4. RESULTS AND DISCUSSIONS
SEFDM is generally defined as a method of
generating non-orthogonal Frequency Division
Multiplexed signals, where the spacing between
sub-carriers can be controlled externally without
the need for re-synthesis. There are two ways of
implementing these signal generation using RAM
for vectoring. In our project the RAM has been
replaced with the CORDIC algorithm as described
in chapter 2 to produce different types of signals
just by changing the rotating angle. The simulation
results and the synthesis report of various above
mentioned implementations are given below.
4.1. MODULOARITHMETIC
IMPLEMENTATION USING PRE-
DETERMINED VALUES OF RAM
4.1.1. RTL SCHEMATIC

Fig. 3 RTL schematic diagram

4.1.2. SIMULATION RESULT

Fig. 4 Simulation result
4.1.3. SYNTHESIS REPORT
SLICE LOGIC UTILIZATION
Number of Slice Registers: 996 out of 28800 3%
Number of Slice LUTs: 2058 out of 28800 7%
Number used as Logic: 2058 out of 28800 7%
IO UTILIZATION:
Number of IOs: 514
TIMING REPORT
Minimum period: 4.947ns (Maximum Frequency:
202.153MHz)
Minimum input arrival time before clock: 7.167ns
Maximum output required time after clock: 2.826ns
4.2. MODULO INDEX IMPLEMENTATION
USING PRE-DETERMINED VALUES OF
RAM

4.2.2. SIMULATION REPORT

Selected Device: 5vlx50tff1136-2
IO UTILIZATION
Number of IOs: 114
TIMING REPORT
305.796MHz)
Maximum output required time after clock:
12.150ns
4.3. MODULO ARITHMETIC
IMPLEMENTATION USING CORDIC
ALGORITHM




SLICE LOGIC UTILIZATION:
Number of Slice Registers: 1046 out of 28800
3%
IO UTILIZATION
Number of IOs: 514
TIMING REPORT:
696.078MHz)
4.4. MODULO INDEX IMPLEMENTATION
USING CORDIC ALGORITHM:



Selected DEVICE: 5vlx50tff1136-2
Number of Slice Registers: 612 out of 28800
1%
IO UTILIZATION
Number of IOs: 114
Number of bonded IOBs: 84 out of 480 17%
TIMING REPORT
285.714MHz)
Maximum output required time after clock:
12.150ns
The parameter differences of all above mentioned
implementations are tabulated below:


DIVISOR INDEX
PARAM
ETERS
RAM
CORD
IC
RAM
CORD
IC
SLICES 996 1046 572 612
LUTs 2058 2158 892 962
IOS 514 514 114 114
MIN.
PERIOD
4.947n
s
5.1ns
3.270n
s
3.5ns
MAX.
FREQU
ENCY
202.15
3MHz
196.07
8MHz
305.79
6MHz
285.71
4MHz

5. CONCLUSION
In this project, a flexible implementation of a
FPGA based SEFDM transmitter, where values of
two integers b and c, control the spacing between
the subsequent output sub-carriers. The values are
limited only by the available resources present in a
target FPGA device. The implications for different
modulo arithmetic functions in VHDL is discussed,
and an optimum solution for the SEFDM purpose is
presented. The VHDL code that describes the
systems is ready to be implemented in hardware
and have real world testing applied. The design can
be easily scaled up in terms of maximum values of
c or N, as new FPGA devices become available.
CORDIC algorithm has been used to produce the
different phase rotated values of SEFDM signals
just by changing the rotating angle.
Future work will be based on design of hardware
detection implementations that can be used in
conjunction with signals generated using the
SEFDM transmitter, to create an SEFDM
transceiver hardware environment. Further, in the
both modulo implementation methods, one hot
method can be replaced by the enumeration types
of state machine devices to reduce the number of
flip-flops. In the index based modulo
implementation, adders can be exchanged with
carry look ahead adders to improve the efficiency.
REFERENCES
1. S.Isam and I. Darwazeh, Simple DSP-IDFT
Techniques for Generating Spectrally Efficient
FDM System Signals, 7th International
Symposium on Communication Systems
Networks and Digital Signal Processing
(CSNDSP), 2010.
2. I. Kanaras, A. Chorti, M. Rodrigues, and I.
Darwazeh, Investigation of a Semi-definite
Programming detection for a spectrally
efficient FDM system, 20th IEEE International
Symposium on Personal, Indoor and Mobile
Radio Communications, pp. 28272832, Sep.
2009.
3. M. Rodrigues and I. Darwazeh, A spectrally
efficient frequency division multiplexing based
communications system, In Proceedings of
2ndInternational Symposium on Broadband
Communications (ISBC), 2006.
4. I. Kanaras, A. Chorti, M. Rodrigues, and I.
Darwazeh, A new quasi-optimal detection
algorithm for a non orthogonal Spectrally
Efficient FDM, 9th International Symposium
on Communications and Information
Technology, pp. 460465, Sep2009.
5. M. Joham, L. Barbero, T. Lang, W. Utschick,
J. Thompson, and T. Ratnarajah, FPGA
implementation of MMSE metric based
Efficient near-ML detection, in IEEE
International ITG Workshop on Smart
Antennas (WSA), 2008
6. X. Huang, C. Liang, and J. Ma, System
Architecture and Implementation of MIMO
Sphere Decoders on FPGA, IEEE
Transactions on Very Large Scale Integration
(VLSI) Systems.


High Throughput Radix-2
^ (K)
Feedforward Fft Architectures

1
Mohana Shankar V,
2
Mageshkumar P,
3
Vinoth kumar S. V,
4
S K Binu Siva Singh

1,2,3,4
Electronics and Communication Engineering, Jeppiaar Engineering College, Chennai, India

ABSTRACT
The appearance of radix-2
2
was a milestone in the design of
pipelined FFT hardware architectures. Later, radix-22 was
extended to radix-2k. However, radix-2
k
was only proposed
for Single-path Delay Feedback (SDF) architectures, but
not for feedforward ones, also called Multi-path Delay
Commutator (MDC). This paper presents the radix-2
k

feedforward (MDC) FFT architectures. In feedforward
architectures radix-2k can be used for any number of
parallel samples which is a power of two. Furthermore,
both decimation in frequency (DIF) and decimation in time
(DIT) decompositions can be used. In addition to this, the
designs can achieve very high throughputs, which make
them suitable for the most demanding applications. Indeed,
the proposed radix-2
k
feedforward architectures require
fewer hardware resources than parallel feedback ones, also
called Multi-path Delay Feedback (MDF), when several
samples in parallel must be processed. As a result, the
proposed radix-2
k
feedforward architectures not only offer
an attractive solution for current applications, but also
open up a new research line on feedforward structures.
1. INTRODUCTION
We are living in an era of electronics and communication.
Since the development of long distance communication
techniques in the 19th century, evolution of communication has
always been striving towards higher data rates and better
quality of information exchange. This has necessitated the
invention of new and newer communication technologies in a
very rapid phase. As advancement, it can be seen that most
wired communication systems are being replaced with wireless
communication systems [1-6]. Though wired transmission can
offer much higher data rates, wireless solutions are preferred
due to its flexibility and when communicating devices are
mobile. Wireless communication is a rapidly developing high
speed and high fidelity technology, which allows short range
and long range transmission, enabling multimedia
communications between portable devices. Initially wireless
communication was popular only for cellular communications.
Later a wide range of new wireless services such as cordless
telephones, Wireless Local Loop (WLL) were introduced.
These services were using analog signals and later revived to
use digital signals. Since 2003, several advancements led to a
fresh interest in wireless communications. Other than cellular
and voice transmission, many other wireless services such as
broadband wireless access systems, including the Wireless
Local Area Networks (WLANs), Wireless Personal Area
Networks (WPANs) and Wireless Metropolitan Area Networks
(WMANs) were introduced. This domain has turned out to be a
subject of extensive research and hence many standardization
activities are undertaken throughout the world. Wireless
applications require complex digital signal processing
algorithms, which demand strong design constraints in terms of
clock frequency, hardware resources, power consumption,
latency, throughput and complex computations. To meet all
these requirements, high speed and complex computation
hardware fabric such as Field Programmable Gate Arrays
(FPGAs) or Application Specific Integrated Circuits (ASICs)
are required. These devices can be clocked at very high
frequencies and they can be used to calculate sophisticated
signal processing algorithms[7-10]. The Fast Fourier Transform
(FFT) is arguably the most important signal processing
algorithm in wireless application. FFT is a mathematical
algorithm to efficiently compute Discrete Fourier Transform
(DFT). FFT is an integral part of the Orthogonal Frequency
Division Multiplexing (OFDM) based wireless systems. In an
OFDM system, a very high rate data stream is divided into
multiple parallel low rate data streams. Each smaller data
stream is then mapped to individual data sub-carrier and
modulated. The modulation of sub-carriers is performed by the
FFT algorithm. The FFT size depends on the number of
subcarriers used in the wireless standard. Considering a specific
wireless standard, the Wimax, FFT length varies from 256 to
2048. In literature many different hardware architectures have
been proposed for different wireless standards and
implemented in FPGAs since the advent of wireless
communications. The architectures are usually designed for
very concrete design specifications in terms of signal length,
precision, performance etc, Further, they target different
wireless standards. In this thesis work, a reconfigurable FFT
hardware architecture is proposed that can be applied to
different OFDM-based wire to calculate FFTs of different
lengths [11-16]. The proposed architecture is designed to
support various FFT lengths, ranging from 64-point to 2048-
point, for different OFDM wireless standards using single
hardware architecture. The proposed scheme uses clock gating
techniques and powers down unused hardware to minimize


power consumption. It is illustrated that the proposed
architecture achieves a more flexible and simpler design in
comparison with the architectures in literature [17].
1.1. DISCRETE FOURIER TRANSFORM
Discrete Fourier Transform (DFT) is a well-used and very
powerful procedure in the field of digital signal processing. It is
the discrete version of the popular continuous Fourier
Transform
Definition (Discrete Fourier Transform) the N-point DFT
for a sequence x[n] is defined as

Where

And k = 0, 1 N-1.
The DFT transforms the complex discrete time domain signal
x[n] to a complex signal in the frequency domain, X[k]. The
frequency-domain samples, the outputs of the DFT, are called
output bins or simply bins
All physical quantities are real-valued and are in many cases
sampled into real numbers, in contrary to complex numbers.
Since real numbers are a subset of complex numbers, the DFT
can be calculated for real valued numbers. The DFT has an
important property when it is calculated on a real-valued set of
inputs. When the input sequence, x[n] where n = 0, 1 N-1, is
real valued, the output of the DFT is conjugate symmetric
X [k] = X [N k], k=1 N-1.
Where superscript * denotes complex conjugation. The
complex conjugation of
x = x
r
+ jx
j
is defined as x = x
r
- jx
j .

The symmetry property shown means that the real part of the
output sequence, X[k] where k = 0, 1 N 1 has even
symmetry and the imaginary part of the output sequence has
odd symmetry. The magnitude of the output sequence is then
even symmetric, j X [k] = X [N k], k=1 N-1. Worth
noticing is the fact that X [0] is independent and do not have a
symmetric sibling. When N is even output bin N/2, X [N/2], is
also independent.
Because of the symmetry, only N=2 + 1 output values are
independent for even numbered N. The rest are redundant and
can be calculated from the set of independent values. This
means that a 1024-point FFT only gives 513 useful output
samples when the input is real-valued.
1.2. FAST FOURIER TRANSFORM
A Fast Fourier Transform is an algorithm that calculates the
Discrete Fourier Transform or its inverse in a more efficient
way compared to direct calculation from the DFT definition.
With the introduction of FFT algorithms, the use of DFT has
become practical for large problem sizes, where the calculation
of DFT are too time consuming.
The Cooley-Turkey algorithm describes a way to decompose an
N = N
1
N
2
- point DFT into two separate N
1
and N
2
point DFTs.
The radix-2 FFT divides an N-point DFT into two N/2-point
interleaved FFTs, which in turn is divided further until a set of
the most basic 2-point DFTs are left. This 2-point DFT is the
atom part of the radix-2 FFT and is called a butterfly operation.
Using this decomposition, the FFT is calculated in a series of n
= log
2
N stages
A radix-2 butterfly operation takes two input samples and
calculates two output samples. The flow graph is shown in
Figure

Figure 1: Flow graph of a radix-2 butterfly element.
Decimation In Frequency (DIF) and Decimation In Time (DIT)
are the two most common ways to decompose the Cooley-
Turkey FFT. DIT separates the input sequence, x[n], into odd
and even samples. Below is the general FFT of a 16 point FFT
radix- 2 algorithm Decimation in Frequency (DIF).
1.3. FEEDFORWARD FFT ARCHITECTURES
The N-point DFT of an input sequence x[n] is defined as:

When N is a power of two, the FFT based on the Cooley-Tukey
algorithm [25] is most commonly used in order to compute the
DFT efficiently. The Cooley-Turkey algorithm reduces the
number of operations from O (N
2
) for the DFT to


O (N log
2
N) for the FFT. In accordance with this, the
FFT is calculated in a series of n = log
N stages, where is the

base of the radix, r.

Fig. 2 The flow graphs of 16-point and radix-2
2
FFTs, decomposed
using decimation in frequency (DIF).
At each stage of the graphs, s {1 . . . n}, butterflies and
rotations have to be calculated. The lower edges of the
butterflies are always multiplied by -1. These -1 are not
depicted in order to simplify the graphs. The numbers at the
input represent the index of the input sequence, whereas those
at the output are the frequencies, k, of the output signal X[k].
Finally, each number, , in between the stages indicates a
rotation by:
As a consequence, samples for which = 0 do not need to be
rotated. Likewise, if 2 [0, N/4, N/2, 3N/4] the samples must
be rotated by 0, 270, 180 and 90, which correspond to
complex multiplications by 1, -j, -1 and j, respectively. These
rotations are considered trivial, because they can be performed
by interchanging the real and imaginary components and/or
changing the sign of the data.
Radix-2
2
is based on radix-2 and the flow graph of a
radix-2
2
DIF FFT can be obtained from the graph of a radix-2
DIF one. This can be done by breaking down each angle, , at
odd stages into a trivial rotation and a non-trivial one, , where
= mod N/4, and moving the latter to the following stage.
This is possible thanks to the fact that in the radix-2 DIF FFT
the rotation angles at the two inputs of every butterfly, A and
B, only differ by 0 or N/4. Thus, if A = and B = + N/4,
the rotation is moved to the following stage in accordance
with:

Where the first side of equation (3) represents the computations
using radix-2
and the second one using radix-2
2
, A and B being the input data
of the butterfly.

1.4. PROPERTIES OF THE RADIX-2^2 FFT
ALGORITHM
TABLE 1: Properties of the radix 2^2 FFT algorithm

These are the properties for radix-2^2 fft algorithm. Only when
these conditions satisfy butterflies, trivial and non trivial
rotations will be computed respectively.
The radix-22 feedforward architectures. First, 16-point 4-
parallel radix-2^2 feedforward FFT architecture is explained in
depth in order to clarify the approach and show how to analyze
the architectures. Then, radix-2
2
feedforward architectures for
different number of parallel samples are presented.
Figure shows 16-point 4-parallel radix-22 feedforward FFT
architecture. The architecture is made up of radix-2 butterflies
(R2), non-trivial rotators (x), trivial rotators, which are
diamond-shaped, and shuffling structures, which consist of
buffers and multiplexers. The lengths of the buffers are
indicated by a number.
The architecture processes four samples in parallel in a
continuous flow. The order of the data at the different stages is
shown at the bottom of the figure by their indices, together with
the bits bi that correspond to these indices. In the horizontal,
indexed samples arrive at the same terminal at different time
instants, whereas samples in the vertical arrive at the same time
at different terminals. Finally, samples flow from left to right.
Thus, indexed samples (0, 8, 4, and 12) arrive in parallel at the


inputs of the circuit at the first clock cycle, whereas indexed
samples (12, 13, 14, and 15) arrive at consecutive clock cycles
at the lower input terminal.
Taking the previous considerations into account, the
architecture can be analyzed as follows. Firstly, it can be
observed that butterflies always operate in pairs of samples
whose indices differ in bit b
ns
, meeting the property in Table I.
For instance, the pairs of data that arrive at the upper butterfly
of the first stage are: (0, 8), (1, 9), (2, 10) and (3, 11). The
binary representation of these pairs of numbers only differs in
b3. As, n = 4 and s = 1 at the first stage, b
ns
= b
41
= b3, so the
condition is fulfilled. This property can also be checked for the
rest of the butterflies in a similar way.

Fig. 3 Proposed 4-parallel radix-2
2
feedforward architecture for the
computation of the 16-point DIF FFT.
1.5. CONDITIONS AND DATA SHUFFLING
TECHNIQUE
Taking the previous considerations into account, the
architecture can be analyzed as follows. Firstly, it can be
observed that butterflies always operate in pairs of samples
whose indices differ in bit b
ns
, meeting the property in Table I.
For instance, the pairs of data that arrive at the upper butterfly
of the first stage are: (0, 8), (1, 9), (2, 10) and (3, 11). The
binary representation of these pairs of numbers only differs in
b3. As, n = 4 and s = 1 at the first stage, b
ns
= b
41
= b3, so the
condition is fulfilled. This property can also be checked for the
rest of the butterflies in a similar way.
Secondly, Table I shows that rotations at odd stages
are trivial and only affect samples whose indices fulfill b
ns
*
b
ns1
= 1. By particularizing this condition for the first stage,
b3 _ b2 = 1 is obtained. In the architecture shown in
Figure 3 the indices that fulfill this condition are those of the
lower edge and, thus, a trivial rotator is included at that edge.
On the other hand, the condition for non-trivial rotations at
even stages is b
ns+1
+ b
ns
= 1, b
3
+b
2
= 1 being for the second
stage. As b
3
+b
2
= 0 for all indexed samples at the upper edge
of the second stage, this edge does not need any rotator.
Conversely, for the rest of edges b
3
+b
2
= 1, so they include
non-trivial rotators. The rotation memories of the circuit store
the coefficients of the flow graph. It can be seen that the
coefficient associated to each index is the same as that in the
flow graph of Fig. 2. For instance, at the flow graph the sample
with index I = 14 has to be rotated by = 6 at the second stage.
In the architecture shown in Fig. 3 the sample with index I = 14
is the third one that arrives at the lower edge of the second
stage. Thus, the third position of the rotation memory of the
lower rotator stores the coefficient for the angle = 6.
Thirdly, the buffers and multiplexers carry out data
shuffling. These circuits have already been used in previous
pipelined FFT architectures [4], [17][20], and Figure 4 shows
how they work. For the first L clock cycles the multiplexers are
set to 0, L being the length of the buffers. Thus, the first L
samples from the upper path (set A) are stored in the output
buffer and the first L samples from the lower path (set C) are
stored in the input buffer. Next, the multiplexer changes
to1,so set C passes to the output buffer and set D is stored in
the input buffer. At the same time, sets A and B are provided in
parallel at the output. When the multiplexer commutes again
to0, sets C and D are provided in parallel. As a result, sets B
and C are interchanged.

Fig. 4 data shuffling circuit


\
Fig. 5-parallel radix-2
2
feedforward FFT
The above fig shows the proposed radix-2^2 feedforward
architectures for the computation of the 64-point DIF FFT. Fig.
show the cases of 2 4-parallel, and. These circuits can be
analyzed as has been done for the architecture in Fig. 3. For this
purpose, the order of the samples at every stage has been added
at the bottom of the architectures. As can be seen in Fig. 5, in
the proposed architectures the number of butterflies depends on
to the number of samples in parallel, for any -parallel -point
FFT the number of butterflies is. Therefore, the number of
complex adders is. Likewise, the number of rotators is. The
only exception is for. In this case, the number of rotators is.
The proposed architectures can process a continuous flow of
data. The throughput in samples per clock cycle is equal to the
number of samples in parallel, whereas the latency is
proportional to the size of the FFT divided by the number of
parallel samples, i.e., . Thus, the most suitable architecture for a
given application can be selected by considering the throughput
and latency that the application demands. Indeed, the number
of parallel samples can be increased arbitrarily, which assures
that the most demanding requirements are met. Finally, the
memory size does not increase with the number of parallel
samples. For the architectures shown in Fig. 5, the shuffling
structure at any stage requires buffers of length. According to
this, the total sample memory of the architectures is (4)
Therefore, a total sample memory of addresses is enough for
the computation of an -point FFT independently of the degree
of parallelism of the FFT. Indeed, the total memory of
addresses that the proposed architectures require is the
minimum amount of memory for an -point -parallel FFT.
Sometimes input samples are provided to the FFT in natural
order and output frequencies are also required in natural order
[27], [28]. Under these circumstances, reordering circuits are
required before and after the FFT to adapt the input and output
orders [27], [28]. For the proposed radix- feedforward FFTs the
memory requirements for natural I/O depend on the FFT size
and on the number of parallel samples. For a -parallel -point
FFT a total memory of size is enough to carry out the input
reordering, whereas a total memory of size is enough for the
output reordering [24].
1.6. EXTENSION TO RADIX-2
k
Table shows the properties for the radix-2^3 and radix-2
4
FFT
algorithms. As for radix-2
2
, these properties have been obtained
directly from the flow graphs of the algorithms. The conditions
for butterflies are the same for all stages of the FFT, whereas
the conditions for rotations depend on the stage, s. Rotations
are classified into trivial (T), non-trivial (NT), and rotations by
W8 or W16. Rotations by W8 and W16 are not-trivial, but
include a reduced set of angles [29]. According to equation (2),
rotations by W8 only consider angles that are multiples of /4,
whereas W16 only includes multiples of /8. This allows for the
simplification of the rotators that carry out the rotations. For
this purpose, different techniques have been proposed in the
literature. They include the use of trigonometric identities [30],
the representation of the coefficients in canonical signed digit
(CSD) [9] and the scaling of the coefficients [29]. Finally, in
the table i Z and, thus, for radix-2
k
the type of rotation repeats
every k stages.

Fig. 6 Proposed radix-2
4
feedforward architectures for the computation
of the 256-point
The proposed radix-2
4
feedforward FFT architectures
for N = 256 are shown in Figure 5.6. The architectures also
include square-shaped rotators, which carry out the rotations by
W16. Note that the 2-parallel radix-2
4
feedforward FFT is very
similar to the 2-parallel radix-2
2
one, with the difference that
general rotators every four stages in radix-2
2
are substituted by
W16 rotators in radix-2
4
. For 4-parallel samples, radix-2
4
also
needs fewer general rotators than radix-2
2
and radix-2
3
.
Architectures for a higher number of samples in parallel can
also be obtained using radix-2
k
. For a general case of a P-
parallel radix-2
k
N-point feedforward FFT, the number of
complex adders is equal to:
P*log2 N
The number of general rotators can be calculated as:


And the total memory is N- P. Likewise, the throughput is
always equal to the number of parallel samples, P, and the
latency is N/P.
2. SIMULATION AND OUTPUT
2.1. GENERAL RADIX 2^2 16 POINT FFT

Device utilization summary:
Slice Logic Utilization:
Timing Summary:
Speed Grade: -2
Minimum period: 6.766ns
Maximum Frequency: 147.790MHz
2.2. FEEDFORWARD 16 POINT RADIX-2^2 FFT

Timing Summary:
Speed Grade: -2

Timing Summary:
Speed Grade: -2


Minimum input arrival time before clock: No path found

Timing Summary:
Speed Grade: -2

3. COMPARISON TABLES
3.1. COMPARISON ON SPEED
TABLE 2. Comparison on speed
ARCHITECTURE FREQUENCY MIN
PERIOD
GENERAL 16 POINT
FFT
147.790MHZ 6.766ns
FEEDFORWARD 16
POINT FFT
191.788MHZ 5.215ns
FEEDFORWARD 64
PONT FFT
139.221MHZ 7.183ns
FEEDFORWARD 256
POINT FFT
135.068MHZ 7.404ns

3.2. COMPARISON ON AREA
TABLE 3. Comparison on area
ARCHITECTURE NO.OF
SLICE
REGISTERS
NO.OF
SLICE
LUTs
GENERAL 16
POINT FFT
988 out of
28800 = 3%

1788 out of
28800 =
6%
FEEDFORWARD
16 POINT FFT
311 out of
28800 = 1%
502 out of
28800 =
1%
FEEDFORWARD
64 PONT FFT
1113 out of
28800 = 3%
1632 out of
28800 =
5%
FEEDFORWARD
256 POINT FFT
1491 out of
28800 = 5%
2884 out of
28800 =
10%

4. CONCLUSION
This project extends the use of radix- 2^kto feedforward
(MDC) FFT architectures. Indeed, it is shown that feedforward
structures are more efficient than feedback ones when several
samples in parallel must be processed. In feedforward
architectures radix- can be used for any number of parallel
samples which is a power of two.. In this project we have
proposed feedforward architectures for 2 parallel, 4 parallel and
8 parallel samples. Indeed, the number of parallel samples can
be chosen arbitrarily depending of the throughput that is
required. In this proposed paper we worked on the concept of
Fast Fourier Transform (FFT) using both general existing
architectures and proposed feedforward architecture and we
have implemented in FPGA. Here in this proposed work we
mainly concentrate on DIF decomposition. Additionally, both
DIF and DIT decompositions can be used. Finally,
experimental results show that the designs are efficient both in
area and performance than the existing general architectures,
being possible to obtain throughputs of the order of G
Samples/s as well as very low latencies.


Finally, FFT using feedforward architectures the proposed
radix-2^k feedforward architectures not only offer an attractive
solution for current applications, but also open up a new
research line on feedforward structures in the future.
REFERENCES
[1]. L. Yang, K. Zhang, H. Liu, J. Huang, and S. Huang, An
efficient locally pipelined FFT processor, IEEE Trans.
Circuits Syst. II, vol. 53, no. 7, pp. 585589, Jul. 2006.
[2]. H. L. Groginsky and G. A. Works, A pipeline fast Fourier
transform, IEEE Trans. Comput., vol. C-19, no. 11, pp.
10151019, Oct. 1970.
[3]. M. Despain, Fourier transform computers using CORDIC
iterations, IEEE Trans. Comput., vol. C-23, pp. 9931001,
Oct. 1974.
[4]. S. He and M. Torkelson, Design and implementation of a
1024-point pipeline FFT processor, in Proc. IEEE Custom
Integrated Circuits Conf., May 1998, pp. 131134.
[5]. M. A. Sanchez, M. Garrido, M. L. Lopez, and J. Grajal,
ImplementingFFT- based digital channelized receivers on
FPGA platforms, IEEE Trans. Aerosp. Electron. Syst., vol.
44, no. 4, pp. 15671585, Oct. 2008.
[6]. Cortes, I. Velez, and J. F. Sevillano, Radix rk FFTs:
Matricial representation and SDC/SDF pipeline
implementation, IEEE Trans. Signal Process., vol. 57, no.
7, pp. 28242839, Jul. 2009.
[7]. E. H. Wold and A. M. Despain, Pipeline and parallel-
pipeline FFT processors for VLSI implementations, IEEE
Trans. Comput., no. 5, pp. 414426, May 1984.
[8]. S.-N. Tang, J.-W. Tsai, and T.-Y. Chang, A 2.4-GS/s FFT
processor for OFDM-based WPAN applications, IEEE
Trans. Circuits Syst. I, vol. 57, no. 6, pp. 451455, Jun.
2010.
[9]. H. Liu and H. Lee, A high performance four-parallel
128/64-point radix-24 FFT/IFFT processor for MIMO-
OFDM systems, in Proc. IEEE Asia Pacific Conf. Circuits
Syst., 2008, pp. 834837.
[10]. L. Liu, J. Ren, X. Wang, and F. Ye, Design of low-power,
1GS/s throughput FFT processor for MIMO-OFDM UWB
communication system, in Proc. IEEE Int. Symp. Circuits
Syst., May 2007, pp. 25942597.
[11]. J. Lee, H. Lee, S. in Cho, and S.-S. Choi, A high-speed,
low-complexity radix-24 FFT processor for MB-OFDM
UWB systems, in Proc. IEEE Int. Symp. Circuits Syst.,
2006, pp. 210213.
[12]. N. Li and N. P. van der Meijs, A radix 22 based parallel
pipeline FFT processor for MB-OFDM UWB system, in
Proc. IEEE Int. SOC Conf., 2009, pp. 383386.
[13]. S.-I. Cho, K.-M. Kang, and S.-S. Choi, Implementation of
128-point fast Fourier transform processor for UWB
systems, in Proc. Int. Wireless Comm. Mobile Comp.
Conf., 2008, pp. 210213.
[14]. W. Xudong and L. Yu, Special-purpose computer for 64-
point FFT based on FPGA, in Proc. Int. Conf. Wireless
Comm. Signal Process., 2009, pp. 13.
[15]. Cheng and K. K. Parhi, High-throughput VLSI architecture
for FFT computation, IEEE Trans. Circuits Syst. II, vol. 54,
no. 10, pp. 863867, Oct. 2007.
[16]. J. A. Johnston, Parallel pipeline fast Fourier transformer,
in IEE Proc. F Comm. Radar Signal Process., vol. 130, no. 6,
Oct. 1983, pp. 564572.
[17]. Gold and T. Bially, Parallelism in fast Fourier transform
hardware, IEEE Trans. Audio Electroacoust., vol. 21, no.
1, pp. 516, Feb. 1973.


Improved Power Factor through Three Phase Quasi
Z-Source Converter for FAHP Motor

Amruth VVKP
1
, Hemantha Kumar R
2
, Dr. M. Sasikumar
3
1
2
Power Electronics and Drives, Jeppiaar Engineering College, Chennai, India
3
Electrical and Electronics Engineering, Jeppiaar Engineering College, Chennai India

ABSTRACT
A modified sinusoidal pulse-width modulation
(SPWM) switching technique is suggested for
the operation of a AC-AC three phase quasi Z-
source converter to optimize the power factor
(PF) for Fly Ash High Pressure (FAHP) Motor.
The idea is to shift the delayed grid current to
the grid voltage, through a modification of the
classical SPWM converter switching technique
in order to improve the PF of induction machine
by extending this idea for three phase systems.
In this way, the decrease in the phase angle
between the fundamental current harmonic and
the voltage at the grid side is feasible, and
consequently, the use of compensation
capacitors can be avoided. Consequently, the PF
optimization as well as an improvement in the
power efficiency can be achieved. The effect of
the proposed switching technique on the PF and
the power efficiency is investigated via
simulation using the software Matlab/Simulink
as well as through appropriate experiments.
Keywords: FAHP Motor, Power Factor
Optimisation, Quasi Z-Source Converter, Three
Phase AC-AC Converter
1. INTRODUCTION
In industrial practice, ACAC line conditioners or
ACAC conversions are commonly implemented
using AC thyristor power controllers, which
employ the phase angle or integral cycle control on
the AC supply in order to obtain a desired output
voltage. However, they have some significant
disadvantages, such as a low input power factor, a
high total harmonic distortion (THD) in the source
current, and a poor power transfer efficiency. It is
well known that the reactive power reduction in a
resistiveinductive load can be achieved using
capacitors, which often have large dimensions and
high costs. The use of capacitors can increase the
harmonic distortion of grid currents and could
create resonance phenomena resulting in over-
voltages and currents within the grid. By this
classical method, only the reactive power
compensation of the fundamental current harmonic
is possible. Also for every AC resistive inductive
load, a capacitor of the corresponding value is
necessary in order to move the fundamental current
harmonic to the sinusoidal source voltage, to obtain
voltage and current waves in phase. It is obvious
that in the case of a controlled RL load through a
power electronic converter, high harmonics and a
lag of the current fundamental harmonic appear,
both reducing the power factor (PF). In this case,
the reactive power compensation through
capacitors seems to be either impossible or very
difficult.
To remove the high harmonics, especially by low
converter switching frequencies, the filter has large
dimensions, so that in fact it cannot be used. To
avoid large filter dimensions, the converter
switching frequency has to be high (e.g. 10 kHz).
Different switching techniques have been
developed and are used in different applications.
Some of these techniques have advantages related
to the PF, some lead to high efficiency and others
offer high credibility. For example, by applying the
hysteresis current control (HCC) technique, which
is one of the methods most used, it is possible to
achieve high PF, but with relatively low efficiency
[28]. The HCC switching frequency does not
remain constant, and consequently, the optimal
design of the input filter is not possible.
Furthermore, the sensors used by the HCC
technique are sensitive to noise. As the current
sampled by the sensors has to vary between two
limits (hysteresis limits), a fault sampling has
immediate influences on the current waveform,
resulting in a decrease in PF.


Often AC controllers can be replaced by sinusoidal
pulse-width modulation (PWM) AC chopper
controllers, which have the following features:
provisions for a better power factor, transient
response and efficiency, a low harmonic current in
the line, and smaller inputoutput filter parameters.
AC AC converters can perform conditioning,
isolating, and input power filtering in addition to
voltage regulation. On the contrary, applying the
sinusoidal pulse-width modulation (sPWM)
technique, there is no immediate influence on the
current caused by fault sampling, as the signal
measured by the current sensor is used for the
calculation of integrals. Also, by the use of the
sPWM technique, the grid voltage is sampled too,
but at the most there are no noise influences. Thus,
the influences on the PF coming from the sensors
by the application of the sPWM technique cannot
be considered significant. Hence, there are
considerable reasons why the sPWM method can
be seen as the most appropriate switching
technique when considering reliability and passive
filter design, in which both PF and efficiency must
be high. Direct PWM ACAC converters can be
derived from DCDC topologies; all of the
unidirectional switches are substituted with
bidirectional devices. These include buck, boost,
buckboost, and cuk converters. However, each
topology has its drawbacks.
Quasi-Z-source converters have advantages, such
as reducing the passive component ratings and
improving the input profiles. The conventional
single-phase Z-source PWM ACAC converters
proposed in have main features in that the output
voltage can be bucked/boosted and be in-phase/out-
of-phase with the input voltage. However, the
conventional Z-source PWM ACAC converters
found in have a significant drawback in that the
input current is operated in a discontinuous current
mode. When the input current operates in this
discontinuous current mode, its waveform is non-
sinusoidal, which increases the input current THD.
Moreover, the peak of the input current in the
discontinuous current mode is higher than it is in
the continuous current mode. Another drawback is
that the input voltage and the output voltage of the
original Z-source PWM ACAC converter do not
share the same ground. As a result, the desired
feature that enables the output voltage to reverse or
maintain its phase angle relative to the input
voltage is not well supported.
In an effort to overcome the inconveniences of the
traditional Z-source ACAC converters, a single-
phase quasi- Z-source ACAC converter has
recently been proposed. In comparison to the
conventional Z-source ACAC converters, the
single-phase quasi-Z-source ACAC converter has
the following unique advantages: the input voltage
and the output voltage share the same ground; the
converter operates in the continuous current mode
with special features such as a reduction in the in-
rush, a harmonic current, an improved power
factor, and an efficient power transfer.
In this paper, a modified three-phase quasi-Z-
source ACAC converter without input or output
filters is presented. The proposed converter inherits
all of the advantages of the traditional single-phase
Z-source ACAC converter; it has buckboost
capabilities and can maintain or reverse the output
phase angle all the while sharing the same ground.
Moreover, the modified single-phase quasi-Z-
source ACAC converter has the following unique
advantages: a smaller converter size, an operation
in the continuous current mode that enables special
features such as a reduction in the in-rush, a
harmonic current, an improved power factor, and
an increased efficiency. A safe-commutation
strategy is provided for the proposed converter that
eliminates voltage spikes on the switches without
the need for a snubber circuit. The operating
principles, compared to those of a conventional
single-phase Z-source ACAC converter, are
thoroughly outlined.
In order to verify the proposed converter, a
laboratory prototype based on a PIC18F4520
micro-controller was built and connected to a
resistive load R, a passive load RL, and a non-
linear load. The experimental results show that the
output voltage can be boosted and be in-phase with
the input voltage, as well as bucked/boosted and be
out-of-phase with the input voltage. The
experimental results show that the use of the safe-
commutation strategy provides a significant
improvement, in that it avoids voltage spikes on the
switches. Moreover, in order to fully explore the
merits of the modified single-phase quasi-Z-source
ACAC converter, when compared to other


conventional single-phase Z-source ACAC
converters, the experimental results exhibit a lower
input-current THD, a higher input power factor,
and a higher efficiency. The proposed converter
effectively becomes a solid-state transformer
with a continuously variable turn ratio. The
proposed converter can be used as a dynamic
voltage restorer to compensate for voltage sags and
swells in ACAC line conditioning without
requiring large energy-storage devices.
2. MODIFIED SINGLE-PHASE QUASI-
Z-SOURCE ACAC CONVERTER
2.1. INTRODUCTION
An AC/AC converter has been recently proposed
for conversion of three phase ac ac waveform.
The idea is to shift the delayed grid current to the
grid voltage, through an AC/AC converter
switching technique in order to improve the PF. In
this way, the decrease in the phase angle between
the fundamental current harmonic and the voltage
at the grid side is feasible, and consequently, the
use of compensation capacitors can be avoided.
Consequently, the PF optimisation as well as an
improvement in the power efficiency can be
achieved. Figure 2 shows the circuit diagram of the
proposed circuit. The effect of the proposed
switching technique on the PF and the power
efficiency is investigated via simulation using the
software Matlab/Simulink as well as through
appropriate experiments. For the experimental
investigation, a prototype has been designed and
constructed in the laboratory. The proposed AC/AC
converter operation has been applied in a single-
phase AC-AC PWM converter supplying a
resistive-inductive load.
2.2. Circuit diagram
Figure 3 shows the acac converter of the proposed
circuit. The acac converter contains an input LC
filter, IGBTs for switching and a common ground
for input as well as output.
3 PHASE
SUPPLY
AC AC
CONVERTER
MOTOR
A
B
C
C`
B`
A`
Fig. 1 Block diagram of the proposed converter
The system has a 415V supply given to the motor.
The motor is a 3 phase squirrel cage induction
motor. The mechanical input given to the motor is
Torque tm. When the ac ac converter is provided
in the circuit, the power factor is improved from
0.86 to 0.9379. Figure 4 shows the single phase
hardware implementation of the proposed system.
A B C
A` B` C`
Fig. 2 AC-AC converter of the proposed circuit
3. PF OPTIMISATION BASED ON
THEPROPOSED TECHNIQUE:
INVESTIGATION VIA SIMULATION
3.1. SIMULATION PROCEDURE
The PF investigation is carried out through
Matlab/Simulink simulation using as a
characteristic example the converter topology
shown in Fig. 1.a & 1.b. previous work deal with
the PF correction based on PWM operation in order
to create a current waveform having significant
reduction in the high harmonics content. In this
work, the AC-AC converter is used, and therefore,
a shifting of the fundamental current harmonic
takes place in order to decrease the phase angle
between this harmonic and the grids voltage. It is
obvious in this way that the reactive power of the
fundamental harmonic can be reduced. In the
present consideration a detailed quantitative
investigation of the power efficiency is carried out.
Especially, the consequences on these two
important power quantities, of three system
parameters the switching frequency the output
power and the shifting angle are studied
extensively, and some characteristic simulation

results are presented. In Fig. , the simulation model
of the system (Fig. 1.a&1.b) is shown. The system
characteristics are V
rms
=415V, Frequency=50Hz,
V
L-L
=410V, stator resistance=1.115, stator
inductance=0.015974H, rotor resistance=1.083,
rotor inductance=0.015974H and mutual
inductance=0.62H.
The switching frequency is chosen as a parameter
in the characteristic range taking into account the
chosen L
f
-C
f
values. The L
f
-C
f
filter plays a
significant role for the reactive power reduction
caused by the high harmonics. The simulation
results include the input active power P
in
, the rotor
speed (rpm) and power factor. Hence the power
factor is calculated
using

.
The apparent power is given
by

.
4. PF OPTIMIZATION: SIMULATION
RESULTS
Changing the shifting angle , the PF cos () and
PF and efficiency () have been calculated. In
Figs. , the simulation results are shown for the
proposed topology. The input voltage V
I=
311.1 and
rotor speed (rpm) =1482rpm.

Fig. 3 Waveform of 3 phase input voltage

Fig. 4 3 phase voltage waveform of AC-AC converter

Fig. 5: Simulation model of the proposed topology


Fig. 6 AC-AC converter of the proposed topology in Simulink

Fig. 7 3 phase stator current waveform

Fig. 8 Waveform of rotor speed

Fig. 9 Waveform of power factor
A. Comparison of simulation results
TABLE 1: Comparison of simulation results
CONVENTIONAL
SYSTEM
PROPOSED SYSTEM
V
i
=415.2V V
i
=311.2V
Rotor speed=1483rpm Rotor speed=1482rpm
Power factor=0.86 Power factor=0.9379
Apparent power=81.39KW Apparent
power=74.63KW
On applying the proposed topology, the total
power savings of the system are 6.76KW.
5. CONCLUSION


A three phase quasi Z-source converter for ac
ac power conversion has been presented in this
paper. The proposed converter, called a
modified three-phase quasi-Z-source acac
converter, inherits all of the advantages of a
traditional three phase Z source acac
converter. It can improve the power factor,
perform buckboost output voltages, as well as
maintaining or reversing the phase angle all
the while sharing the same ground. The unique
advantages in that the size of the converter is
reduced and the operation of the input current
is continuous, with additional features, such as
a reduction in the in-rush, a harmonic current.
REFERENCES
[1] Pritam Das, Majid Pahlevaninezhad, Josef
Drobnik, Gerry Moschopoulos, and Praveen K.
Jain, A Nonlinear Controller Based on a Discrete
Energy Function for an AC/DC Boost PFC
Converter, IEEE Transactions On Power
Electronics, Vol. 28, No. 12, December 2013.
[2] Yungtaek Jang, and Milan M. Jovanovic, The
TAIPEI RectifierA New Three-Phase Two-
Switch ZVS PFC DCM Boost Rectifier", IEEE
Transactions On Power Electronics, Vol. 28, No. 2,
February 2013.
[3] RasoolHaghi, Mohammad Reza Zolghadri, and
Reza Beiranvand, Novel Zero-Voltage-Switching
Bridgeless PFC Converter, Journal of Power
Electronics, Vol. 13, No. 1, January 2013.
[4] M. Sasikumar, S. ChenthurPandian, Modified Bi-
directional AC/DC Power Converter with Power
Factor Correction, IJE TRANSACTIONS B:
Applications Vol. 25, No. 3, (August 2012) 175-
180.
[5] Minh-Khai Nguyen, Young-Cheol Lim, and Yong-
Jae Kim, A Modified Single-Phase Quasi-Z-Source
ACAC Converter, IEEE Transactions On Power
Electronics, Vol. 27, No. 1, January 2012.
[6] Chien-Ming Wang, Chang-Hua Lin, and Teng-
Chieh Yang, High-Power-Factor Soft-Switched DC
Power Supply System,IEEE Transactions On
Power Electronics, Vol. 26, No. 2, February 2011.
[7] Dara L. OSullivan, Michael G. Egan, and Michael
J. Willers, A Family of Single-Stage Resonant
AC/DC Converters With PFC,IEEE Transactions
On Power Electronics, Vol. 24, No. 2, February
2009.
[8] K. Georgakas, A. Safacas, Modified sinusoidal
pulse-width modulation operation technique of an
ACAC single-phase converter to optimise the
power factor, IET Power Electronics, Received on
12th August 2008, Revised on 6th November 2009,
doi: 10.1049/iet-pel.2009.0092, ISSN 1755-4535.
[9] Chien-Ming Wang, A New Single-Phase ZCS-
PWM Boost Rectifier with High Power Factor and
Low Conduction Losses, 0-7803-8269-2/04/ (C)
2004 IEEE.

www.ijrde.com

Light Scattering Spectroscopic Imaging For
And Pathologic
Hitesh Y Surej
Electronics and Communications
ABSTRACT
The image analysis method for pathologic
tissues of skin, based on light scattering
spectroscopy deals with parameters such as
polarization and spectral changes of the
tissues scattering light. This metho
provides histological information and
spatial characteristic changes of pathologic
tissue and also used to measure the infected
area of the skin. Further it is analyzed and
compared with normal tissue of skin
detect and diagnose pathological changes i
tissues of skin. The main two principle
this spectroscopy method is coherent
scattering and multiple light scattering. The
analysis and comparison of normal and
pathologic tissues of skin using above
principles is evaluated and obtained
are tabulated. The best outcome
method is proposed in real time applications
such as cancer diagnosis, medical
spectroscopy, imaging of skin
chromophores and treatment of pathologic
skin.
Keywords: Pathologic tissues, S
changes, Spectroscopy, H
information.
1. INTRODUCTION
Light-scattering spectroscopy has been
extensively used in physical science to study a
variety of materials. Although biological tissue
is different from mineral, it can also be studied
with a light-scattering spectrum. It has been
demonstrated that the light-scattering spectrum
can provide structural and functional
information about biological tissues. When
linearly polarized light propagates through
biological tissue, it will be rapidly depolarized
by birefringent collagen fibers. The
polarization states of the scattered light can be
used to describe the birefringence information
about the biological tissue. Light traversing the
epithelial layer can be scattered by cell
ISSN: 2279-0500 Specia
Scattering Spectroscopic Imaging For Normal
Pathologic Tissues Of Skin
Hitesh Y Surej
1
, C.Edwin Suren
2
ommunications Engineering, Jeppiaar Engineering College, Chennai, India

method for pathologic
light scattering
spectroscopy deals with parameters such as
polarization and spectral changes of the
tissues scattering light. This method
provides histological information and
spatial characteristic changes of pathologic
tissue and also used to measure the infected
area of the skin. Further it is analyzed and
compared with normal tissue of skin to
detect and diagnose pathological changes in
principles of
this spectroscopy method is coherent light
and multiple light scattering. The
analysis and comparison of normal and
pathologic tissues of skin using above two
obtained data
are tabulated. The best outcome of the
is proposed in real time applications
such as cancer diagnosis, medical
spectroscopy, imaging of skin
chromophores and treatment of pathologic
Pathologic tissues, Spectral
copy, Histological
scattering spectroscopy has been
extensively used in physical science to study a
variety of materials. Although biological tissue
is different from mineral, it can also be studied
scattering spectrum. It has been
scattering spectrum
can provide structural and functional
information about biological tissues. When
linearly polarized light propagates through
biological tissue, it will be rapidly depolarized
by birefringent collagen fibers. The
f the scattered light can be
used to describe the birefringence information
about the biological tissue. Light traversing the
epithelial layer can be scattered by cell
organelles of various sizes, such as
mitochondria and nuclei, which have refractive
indices higher than that of the surrounding
cytoplasm. The cell nuclei are appreciably
larger than the optical wavelength (typically 5
10 m versus 0.5 m). They predominantly
scatter light in the forward direction, and there
is appreciable scattering in the b
direction, as well. The backscattered light has a
wavelength-dependent oscillatory componen
By analyzing the frequency and amplitude of
this oscillatory component, the size
distribution and density of epithelial nuclei can
be extracted. In this paper, we discuss the use
of polarized light in LSS, and show that it
provides a direct experimental method for
background removal, as well as other
advantages[1-2].
According to the image chain theory, by
exploiting more information about the object
of interest, better identification performance
can be obtained. If polarization and spectral
information can be effectively used to describe
skin pathology, more accurate analysis can be
expected. The introduction of imaging
spectropolarimetry makes it possible
combine the spectral, polarimetric, and spatial
information. The computational methods
originally developed for solving remote
sensing problems have been adapted and
modified for biomedical applications.
Considering the spectral and polarimetric
variations for different biological tissue states,
an imaging spectropolarimeter could be used to
improve the capability of automated systems
for biological tissue analysis. Skin is the
largest organ of the human body, and the
interaction between skin and light
involves localized or diffuse changes in spectra
and polarization states. Since the penetration
depth in tissue substantially exceeds the
epithelial thickness, the backscattered light
al Issue: pp- 373-380
373 | P a g e
Normal
Chennai, India
organelles of various sizes, such as
mitochondria and nuclei, which have refractive
ces higher than that of the surrounding
cytoplasm. The cell nuclei are appreciably
larger than the optical wavelength (typically 5
m). They predominantly
scatter light in the forward direction, and there
is appreciable scattering in the backward
The backscattered light has a
dependent oscillatory component.
By analyzing the frequency and amplitude of
this oscillatory component, the size
distribution and density of epithelial nuclei can
paper, we discuss the use
of polarized light in LSS, and show that it
provides a direct experimental method for
background removal, as well as other
According to the image chain theory, by
exploiting more information about the object
terest, better identification performance
can be obtained. If polarization and spectral
information can be effectively used to describe
skin pathology, more accurate analysis can be
The introduction of imaging
spectropolarimetry makes it possible to
combine the spectral, polarimetric, and spatial
information. The computational methods
originally developed for solving remote
sensing problems have been adapted and
modified for biomedical applications.
Considering the spectral and polarimetric
ions for different biological tissue states,
an imaging spectropolarimeter could be used to
improve the capability of automated systems
for biological tissue analysis. Skin is the
largest organ of the human body, and the
interaction between skin and light often
involves localized or diffuse changes in spectra
Since the penetration
depth in tissue substantially exceeds the
epithelial thickness, the backscattered light
www.ijrde.com

from epithelial nuclei is ordinarily very small
in amplitude, and it is easily masked by the
diffuse background from the underlying tissue
[3]. To analyze the backscattered component,
this background must be removed.
One important application of a technique
capable of measuring quantitative changes of
intracellular structures in situ is early diagnosis
of cancer or precancerous lesions. More than
90% of all cancers are epithelial in origin.
Most epithelial cancers have a well
precancerous stage characterized by nuclear
atypia and dysplasia .To optimize the use of
LSS for various medical applications, it is of
interest to consider more robust methods of
removing or significantly reducing the diffuse
component of the scattered light
reports an experimental means of isolating the
scattering from epithelial cell nuclei using
polarized light. It is well known t
polarized light loses its polarization when
traversing a turbid medium of
tissue.
2. EXISTING MODEL
To study the spectrum of polarized back
scattered light, we employ an instrumen
delivers collimated polarized light on tissue
and separates two orthogonal polarizations of
backscattered light. In our system (Fig. a
light from a broadband source (250
tungsten lamp) is collimated and then
refocused with a small solid angle on
sample, using lenses and an aperture. A broad
band polarizer linearly polarizes the incident
beam. In order to avoid specular reflectance,
the incident beam is oriented at an angle of
15degree to the normal to the surface of the
sample. The sample is illuminated by a circular
spot of light of 2 mm in diameter. The
reflected light is collected in a narrow cone (
0.015 rad), and two polarizations are separated
by means of a broad-band polarizing beam
splitter cube, which also serves as our
analyzer. The output from this analyzer is
delivered through 200- m core diameter
optical fibers into two channels of a
multichannel spectroscope. This enables the
spectra of both components to be measured
from epithelial nuclei is ordinarily very small
it is easily masked by the
diffuse background from the underlying tissue
ze the backscattered component,

One important application of a technique
capable of measuring quantitative changes of
is early diagnosis
of cancer or precancerous lesions. More than
90% of all cancers are epithelial in origin.
Most epithelial cancers have a well-defined
precancerous stage characterized by nuclear
To optimize the use of
LSS for various medical applications, it is of
interest to consider more robust methods of
removing or significantly reducing the diffuse
.This paper
reports an experimental means of isolating the
l cell nuclei using
polarized light. It is well known that initially
oses its polarization when
versing a turbid medium of biological
To study the spectrum of polarized back-
scattered light, we employ an instrument that
delivers collimated polarized light on tissue
and separates two orthogonal polarizations of
red light. In our system (Fig. a),
light from a broadband source (250-W
tungsten lamp) is collimated and then
refocused with a small solid angle onto the
sample, using lenses and an aperture. A broad-
band polarizer linearly polarizes the incident
beam. In order to avoid specular reflectance,
the incident beam is oriented at an angle of
15degree to the normal to the surface of the
s illuminated by a circular
spot of light of 2 mm in diameter. The
reflected light is collected in a narrow cone (
0.015 rad), and two polarizations are separated
band polarizing beam
splitter cube, which also serves as our
e output from this analyzer is
m core diameter
optical fibers into two channels of a
multichannel spectroscope. This enables the
spectra of both components to be measured
simultaneously in the range from 400 to 900
nm. The beams are not perfectly collinear, and
when they pass through the polarizer and
analyzer cubes this gives rise to a small
amount of distortion. Furthermore, the beam
splitter has different reflectivities for and
polarizations. A diffusely reflective white
surface was used as a standard to correct for
wavelength non uniformity, and to calibrate
the signals in the two channels. I Perpendicular
and I were each normalized to the
corresponding background spectra, and taken
with the white diffusing surface. This remo
spectral non uniformities in the light source.
Thus, the experiments actually measured the
normalized residual intensity.
Fig 1.a. Schematic diagram of polarization LSS
system.
3. PROPOSED WORK
Fig. 1.b.Illustration of the established
spectropolarimetric imaging system.
The spectral range from 400 to 720nm. There
are a total of 32 spectral bands with 10nm
374 | P a g e
simultaneously in the range from 400 to 900
not perfectly collinear, and
when they pass through the polarizer and
analyzer cubes this gives rise to a small
amount of distortion. Furthermore, the beam
splitter has different reflectivities for and
polarizations. A diffusely reflective white
s used as a standard to correct for
wavelength non uniformity, and to calibrate
the signals in the two channels. I Perpendicular
were each normalized to the
corresponding background spectra, and taken
with the white diffusing surface. This removed
spectral non uniformities in the light source.
Thus, the experiments actually measured the

Schematic diagram of polarization LSS

Illustration of the established
The spectral range from 400 to 720nm. There
are a total of 32 spectral bands with 10nm
www.ijrde.com

space between each band. The linear
polarization characteristicsintensity, the
degree of linear polarization, and the phase of
polarization at each bandcan be acquir
Fig. 2. Percentage of linearly polarized light,
oriented so that maximum transmission is attained,
passing through the filter relative to the amount that
entered.

Fig. 3. Structure of the spectropolarimetric imaging
and analysis system
space between each band. The linear
intensity, the
polarization, and the phase of
can be acquired

Percentage of linearly polarized light,
oriented so that maximum transmission is attained,
passing through the filter relative to the amount that
Structure of the spectropolarimetric imaging

Fig. 4. Series of examples skin images at different
spectral bands: (a) 530 nm, (b) 560 nm, (c) 590 nm,
(d) 620 nm, (e) 650 nm, (f) 680 nm
Fig. 5.Skin image described by different
polarimetric parameters at 590nm: (a) S
S
2
, (d) DoLP.
2.1. IMAGING
SPECTROPOLARIMETER
The imaging spectropolarimeter is
schematically depicted in Fig 1. An incoherent
white light source (halogen light source) is
used. The light is collimated by a 20cm focal
length lens and delivered to the skin at an angle
of 25 to the normal of the skin surface. The
choice of angle is not critical, and oblique
angles of illumination other than 25 also
375 | P a g e

. Series of examples skin images at different
spectral bands: (a) 530 nm, (b) 560 nm, (c) 590 nm,

.Skin image described by different
S
0
, (b) S
1
, (c)
SPECTROPOLARIMETER:
The imaging spectropolarimeter is
. An incoherent
white light source (halogen light source) is
used. The light is collimated by a 20cm focal
length lens and delivered to the skin at an angle
of 25 to the normal of the skin surface. The
choice of angle is not critical, and oblique
other than 25 also
www.ijrde.com

work. The 12bit CCD camera, with a macro
lens, collects only light that enters the skin and
is backscattered toward the camera. A liquid
crystal tunable filter (LCTF), made by
Cambridge Research Instruments,
incorporated with a CCD to acquire the
spectropolarimetric images. The full width
half maximum has three options (7, 10, and
20nm), which are set during the design and
manufacturing process and cannot be adjusted
by the end user. The spectral range of the
LCTF is 400720nm.The LCTF is a band
filter that can control the wavelength of the
transmitting light. It is based on a multistage
Lyot-type polarization interference filter with
an electronically controllable liquid
wave plate in each stage to provi
retardance. A linear polarizer is included in the
filter that allows the transmission of only the
associated polarized component. The
percentage of linearly polarized light, oriented
so that maximum transmission is attained,
passing through the filter relative to the amount
that entered, is shown in Fig 2. In the imaging
system, the LCTF in front of the camera is
manually aligned at four different angles: 0,
45, 90 and 135. Four image sequences are
acquired at each band i0, i45, i90 and
i135, where = 1, 2 ,K is the number of
bands. The system is operated using a personal
computer running the windows oper
system. A set of software was developed to
control instrument driver routines for CCD
detector. The software allows the user sel
experimental parameters such as the CCD
detector shutter exposure time. The structure of
spectropolarimetric imaging systems and
associated image analysis procedures
shown in Fig 3. An example of six band
intensity images (530,560,590,620,650 and
680 nm) collected by the CCD detector is
shown Fig 4. There is progression from
dimmer images to brighter images because of
the light sources spectrum shape. In order to
compute the wavelength of the skin it is
necessary to normalize the images to elimini
the effect of light source shape .The calculated
polarimetric images (s0, s1, s2, and D0LP) in
the 590 nm band are shown Fig 5.
, with a macro
lens, collects only light that enters the skin and
is backscattered toward the camera. A liquid
crystal tunable filter (LCTF), made by
Cambridge Research Instruments, is
ed with a CCD to acquire the
spectropolarimetric images. The full width at
aximum has three options (7, 10, and
20nm), which are set during the design and
manufacturing process and cannot be adjusted
by the end user. The spectral range of the
720nm.The LCTF is a band pass
filter that can control the wavelength of the
transmitting light. It is based on a multistage
type polarization interference filter with
an electronically controllable liquid-crystal
wave plate in each stage to provide variable
A linear polarizer is included in the
filter that allows the transmission of only the
associated polarized component. The
percentage of linearly polarized light, oriented
so that maximum transmission is attained,
filter relative to the amount
. In the imaging
system, the LCTF in front of the camera is
manually aligned at four different angles: 0,
Four image sequences are
i0, i45, i90 and
135, where = 1, 2 ,K is the number of
The system is operated using a personal
computer running the windows operating
was developed to
control instrument driver routines for CCD
The software allows the user select
experimental parameters such as the CCD
detector shutter exposure time. The structure of
spectropolarimetric imaging systems and
associated image analysis procedures are
An example of six band
intensity images (530,560,590,620,650 and
the CCD detector is
. There is progression from
dimmer images to brighter images because of
. In order to
compute the wavelength of the skin it is
necessary to normalize the images to eliminiate
the effect of light source shape .The calculated
s2, and D0LP) in

2.2. SPECTROPOLARIMETRIC
CORRECTION
In the imaging process, the sensed light
contains not only light scattered by tissues but
also light scattered/reflected by surroundings.
The spectral channels have unknown gains due
to filter transmission and CCD response and
have unknown offsets due to dark current.
These images must be corrected to make the
acquired spectropolarimetric information more
precise. Therefore, we propose a method to
convert the raw images into
spectropolarimetric reflectance images for
analysis. Two Spectralon panels and a
spectrometer are used in calibration
panel, with approximately 99% reflectance, is
referred to as white Spectralon, and a panel
with lower than 5% and symmetrical
reflectance is referred to as black Spectralon.
Fig. 6. Reconstructed spectropolarimetric curves of
normal tissue and chilblain tissue: (a) S
S
2
, and (d) DoLP. The x coordinate represents
wavelength, and the y coordinate represents
reflectance.
2.3. Visual Enhancement Algorithm
It is crucial to point out the pathological tissue
region clearly and show its boundary
accurately for computer-aided clinica
diagnosis. Light-scattering spectrum and
polarization states can provide different
structural and functional information about the
biological tissues. The Stokes parameter
gives the intensity of the beam at wavelength
376 | P a g e
SPECTROPOLARIMETRIC
In the imaging process, the sensed light
contains not only light scattered by tissues but
also light scattered/reflected by surroundings.
The spectral channels have unknown gains due
to filter transmission and CCD response and
have unknown offsets due to dark current.
These images must be corrected to make the
mation more
precise. Therefore, we propose a method to
convert the raw images into
spectropolarimetric reflectance images for
analysis. Two Spectralon panels and a
are used in calibration. The
panel, with approximately 99% reflectance, is
rred to as white Spectralon, and a panel
with lower than 5% and symmetrical
Spectralon.

. Reconstructed spectropolarimetric curves of
S
0
, (b) S
1
, (c)
coordinate represents
coordinate represents
Visual Enhancement Algorithm
It is crucial to point out the pathological tissue
region clearly and show its boundary
aided clinical
scattering spectrum and
polarization states can provide different
structural and functional information about the
biological tissues. The Stokes parameter S
0;
gives the intensity of the beam at wavelength
www.ijrde.com

, and it can be used to describe the tissue
spectral characteristics. The spectral difference
between the normal tissue and the pathological
tissue across the bands is shown in Fig.
DoLP reflects the proportion of linear
polarization energy in the whole beam
energy, and it can be used to describe the
tissues polarimetric characteristics. Figure
6(d) shows the polarimetric difference between
the normal tissue and the pathological tissue
across the bands. On the other hand, there are
some differences of spatial characteri
among Stokes parameters and DoLP. These
differences can be observed in Fig.
image contains more abundant texture
information than the S
1
, S
2
, and DoLP images.
The DoLP image has an advantage in
describing the polarimetric difference. By
exploiting more information about the objects
can be achieved. If the S
0
image can be fused
with the DoLP images, an image with better
contrast and more detailed textures can be
expected. We propose here a false c
mapping based spectropolarimetric imagery
fusion method to exploit the information from
both the spectrum and the polarization states. It
can integrate the texture information from the
high spatial resolution S
0
image with the
polarimetric information from the low spatial
resolution DoLP images in different bands to
achieve better discriminability of different
pathological regions. The fusion algorithm is
named spectropolarimetric false color image
fusion, which is described as follows.
Algorithm of spectropolarimetric false color
image fusion The pre-processing, including
denoising and normalization, is applied to the
S
0
and DoLP image sequences
component analysis (PCA) is applied to the
image sequence and the DoLP image
sequence. We use the S
0
image sequence to
illustrate the process, and the same procedure
is applied to the DoLP sequence. Suppose
there are

N images in the S
0
image sequence
and denote by S
0, n
, n 1; 2; ; N
vector that contains all the pixels in the
image. Find the common spectral information
in S
0;1
, S0;2, and S0;3: Find the common
polarimetric information in DoLP
and DoLP
3
: Calculate the unique part in each
describe the tissues
spectral characteristics. The spectral difference
between the normal tissue and the pathological
tissue across the bands is shown in Fig. 6(a).
DoLP reflects the proportion of linear
polarization energy in the whole beams
it can be used to describe the
s polarimetric characteristics. Figure
shows the polarimetric difference between
the normal tissue and the pathological tissue
On the other hand, there are
some differences of spatial characteristics
among Stokes parameters and DoLP. These
differences can be observed in Fig.5. The S
0
image contains more abundant texture
, and DoLP images.
The DoLP image has an advantage in
describing the polarimetric difference. By
oiting more information about the objects
image can be fused
with the DoLP images, an image with better
contrast and more detailed textures can be
expected. We propose here a false color
mapping based spectropolarimetric imagery
fusion method to exploit the information from
both the spectrum and the polarization states. It
can integrate the texture information from the
image with the
from the low spatial
resolution DoLP images in different bands to
achieve better discriminability of different
pathological regions. The fusion algorithm is
named spectropolarimetric false color image
fusion, which is described as follows.
ectropolarimetric false color
processing, including
denoising and normalization, is applied to the
and DoLP image sequences Principal
component analysis (PCA) is applied to the S
0
image sequence and the DoLP image
image sequence to
illustrate the process, and the same procedure
is applied to the DoLP sequence. Suppose
image sequence
N, the column
vector that contains all the pixels in the nth
Find the common spectral information
Find the common
polarimetric information in DoLP
1
, DoLP
2
,
e the unique part in each
image The pairwise subtraction of multiband
images can be used to enhance the difference
between them. Through subtraction of the
common component, the unique information
will be enhanced in each image.
images by using the unique components
unique components calculated are subtracted
from the original image of other modalities.
This step serves to enhance the representation
of each modalitys specific details in the final
fused result. The resulting images can then be
combined into a composite false color image
by representing the processed S
0**
image as the
red channel, the DoLP** image as the green
channel, and the S
0
image as the blue channel
of a red-green-blue (RGB) display.
Fig. 7. Example of the spectropolarimetric false
color image fusion process: (a) image of Co
image of Co
DoLP
, (c) image of DoLP*, (d) image of
S
0*,
(e) image of S
0**
, (f) image of DoLP
visually enhanced result, (h) reflectance image of
chilblain at 590nm.
In this subsection we use an example to
illustrate the proposed spectropolarimetric
false color image fusion process. Figure
shows an image that contains the common
spectral information from the first three PCA
components of the S
0
image sequence. Figure
377 | P a g e
The pairwise subtraction of multiband
images can be used to enhance the difference
hrough subtraction of the
common component, the unique information
Adjust the
by using the unique components The
are subtracted
from the original image of other modalities.
This step serves to enhance the representation
s specific details in the final
The resulting images can then be
e color image
image as the
image as the green
image as the blue channel
.

Example of the spectropolarimetric false
color image fusion process: (a) image of CoS
0
, (b)
, (d) image of
, (f) image of DoLP** , (g)
visually enhanced result, (h) reflectance image of
In this subsection we use an example to
illustrate the proposed spectropolarimetric
false color image fusion process. Figure 7(a)
spectral information from the first three PCA
image sequence. Figure
www.ijrde.com

7(b) shows an image that contains the common
polarimetric information from the first three
PCA components of the DoLP image
sequence. The results shown in Figs.
7(d), and these two images demonstrate that
pairwise subtraction of multiband images can
be used to enhance the difference between
them. Figures 7(e) and 7(f) show the unique
components calculated. We see that the
specific details of each modality are enhanced.
Figure 7(g) shows the final fusion results, and
Fig. 7(h) shows the spectral image at 590nm.
By comparing Figs. 7(g) and 7(h)
concluded that it is much easier to separate the
pathological tissue (highlighted in red online)
in Fig. 7(g) by using the proposed method. The
pathological tissue region is enhanced, and its
boundary can be clearly identified. This is very
helpful in computer-aided diagnosis to
improve clinical diagnosis accuracy.
4. EXPERIMENTAL RESULTS AND
DISCUSSION
Fig. 8. Benign pigmented nevus images at
intensities of (a) 560nm, (b) 590nm, (c) 620nm, (d)
650nm, (e) S
0
image at 590nm, (f)
590nm, (g) S
2
image at 590nm, and (h) DoLP image
at 590nm.
polarimetric information from the first three
PCA components of the DoLP image
shown in Figs. 7(c) and
, and these two images demonstrate that
on of multiband images can
be used to enhance the difference between
show the unique
. We see that the
specific details of each modality are enhanced.
shows the final fusion results, and
shows the spectral image at 590nm.
(h), it can be
concluded that it is much easier to separate the
pathological tissue (highlighted in red online)
by using the proposed method. The
nhanced, and its
boundary can be clearly identified. This is very
aided diagnosis to
improve clinical diagnosis accuracy.
RIMENTAL RESULTS AND

. Benign pigmented nevus images at
intensities of (a) 560nm, (b) 590nm, (c) 620nm, (d)
image at 590nm, (f) S
1
image at
image at 590nm, and (h) DoLP image
To document the performance of the proposed
method, we applied it to the images collected
from the forearms of 10 volunteer subjects
with two different tissues: ulcerated chilblain
and benign pigmented nevus. Figure
the polarimetric images S
0
, S
1
, S
2
, and DoLP at
590nm (ulcerated chilblain). Figure
the spectropolarimetric difference of ulcerated
chilblain tissue and ambient normal tissue. It
can be concluded that the spectropolarimetric
differences of these two types of tissues
change with the variation of wavelength.
equivalent to the total reflectance. S
the difference in intensity between horizontal
and vertical linearly polarized components.
is the difference between linearly polarized
components oriented at +45 and
comparing S
0
, S
1
, and S
2
images, it can be se
that there is a great increase of gray level
difference between ulcerated chilblain and
normal tissue due to the skins superficial
scattering of incident polarized light. DoLP is
the combination of S
0
, S
1
, and
emphasizes the scattering of incident polarized
light by superficial tissues.The S
0
image shows
the ulcerated chilblain region as a slightly
darker region due to the darker color of
ulcerated chilblain. However, the
DoLP images show this region as a darker
signal than normal skin. The collagen fibers in
the ulcerated chilblain randomize the polarized
illumination faster than they backscatter the
polarized illumination. The balance between
the rate of randomization and the rate of
backscattering may be influenced by the size
of collagen fiber bundles in the ulcerated
chilblain. The S
1
, S
2
, and DoLP images can
reveal some structural information about the
ulcerated chilblain, suggesting that they could
be helpful in evaluating the topography of
ulcerated chilblain. The curves of
polarimetric parameters versus wavelength
dependency are shown in Fig. 6. Figure
shows the reflectance images at 590nm, and
Fig.7(g) shows the visual enhancement result,
where the ulcerated chilblain region is shown
in red online. Although the reflectance
normal tissue is obvious as shown in Fig.
it is difficult to determine the range of
ulcerated chilblain region. On the other hand,
378 | P a g e
To document the performance of the proposed
t to the images collected
from the forearms of 10 volunteer subjects
with two different tissues: ulcerated chilblain
and benign pigmented nevus. Figure 5 shows
, and DoLP at
590nm (ulcerated chilblain). Figure 6 shows
the spectropolarimetric difference of ulcerated
chilblain tissue and ambient normal tissue. It
can be concluded that the spectropolarimetric
differences of these two types of tissues
change with the variation of wavelength. S
0
is
S
1
represents
the difference in intensity between horizontal
and vertical linearly polarized components. S
2
is the difference between linearly polarized
45 and -45. By
images, it can be seen
that there is a great increase of gray level
s superficial
scattering of incident polarized light. DoLP is
, and S
2
, and it
cident polarized
image shows
the ulcerated chilblain region as a slightly
darker region due to the darker color of
ulcerated chilblain. However, the S
1
, S
2
, and
DoLP images show this region as a darker
skin. The collagen fibers in
the ulcerated chilblain randomize the polarized
illumination faster than they backscatter the
polarized illumination. The balance between
the rate of randomization and the rate of
backscattering may be influenced by the size
f collagen fiber bundles in the ulcerated
, and DoLP images can
reveal some structural information about the
ulcerated chilblain, suggesting that they could
be helpful in evaluating the topography of
ulcerated chilblain. The curves of these
polarimetric parameters versus wavelength
. Figure 7(h)
shows the reflectance images at 590nm, and
shows the visual enhancement result,
where the ulcerated chilblain region is shown
in red online. Although the reflectance
normal tissue is obvious as shown in Fig. 6(a),
it is difficult to determine the range of the
ulcerated chilblain region. On the other hand,
www.ijrde.com

the ulcerated chilblain affects not only the skin
vasculature but also the collagen fibers, while
collagen fibers can rapidly depolarize the
incident light . Through fusing the information
provided by spectral and polarimetric images,
better contrast can be obtained. In the fusion,
both the spectral difference and polarimetric
normal tissue are exploited. Comparing Figs.
7(a) and 7(b), it can be clearly seen that t
boundary between these two tissues is much
enhanced. Figure 8 shows four benign
pigmented nevus regions, marked by four
circles, 1, 2, 3, and 4. The pigmented nevus 2
and 3 can be obviously seen in the spectral
images because of their black color; howev
pigmented nevus 1 and 4 are relatively unclear.
In the S0 image at 590nm, the fourth
pigmented nevus can be observed, while there
is some confusion of the locations of the
benign pigmented nevus regions in the DoLP
image. This is mainly due to the infl
collagen fibers. On the other hand, the
difference between the nevus and the normal
tissue becomes more and more obvious with
the increase of wavelength. This is because the
spectral reflectance is sensitive to the variation
of melanosomes, as shown in Figs.
9(b). From Figs. 9(a) and 9(b)
observed that the spectral difference from 500
to 600nm is relatively small but the DoLP
difference is much more obvious.
Figure 10(a) shows the reflectance image at
590nm, where the brown pigmented nevus is
almost invisible. Figure 10(b) shows the visual
enhancement result of melanin, where the
pigmented nevus is shown in black and the
surrounding skin is shown in green online. By
comparing Figs. 10(a) and 10(b), it is seen that
through spectropolarimetric image fusion, the
boundary of benign pigmented nevus can be
much better determined. It is very desirable in
monitoring the variation of the size of
pigmented nevus.
The two different tissues in the experiment
contain vasculature, collagen fibers, and
melanin structures, and they will change the
light-scattering spectra and polarization states.
Vasculature, collagen, and melanin a
the ulcerated chilblain affects not only the skin
vasculature but also the collagen fibers, while
collagen fibers can rapidly depolarize the
incident light . Through fusing the information
tral and polarimetric images,
obtained. In the fusion,
e spectral difference and polarimetric
normal tissue are exploited. Comparing Figs.
, it can be clearly seen that the
boundary between these two tissues is much
shows four benign
pigmented nevus regions, marked by four
circles, 1, 2, 3, and 4. The pigmented nevus 2
and 3 can be obviously seen in the spectral
images because of their black color; however,
relatively unclear.
In the S0 image at 590nm, the fourth
pigmented nevus can be observed, while there
is some confusion of the locations of the
benign pigmented nevus regions in the DoLP
image. This is mainly due to the influence of
collagen fibers. On the other hand, the
difference between the nevus and the normal
tissue becomes more and more obvious with
the increase of wavelength. This is because the
spectral reflectance is sensitive to the variation
wn in Figs. 9(a) and
(b), it can be
observed that the spectral difference from 500
to 600nm is relatively small but the DoLP

shows the reflectance image at
590nm, where the brown pigmented nevus is
shows the visual
enhancement result of melanin, where the
pigmented nevus is shown in black and the
surrounding skin is shown in green online. By
, it is seen that
through spectropolarimetric image fusion, the
boundary of benign pigmented nevus can be
much better determined. It is very desirable in
monitoring the variation of the size of
ssues in the experiment
contain vasculature, collagen fibers, and
melanin structures, and they will change the
scattering spectra and polarization states.
Vasculature, collagen, and melanin are typical
structures of cancer. Cancer tends to result in
the denaturisation of the collagen, thus
resulting in a loss of birefringence due to the
deformation of the regular molecular binding
structure, and light scattering
states will also be changed according to the
variation of birefringence. At the same time,
the variation of melanin and vasculature will
change the light-scattering spectra. Through
spectropolarimetric false color image fusion,
the spectral and polarimetric difference can be
utilized jointly, and the difference of normal
tissue and pathological tissue can be enhanced.
This can benefit the detection and
identification of pathological tissues.
Fig. 9. Reconstructed spectropolarimetric curves of
normal tissue and benign pigmented nevus: (a)
S
0
,(b) DoLP. The x coordinate is the wavelength,
and the y coordinate is reflectance.
379 | P a g e
. Cancer tends to result in
of the collagen, thus
resulting in a loss of birefringence due to the
deformation of the regular molecular binding
polarization
states will also be changed according to the
he same time,
the variation of melanin and vasculature will
scattering spectra. Through
spectropolarimetric false color image fusion,
the spectral and polarimetric difference can be
utilized jointly, and the difference of normal
pathological tissue can be enhanced.
This can benefit the detection and
identification of pathological tissues.

. Reconstructed spectropolarimetric curves of
normal tissue and benign pigmented nevus: (a)
coordinate is the wavelength,
www.ijrde.com

Fig. 10. (a) Reflectance image of benign pigmented
nevus at 590nm, (b) visually enhanced result of (a).

5. CONCLUSION
We have reported a new spectropolarimetric
imaging method for analysis of tissue
characteristics and proposed a visual
enhancement method to fuse the acquired
spectral and polarimetric information by using
false colour mapping. The experimental results
show that spectropolarimetric imaging can be
used to discriminate the different pathological
tissues efficiently. The spectral and
polarimetric information can reveal
biochemical and structural information about
the tissue. The proposed visual enhancement
algorithm provides an intuitive and obvious
clue of the pathological tissue region for
computer-aided diagnosis.
REFERENCES
[1]. V. Backman, R. Gurjar, K. Badizadegan,
I. Itzkan, R. Dasari,L. Perelman, and M.
Feld, Polarized light scattering
spectroscopy for quan
measurement of epithelial cellular

a) Reflectance image of benign pigmented
nevus at 590nm, (b) visually enhanced result of (a).
We have reported a new spectropolarimetric
imaging method for analysis of tissue
characteristics and proposed a visual
enhancement method to fuse the acquired
spectral and polarimetric information by using
mapping. The experimental results
w that spectropolarimetric imaging can be
used to discriminate the different pathological
tissues efficiently. The spectral and
polarimetric information can reveal
biochemical and structural information about
the tissue. The proposed visual enhancement
orithm provides an intuitive and obvious
clue of the pathological tissue region for
V. Backman, R. Gurjar, K. Badizadegan,
I. Itzkan, R. Dasari,L. Perelman, and M.
Polarized light scattering
spectroscopy for quantitative
measurement of epithelial cellular
structures in situ, IEEE J. Sel. Top.
Quantum Electron. 5, 10191026 (1999).
[2]. R. S. Gurjar, V. Backman, L. T.
Perelman, I. Georgakoudi,K.
Badizadegan, I. Itzkan, R. Dasari, and M.
Feld,Imaging human epithelial
properties with polarized lightscattering
spectroscopy, Nat. Med. 7
(2001).
[3]. .L. T. Perelman, V. Backman, M.
Wallace, G. Zonios, R. Manoharan, A.
Nusrat, S. Shields, M. Seiler, C. Lima, T.
Hamano, I. Itzkan, J. Van Dam, J. M.
Crawford, and M. S. Feld,
of periodic fine structure in reflectance
from biological tissue: A new technique
for measuring nuclear size distribution
Phys. Rev. Lett., vol. 80, pp. 627
1998.

380 | P a g e
IEEE J. Sel. Top.
1026 (1999).
R. S. Gurjar, V. Backman, L. T.
Perelman, I. Georgakoudi,K.
Badizadegan, I. Itzkan, R. Dasari, and M.
Imaging human epithelial
properties with polarized lightscattering
7, 12451248
.L. T. Perelman, V. Backman, M.
Wallace, G. Zonios, R. Manoharan, A.
Nusrat, S. Shields, M. Seiler, C. Lima, T.
Hamano, I. Itzkan, J. Van Dam, J. M.
Feld, Observation
of periodic fine structure in reflectance
from biological tissue: A new technique
for measuring nuclear size distribution,
, vol. 80, pp. 627630,


Noise Cancellation in Acoustic System using TMS
Processor
Janani. Jayasree S
1
, Anusha Kurian
2
, Josephine Iswarya
3
, V J.Jebastine
4


ABSTRACT
This project aims at the removal of noise signals
such as echo, pink noise, impulse and background
from speech signal such as FM, CD, Auditorium
and Teleconference using adaptive filters. The
canceller uses some adaptive algorithms such as
RLS (recursive least mean square), LMS (fast least
mean square) and FxT-RLS (Fast Sectional
Convolution Transversal Recursive Least Square)
FxT-RLS Algorithm is implemented by using a
traversal structure for the sectional convolution
FFT in F-RLS. In this method the signals are
converted to frequency domain by taking FFT
using a traversal structure. In case of RLS and
LMS, feedback loop is used whereas in FxT-RLS
the blocks are used in the adaptive filter. These
algorithms uses FIR filters with taps , which are
chosen to minimize the error signal coming from
the system where minimization of the error are
based on the stochastic gradient method. The noise
signal and algorithm are implemented in
TMS320C6713.These algorithms are based on the
following criteria i) stability ii) complexity iii) step-
size. The various parameters used are 1) SNR,2)
BER ,3) Stability and 4) Convergence Speed: Here
we are comparing all the algorithms and based on
the above parameters FxT-RLS algorithm is found
to be better than other two.
Keywords: Adaptive filters, LMS algorithm, RLS
algorithm, FxT-RLS algorithm, TMS320C6713.
1. INTRODUCTION
Noise refers to influences on effective communication
that influence the interpretation of conversations.
Noise can include physical noise, physiological and
semantic noises. An urge to control the noise has
become the focus of a number of researchers over the
years [1-5]. Therefore, various adaptive algorithms are
implemented for echo/ noise cancellation. In the
process of transmission of information from the source
to receiver side, noise from the surroundings
automatically gets added to the signal. This acoustic
noise picked up by microphone is undesirable, as it
reduces the perceived quality or intelligibility of the
audio signal. The problem of effective removal or
reduction of noise is an active area of research. The
usage of adaptive filters is one of the most popular
proposed solutions to reduce the signal corruption
caused by predictable and unpredictable noise. An
adaptive filter has the property of self-modifying its
frequency response to change the behavior in time,
allowing the filter to adapt the response to the input
signal characteristics change. Due to this capability the
overall performance and the construction flexibility,
the adaptive filters have been employed in many
different applications, some of the most important are:
telephonic echo cancellation, radar signal processing,
navigation systems, communications channel
equalization and biometrics signals processing. The
purpose of an adaptive filter in noise cancellation is to
remove the noise from a signal adaptively to improve
the signal to noise ratio. Figure 1 shows the diagram of
a typical Adaptive Noise Cancellation (ANC) system.
The discrete adaptive filter processed the reference
signal x(n) to produce the output signal y(n) by a
convolution with filters weights w(n).The filter output
y(n) is subtracted from d(n) to obtain an estimation
error e(n). The primary sensor receives noise x1(n)
which has correlation with noise x (n) in an unknown
way. The objective here is to minimize the error signal
e (n) [6]. This error signal is used to incrementally
adjust the filters weights for the next time instant. The
basic adaptive algorithms which widely used for
performing weight updating of an adaptive filter are:
the LMS (Least Mean Square), FLMS (Fast Least
Mean Square) and the RLS (Recursive Least Square)
algorithm. Among all adaptive algorithms LMS has
probably become the most popular for its robustness,
good tracking capabilities and simplicity in stationary
environment [7]. RLS is best for non-stationary
environment with high convergence speed but at the
cost of higher complexity. Therefore a tradeoff is
required in convergence speed and computational
complexity, FxT-RLS provides the right solution.
Noise cancellation is often used to extract the desired
speech from the given noisy speech. The noise

cancellation plays an important role in digital voice
communication systems for e.g. Cell phones require
adaptive noise cancellation to reduce further
degradation of vo-coded speech. Active noise control
(ANC) (also known as noise cancellation, active noise
reduction (ANR) or anti-noise) is a method for
reducing unwanted sound. The following figure shows
the block diagram of an Active Noise Control (ANC)
system. It incorporates an adaptive filter, whose
coefficients are updated from the error function, e (n).

2. LEAST MEAN SQUARE
Echo mainly occurs when there is a feedback path
between the near end signal and far end signal. Due to
this, the speaker listens to his own voice. This is
termed as echo and it degrades the quality of speech.
The most popular algorithm used in echo cancellation
is the LMS but it lags in terms of convergence rate
which leads to echo. An adaptive FIR filter with LMS
is developed to cancel the noise from the audio speech
signal. It is also one of the most effective criteria for
determining the values of adaptive noise cancellation
coefficients in communication systems. The LMS
algorithm is by far the most widely used algorithm in
adaptive ltering for several reasons. The main
features that attracted the use of the LMS algorithm
are low computational complexity, proof of
convergence in stationary environment, unbiased
convergence in the mean to the Wiener solution, and
stable behavior when implemented with nite-
precision arithmetic. The convergence analysis of the
LMS presented here utilizes the independence
assumption. The minimum mean-square error in
estimating the reference signal is d (k). The optimal
(Wiener) solution is given by Wo = (R1p) where R =
E[x(k)xT(k)] and p = E[d(k)x(k)], assuming that d(k)
and x(k) are jointly wide-sense stationary. If good
estimates of matrix R, denoted by R (k), and of vector
p, denoted by p(k), are available, a steepest-descent-
based algorithm can be used to search the Wiener
solution of equation (3.1) as follows:
w(k+1)=w(k)gw(k)
= w(k)+2(p(k)R(k)w(k))
For k = 0, 1, 2... Where gw(k) represents an estimate
of the gradient vector of the objective function with
respect to the lter coefficients.
One possible solution is to estimate the gradient vector
by employing instantaneous estimates for R and p as
follows:
R(k) = x(k)xT(k)
p(k) = d(k)x(k)
The resulting gradient estimate is given by
gw(k) = 2d(k)x(k)+2x(k)xT(k)w(k)
= 2x (k) (d (k) +xT (k)w(k))
= 2e (k) x (k)
Note that if the objective function is replaced by the
instantaneous square error e2 (k), instead of the MSE,
the above gradient estimate represents the true
gradient vector since:
e2(k)w =[ 2e(k) e(k)w0(k) 2e(k) e(k)w1(k) ...
2e(k) e(k)wN(k)]
t

= 2e (k) x (k)
= = gw (k)
The resulting gradient-based algorithm is known1 as
the least-mean-square (LMS) algorithm, whose
updating equation is:
w (k + 1) = w(k)+2e(k)x(k)
Where the convergence factor should be chosen in a
range to guarantee convergence. Using the LMS
adaptive noise canceller in voice communication with
a control Bus system: The proposed method with the
DTW criterion was used for optimal settings
parameters of the LMS adaptive noise canceller,
implemented on the TMS320C6713 DSK, applied in
voice communications with the control Bus system.
The control Bus system was used in the application of
visualization operational control of the technical
functions of the building with the visualization

software promo tic. Software My Voice linked with
software Promo tic was used for the speech
recognition in voice communication with the control
Bus system. By use of the software My Voice
operational technical functions in the buildings can be
done through voice control. In voice communication
with the control Bus system were used voice
commands, for example switch on/off lights, increase
of temperature, decrease of temperature, reducing of
temperature by degree Celsius, turn on/off one boiler.

3. RECURSIVE LEAST SQUARE (RLS)
ADAPTIVE FILTER
The Recursive Least Squares (RLS) filter is a better
filter than the LMS filter, but it is not used as often as
it could be because it requires more computational
resources. The LMS filter requires 2N+1 operation per
filter update, whereas the RLS filter requires 2.5N2 +
4N.It has been successfully used in system
identification problems and in time series analysis
where its real-time performance is not an issue. The
Recursive least squares (RLS) adaptive filter is an
algorithm which recursively finds the filter
coefficients that minimize a weighted linear least
squares cost function relating to the input signals. This
is in contrast to other algorithms such as the least
mean squares (LMS) that aim to reduce the mean
square error. In the derivation of the RLS, the input
signals are considered deterministic, while for the
LMS and similar algorithm they are considered
stochastic. Compared to most of its competitors, the
RLS exhibits extremely fast convergence. However,
this benefit comes at the cost of high computational
complexity, and potentially poor tracking performance
when the filter to be estimated changes. In general, the
RLS can be used to solve any problem that be solved
by adaptive filters. For example, suppose that a signal
d (n) is transmitted over an echoic, noisy channel that
causes it to be received as
Where v (n) represents additive noise. We will attempt
to recover the desired signal d (n) by use of a p-tap
FIR filter,
Is the vector containing the p most recent samples of x
(n).Our goal is to estimate the parameters of the filter
W and at each time n we refer to the new least squares
estimate by Wn . As time evolves, we would like to
avoid completely redoing the least squares algorithm
to find the new estimate for W, in terms of Wn+1.

In the simulation the reference input signal x(n) is a
white Gaussian noise of power two-dB generated
using random function in MATLAB, the desired
signal d(n) obtained by adding a delayed version of
x(n) into clean signal s(n), d(n) = s(n) + x1(n). The
clean speech signal typically exists in a subspace of
the Input. The speech signal is a sentence that is

repeated four times. The distorted Speech & noise
signal is fed to input as original wav manually. Then
we can choose to enhance or improved results stored
in the same directory.

4. CALCULATION OF VARIOUS
PARAMETERS
4.1. SIGNAL TO NOISE RATIO
Of course, in addition to noise, the input to an
amplifier in a receiver will typically include our
desired signal. Say the power of this input signal is
Psin. The output of the amplifier will therefore include
both a signal with power Psout, and noise with power
P
n
out
. In order to accurately demodulate the signal, it is
important that signal power be large in comparison to
the noise power. Thus, a fundamental and important
measure in radio systems is the Signal-to-Noise Ratio
(SNR):
SNR=Ps/Pn
4.2. BIT ERROR RATE
The bit error function compares two sets of data and
computes the number of bit errors and the bit error
rate. The symerr function compares two sets of data
and computes the number of symbol errors and the
symbol error rate. An error is a discrepancy between
corresponding points in the two sets of data. Of the
two sets of data, typically one represents messages
entering a transmitter and the other represents
recovered messages leaving a receiver.
4.3. SIMULATION PROCEDURE
4.4.1. RUN TRANSMITTER
The first step in the simulation is to use the transmitter
to create a digitally modulated signal from a sequence
of pseudo-random bits. Once we have created this
signal, x (n), we need to make some measurements of
it.
4.4.2. ESTABLISH SNR
The signal-to-noise-ratio (SNR), Eb /N0, is usually
expressed in decibels, but we must convert decibels to
an ordinary ratio before we can make further use of
the SNR. If we set the SNR to m dB, then Eb/N0 =
10m/10. Using Matlab, we find the ratio, ebn0, from
the SNR in decibels, snrdb, as:
ebn0= 10^ (snrdb/10).
Note that Eb/N0 is a dimensionless quantity.
4.4.3. DETERMINE EB:
Energy-per-bit is the total energy of the signal, divided
by the number of bits contained in the signal. We can
also express energy-per-bit as the average signal
power 3 multiplied by the duration of one bit. Either
way, the expression for Eb is:
Eb =1 N fbi tNX
n=1 x2(n),
Where N is the total number of samples in the signal,
and fbi t is the bit rate in bits- per-second. Using
Matlab, we find the energy-per-bit, eb, of our
transmitted signal, x, that has a bit rate fb, as:
eb = sum (x. ^2)/(length(x)fb).
Since our signal, x(n), is in units of volts, the units of
Eb are Joules.
4.4.4. CALCULATE N0
With the SNR and energy-per-bit now known, we are
ready to calculate N0, the one- sided power spectral
density of the noise. All we have to do is divide Eb by
the SNR, providing we have converted the SNR from
decibels to a ratio. Using Mat lab, we find the power
spectral density of the noise, n0, given energy- per-
bit eb, and SNR ebn0, as: n0 = eb/ebn0.
The power spectral density of the noise has units of
Watts per Hertz.


4.4.5. CALCULATE N
The one-sided power spectral density of the noise, N0,
tells us how much noise power is present in a 1.0 Hz
bandwidth of the signal. In order to find the variance,
or average power, of the noise, we must know the
noise bandwidth. For a real signal, x (n), sampled at fs
Hz, the noise bandwidth will be half the sampling rate.
Therefore, we find the average power of the noise by
multiplying the power spectral density of the noise by
the noise bandwidth:
n = N0 fs 2
,where n is the noise variance in W, and N0 is the
one-sided power spectral density of the noise in W/Hz.
Using Mat lab, the average noise power, pn, of noise
having power spectral den-sity n0, and sampling
frequency fs, is calculated as: pn= n0fs/2. The
average noise power is in units of Watts.
4.4.6. GENERATE NOISE
Although the communications toolbox of Mat lab has
functions to generate additive white Gaussian noise,
we will use one of the standard built-in functions to
generate AWGN. Since the noise has a zero mean, its
power and its variance are identical. We need to
generate a noise vector that is the same length as our
signal vector x (n), and this noise vector must have
variance n W. The Mat lab function randn
generates normally distributed random numbers with a
mean of zero and a variance of one. We must scale the
output so the result has the desired variance, n. To
do this, we simply multiply the output of the randn
function by pn. We can generate the noise vector n,
as: n = sqrt (pn) randn (1, length(x)); Like the signal
vector, the samples of the noise vector have units of
volts.
4.4.7. ADD NOISE
We create a noisy signal by adding the noise vector to
the signal vector. If we are run-ning a fixed-point
simulation, we will need to scale the resulting sum by
the reciprocal of the maximum absolute value, so the
sum stays within amplitude limits of 1.0. Otherwise,
we can simply add the signal vector x to the noise
vector n to obtain the noisy signal vector y as: y =
x+n;.
4.4.8. RUN RECEIVER
Once we have created a noisy signal vector, we use the
receiver to demodulate this signal. The receiver will
produce a sequence of demodulated bits, which we
must compare to the transmitted bits, in order to
determine how many demodulated bits are in error.
4.4.9. DETERMINE OFFSET
Due to filtering and other delay-inducing operations
typical of most receivers, there will be an offset
between the received bits and the transmitted bits.
Before we can compare the two bit sequences to check
for errors, we must first determine this offset. One
way to do this is by correlating the two sequences,
then searching for the correlation peak. Suppose our
transmitted bits are stored in vector tx, and our
received bits are stored in vector rx. The received
vector should contain more bits than the transmitted
vector, since the receiver will produce (meaningless)
outputs while the filters are filling and flushing. If the
length of the transmitted bit vector is lt x, and the
length of the received vector is lrx , the range of
possible offsets is between zero and lrx lt x 1. We
can find the offset by performing a partial cross-
correlation between the two vectors. Using Matlab, we
can create a partial cross-correlation, cor, from bit
vectors tx and rx, with the following loop:
for lag= 1 : length(rx)length(tx)1,
cor (lag) = txrx (lag : length(tx)1+lag);
end. The resulting vector, cor, is a partial cross-
correlation of the transmitted and received bits, over
the possible range of lags: 0 : lrx lt x 1. We need to
find the location of the maximum value of cor, since
this will tell us the offset between the bit vectors.
Since Matlab numbers array elements as 1 : N instead
of as 0 :N1, we need to subtract one from the index
of the correlation peak. Using Matlab, we find the
correct bit offset, off, as: off= find (cor== max
(cor))1.
4.4.10. CREATE ERROR VECTOR
Once we know the offset between the transmitted and
received bit vectors, we are ready to calculate the bit
errors. For bit values of zero and one, a simple
difference will reveal bit errors. Wherever there is a
bit error, the difference between the bits will be 1,
and wherever there is not a bit error, the difference
will be zero. Using Matlab, we calculate the error
vector, err, from the transmitted bit vector, tx, and
www.ijrde.com

the received bit vector, rx, having an offset of off,
as:
err= txrx(off+1 : length(tx)+off);.
4.4.11. COUNT BIT ERRORS
The error vector, err contains non-zero elements in
the locations where there were bit errors. We need to
tally the number of non-zero elements, since this is the
total number of bit errors in this simulation. Using
Matlab, we calculate the total number of bit errors,
te, from the error vec-tor err as: te= sum (abs(err)).
4.4.12. CALCULATE BIT-ERROR
Each time we run a bit-error-rate simulation we
transmit and receive a fixed number of bits. We
determine how many of the received bits are in error,
then compute the bit-error-rate as the number of bit
errors divided by the total number of bits in the
transmitted signal. Using Matlab, we compute the bit
error-rate, ber, as:
ber= te/length (tx), where te is the total number of bit
errors, and tx is the transmitted bit vector.
4.4. CONVERGENCE SPEED:
Let the sequence {rn} converge to
difference between rn and r by en; i.e.
there exists a positive number p 1 and a constant
such that Then p is called the order of convergence of
the sequence. The constant c is called the asymptotic
error constant. If p is large, then the sequence {
converges rapidly to r. If p = 1 and
convergence is said to be linear, and c is called the rate
of convergence; If p = 2, then it is quadratic
4.5. STABILITY:
A system, including analog or digital filters, is not
stable if its output grows without bound no matter
what the input is, or even without an input but because
of initial conditions or noise. For analog systems, if
any root of the denominator of T (s) is in the right half
of the s-plane, it is unstable (as well as if there are
repeated roots on the imaginary or j w ax
shown in Figure 8.1. The methods used to design
analog filters do not generate unstable filters, but
filters that are near being unstable have initial outputs
that may be undesirable. The student will see in
Chapter 9 that digital filters are usually much more
an offset of off,
zero elements in
the locations where there were bit errors. We need to
zero elements, since this is the
of bit errors in this simulation. Using
Matlab, we calculate the total number of bit errors,
tor err as: te= sum (abs(err)).
ERROR-RATE:
rate simulation we
number of bits. We
determine how many of the received bits are in error,
rate as the number of bit
errors divided by the total number of bits in the
transmitted signal. Using Matlab, we compute the bit-
= te/length (tx), where te is the total number of bit
errors, and tx is the transmitted bit vector.
} converge to r. Denote the
i.e. en = rn - r . If
1 and a constant c 0
Then p is called the order of convergence of
the sequence. The constant c is called the asymptotic
is large, then the sequence {rn}
1 and c<1, then the
is called the rate
= 2, then it is quadratic.
A system, including analog or digital filters, is not
stable if its output grows without bound no matter
nput is, or even without an input but because
of initial conditions or noise. For analog systems, if
any root of the denominator of T (s) is in the right half
plane, it is unstable (as well as if there are
repeated roots on the imaginary or j w axis). This is
shown in Figure 8.1. The methods used to design
analog filters do not generate unstable filters, but
filters that are near being unstable have initial outputs
that may be undesirable. The student will see in
usually much more
sensitive to numerical tolerances than analog filters, as
well as sensitive to changes in the sample period T for
which it was designed. It would be nice to find a
relationship between the denominator roots of T (z)
and digital filter stability.
An analog system is unstable if its transfer function T
(s) has any root of its denominator, called poles
RH P or right half of the s-plane. Most students are
familiar with this from analog signal processing and
control systems courses. The transfer function T (s) is
a ratio of polynomials.
5. SIMULATION AND OUTPUT
5.1. FxT-RLS FILTER COEFFICIENT
5.2. RLS SPECTRUM
sue: pp- 381-387
386 | P a g e
sensitive to numerical tolerances than analog filters, as
well as sensitive to changes in the sample period T for
which it was designed. It would be nice to find a
relationship between the denominator roots of T (z)
An analog system is unstable if its transfer function T
called poles, in the
plane. Most students are
familiar with this from analog signal processing and
control systems courses. The transfer function T (s) is

RLS FILTER COEFFICIENT


5.3. FxT-RLS SNR

5.4. FxT-RLS BER

5.5. TIME SCOPE

6. CONCLUSION
In this paper we considered mainly FxT-RLS
algorithm for the removal of noise. From this
algorithm we obtain the following conclusions: This
algorithm is easy to calculate and is said to have the
best convergence speed and stability rate from the
comparison shown above. Even from the other various
parameters such as SNR and bit error rate we have
considered FxT-RLS algorithm to be the best. It is
used in all mobile applications. It is also used in the
transmissions of telephone signals at the receiver end.
REFERENCES
[1]. Sushir Kumar Dubey & Nirmal Kumar Rout- FLMS
algorithm for acoustic echo cancellation & its
comparison with LMS. At International journal of
wisdom based computing, vol1 (3), Dec 2011.
[2]. S.K.Agarwal & Raj Kumar Thenua- Simulation &
performance analysis of adaptive filter in noise
cancellation. At International journal of Eng. & Tech
Vol.2 (9), 2010.
[3]. Shadab Ahmad, Tazeem Ahmad- Implementation of
RLS adaptive filter for noise cancellation. At
International journal of Scientific Eng. & Tech, (ISSN:
2277-1581) Oct 2012.
[4]. Rohit Srivastava, Dheeraj Kumar Singh & Jwalant
Baria- Matlab implementation of Echo Cancellation
in Telephone line. At International journal of
emerging tech & advanced Engg (ISSN 2250-2459,
vol 2, Issue 10, Oct 2012)
[5]. Daisuke Ikefuji, Masato Nakayama, Takanabu
Nishiura and Yoich Yamashita- An active
unpleasantness control system for indoor noise based
on auditory masking. At Graduate School of
Information Science and Engineering, Ritsumeikan
University.
[6]. Takayuki Iriki(1), Masanori Morise(2) and Takanobu
Nishiura(2), Noise suppression method for a high-
realistic reproduction system with active noise
control. Proceedings of 20th International Congress
on Acoustics, ICA 2010 23-27 August 2010, Sydney,
Australia.
[7]. Radhika Chinaboina, D.S.Ramkiran, Habibulla Khan,
M.Usha, B.T.P.Madhav, 1K.Phani Srinivas &
1G.V.Ganesh ADAPTIVE ALGORITHMS FOR
ACOUSTIC ECHO CANCELLATION IN SPEECH
PROCESSING.



NSCT Based Multimodal Medical Image Fusion
S. Niveditha
1
, P. Mahalakshmi
2
, Florence Valencia Henry
3


ABSTRACT
Fusion imaging is one of the most accurate and
useful diagnostic techniques in medical imaging.
Although image fusion can have different purposes,
the main aim of fusion is spatial resolution
enhancement or image sharpening. This paper
proposes a new image fusion framework for
multimodal medical images, which relies on the
non-subsampled contour let transform (NSCT)
domain. The source medical images are
transformed using NSCT into low and high
frequency components. Phase congruency and
directive contrast are used for combining low and
high-frequency coefficients respectively. The fused
image is constructed by the inverse NSCT with all
composite coefficients. Experimental results and
comparative study show that the proposed fusion
framework provides an effective way to enable
more accurate analysis of multimodality images.
Keywords Image fusion, NSCT, Phase
Congruency, Sum-Modified-Laplacian, Directive
Contrast, Inverse NSCT.
I. INTRODUCTION

Fusion imaging is one of the most modern, accurate
and useful diagnostic techniques in medical imaging
today. Although image fusion can have different
purposes, the main aim of fusion is spatial resolution
enhancement or image sharpening. Also known as
integrated imaging, the benefits are even more
profound in combining anatomical imaging modalities
with functional ones. Different modalities of medical
imaging reflect different information of human organs
and tissues, and have their respective application
ranges [1-4]. A single modality of medical image
cannot provide comprehensive and accurate
information. As a result, combining anatomical and
functional medical images to provide much more
useful information through image fusion has become
the focus of imaging research and processing.
Multimodal medical image fusion not only helps in
diagnosing diseases, but it also reduces the storage cost
by reducing storage to a single fused image instead of
multiple-source images. So far, extensive work has
been made on image fusion technique with various
techniques dedicated to multimodal medical image
fusion. These techniques have been categorized into
three categories according to merging stage. These
include pixel level, feature level and decision level
fusion where medical image fusion usually employs the
pixel level fusion due to the advantage of containing
the original measured quantities, easy implementation
and computationally efficiency [5-8].

The well-known pixel level fusion is based on principal
component analysis (PCA), independent component
analysis (ICA), contrast pyramid (CP), gradient
pyramid (GP) filtering, etc. These are not the highly
suitable for medical image fusion. Wavelet transform
has been identified ideal method for image fusion.
However, it is argued that wavelet decomposition is
good at isolated discontinuities, but not good at edges
and textured region [9]. However, these methods often
produce undesirable side effects like block artifacts,
reduced contrast etc. due to the drawbacks of wavelet
transform such as lack of symmetry, critical sampling,
less vanishing moments etc.

This project is an attempt to rectify the drawbacks of
wavelet transform in image fusion. For this purpose,
non-subsampled contour let transform (NSCT) is used
in the proposed framework. NSCT has properties such
as multistate, localization, multidirectional, and shift
invariance, but only limits the signal analysis to the
time frequency domain. Two different fusion rules are
proposed for combining low and high-frequency
coefficients. For fusing the low-frequency coefficients,
the phase congruency based model is used. A new
definition of directive contrast in NSCT domain is
proposed and used to combine high-frequency
coefficients. Finally, the fused image is constructed by
the inverse NSCT with all composite coefficients.
Experimental results and comparative study show that
the proposed fusion framework provides an effective
way to enable more accurate analysis of multimodality
images. The salient contributions of the proposed

framework over existing methods can be summarized
as follows.
This paper proposes a new image fusion
framework for multimodal medical images, which
relies on the NSCT domain.
Two different fusion rules are proposed for
combining low and high-frequency coefficients.
For fusing the low-frequency coefficients, the
phase congruency based model is used. The main
benefit of phase congruency is that it selects and
combines contrast- and brightness-invariant
representation contained in the low frequency
coefficients.
On the contrary, a new definition of directive
contrast in NSCT domain is proposed and used to
combine high-frequency coefficients. Using directive
contrast, the most prominent texture and edge
information are selected from high-frequency
coefficients and combined in the fused ones.
The definition of directive contrast is
consolidated by incorporating a visual constant to the
SML based definition of directive contrast which
provides a richer representation of the contrast.

II. PRELIMINARIES
This section provides the description of concepts on
which the proposed framework is based. These
concepts include NSCT and phase congruency and
directive contrast are described as follows.

1. NON SUBSAMPLED CONTOURLET
TRANSFORM (NSCT)
NSCT, based on the theory of CT, is a kind of multi-
scale and multi-direction computation framework of
the discrete images. It can be divided into two stages
including non-subsampled pyramid (NSP) and non-
subsampled directional filter bank (NSDFB). The
former stage ensures the multiscale property by using
two channel non-subsampled filter bank, and one low-
frequency image and one high-frequency image can be
produced at each NSP decomposition level. The
subsequent NSP decomposition stages are carried out
to decompose the low-frequency component available
iteratively to capture the singularities in the image. As
a result, NSP can result in k+1 sub-images, which
consists of one low- and high-frequency images having
the same size as the source image where denotes the
number of decomposition levels.

Fig 1. Three-stage non-subsampled pyramid decomposition

Fig 2. Four-channel non-subsampled directional filter bank

Fig 1. Gives the NSP decomposition with levels. The
NSDFB is two channel non subsampled filter banks
which are constructed by combining the directional fan
filter banks. NSDFB allows the direction
decomposition with stages in high-frequency images
from NSP at each scale and produces directional sub-
images with the same size as the source image.
Therefore, the NSDFB offers the NSCT with the multi-
direction property and provides us with more precise
directional details information. A four channel NSDFB
constructed with two-channel fan filter banks is
illustrated in Fig. 2.

2. PHASE CONGRUENCY:
Phase congruency is a measure of feature perception in
the images which provides an illumination and contrast
invariant feature extraction method. This approach is
based on the Local Energy Model, which postulates
that significant features can be found at points in an
image where the Fourier components are maximally in
phase. First, logarithmic Gabor filter banks at different
discrete orientations are applied to the image and the
local amplitude and phase at a point (x,y) are obtained.

The phase congruency, P
o
x,y
is then calculated for each
orientation as P
o
x,y
shown

where W
o
z,y
is the weight factor based on the frequency
spread, A
o,n
x,y
and
o,n
x,y
are the respective amplitude
and phase for the scale n,
o
x,y
is the weighted mean
phase, is a noise threshold constant and is a small
constant to avoid divisions by zero. The symbol +
denotes that the enclosed quantity is equal to itself
when the value is positive, and zero otherwise. Only
energy values that exceed T the estimated noise
influence and are counted in the result. The appropriate
noise threshold T is readily determined from the
statistics of the filter responses to the image. The main
properties, which acted as the motivation to use phase
congruency for multimodal fusion, are as follows.
The phase congruency is invariant to different
pixel intensity mappings. The images captured with
different modalities have significantly different pixel
mappings, even if the object is same. Therefore, a
feature that is free from pixel must be preferred.
The phase congruency feature is invariant to
illumination and contrast changes. The capturing
environment of different modalities varies and results
in the change of illumination and contrast.
Phase congruency provides the improved
localization of the image features, which lead to
efficient fusion.

2.1. DIRECTIVE CONTRAST IN NSCT
DOMAIN:
The contrast feature measures the difference
of the intensity value at some pixel from the
neighboring pixels. Local contrast is developed and is
defined as

Where L is the local luminance and L
B
is the luminance
of the local background. Generally, L
B
is regarded as
local low-frequency and hence, L - L
B
= L
H
is treated as
local high-frequency. This definition is further
extended as directive contrast for multimodal image
fusion. These contrast extensions take high-frequency
as the pixel value in multiresolution domain. However,
considering single pixel is insufficient to determine
whether the pixels are from clear parts or not.
Therefore, the directive contrast is integrated with the
sum-modified- Laplacian to get more accurate salient
features.
In general, the larger absolute values of high-frequency
coefficients correspond to the sharper brightness in the
image and lead to the salient features such as edges,
lines, region boundaries, and so on. However, these are
very sensitive to the noise and therefore, the noise will
be taken as the useful information and misinterpret the
actual information in the fused images. Hence, a proper
way to select high-frequency coefficients is necessary
to ensure better information interpretation. Hence, the
sum-modified-Laplacian is integrated with the directive
contrast in NSCT domain to produce accurate salient
features.
Mathematically, the directive contrast in NSCT domain
is given by:

Where SML
l,
is the sum-modified-Laplacian of the
NSCT frequency bands at scale l and orientation . On
the other hand, IL (i, j) is the low-frequency sub-band
at the coarsest level (l). The sum-modified-Laplacian is
defined by following equation

Where

In order to accommodate for possible
variations in the size of texture elements, a variable
spacing (step) between the pixels is used to compute
partial derivatives to obtain SML and is always equal
to 1. Hence, the directive contrast in NSCT domain is
given as.

Where as a visual constant representing the slope of
the best-fitted lines through high-contrast data, which is
determined by physiological vision experiments, and it
ranges from 0.6 to 0.7. The proposed definition of
directive contrast, not only extract more useful features
from high-frequency coefficients but also effectively

deflect noise to be transferred from high-frequency
coefficients to fused coefficients.

III. PROPOSED IMAGE FUSION FRAME
WORK
Considering, two perfectly registered source images A
and B, the proposed image fusion approach consists of
the following steps:
1. Perform l-level NSCT on the source images to
obtain one low-frequency and a series of high-
frequency sub-images at each level and direction , i.e.,
A :{C
l
A
, C
A
l,
} and B:{C
l
B
, C
B
l,
}
Where C
l
*
are the low-frequency sub-images and C
*
l,

represents the high frequency sub images at level l
[1,l] in the orientation .
2. Fusion of Low-frequency Sub-images: The
coefficients in the low-frequency sub-images represent
the approximation component of the source images. A
new criterion is proposed here based on the phase
congruency. The complete process is described as
follows.
a. First, the features are extracted from low-
frequency sub-images using the phase congruency
extractor, denoted by PC
l
A
and PC
l
B
respectively.
b. Fuse the low frequency sub-images as

3. Fusion of High-frequency Sub-images: The
coefficients in the high-frequency sub-images usually
include details component of the source image. Noise
is also related to high-frequencies and may cause
miscalculation of sharpness value and therefore affect
the fusion performance. Therefore, a new criterion is
proposed here based on directive contrast. The whole
process is described as follows.
a. First, the directive contrast for NSCT high-
frequency sub-images at each scale is obtained and
denoted by and at each level l [1, l] in
the direction .
b. Fuse the high-frequency sub-images as

4. Perform l-level inverse NSCT on the fused
low-frequency (C
F
l
) and high frequency (C
F
l,
)
subimages, to get the fused image (F).


Some general requirements for fusion algorithm are:
It should be able to extract complimentary
features from input images,
It must not introduce artifacts or
inconsistencies according to Human Visual System
It should be robust and reliable. Generally,
these can be evaluated subjectively or objectively.
IMAGE DATA SET 1:

Fig 3. Image data set 1

RMSE = 0.0516
The psnr performance w.r.t. MRI is 33.88 dB
RMSE = 0.0211
The psnr performance w.r.t. CT is 41.66 dB

Fig 4. MR-CT Data Set



Fig 5. Other transformation methods

Fig 6. NSCT fused image

From figure and table, it is clear that the proposed
algorithm not only preserves spectral information but
also improve the spatial detail information than the
existing algorithms, which can also be justified by the
obtained maximum values of evaluation indices. The
PCA algorithm gives baseline results. PCA based
methods give poor results relative to other algorithms.
This was expected because this method has no scale
selectivity therefore it cannot capture prominent
information localized in different scales. This
limitation is rectified in pyramid and multiresolution
based algorithms but on the cost of quality i.e., the
contrast of the fuse image is reduced which is greater in
pyramid based algorithms and comparatively less in
multiresolution based algorithms.
Among multiresolution based algorithms, the
algorithms based on NSCT performs better. This is due
to the fact that NSCT is an multi-scale geometric
analysis tool which utilizes the geometric regularity in
the image and provide asymptotic optimal
representation in the terms of better localization,multi-
direction and shift invariance. This is also justified by
the fact that shift-invariant decomposition overcomes
pseudo-Gibbs phenomena successfully and improves
the quality of the fused image around edges.
The main reason behind the better performance is the
proposed fusion rules for low- and high-frequency
coefficients which extract all prominent information
from the images and provide more natural output with
increased visual quality. Therefore, it can be concluded
that both the visual and statistical evaluation proves the
superiority of the proposed method over existing
methods.

V. CONCLUSION
In the project, a novel image fusion framework is
proposed for multi-modal medical images, which is
based on non-subsampled contourlet transform and
directive contrast. For fusion, two different rules are
used by which more information can be preserved in
the fused image with improved quality. The low
frequency bands are fused by considering phase
congruency whereas directive contrast is adopted as the
fusion method for high-frequency bands. Three groups
of CT/MRI images are fused the proposed framework.
The visual and statistical comparisons demonstrate that
the proposed algorithm can enhance the details of the
fused image, and can improve the visual effect with
much less information distortion than its competitors.
These statistical assessment findings agree with the
visual assessment.

REFERENCES
[1] F. Maes, D. Vandermeulen, and P. Suetens,
Medical image registration using mutual information, Proc.
IEEE, vol. 91, no. 10, pp. 16991721, Oct. 2003.
[2] G. Bhatnagar, Q. M. J. Wu, and B. Raman, Real
time human visual system based framework for image
fusion, in Proc. Int. Conf. Signal and Image Processing,
Trois-Rivieres, Quebec, Canada, 2010, pp. 7178.
[3] Cardinali and G. P. Nason, A statistical multiscale
approach to image segmentation and fusion, in Proc. Int.
Conf. Information Fusion, Philadelphia, PA, USA, 2005, pp.
475482.
[4] P. S. Chavez and A. Y. Kwarteng, Extracting
spectral contrast in Landsat thematic mapper image data
using selective principal component analysis,
Photogrammetric Eng. Remote Sens., vol. 55, pp. 339348,
1989.
[5] Toet, L. V. Ruyven, and J. Velaton, Merging
thermal and visual images by a contrast pyramid, Opt. Eng.,
vol. 28, no. 7, pp. 789792, 1989.
[6] http://www.mathworks.in/products/matlab/descripti
on1.html
[7] H. Li, B. S. Manjunath, and S. K. Mitra,
Multisensor image fusion using the wavelet transform,


Graph Models Image Process., vol. 57, no. 3, pp. 235245,
1995.
[8] A. Toet, Hierarchical image fusion, Mach. Vision
Appl., vol. 3, no.1, pp. 111, 1990.
[9] X. Qu, J. Yan, H. Xiao, and Z. Zhu, Image fusion
algorithm based on spatial frequency-motivated pulse
coupled neural networks in nonsubsampled contourlet
transform domain, Acta Automatica Sinica, vol. 34, no. 12,
pp. 15081514, 2008.



Power Quality Improvement by Suppressing Harmonics
Using a Current Source Converter Based Active Power
Filters
Amudha.A
1
, Ancy beril.J
2
, Rajeswari.D
3


ABSTRACT
The new approach for the design of current-
source converter (CSC)-based shunt active
power filters (APFs) to suppress the
amplification of lower order harmonics in
distribution system. This is called as the
selective harmonic amplification method
(SHAM), and is based on the amplification of
some selected harmonic current components of
CSC by the LC filter, and the control scheme of
CSC is specially designed in this paper. Four
CSC based APF modules was designed are
operated in parallel, and connected to the bus
via a specially designed ideal transformer. The
APF module is specially designed LC-type input
filter eliminates the switching frequency ripples,
and active damping method is used to control
software suppresses harmonic frequencies
around the corner frequency of the input filter.
The inner current control loop is used to
generate step pulse-width modulation signal to
operate the each apf module of current source
converter, Phase Locked Loop is used to control
the angle of vector orientation of a source
current which cancels the effect of harmonics in
the distribution network. Shunt active power
filter is implemented successfully for harmonic
and current distribution compensation of the
three phase three wire line at distribution
system. The resulting system can operate to
relatively high frequencies, depending upon
which selected harmonics of 5th, 7th, 11th, and
13th are to be eliminated. The simulation
analysis results are carried out in
MATLAB/SIMULINK model. Simulation and
field test results has shown that SHAM can
successfully implemented for a CSC-based APF
for reduction of the lower order current
harmonics rating, thus making it a cost-effective
than voltage-source-converter-based APFs are
used in industries.
Keywords: Active Power Filter, Current Source
Converter, Harmonic Current, Power Quality
(PQ), SHAM.
1. INTRODUCTION
The objective of the electric utility is to deliver
sinusoidal voltage at fairly constant magnitude
throughout the system. This objective is
complicated by the fact that there are non-linear
load on the system that produce harmonic currents.
These current resulted in distorted voltages and
currents that can adversely impact the system
performance. The paper present the utilities and the
operators have designed the codes and regulations
in order to ensure quality of the electrical power in
transmission and distribution network. The flow of
reactive power in O/H lines and feeders should be
kept under control. For an example, tight gird
codes regulations have been imposed on customers
and distribution companies. If these limits are
exceeded, the operators penalizes its customer for
the total amount of reactive energy consumed (the
unit price of reactive energy is nearly half of the
unit price of active energy). However, this is not
applicable for the case of harmonics and other PQ
parameters. Therefore, the industrial and
customers pay their attention to the power factor
correction by installing capacitors to their facilities.
In case, the customers are using a tuned or de-tuned
shunt harmonic filters (HF) are fed with current
overloading problems, resulted the flow of
harmonic currents generated by neighbouring
customer and industrial plant to their HF
installations.
To cope with these problems, Active power filters
(APF) is widely used for power quality and custom
power problems in the distribution system due to
non-linear loads [1]. Continuing proliferation of
non-linear loads such as rectifiers, variable speed
drives, SMPS, and UPS are producing harmonic
pollution in the power distribution grid [2]. The
presence of harmonic current in the system results
in several causes such as heating losses in
transformers, low power factor, and this affects the
neighbouring customers load at point of common
coupling (PCC) [3],[4] . Traditionally, these
problems were solved by passive LC filters. But in

case of commercial usage, passive filters persists
its inability to compensate random frequency
variation in current, tuning problem and parallel
resonance [5]. Different configurations of static
VAR compensators (SVCs) have been proposed to
solve these problems. Disastrously, SVCs generate
lower-order harmonics themselves and the response
time of SVC systems may be too long to be
acceptable for frequently fluctuating loads [6]. The
APF is a suitable mitigation for solving fluctuating
harmonic compensation. The current source
converter with APF is configured using PWM-
based voltage source inverters (VSI) owing to its
cost, lightweight, and expandability toward
multilevel version to improve high-power rating
compensation with lower switching frequencies
[7]. The shunt APF enhances different choice of
compensation such as current harmonic
attenuation, load balancing, and displacement
power factor correction [8]. This APF is a current
controlled device and hence the amplitude and
wave shape of the current supplied by the active
power filter.
The majority of shunt APFs are based on voltage
source converters (VSCs) with capacitors with a dc
link, and are considered for connection to low
voltage buses [9], [10]. Although various aspects
of current-source converter (CSC)-based and shunt
APFs with a inductor in the dc link have been
examined in [11]CSC-based APFs are compared
with VSC-based APFs theoretically and on small-
scale laboratory prototypes in [12] and [13] to
obtain higher efficiency and reliability figures.
2. ACTIVE POWER FILTER
The circuit diagram of each CSC based APF
module is as given in Fig.1. DC-link current, Idc of
each CSC is kept constant over the entire operating
range. DC-link current is chopped by IGBTs of
CSC in order to create the selected current
harmonic components by PWM signal. The
fundamental current generation is to allow required
amount of active power flow from the interface bus
in order to compensate the losses in CSC with APF
and hence the DC-line current is maintained
constant. The current waveform of the CSC based
APF on its AC side is created by the Modified
Dead-Band Sinusoidal PWM technique [16]. The
input filter of the APF described in this paper is
carefully designed to suppress satisfactorily the 5th
harmonic current component in the transmission
lines.

Fig.1 Circuit diagram of each CSC based APF module
As proven in this paper, the controlled
amplification of the selected harmonic current
components reduces the installed kVA capacity of
CSC significantly in comparison with the
traditional ac-side filter design approach. This
paper also describes the application of the proposed
CSC-based APF to a MV power system via a
coupling transformer, to validate the effectiveness
of the SHAM in reducing the CSC kVA rating.

3. SELECTIVE HARMONIC
AMPLIFICATION METHOD

Harmonic current characteristics of the load should
be obtained by means of at least one week
continuous measurements in accordance with IEC
61000-4-30 [24] prior to the design of the APF.
The results of these measurements should then be
investigated carefully in order to determine which
harmonic components do not comply with IEEE
Std. 519, and whether elimination of these
harmonics in the load current waveforms could
satisfy TDD limit, or not. The result of this study
will help to determine the harmonic components to
be eliminated by APF, their maximum magnitudes
and hence the kVA rating of the APF installation.
As an example, if 11th and 13th harmonic current
components of the load have maximum amplitudes
of and amps-rms on the MV side, then a kVA
rating of APF can be calculated by using:

Where is the rms value of the line-to-line
fundamental voltage at the input of the coupling
transformer, and is the fundamental current drawn
by the APF from the supply which corresponds to
transformer and CSC losses.



Fig.2 Block diagram representation of the control system
for each APF module
If the system is partly dedicated to reactive power
compensation in D-STATCOM mode in addition to
major action of active power filter, the generation
of reactive current in the circuit should be included.
Theoretically, and generated by the APF would be
equal in magnitude to 11th and 13th harmonic
current components of nonlinear load(s), but in
anti-phase.

3.1. INPUT FILTER VDESGIN

Fig. 2 shows the harmonic equivalent circuit of the
overall system. Since all currents and voltages are
harmonic components excluding the fundamental,
is shown to be short circuited in Fig. 1. And in Fig.
2 are harmonic components of supply current, load
current, APF current, CSC current, and ac-side
filter capacitor voltage, respectively. The nonlinear
load injects harmonic currents into the supply. As
an example, let 11th and 13th current harmonics be
the dominant harmonics of the nonlinear load,
thereby an ideal APF should generate 11th and
13th harmonics of the same magnitude but in anti-
phase with the load harmonics. This is achieved
first by generating 11th and 13th harmonics in with
magnitudes lower than those needed for ideal
harmonic cancellation, and then rising them to the
required levels by using the inherent amplification
property of the ac-side filter. In other words,
selected harmonic currents of APF are higher in
magnitude than those produced by VSC with APF


4.1. CSC WITHOUT APF
This section represents the simulation result of a
nonlinear load before connecting Active Power
Filter by using MATLAB/SIMULINK.

Fig.4 Source current of CSC without APF module

Fig.5 Load current of CSC without APF module

Fig.6Harmonic spectrum of the source current (THD=
28.54)
4.2. CSC WITH APF
To get a balanced and sinusoidal source current and
lower switching frequency should maintained by
using APF module based current source converter
circuit. The Harmonics are eliminated in source
line current.

Fig.7 Source current of CSC with APF module

Fig.8 Load current of CSC with APF module



Fig.9Harmonic spectrum of the source current (THD=
0.154)

From fig 6 and 9 shows the FFT analysis of source
harmonic elimination in csc based apf and order of
harmonics of 5th, 7th, 11th and 13
th
level.

5. CONCLUSION
In this work, CSC based APF is connected at the
interface bus between the source and the load, has
been proposed as a permanent solution to the
harmonic resonance. Relatively low installed kVA
capacity can be used by choosing a CSC with APF
rather than a VSC based APF more efficient. The
Selective Harmonic Amplification Method is used
to selected harmonics of 5th, 7th, 11th, and 13th
are to be mitigated and THD level is maintained
within the harmonic limits was discussed from the
result.
REFERENCE
[1]. Arrillaga. J, Watson. N.R, "Power System
Harmonics," 2nd Ed., Wiley, 2004.
[2]. Inzunza. R, Akagi. H, "A 6.6 kV Transformerlerss
Shunt Hybrid ActiveFilter for Installation on a
Power Distribution System, "35th IEEE Annual
Power Elect. Spec. Conf., pp. 4630-4636, 2004.
[3]. Jintakosonwit. P, Akagi. H, Fujita. H, Ogasawara.
S, "Implementationand performance of automatic
gain adjustment in a shunt active filter forharmonic
damping throughout a power distribution system,"
IEEE Trans. on Power Elect., vol. 17, no.3, pp.
438-447, May 2002.
[4]. Kawaguchi. I, Ikeda. H, Kitano. J. I, Ogihara. Y,
Syogaki.M, Morita. H, "Novel active filter system
composed of inverter bypass circuit for
suppression of harmonic resonance at the
Yamanashi Maglev test line, " Proc. of IEEE Power
Conversion Conf., vol.1, pp. 175-180, 1997.
[5]. Shen. D, Lehn. P. W, "Modelling, Analysis, and
Control of a Current Source Inverter-Based
STATCOM", IEEE Trans. on Power Delivery,
vol.17, pp. 248-253, Jan. 2002.
[6]. Terciyanli. A, "Design and Implementation of a
Current Source Converter Based Active Filter for
Medium Voltage Applications," Ph.D. Dissertation,
Middle East Technical University, March, 2010.
[7]. IEEE Tutorial on Harmonics Modeling and
Simulation, IEEE PowerEng.Society, 1998.
[8]. National Instruments Multisim Spice Simulator,
Analog Devices Edition, 2009.



Substation Automation with Disturbance Recording Using
Power Line Carrier Communication

GAYATHRI.T
1
, PRABA. D.R
2
, DEVI.M
3
ABSTRACT
This project presents the development of a
power line carrier in substation distribution
automation system (DAS) for controlling the
substation downstream [5]. Supervisory Control
and Data Acquisition (SCADA) based Remote
Terminal Unit (RTU) along power line
communication (PLC) system are used for DAS
development that practically simulates the
downstream distribution system functions in an
automated manner. It is the first DAS research
work done on customer side substation for
operating and controlling between the consumer
side system and the substation using PLC. Most
of the work in this project is focused on PLC
that provides an effective communication system
for both RTU and SCADA systems. The Human
Machine Interface for SCADA system is
developed using customized software and an
RTU microprocessor and its software
implements.This project also employs the use of
disturbance recorder and event logger.
Disturbance recorder records the abnormal
condition and the event logger records the
events collected during the normal operation.
1. INTRODUCTION
Different communication technologies are being
used for the transmission of information from one
end to another depending on the feasibility and
needs [2]. Some include Ethernet cables, fiber
optics, wireless transmission, satellite transmission,
etc. A vast amount of information travels through
the entire earth every day and it creates an essential
need for a transmission medium that is not only fast
but economically reasonable as well. One of the
technologies that fit in the above stated criteria is
PLCC.PLCC, Power Line Carrier Communication,
is an approach to utilize the existing power lines for
the transmission of information. In todays world
every house and building has properly installed
electricity lines and the transmission lines.By using
the existing AC power lines as a medium to
transfer the information, it becomes easy to connect
the houses with a high speed network access point
without installing new wirings.This technology has
been in wide use since 1950 and was mainly used
by the grid stations to transmit information at high
speed. Now a days this technology is finding wide
use in building/home automation as it avoids the
need of extra wiring. The data collected from
different sensors is transmitted on these power lines
thereby also reducing the maintenance cost of the
additional wiring. In some countries this
technology is also used to provide Internet
connection.
2. CIRCUIT DESCRIPTION
The communication device used for the
communication over the power line is a MODEM,
commonly known as Power Line MODEM (PLM).
It works as both transmitter and receiver, i.e., it
transmits and receives data over the power lines. A
power line modem not only modulates the data to
transmit it over the power lines and but also
demodulates the data it receives from the power
lines. By using modulation techniques, binary data
stream is keyed on to a carrier signal and then
coupled on to the power lines by PLM. At the
receiver end another PLM detects the signal and
extracts the corresponding bit stream.

Fig, 1Working of PLCC System
www.ijrde.com


Data is processed before transmission on power
lines. First data is modulated & filtered and then by
using couplers, it is sent over the power lines.
2.1. PLC MODEMS/TRANSCEIVERS
PLC Transceiver is the key component of a PLCC
system. It is the device which transmits & receives
data to & from the power lines and acts as a hub
between the power stations and our
Computers/Network utilization devices. They are
wired with the electrical voltage lines at home or
business and work on two modes transmit mo
and receive mode. In transmit mode, they simply
receive data from receiver end installed on the
same network and further transmit them. In receive
mode, they work the opposite way.
3. MODULATION TECHNIQUES
PLCC needs a technique that can deal with the
unpredictable attenuation and phase
shifts. Modulation techniques that operate at lower
frequency ranges of 35 KHz to 95 KHz can
perform better as compared to the ones using the
whole available frequency band.
(Orthogonal Frequency Division Multiplexi
the modulation technique that is used in HomePlug
specification network appliances. In OFDM,
information is modulated on to multiple carriers
where each carrier occupies its own frequency in
the range of 4.3 to 20.9 MHz Incoming bit stream
is demultiplexed into N number of parallel bit
streams each with 1/N of original bit rate which are
then modulated on N orthogonal carriers. By using
multiple carriers at a time, the modulation
technique uses the available spectrum most
efficiently. During the transmission, each

Data is processed before transmission on power
. First data is modulated & filtered and then by
using couplers, it is sent over the power lines.
ERS
PLC Transceiver is the key component of a PLCC
e which transmits & receives
data to & from the power lines and acts as a hub
between the power stations and our
Computers/Network utilization devices. They are
wired with the electrical voltage lines at home or
transmit mode
and receive mode. In transmit mode, they simply
receive data from receiver end installed on the
same network and further transmit them. In receive
MODULATION TECHNIQUES
PLCC needs a technique that can deal with the
unpredictable attenuation and phase
Modulation techniques that operate at lower
frequency ranges of 35 KHz to 95 KHz can
perform better as compared to the ones using the
whole available frequency band. OFDM
Orthogonal Frequency Division Multiplexing) is
the modulation technique that is used in HomePlug
specification network appliances. In OFDM,
information is modulated on to multiple carriers,
where each carrier occupies its own frequency in
Incoming bit stream
tiplexed into N number of parallel bit
streams each with 1/N of original bit rate which are
then modulated on N orthogonal carriers. By using
multiple carriers at a time, the modulation
technique uses the available spectrum most
nsmission, each
frequency is monitored and if any interference,
noise or data loss occurs, the responsible frequency
is removed. However this technique does not
perform well when a large attenuation and jamming
occurs in the communication channel, but stil
can be very efficient comparatively.
3.1. HOW SIGNALS ARE SUPE
ON POWER LINES
There are two different ways by which we can
connect a PLC unit with the power lines
capacitive coupling and inductive coupling
capacitive coupling, a capacitor
superimpose the modulated signal on to the
networks voltage waveform. Another way is
inductive coupling which employs an inductor to
couple the signal with the networks waveform.
3.2. POWER- LINE CARRIER
COMMUNICATION
Power-line carrier communication
carries data on a conductor that is also used
simultaneously for AC electric power transmission
or electric power distribution [2] to consumers. It is
also known as power-line carrier, power
subscriber line (PDSL), mains communication
power-line telecommunications, or
networking (PLN).
3.3. PLCC MODEM
The PLCC Modem is a dedicated device for
transferring data over low voltage
convenient as it eliminates the need to lay
additional cables. The modem at the transmission
end modulates the signal from data terminal
through RS-232 interface onto the carrier signal in
the power line. At the receiving end, the modem
recovers the data from the power line carrier signal
by demodulation and sends the data to data
terminals through RS-232 interface.
3.4. DISTURBANCE RECORDER
Disturbance recorders are intended to be used for
verifying the proper operation of protection relays
and circuit breakers and for analyzing
problems in electrical power systems. The
disturbance recorder captures the curve forms of
the monitored quantities of the supervised object,
both under normal service conditions and when the
protection relay operates. Thus the relay settings
can be based on the recorded information.
sue: pp- 398-402
399 | P a g e
frequency is monitored and if any interference,
noise or data loss occurs, the responsible frequency
is removed. However this technique does not
perform well when a large attenuation and jamming
occurs in the communication channel, but still it
can be very efficient comparatively.
HOW SIGNALS ARE SUPERIMPOSED
There are two different ways by which we can
connect a PLC unit with the power lines
inductive coupling. In
capacitive coupling, a capacitor is used to
superimpose the modulated signal on to the
networks voltage waveform. Another way is
inductive coupling which employs an inductor to
couple the signal with the networks waveform.
communication (PLCC) [7]
carries data on a conductor that is also used
power transmission
to consumers. It is
power-line digital
mains communication,
, or power-line
The PLCC Modem is a dedicated device for
power line. It is
convenient as it eliminates the need to lay
additional cables. The modem at the transmission
end modulates the signal from data terminal
232 interface onto the carrier signal in
the power line. At the receiving end, the modem
recovers the data from the power line carrier signal
by demodulation and sends the data to data
232 interface.
DISTURBANCE RECORDER
isturbance recorders are intended to be used for
verifying the proper operation of protection relays
analyzing protection
problems in electrical power systems. The
disturbance recorder captures the curve forms of
the monitored quantities of the supervised object,
both under normal service conditions and when the
protection relay operates. Thus the relay settings
an be based on the recorded information.


There are typically four types of disturbance or
event records of interest to a protection engineer.
These are categorized by the event duration as
follows:
1. Transient - These are very short in duration and
typically include faults that are cleared immediately
by circuit breaker operation. These events are
generally no longer than 8 cycles for high speed
clearing and 16 cycles for sequential line clearing.
These events are usually analyzed to determine
correct protection operation, fault location, or
verification of system model parameters.
2. Short Term - These generally include all other
time-delayed fault clearing and reclosing events
where the system operation (stability) is not
affected. These events are typically 20 to 60 cycles
in length but may be longer if multiple protection
operations are required to clear the fault. These
events are usually analyzed to determine correct
protection operation, fault location or verification
of system model parameters.
3. Long Term- These include those events that
affect system stability such as power swings,
frequency variations and abnormal voltage
problems. These events are usually analyzed to
determine causes of incorrect system operations.
Data management techniques [5] are employed to
process a number of samples and record the value
for the parameter of interest. Record length
parameters may be defined.
4. Steady State - There are steady state disturbances
where system operation is not threatened, but
power quality is affected. This may include
harmonics or sub-harmonics produced by the load
and/or the interaction between power systems
components. Depending upon the type of
phenomena being analyzed, higher sample rates
may be required to capture the events and data of
interest. Record length parameters may be defined.
3.5. DESCRIPTION FUNCTIONS

- Disturbance recorder
- Disturbance recorder + Fault recorder
Recording Functions
- Recording triggered on:
Analog channels (threshold, gradient,
harmonic contents).
Calculated frequency (threshold, gradient).
Calculated positive sequence (threshold,
gradient).
Calculated negative sequence (threshold,
gradient).
Calculated zero sequence (threshold).
Digital channels (triggered on leading /
trailing edge).
Other: external pickup, keypad,
communications.
- Sampling frequency (selectable from 16 to 384
samples / cycle).
- Metering accuracy: less than 0.1%.
- Analog inputs: 8 and 16 AI.
- Digital inputs: 16 and 32 DI.
- Digital outputs: 8DO.
- Connection to portable recording storage device.
- Control and monitoring: Alphanumeric display
and Keyboard..
- Communications ports (local):
One (1) port RS232
One (1) port USB (removable disk connection).
- Communications ports (remote 1):
One (1) port RS232 (Full Modem).
One (1) port F.O.
One (1) port RS232.
One (1) port RS485.
One (1) port F.O.
One (1) Ethernet 10/100 base T, RJ45.
One (1) port USB (printer output).
One (1) port BNC (IRIG-B connection).
One (1) port NMEA (synchronism input).
One (1) port F.O, for relay synchronization
(Cross-Trigger).
- Communications protocols: Procome 3.0.
- LEDs.
- Time synchronization.
- Event and metering history records.
- Oscillographic record (COMTRADE 99 format).
- ZiverComPlus communications software.
Extreme digital fault recorder and power generation
monitor with multifunctional capabilities contained
in one device:
Digital fault recorder (DFR)
Dynamic system monitor (DSM)
Dynamic Monitoring Equipment (DME)
Dynamic Disturbance Recorder (DDR)
Continuous recorder (CR)
Class A power quality meter (PQ)
Phasor measurement unit (PMU)
www.ijrde.com


Impedance-based fault location
Sequence of events type display
and sequential of events integration with
Qualitrol SER 4100 alarm and events
monitor
Full NERC compliance
3.6. APPLICATIONS
Event detection and location, Visualization
Oscillation detection, Inter area Oscillation Modal
Analysis.
3.7. EVENT LOGGER
When using a front connected pc or substation
monitoring system an event list is available for
each of recorded disturbances in disturbance
recorder. Each list contains up to 150 time tagged
events .This list is a useful instrument for
evaluating a fault and is a complement to
disturbance recorder. When one trigger condition is
activated in disturbance recorder, the events are
collected by main processing unit from 48 selected
binary signals. The events are collected during the
total recoding time and stored in distu
recorder memory at end of each recording. Normal
operation time is also recorded.
4. SIMULATION AND RESULTS
The proposed system simulation results for the
disturbance recorder which records the abnormal
conditions and the event logger which records the
events during the normal operation are obtained.
The graph for the disturbance recorder and event
logger is being displayed in this chapter. The input
and output voltage, current values of both the
incoming and outgoing feeders are also being
displayed.
5.1. SOFTWARE USED
Visual basic
5.2. THE OVERALL SIMULATION
PLATFORM
based fault location (FL)
Sequence of events type display (SOE)
and sequential of events integration with
Qualitrol SER 4100 alarm and events
Visualization,
Inter area Oscillation Modal
a front connected pc or substation
monitoring system an event list is available for
each of recorded disturbances in disturbance
recorder. Each list contains up to 150 time tagged
events .This list is a useful instrument for
mplement to
disturbance recorder. When one trigger condition is
activated in disturbance recorder, the events are
collected by main processing unit from 48 selected
binary signals. The events are collected during the
total recoding time and stored in disturbance
recorder memory at end of each recording. Normal
SIMULATION AND RESULTS
The proposed system simulation results for the
disturbance recorder which records the abnormal
conditions and the event logger which records the
events during the normal operation are obtained.
The graph for the disturbance recorder and event
logger is being displayed in this chapter. The input
and output voltage, current values of both the
incoming and outgoing feeders are also being
THE OVERALL SIMULATION
5.3. SIMULATION RESULTS
The simulation results are being discussed into
three cases:
Case 1: Input and Output Details
Case 2: Disturbance Recording
Case 3: Event Logger
5.3.1. CASE 1: INPUT AND OUTPUT
DETAILS
The incoming and outgoing voltage & current
values of the incoming and outgoing feeders are
being displayed.
Input voltage: 232 V
Input current: 108mA
Out1 voltage: 232V
Out1 current: 0mA
Out2 voltage: 232V
Out2 current: 98mA
Fig. 4Input and Output values
5.3.1. CASE 2: DISTURBANCE RECORDING
The disturbances i.e. the abnormal conditions are
being displayed in the form of graph for both
voltage and current which is shown. Disturbance
Recorder contains the collection of system data and
at occurrence of a fault, storing of certain amount
of pre-fault and post fault data.
sue: pp- 398-402
401 | P a g e

The simulation results are being discussed into
OUTPUT
The incoming and outgoing voltage & current
values of the incoming and outgoing feeders are

CASE 2: DISTURBANCE RECORDING
the abnormal conditions are
being displayed in the form of graph for both
voltage and current which is shown. Disturbance
Recorder contains the collection of system data and
at occurrence of a fault, storing of certain amount
www.ijrde.com


Fig. 5 Disturbance Recording
5.3.2. CASE 3: EVENT LOGGER
The event logger displays the disturbances and
events took place with date and time in excel sheet
which is shown. The event logger contains an event
list with time tagged events. In station monitoring
system this list is directly connected to a
disturbance.
Fig. 6 Event Logger
Fig. 7 Overall Simulated Output View
The overall simulated output view of the propose
system which displays the disturbances of voltage
and current in a graph and the values of voltage
current of both the incoming and outgoing feeders
are also shown. It also opens the excel sheet which
has the database of disturbance recording and the
event logger.
5. CONCLUSION
In this project we have studied the basics of pow
line carrier communication, its transmission and
reception. In the existing method of reading
analysis the individual person is recommended to
go to a particular place in order to note down the
units of power used whereas in our project a meter

The event logger displays the disturbances and
events took place with date and time in excel sheet
. The event logger contains an event
list with time tagged events. In station monitoring
system this list is directly connected to a

The overall simulated output view of the proposed
which displays the disturbances of voltage
of voltage and
current of both the incoming and outgoing feeders
are also shown. It also opens the excel sheet which
has the database of disturbance recording and the
CONCLUSION
In this project we have studied the basics of power
line carrier communication, its transmission and
reception. In the existing method of reading
analysis the individual person is recommended to
rticular place in order to note down the
units of power used whereas in our project a meter
placed at a central station is sufficient to gather the
overall power consumption. Since no additional
cable installation is required, the transmission and
reception of power and data becomes easier. Here
we are measuring the current, voltage, power and
frequency separately. And also fault detection and
isolation is done.Disturbance recorder records the
abnormal condition and the event logger records
the events collected during the normal operation.
PLCC is used for active distribution network
(distributed local generation and storage) where
integrated communications is also made possible.
Distributed operation and control becomes more
flexible and robust.
REFERENCES
[1]. Archnet, Embedded Power Line
available online:
http://www.archnetco.com/english/product/ATL90.
htm.
[2]. CIRED, Distribution Utility Telecommunication
Interfaces, Protocols and Architectures
Report of the CIRED Working Group
September 2003. pp.52
[3]. Customized Non-interruptible Distribution
Automation System, Short Term Project No.
PJP/2006/FKE (1),UTeM, 2005-2006
[4]. K Dostert, 1997, Telecommunications over the
Power Distribution Grid- Possibilities and
Limitations Proc 1997 Internat.Symp. On Power
Line Comms and its Applications pp1
[5]. Intelligent Distribution Automation System:
Customized SCADA Based RtuFor Distribution
Automation System, M.Sc. Research Project,
UTeM, 2005-2007.
[6]. K.W. Louie, A. Wang, P.Wilson, and P.Buchanan,
Discussion on Power Line Carrier Applications
Manitoba HVDC Research Centre, IEEE, 2006,
pp.655
[7]. K.W. Louie, A. Wang, P.Wilson, and P.Buchanan,
Discussion on Power Line Carrier Applications
pp.656
sue: pp- 398-402
402 | P a g e
placed at a central station is sufficient to gather the
overall power consumption. Since no additional
cable installation is required, the transmission and
n of power and data becomes easier. Here
we are measuring the current, voltage, power and
frequency separately. And also fault detection and
Disturbance recorder records the
abnormal condition and the event logger records
cted during the normal operation.
PLCC is used for active distribution network [2]
(distributed local generation and storage) where
integrated communications is also made possible.
Distributed operation and control becomes more
Embedded Power Line Carrier Modem,
http://www.archnetco.com/english/product/ATL90.
Distribution Utility Telecommunication
Interfaces, Protocols and Architectures, Final
Report of the CIRED Working Group WG06,
interruptible Distribution
, Short Term Project No.
2006
Telecommunications over the
Possibilities and
nternat.Symp. On Power
Line Comms and its Applications pp1-9
Intelligent Distribution Automation System:
Customized SCADA Based RtuFor Distribution
, M.Sc. Research Project,
K.W. Louie, A. Wang, P.Wilson, and P.Buchanan,
Discussion on Power Line Carrier Applications,
K.W. Louie, A. Wang, P.Wilson, and P.Buchanan,
Discussion on Power Line Carrier Applications,


Tracking Of Maximum Power Point for a Photovoltaic Cell
Using Fuzzy Logic
M.HARILAKSHMI
1
, P.V.JEEVETHA
2
, S.KRITHIKA
3

1,2,3

ABSTRACT
To meet the future energy requirement and to
give quality and pollution free supply to growing
and environment conscious population, the
present world is giving special attention to
natural, clean and renewable energy sources.
Due to growing demand for electrical energy
and environmental issues such as pollution and
global warming effect, solar energy is considered
among one of the best options for generating
clean energy. Maximum power point tracking
(MPPT) techniques are employed in
photovoltaic (PV) systems to maximize the PV
array output power which depends on solar
irradiance and temperature. Among all the
MPPT strategies, the P&O method in Maximum
Power Point Tracking algorithm is mostly used,
due to its ease of implementation. On the other
hand, its main drawbacks are the waste of
energy in steady state conditions, when the
working point moves across the MPP and the
poor dynamic performances exhibited when a
step change in solar irradiance or in
temperature occurs. Compared with the
conventional fixed step size method, the
proposed approach can effectively improve the
MPPT speed and efficiency simultaneously.
Maximum power point tracking is a technique
that grid inverters, solar battery chargers and
similar devices to get the maximum possible
power from one or more photovoltaic cells,
typically solar panels and also from any
environmental conditions. In this paper a fuzzy
logic controller (FLC) is used as an intelligent
method for Maximum Power Point Tracking
(MPPT) for a Photo Voltaic (PV) system.
1. INTRODUCTION
One of the major concerns in the power sector is the
day-to-day increasing power demand but the
unavailability of enough resources to meet the power
demand using the conventional energy sources.
Demand has increased for renewable sources of
energy to be utilized along with conventional systems
to meet the energy demand.
Solar energy is abundantly available that has made it
possible to harvest it and utilize it properly. Solar
energy can be a standalone generating unit or can be
a grid connected generating unit depending on the
availability of a grid nearby [1-5]. Thus it can be
used to power rural areas where the availability of
grids is very low. Another advantage of using solar
energy is the portable operation whenever wherever
necessary.
In order to tackle the present energy crisis one has to
develop an efficient manner in which power has to
be extracted from the incoming solar radiation. The
power conversion mechanisms have been greatly
reduced in size in the past few years. The
development in power electronics and material
science has helped engineers to come up very small
but powerful systems to withstand the high power
demand. But the disadvantage of these systems is the
increased power density. Trend has set in for the use
of multi-input converter units that can effectively
handle the voltage fluctuations. But due to high
production cost and the low efficiency of these
systems they can hardly compete in the competitive
markets as a prime power generation source [6-7].
2. BLOCK DIAGRAM & ITS
DESCRIPTION
www.ijrde.com


A solar cell (also called a photovoltaic cell
electrical device that converts the energy
of light directly into electricity by th
effect [8-10]. It is a form of photoelectric cell
its electrical characteristicse.g. current, voltage, or
resistancevary when light is inciden
which, when exposed to light, can generate and
support an electric current without being attached to
any external voltage source, but do require an
external load for power consumption.
The solar cell works in three steps:
1. Photons in sunlight hit the solar panel and are
absorbed by semiconducting materials, such as
silicon.
2. Electrons (negatively charged) are knocked
loose from their atoms, causing an electric
potential difference. Current starts flowing
through the material to cancel the potential and
this electricity is captured. Due to the special
composition of solar cells, the electrons are only
allowed to move in a single direction.
3. An array of solar cells converts solar energy
into a usable amount of direct current
electricity.
Fig. 3 Simplified PV Cell

photovoltaic cell) is an
electrical device that converts the energy
by the photovoltaic
photoelectric cell (in that
e.g. current, voltage, or
vary when light is incident upon it)
which, when exposed to light, can generate and
support an electric current without being attached to
any external voltage source, but do require an

hit the solar panel and are
absorbed by semiconducting materials, such as
(negatively charged) are knocked
loose from their atoms, causing an electric
potential difference. Current starts flowing
through the material to cancel the potential and
tricity is captured. Due to the special
composition of solar cells, the electrons are only
allowed to move in a single direction.
An array of solar cells converts solar energy
direct current (DC)

From the equivalent circuit it is evident that the
current produced by the solar cell is equal to that
produced by the current source, minus that which
flows through the diode, minus that which flows
through the shunt resistor:
I = output current (
I
L
= photo generated
(ampere)
I
D
= diode current (ampere)
I
SH
= shunt current (ampere).
The figure below shows a step
converter. It consists of a dc input
V
g
,boost inductor L , controlled
,filter capacitor C, and the load
the switch S is in the on state, the
inductor increases linearly and the
that time. When the switch S is tur
stored in the inductor is released
the output RC circuit.
There are many methods us
maximum PowerPoint tracking and
are listed below:
Perturb and Observe method
algorithm is also called hil
involves a perturbation in the op
the DC link between the solar
converter. In this case, by perturbing the
of the power converter impli
voltage of the DC link between
power converter. The perturbation v
the reference value for the solar
cell current or duty cycle of the
But here in this case solar cell vol
sue: pp- 403-407
404 | P a g e
From the equivalent circuit it is evident that the
current produced by the solar cell is equal to that
produced by the current source, minus that which
flows through the diode, minus that which flows
Where,
current (ampere)
photo generated current
= diode current (ampere)
= shunt current (ampere).
step-up or PWM boost
input voltage source
d switch S, diode D
resistance R. When
the current in the boost
the diode D is off at
turned off, the energy
d through the diode to

thods used for
g and a few
thod- The P&O
l-climbing, which
on in the operating voltage of
solar cell and the power
bing the duty cycle
ies modifying the
n the solar and the
on variable can be
solar cell voltage, solar
the MPPT converter.
voltage is chosen as


the perturbation variable.
In this method, the sign of the last perturbation and
the sign of the last increment in the power are used
to decide what the next perturbation should be. If
there is an increment in the power, the perturbation
should be kept in the same direction and if the
power decreases, then the next perturbation should
be in the opposite direction.
In the P&O algorithm, the operating voltage of the
solar cell is perturbed by a small amount, and the
resulting change in power is measured. If the change
in power is positive, then the perturbation of the
operating voltage moved the solar cell operating
point closer to the MPP. Thus, further voltage
perturbations in the same direction (that is, with the
same algebraic sign) should move the operating
point toward the MPP. If the change in power is
negative, the system operating point has moved
away from the MPP, and the algebraic sign of the
perturbation should be reversed to move back
toward the MPP. This methods based on the slope of
PV curve of solar PV array.
Incremental Conductance method - This method
uses the PV array's incremental conductance (/)
to compute the sign of (/). When (/) is
equal and opposite to the value of I/V (where
(/)=0) the algorithm knows that the maximum
power point is reached and thus it terminates and
returns the corresponding value of operating voltage
for MPP. One complexity in this method is that it
requires many sensors to operate and hence is
economically less effective.
Parasitic Capacitance method This method is an
improved version of the incremental conductance
method, with the improvement being that the effect
of the PV cell's parasitic union capacitance is
included into the voltage calculation.
Constant Voltage method- This method which is a
not so widely used method because of the losses
during operation is dependent on the relation
between the open circuit voltage and the maximum
power point voltage. The ratio of the set w
o
voltages
is generally constant for a solar cell, roughly around
0.76.Thus the open circuit voltage is obtained
experimentally and the operating voltage is adjusted
to 76%ofthis value.
Constant Current method Similar to the constant
voltage method, this method is dependent on the
relation between the open circuit current and the
maximum power point current. The ratio of these two
currents is generally constant for a solar cell, roughly
around 0.95.Thus the short circuit current is obtained
experimentally and the operating current is adjusted
to 95% of this value.
Every method has certain advantages and certain
disadvantages. Choice is to be made regarding
which algorithm to be utilized looking at the need of
the algorithm and the operating conditions. For
example, if there quired algorithmic to be simple and
not much effort is given on the reduction of the
voltage ripple then P&O is suitable.
In electronics, signal conditioning means
manipulating an analog signal in such a way that it
meets the requirements of the next stage for further
processing. Most common use is in analog-to-digital
converters.
In control engineering applications, it is common to
have a sensing stage (which consists of a sensor), a
signal conditioning stage (where usually
amplification of the signal is done) and a processing
stage (normally carried out by an ADC and a micro-
controller). Operational amplifiers (op-amps) are
commonly employed to carry out the amplification of
the signal in the signal conditioning stage. Thus the
block diagram of signal conditioning is as shown
below


Block diagram of signal conditioning

Fuzzy Logic block diagram
The fuzzy controller is composed of the following
four elements:
1) A Rule-Base (a set of If-Then rules), which
contains a fuzzy logic quantification of the experts
linguistic description of how to achieve good control.
2) An Inference Mechanism(also called an inference
engine or fuzzy inference module), which
emulates the experts decision making in interpreting
and applying knowledge about how best to control
the plant.
3) A Fuzzification interface, which converts
controller inputs into information that the inference
mechanism can easily use to activate and apply rules.
4) A Defuzzification interface, which converts the
conclusions of the inference mechanism into actual
inputs for the process.
3. APPLICATION OF FL
Aircraft/ spacecraft: Flight control, engine
control, avionics systems, failure diagnosis,
navigation and satellite control.
Automated highway systems: Automatic steering,
braking and throttle control for vehicles.
Autonomous vehicles: Navigation of ground and
underwater vehicles.
Manufacturing Systems: Scheduling and
deposition process control.
Power industry: Motor control, power control/
distribution and load estimation.
Robotics: Position control and path planning.
Microcontrollers, as the name suggests, are small
controllers. A controller is used to Control some
process, in this implementation, the speed of the
motor. The microcontroller could be called a "one-
chip solution. It typically includes CPU (central
processing unit), Memory and Peripherals.

Plot of Power and Voltage Curve as Output


Plot of Current and Voltage Curve as Output
4. CONCLUSION
In this paper, a Photovoltaic system with an
intelligent Maximum power point tracker (MPPT)
has been modeled and output is determined. The
algorithm used for MPPT controller is based on
Fuzzy Logic. Fuzzy logic controller is modeled using
fuzzy toolbox. The entire PV system was calculated
and output results are verified. From the results it was
clearly found that the PV system becomes more
efficient when a MPPT controller is included in the
system when compared to a PV system without
MPPT controller.
Obviously, it can be deduced that the fuzzy controller
is faster than the P&O controller in the transitional
state, and presents also a much smoother signal with
less fluctuations in steady state. In this work, the aim
was to control the voltage of the solar panel in order
to obtain the maximum power possible from a PV
generator, whatever the solar insolation and
temperature conditions. Since quite a few control
scheme had already been used and had shown some
defects, it was necessary to find and try some other
methods to optimize the output, fuzzy logic controller
seemed to be a good idea. The controllers by fuzzy
logic can provide an order more effective than the
traditional controllers for the nonlinear systems,
because there is more flexibility. A fast and steady
fuzzy logic MPPT controller was obtained. It makes
it possible indeed to find the point of maximum
power in a shorter time runs compared to the well-
known P&O controller.
REFERENCES
[1]. Kimiyoshi Kobayashi, Hirofumi Matsuo and Yutaka
Sekine, A novel optimum operating point tracker of
the solar cell power supply system ,IEEE Conference
on Power Electronics, Volume 3, 20-25 June 2004
,Page(s):2147 2151 Vol.3.
[2]. M.GodoySimdes and N.N.Franceschetti, Fuzzy
optimisation based control of a solar array system, IEE
Proc.-Electr. Power Appl., Vol. 146, No. 5, September
I999, IEE Proceedmgs online no. 19990341
[3]. M. G. Villalva, J. R. Gazoli, and E. R. Filho
Comprehensive Approach to Modeling and Simulation
of Photovoltaic Arrays IEEE Trans. Power Electr.,
vol.24, no. 5, pp. 1198-1208, May 2009.
[4]. Y.Kuo-Maximum Power Point Tracking controller for
photovoltaic energy conversion system-IEEE Trans
Ind. Electron-Volume 48-2001.
[5]. Nicola Femia, Giovanni Petrone, Giovanni Spagnuolo,
Massimo Vitelli Optimization of Perturb and Observe
Maximum Power Point Tracking Method IEEE
transactions on power electronics, vol. 20, no. 4, july
2005
[6]. D. P. Hohm and M. E. Ropp, Comparative Study of
Maximum Power Point Tracking Algorithms, Progress
in photovoltaics: research and applications Prog.
Photovolt: res. Appl. 2003; 11:4762 (doi:
10.1002/pip.459)
[7]. Xuejun Liu and Luiz A. C. Lopes , An Improved
Perturbation and Observation
[8]. Maximum Power Point Tracking Algorithm for PV
Arrays, 2004 35th Annul IEEE Power Electronics
Specialists Conference
[9]. Chung-Yuen Won, Duk-Heon Kim, Sei-Chan Kim A
New Maximum Power Point Tracker of Photovoltaic
Arrays Using Fuzzy Controller,IEEE transaction1994
[10]. S. Armstrong and W.G Hurley Investigating the
Effectiveness of Maximum Power Point Tracking for a
Solar System, IEEE Conference on Power Electronics,
2005 Page(s):204 209.

Video Stabilization Based On Global Motion Estimation
Using Background Feature Point Classification
Anupriya R , Gomathy U , Karunya C , Anitha Y(Assistant Professor)
Electronics and Communication Engineering, Jeppiaar Engineering College

ABSTRACT: The performance of video
stabilization is dependent on the accuracy of
global motion estimation between two successive
frames. In this paper, we propose a novel method
to estimate the global motion accurately using the
classified background (BG) feature points (FPs).
In the proposed method, global motion estimation
and FP classification are jointly performed using
the global motion parameters of the previous
frame. The experimental results show that video
stabilization using the proposed method
outperforms the conventional stabilization
methods, especially when the moving foreground
(FG) objects occupy a large part of the image.

Index Terms Feature point classification,
global motion estimation, video stabilization.
I.INTRODUCTION
A hand held camera acquires image sequences that
are affected by both desired and undesired motion.
The latter motions are often irregular and unsmooth.
In case of hand held camera, the intention may have
been to pan the camera smoothly, but the hand
holding the camera may have been unsteady. Videos
captured by hand leads visible frame to frame jitter
and perceived as shaky, which is not enjoyable to
watch. The jerky image sequences also have negative
impact on image sequence encoding efficiency which
decreases the quality of image sequences [1-5].
Video stabilization is, therefore becoming an
essential technique that is used in advanced digital
cameras and camcorders. It is defined as the
elimination of undesired motions to remove shaking
from hand held cameras. It is an important video
enhancement technology which aims at removing
shaky motion from videos. The implementation of
video stabilization algorithms has to be cheap and use
less memory. Digital Image Stabilization (DIS) meets
these demands as it uses the image stream for
stabilization and therefore does not need any
additional equipment Digital Image Stabilization
(DIS) system can be divided into three modules
Motion estimation, detection of unwanted
movements and motion compensation [6-8]. The
main goal is to compensate the unwanted shaking
movements without affecting moving objects. By
calculating a smooth motion close to the actual
motion of the device by employing image processing,
much of this shaking in videos can be reduced. This
describes SIFT feature matching to estimate the inter
frame motion to account for Global Motion
Estimation and Motion smoothing is performed to
smooth the GMV used for stabilizing the video.
While the motion estimation is achieved by selecting
the reliable features from four blocks and
triangulation method is adapted to find the best
feature matches and smoothing is done by adaptive
fuzzy filtering and Kalman filtering. Feature
matching algorithm is used as it produces accurate
results and less computational load. The developed
algorithm provides a fast and robust stabilization and
alters real time performance. Results show that video
stabilization using SIFT feature matching is superior
in stabilizing the shaky videos in terms of accuracy
and efficiency [9-15].
II.PROPOSED METHOD
In Feature Based Motion estimation, the most time
consuming process is the key point extraction and
their similarity measurement from which few features
are selected and are used to calculate the Global
motion vectors between two frames [16-18]. The
computation complexity is higher if the whole image
is used to extract points because it is proportional to

the area of the images (frames) and the complexity of
similarity measurement is proportional to the square
of the area. In this, block based background feature
extraction is done by using four blocks in the four
corners of the frame and SIFT is used to extract key
points and measure similarity. Now several reliable
matches from each block are obtained, yet
interference of moving objects may cause error in
global motion estimation. This error can be removed
by applying inter block feature matching. Randomly
select three points and calculate the area formed by
the triangle in both the images [18-23]. This
matching will give features which are not part of
local motion caused by moving objects. Mismatch is
always inevitable in motion estimation for feature
based methods. To solve this problem, a novel idea of
forming a triangle based on three best features is
proposed. The pixel values of the triangle formed in
two images is accumulated and matched. This
matching ensures the removal of faulty features. Now
with the best matched features, global motion vectors
are calculated. The global motion vectors are
smoothed by using filter. The smoothened motion
vectors are used to stabilize the video.
III.SIFT (Scale Invariant Feature Transform)
SIFT have been developed by David Lowe in 1999
for extracting highly distinctive invariant features
from images, to perform reliable matching of the
same between different images. SIFT features are
invariant to image scaling, rotation and translation,
provides reliable matching with the changes in 3D
viewpoint and illumination [10]. By using this
approach large number of features can be generated
that cover the image over full range of scales and
rotation. Previously SIFT features are mostly used for
object recognition where features detected are
matched to database of already extracted features
from different objects at different locations.
The stages of computing set of images features are
1. Scale space extreme detection
2. Key-point localization
3. Orientation assignment
4. Key point descriptor.
SCALE-SPACE EXTREMA DETECTION
The first step in feature extraction is identifying
candidate feature points. This step results in
identifying features that will be invariant to scale. In
the first stage of key-point detection, the
identification of locations and scales that can be
repeatable assigned under differing views of the same
object is done [24-25]. Using a continuous function
of scale known as scale space, detection of locations
that are invariant to scale change of the image can be
masterful by searching for stable features across all
possible scales. The scale space of an image is
defined from the function L(x,y,). This is produced
from the equation:
L(x,y,) = G(x,y,)*I(x,y) (1)


Fig 1: Block Diagram of the Proposed Algorithm
Where

Where G(x,y,) and I(x,y) are variable-scale
Gaussian and input image and * is convolution
operation in x and y.
The key-points are identified by finding the extrema
in difference of Gaussian convolved with the image
D(x,y, ) where

The above equation is the difference of Gaussian
function which scales with constant factor (k-1)
where k=2 and is image blur chosen as 1.6 in the
algorithm. Five blurred images are created by
repeatedly convolving original image with Gaussian
in order to complete an octave. The difference of
Gaussian is calculated by subtracting adjacent images
and it is done for one octave, then the image is
resample to half of its size and the process is repeated
to identify same object in different scale [10]. For the
purpose of video stabilization, it is enough for one
octave as scaling does not vary much between two
successive frames. The key-points are selected by
finding local maxima and minima in G(x,y,), and
then each pixel is compared with its eight neighbors
in the current scale, nine neighbors in the scale above
and below shown in the figure. The pixels are
considered as key-point if it is larger than or smaller
than all of them.

Fig 2: Nine Neighbors in the Scale
KEY-POINT LOCALIZATION
This step in the algorithm performs a detailed fit to
the nearby data for accurate location, scale, and ratio
of principal curvatures. This information allows
points to be rejected that have low contrast (therefore
sensitive to noise) or poorly localized along an edge
as the scale-space produces key- points.
Taylor expansion is given by,

Where D and its derivatives are evaluated at the
sample point and is the offset from
this point. The location of the extremism, , is
determined by taking the derivative of this function
with respect to x and setting it to zero, given by:

ORIENTATION ASSIGNMENT
Here each key-point is assigned one or more
orientations based on local image gradient directions
to achieve invariance to rotation as the key-point
descriptor can be represented relative to this
orientation. The Gaussian-smoothed image at the
key-point scale is taken so that all computations are
performed in a scale-invariant manner. For an image
L(x,y,) sample L(x,y) at scale , the gradient
magnitude, m(x, y), and orientation, (x,y), are
precompiled using pixel differences [10].

Within a region around the key-point an orientation
histogram is constructed from the gradient
orientations of sample points. This contains 36 bins
covering the 360 degree range of orientations. Each
sample added to the histogram is weighted by its
gradient magnitude and by a Gaussian-weighted
circular window with that is 1.5 times the key-point
scale. The peak in the orientation histogram denotes
the dominant orientation at that key-point and if there
is another peak in the histogram that is equal to 80%
of highest peak then it is also considered as valid
gradient orientation. The result is the creation of
another key point at the same location with gradient
orientation.
KEY-POINT DESCRIPTOR
The above steps include key-point locations at
particular scales and assigned orientations. The
invariance is applied to image location, scale and
rotation. A descriptor vector for each key-point
should be computed such that the descriptor is highly
distinctive and partially invariant to the remaining
variations such as illumination, 3D viewpoint, etc.
This step is performed for image closest to the key-
point's scale in a scale.
At first the orientation histograms are created on 4x4
pixel neighborhoods with 8 bins each. The magnitude
of the gradients that go in each bin is multiplied by a
Gaussian with 1.5 times the scale of the key-point.
The final descriptor has 4x4x8=128 elements [10] to
represent a feature point. Each element in the feature
vector is threshold to a value of 0.2 in order to
eliminate too much variation. For achieving
illumination invariance, each vector is normalized to
make it a unit vector after threshold.
IV.KEY-POINT MATCHING
The basic idea of Feature matching is to find
matching key-point from the neighbor frames. The
best candidate match for each key-point is found by
identifying its nearest neighbor of the key-points
from the adjacent frames. SIFT implements Best-Bin-
First algorithm (BBF) to search for nearest neighbor
explained in 2.5. The nearest neighbor is the key-
point with minimum distance for the invariant
descriptor. These are the only points that have the
chance of having matching descriptors. An effective
measure can be obtained by comparing the distance
of the closest neighbor to that of second closest
neighbor. This method performs well as the correct
matches need to have closest neighbor, to achieve
reliable matching. For other false matches sometimes
the similar distance will be there, and then the second
closest match will be discarded as providing an
estimate of false match.
In each block, a key-point from previous frame is
selected and finds the nearest neighbor and second
nearest neighbor key-point from the next frame.

Calculate the distance between key-point from
previous frame to that of next frame nearest neighbor
and second nearest neighbor. If the distance ratio to
the nearest neighbor is less than threshold value then
the nearest neighbor will be selected as best match to
the key-point of the previous frame, else check the
distance for the second nearest neighbor. Suppose X
is a key-point from previous frame and Y is the
nearest neighbor, Z is the second nearest neighbor in
the next frame. The probability that Y is Xs best
match if the distance ratio between X and Y is less
than the threshold. If not then check the distance ratio
of X and Z i.e. second nearest neighbor. The key
points with more than the threshold value will be
discarded to obtain reliable matching.
i.e. R(X) = r(Y)/r (Z) <Threshold. The distance ratio
of point X to point Y will be less than the threshold
value. By following this process the best key-points
from all the blocks for matching will be selected.
Now after having the matched key points obtained
from the nearest neighbor method using SIFT, select
the key points that helps in calculating in GMV as
some features tends to represent the moving objects
in the image. Only consider the key points that
represent the background in the image to know the
inter-frame motion as the moving objects consists of
velocity which leads to errors in calculating the
model parameters. To overcome the errors in
calculating GMV, use distance invariance to select
the optimal matching points. Using this the mismatch
caused due to interference of moving objects will be
avoided. The basic idea is to randomly select three
key-points from three different blocks to form a
triangle. These selected key-points are the best
matches obtained from the similarity measurement
using SIFT. Then calculate the area of triangle
formed by the key-points and compare to the area
formed by key-points of same blocks in the next
frame. If the area of triangle formed from the
previous frame is matched to the area formed from
the next frame, then consider these key-points as best
match pairs otherwise discard as mismatch may
occur.

Fig 3: Triangular method
Suppose that ABC are the key-points of the triangle
formed in previous frame and A'B'C' are the key-
points of the triangle formed in next frame. If the area
of ABC is equal to the area of A'B'C', then consider
the matched pairs (A, A') (B, B) (C, C') as best
matches.

Area of triangle used for matching the key points can
be given as

Where a, b and c are the distance between
coordinates of the triangle and given as

Where (x
A
,y
A
) (x
B
,y
B
) (x
C
,y
C
) are the coordinates of
ABC respectively.
After having the matched pairs obtained from the
above step the pixel difference of the matched pairs is
calculated. If the pixel difference is less than the
value 10 (approximately equal) then consider these
matched pairs as final best matches and discard the
key points above it. The reason behind calculating the
pixel difference is that the area of triangle may be

equal, while the distance between the key points of
the triangle formed are different which gives
incorrect matching. The value 10 is selected as the
images contain some blur in the frames.

After calculating the pixel difference the matched
pairs (A, A') (B, B') (C, C') are selected as final best
matches for calculating the Global motion
parameters.
V.GLOBAL MOTION ESTIMATION
The Global Motion Estimation unit produces a
unique global motion vector (GMV) for each video
frame that represents the camera motion during the
time interval of two frames. The GMV consists of
both handshake movement and intended camera
movement. Handshake movement is calculated
separately and eliminated in order to get the
stabilized video and intentional camera motion is
calculated by smoothing the global motion vector. In
this method the GMV is calculated by taking the
mean value of the selected matched pair in each
frame in both X-direction and Y-direction

VI.ADAPTIVE FUZZY FILTER
In recent years, Image processing and signal
processing applications uses these fuzzy logic based
systems extensively. This system gives effective
results in a smart way of approach to nonlinear and
uncertain systems. For input and output, both the
membership functions of vertical and horizontal are
used in fuzzy systems as the smoothing filter is
implemented on both the directions in video. These
membership functions are selected for obtaining
decent performances whereas few membership
functions perform low system complexity. The value
of Input1 (horizontal) is proportional to the noise
amplitude and the value of Input2 (vertical) is
proportional to the intentional motion acceleration.
IIR FILTER
GMV consists of two major components:
(i) Intentional motion component (e.g.
corresponding to camera panning) and
(ii) (ii) Un-intentional motion component
(e.g. corresponding to handshake).
A better motion algorithm should remove the un-
wanted motion and maintain the intentional motion.
Assume that the unwanted motion is corresponding to
the high frequency component and the proposed
algorithm uses a low pass filter to remove the
unwanted motion component. A smooth motion
vector (SMV) is resulted by filtering that resembles
the intentional camera movement [17]. The method
which calculates the SMV in the form of first-order
auto regression from equation:

The smoothing filter is implemented on the vertical
and horizontal components of the global motion
vectors independently and smoothing factor of filter
is adjusted by a fuzzy system continuously. Both
fuzzy systems with a same structure are used similar
to the vertical and horizontal motion components.
This system consists of two inputs (Input1, Input2)
and one output where inputs are defined by functions:

Input1(x1, y1) is quantitative representations of
unwanted camera motion (noise) and Input2(x2, y2)
is intentional camera motion (acceleration). The
value of Input1 is proportional to the noise amplitude

and the value of Input2 is proportional to the
intentional motion acceleration [17]. In the first-order
IIR filter, a higher noise needs a larger smoothing
factor for filtering. On the other hand, a large
smoothing factor prevents tracking of intentional
camera motion when acceleration. Therefore, the
smoothing factor should be tuned carefully. This
fuzzy system tunes the smoothing factor of the IIR
filter adaptively according to the amount of noise and
camera motion acceleration.
VII. UNWANTED MOTION ESTIMATION
Unwanted motion estimation (UMV) in the proposed
method is obtained after obtaining the (SMV) by
using the adaptive fuzzy filter. UMV can be given as
UMV(n) = GMV(n) SMV(n)
This unwanted motion is removed from the videos
with the proposed new method by using
Accumulative Motion Vectors (AMV) and it is given
as

To obtain the stabilized video, the frames are
wrapped back to its original position i.e
Stabilized video = offset AMV (n).
VIII.RESULT
These results are based on the experiment performed
in the chapter 3. The performance of the algorithm is
evaluated with different types of videos. Total of 16
un-stabilized videos were used for testing the
algorithm and 6 videos are finalized as they are
different in the camera motion than the others which
are quite similar. The description of each video is
given in the tabular form. The video sequences that
are selected for testing the algorithm consists of
different resolution as CIF, QCIF, VGA, QVGA with
different frame rate of 15 fps and 25 fps. All the
video sequences used for the algorithm consists of
.avi format. The performance of the algorithm is
evaluated with different types of videos. Total of 16
un-stabilized videos were used for testing the
algorithm and 6 videos are finalized as they are
different in the camera motion than the others which
are quite similar. The description of each video is
given in the tabular form. The video sequences that
are selected for testing the algorithm consists of
different resolution as CIF, QCIF, VGA, QVGA with
different frame rate of 15 fps and 25 fps. All the
video sequences used for the algorithm consists of
.avi format.
Table1 : Time Consumption of Motion Estimation
using the Proposed Method and Traditional Method
S.No
SIFT block
(in seconds)
Traditional
(in seconds)
1 30.23 70.55
2 30.23 80.34
3 40.53 110.12
4 37.16 125.13
5 44.21 156.33
6 39.49 87.21

The above table describes the time consumed in
seconds for calculating the Global Motion Vectors
using the proposed method with SIFT which extracts
the features using four different blocks and traditional
method [20] which considers the full image for
extracting the features. It is clear that this method has
less time consumption than the traditional method as
the complexity of feature extraction is proportional to
the area and the similarity measurement is
proportional to the square of the area. The complexity
is less than half to that of traditional method. The
complexity of this process includes the key point
extraction, similarity measurements of the extracted
key points and final best matches obtained from the
similarity measurement. The complexity of
calculating the GMV using SIFT block based
approach will extremely reduce the total
computational complexity of the algorithm making it

time saving and producing accurate matching of key
points.
IX.CONCLUSION
This a novel approach for video stabilization based
on the extraction and matching of SIFT features
through video frame have been proposed. Feature-
based motion estimation algorithm is used that
extracts SIFT features from frames of video and then
evaluation of trajectory is performed to estimate the
inter frame motion, thus allowing to calculate Global
Motion Vector (GMV). The intentional cameras
motion is filtered using adaptive fuzzy filtering. The
experiments confirm the effectiveness of the method
with desired performance by panning and removing
unwanted shake in different types of video. The
algorithm would be effective for analysis of un-
stabilized videos in digital cameras and mobile
devices.
Shaky effect in un-stabilized videos is reduced by
estimating the inter frame motion using SIFT
algorithm. SIFT features are extracted between
images and key point similarity measurement is used
to select the matched pairs of key points between
neighboring images. The matched points are the best
matches between the successive frames allow to
estimate the inter frame motion as their scale and
location is identified, thus calculating GMV. GMV
consists of both wanted and un-wanted motion. The
GMV is filtered using Adaptive-Fuzzy filter and then
SMV is calculated. The un-wanted motion estimation
is obtained by UMV=GMV(n)-SMV(n). Motion
compensation is performed by wrapping the frames
back to its original position.
X.FUTURE WORK
In this study, mainly focuses on stabilization of
videos which are already taken from a camera or
mobile device. Here available resolution videos with
three filters in comparison have been taken. In future,
experimentation and subjective analysis can be done
by using different types of filters and compare them
even with high resolution videos and for the more
even experiment improving the method on live
streaming videos. And can also compare the cost,
time consuming and effectiveness of the proposed
method with different tools available in market for
video stabilization.
REFERENCES
[1] L. M. Abdullah, N. Md Tahir, and M. Samad,
"Video stabilization based on point feature matching
technique," in Control and System Graduate Research
Colloquium (ICSGRC), 2012 IEEE, 2012, pp. 303-
307.
[2] L. Chang and L. Yangke, "Global motion
estimation based on SIFT feature match for digital
image stabilization," in Computer Science and
Network Technology (ICCSNT), 2011 International
Conference on, 2011, pp. 2264-2267.
[3] B. Pinto and P. R. Anurenjan, "Video stabilization
using Speeded Up Robust Features," in
Communications and Signal Processing (ICCSP),
2011 International Conference on, 2011, pp. 527-531.
[4] H. Rong, S. Rongjie, I. f. Shen, and C. Wenbin,
"Video Stabilization Using Scale-Invariant Features,"
in Information Visualization, 2007. IV '07. 11th
International Conference, 2007, pp. 871-877.
[5] K. L. Veon, M. H. Mahoor, and R. M. Voyles,
"Video stabilization using SIFT-ME features and
fuzzy clustering," in Intelligent Robots and Systems
(IROS), 2011 IEEE/RSJ International Conference on,
2011, pp. 2377-2382.
[6] J. M. Wang, H. P. Chou, S. W. Chen, and C. S.
Fuh, "Video stabilization for a hand-held camera
based on 3D motion model," in Image Processing
(ICIP), 2009 16th IEEE International Conference on,
2009, pp. 3477-3480.
[7] S. Yao, P. Guturu, T. Damarla, B. Buckles, and
K. Namuduri, "Video stabilization using principal
component analysis and scale invariant feature
transform in particle filter framework," Consumer
Electronics, IEEE Transactions on, vol. 55, pp. 1714-
1721, 2009.

[8] R. Yeon Geol, R. Hyun Chul, and C. Myung Jin,
"Long-time video stabilization using point-feature
trajectory smoothing," in Consumer Electronics
(ICCE), 2011 IEEE International Conference on,
2011, pp. 189-190.
[9] L. Zhaoxia and A. Jubai, "A new algorithm of
global feature matching based on triangle regions for
image registration," in Signal Processing (ICSP),
2010 IEEE 10th International Conference on, 2010,
pp. 1248-1251.
[10] D. Lowe, "Distinctive Image Features from
Scale-Invariant Keypoints," International Journal of
Computer Vision, vol. 60, pp. 91-110, 2004/11/01
2004.
[11] C. Tomasi and T. Kanade, Detection and
Tracking of Point Features: School of Computer
Science, Carnegie Mellon Univ., 1991.
[12] H. R. Pourreza, M. Rahmati, and F. Behazin,
"Weighted multiple bit-plane matching, a simple and
efficient matching criterion for electronic digital
image stabilizer application," in Signal Processing,
2002 6th International Conference on, 2002, pp. 957-
960 vol.2.
[13] J. Tang, X. Han, Z. Yuan, and H. Zhao, "An
Approach of Electronic Image Stabilization Based on
the Representative Point Matching," in Genetic and
Evolutionary Computing, 2009. WGEC '09. 3rd
International Conference on, 2009, pp. 347-350.
[14] P. C. Shenolikar and S. P. Narote, "Different
approaches for motion estimation," in Control,
Automation, Communication and Energy
Conservation, 2009. INCACEC 2009. 2009
International Conference on, 2009, pp. 1-4.
[15] D. T. Vo, T. Q. Nguyen, Y. Sehoon, and A.
Vetro, "Adaptive Fuzzy Filtering for Artifact
Reduction in Compressed Images and Videos,"
Image Processing, IEEE Transactions on, vol. 18, pp.
1166-1178, 2009.
[16] M. K. Gullu and S. Erturk, "Membership
function adaptive fuzzy filter for image sequence
stabilization," Consumer Electronics, IEEE
Transactions on, vol. 50, pp. 1-7, 2004.
[17] M. J. Tanakian, M. Rezaei, and F. Mohanna,
"Real-time video stabilization by adaptive fuzzy
filtering," in Computer and Knowledge Engineering
(ICCKE), 2011 1st International eConference on,
2011, pp. 126-131.
[18] W. Chuntao, K. Jin-Hyung, B. Keun-Yung, N.
Jiangqun, and K. Sung-Jea, "Robust digital image
stabilization using the Kalman filter," Consumer
Electronics, IEEE Transactions on, vol. 55, pp. 6-14,
2009.
[19] S. Ertrk, "Real-Time Digital Image
Stabilization Using Kalman Filters," Real-Time
Imaging, vol. 8, pp. 317-328, 8// 2002.
[20] S. Battiato, G. Gallo, G. Puglisi, and S. Scellato,
"SIFT Features Tracking for Video Stabilization," in
Image Analysis and Processing, 2007. ICIAP 2007.
14th International Conference on, 2007, pp. 825-830.
[21] I.-T. R. P.910, "Subjective video quality
assessment methods for multimedia applications,"
International telecommunications union
telecommunication sector, 1999.
[22] I.-T. RECOMMENDATION, "Subjective video
quality assessment methods for multimedia
applications.," 1995.
[23] http://www.cs.ubc.ca/~lowe/keypoints/ [Online].
[24] Matlab, ""Shaky car."," ed.
[25] D. G. Lowe, "Object recognition from local
scale-invariant features," in Computer Vision, 1999.
The Proceedings of the Seventh IEEE International
Conference on, 1999, pp. 1150-1157 vol.2.


VoIP Receiver Based Adaptive Playout Scheduling and
Packet Loss Concealment Technique
Chrishia Christudhas
1
, Christina.P
2
, Sharmila.S
3


ABSTRACT
This paper proposes high performance play out
scheduling and packet loss concealment
algorithm at the receiver for enhancing Voice
over Internet Protocol (VoIP) speech quality.
VoIP does not yet provide toll-quality voice over
the networks, which is a major challenge. A
number of factors may affect the service quality
of VoIP, such as packet loss, packet delay, and
network delay variation. The design involves a
computationally efficient receiver-based
enhancing method of VoIP speech quality that
can be used to solve the problems described. The
important functionality to be implemented at
the receiver is an adaptive play out scheduling
(PS) and packet loss concealment (PLC) scheme
using effective signal classification. Using
accurate jitter estimation and robust signal
classification, the play out-buffer scheduling
algorithm makes it possible to trade-off the
buffering time with the rate of packet loss.
1. INTRODUCTION
Voice over Internet Protocol (VoIP) is a recent
emerging technology in the area of voice
communications. As more and more smartphone
users are taking advantage of mobile VoIP
services, the markets of VoIP-based
communication systems and consumer electronics
is growing dramatically [1]. Unfortunately, VoIP
does not yet provide toll-quality voice over the
networks, which is a major challenge. A number of
factors may affect the service quality of VoIP, such
as packet loss, packet delay, and network delay
variation also known as jitter. Considerable effort
has been made within different layers of current
communication systems to reduce delay, smooth
jitter, and recover loss. In this paper, we focus on
enhancing VoIP speech quality only at receiving
portion of a mobile Internet phone [2-3].
For concealing packet loss or recovering lost
packets, several methods have been developed.
These methods can be roughly divided into two
types: waveform substitution in estimation with
high accuracy. It reacts to the changes in network
conditions immediately. The second method is
packet compression considering signal class is
very important. This reduces the buffering delay. In
this paper, we propose a computationally efficient
receiver-based enhancing method of VoIP speech
quality that can be used to solve the problems
described. The important functionality to be
implemented at the receiver is an adaptive play out
scheduling (PS) and packet loss concealment
(PLC) scheme using effective signal
classification[4-5].
2. BLOCK DIAGRAM

DESRIPTION
2.1. SIGNAL INPUT
Signa
Code
Signa
Signal
analys
Jitter
solvin
Loss
conc
Signal
framin
Output
device


The analog signal is given as input through a
microphone connected to a server computer.
2.2. CODEC MODULE
The analog signal is converted into a digital signal
through A/D Converter and is divided into packets.
2.3. SIGNAL BUFFER
When a packet arrives at the receiver, it strips the
packet information and decodes the packet
information at a regulated speed. At the receiver,
these decoded packets are stored adequately in the
signal frame buffer.
2.4. SIGNAL FRAME
The signal frame is classified into one of the three
classes: voiced, unvoiced and silence or
background types. The classified results are then
used in the adaptive play out scheduling and packet
loss concealment.
2.5. JITTER ESTIMATION
This involves detection of rapid spike and predicts
network delay, including spike delays. The inter-
arrival jitter of the k
th
arriving packet n. The i
th
talk interval is computed as:
J
i,k =
n
i,k
n
i,k-1
= ( a
i,k
g
i.k
) ( a
i,k-1
g
i,k-1
)
Where j
i,k
denotes the inter-arrival jitter
and n
i,k
, a
i,k
and g
i,k
are the network delay of k
th

packet.
2.6. LOSS CONCEALMENT
If the i
th
signal frame is absent from the signal
buffer, a packet is declared lost. To recover lost
packets, the loss concealment module often makes
a subsequent frame demand from the voice
decoder.
2.7. SIGNAL FRAMING
A digital to analog converter regularly converts the
processed signal frame at a scheduled time into an
analog signal.

2.8. OUTPUT DEVICE
Finally, the user hears the analog voice
signal through a speaker.
3. SOFTWARE REQUIREMENTS:
Operating system: Ubuntu 12.04
Platform: Linux
Embedded Linux typically refers to a complete
system, or in the context of an embedded Linux
vendor, to a distribution targeted at embedded
devices. Although the term embedded is often
also used in kernel discussions (especially between
developers who have embedded concerns
words often used in the community), there is no
special form of the Linux kernel targeted at
embedded applications.
4. RESULT AND DISCUSSION
4.1. EXECUTION OF EXISTING SYSTEM:
The input signal is given by using microphone.
First we execute the built-in operation (program to
give input signal and playing the saved voice) in
Ubuntu terminal.
sh client.sh records the input signal from
microphone.
Then by using following commands we can
play the saved input voice:
ls Displays the contents of directory
aplay out.wav plays the recorded voice signal
where out.wav is saved file.
Two computer are connected via Ethernet cable. In
this one system acts as a client and another one acts
as server. The server system records the input
signal from microphone and passes the signal
(broadcasting) to the client system by using the IP
address of it. Client system (listener) receives the
signal and plays by using the following commands.
SERVER PART
Sh client.sh record the input voice from
microphone.
ls - displays the contents of current directory.

./broadcaster 10.0.0.13 passes information to
client system via IP address.
CLIENT PART
./listener receives signal from server.
Sh server.sh plays the received signal.
4.2. EXECUTION OF PROPOSED THEORY
4.2.1. RECEIVING END
A wireless modem has to be attached to the
receiving system B. By executing the terminal
commands, b waits for the call of sending system
A. the specific command used to wait for the call:
sh voip.sh wait for receive call.

4.2.2. SENDING END
A computer system A sends the audio signal to the
other end system B by calling the IP address of B.
A wireless modem (NETGEAR) is attached to the
A or B system. By executing the terminal
commands, system A sends the audio signal to the
receiving end B. The command used to send audio:
Sh voipdesktop.sh sends the respective signal to
receiver.

The following results and observations were made
through the experiment. They are listed below:
No
.

Time-Scale
Modificatio
n
Approach
Adaptive play
out
Scheduling
and Loss
Concealment
1. RECEIVE
R-BASED

Yes Yes
2. Minimizes
overall
delay and
packet loss
Yes Yes, with less
buffering delay

3. Minimizes
jitter-loss
No Yes
4.

Scheduling
Time
Varying Constant

5. CONCLUSION
A VoIP receiver-based adaptive play out
scheduling and packet loss concealment method
was proposed and evaluated. Compared to
conventional methods, the proposed method has
lower computational complexity and enables users
to deliver higher quality voice. For example, the
burst loss rate can be reduced from 12 to 1% at 40
ms buffering delay, which results in significantly
improved audio quality. The experimental results
encourage the use of the proposed fully receiver-
based enhancing algorithm in many practical
mobile VoIP applications. In future work, we will
apply the method to multi-party teleconferencing
applications running on smart-TV and mobile
phones. This VOIP transmission technique replaces
the RIL layer in mobile.
REFERENCES
[1]. Dinei Florencio and Li-Wei He (2003)
Enhanced Adaptive Playout Scheduling and
Loss Concealment Techniques for Voice over
IP Networks, Microsoft Research, One
Microsoft Way, Redmond, WA 98052.
[2]. Ibikunle Frank, Jakpa Orunta, Ike Dike (2013)
Broadband Wireless Access Deployment


Approach to Rural Communities, Journal of
Computer Networks, [Vol. 1, No. 3, 38-45].
[3]. Kuo-Kun Tseng, Yuan-Cheng Lai and Ying-
Dar Lin (1998) Perceptual Codec and
Interaction Aware Playout Algorithms and
Quality Measurement for VoIP Systems, IEEE
INFOCOMM, [pp. 680-686].
[4]. Sue Moon, Jim Kurose, Don Towsley (1998)
Packet audio playout delay adjustment:
performance bounds and algorithms ,
Multimedia Systems, [pp. 6:1728].
[5]. Wen-Hui Chiang, Wei-Cheng Xiao, and
Cheng-Fu Chou (2006) A Performance Study
of VoIP Applications: MSN vs. Skype, ICIP,
[vol. 1, pp. 331-335].


Advanced Speed Regulation in Automobiles Using GPS
Dr. G. Sathiyabama
1
, Mrs.Shanmugha Kani
2
, Arul Clinton
3
, Deepak Anto
4
, Zenith
Alex
5
Faculty
1,2
, U.G Scholar
3,4,5
, Jeppiaar Engnieering College, Chennai - 600 119

ABSTRACT
Traffic issues and accidents due to over speeding
are increasing in a faster rate all over the world.
To avoid this speed breakers, cameras, speed
barriers etc., are used, which are also one or the
way hazardous for the drivers. The paper puts
forth a theory which proposes that any given city,
town, village can be divided into physical zones
which are classified according to different speed
ranges. A Global Positioning System is fixed in the
automobile to sense the speed limit of the current
road in which the automobile is travelling. The
GPS is preprogramed with the maximum speed
limits of all roads in a particular town, city, and
state. The signal from the GPS is send as an input
to a preprogramed Microcontroller embedded
within the automobile which compares the speed
of the vehicle and the speed limit of the current
road which is the allowable speed of an
automobile to travel. This is done by introducing a
device which opposes the throttle valve in the
opposite direction. This paper also discusses
related work, prototype design and interaction. It
concludes with an outlook to future research.
KEYWORDS: Global Positioning System,
automobile, accelerator pedal , throttle cable ,
speed governor.

I INTRODUCTION
Direct speed governing and the
supplemental adjustment of speed governor set points
are the methods used on present day power systems
for matching generation to load, for the allocation of
the generation output among generation sources and
for the achievement of desired system frequency[1-
3]. This same system is used in heavy buses and
trucks to limit their speed within a limit. To introduce
this system to cars and small sized automobiles an
electronic variable speed governor is used. This paper
provides with the basic information on speed
governor and their application for system control. All
speed governors, whether mechanical hydraulic,
electrohydraulic or digital electrohydraulic, have
similar steady state speed output characteristics, so
their application for system control (for slow
changes) is the same [4-5]. Then a speed governor
was introduced which limits the automobiles to run a
speed which is set in the governor. Usually 60kmph
speed limit is fixed in heavy vehicles. But there are
road with speed limits less than and greater than
60kmph. So there is a possibility to violate speed
regulations in those roads. In this paper we are
adding hardware to the automobile like speed
governor which will sense the speed limit of the
current road and does not allows the driver to violate
speed regulations of the road [6-7]. A simple block
diagram of throttle valve control is shown in figure 1.

Figure 1: Simple Block Diagram of Throttle Valve Comtrol
The major advantage of this proposed
concept is that will reduce the risk of accidents due
to over speeding and reduce traffic jams. It can be
accommodated into smaller automobile since it
doesnt acquire large space [8-9].
In this paper, section II describes the prior
work that has been carried out, Section III deals
with the proposed prototype design, Section IV
gives a detailed discussion about the results


obtained and in Section V this paper concludes with
an outlook for future research.

II PRIOR WORK
There has been several research projects have been
carried out to provide assistive technologies for this
issue. Introduction of speed governors could only set
the speed of the vehicle. Once set then it cannot be
changed. For example, if it is set to 60kmph, then the
speed of the vehicle wont go more than 60kmph.
One of the disadvantages is that it required lot of
space so it was unable to fix in smaller vehicles.
Some of the prior work includes, Theraja, B.L[1],Del
Toro, V[2],Daniel W.Lewis,[9].etc
III PROPOSED PROTYPE DESIGN
The main motive of this project is to develop a
variable speed governor which can vary its value
according to the speed limit of the road in which the
automobile is travelling. So we did some back
ground study on the existing speed governors and
we found some positives as well as negatives.
The motive of the project is enhanced and
developed into the steps to be followed by the
instrument which we are going to develop to limit the
speed. The first step is to sense the location of the car
and read the maximum speed limit of the road. The
second step is to develop a speed governor which can
vary its maximum speed limit digitally. The third step
is to connect the step one and step two i.e., the
maximum speed limit sensed in the first step should
be given to the speed control mechanism which
should control the speed according to the maximum
speed limit of the road.
So to fabricate the step one we found a
device which can sense our location and show our
self in a map that device is called GPS in abbreviate
Global Positioning System. There are hundreds of
GPS devices available in the market. They all hold
specific features. The basic GPS devices fitted in the
cars can show the maps and navigate to our
destinations. But we are going to use some advanced
GPS devices which can show the maximum speed
limit of the road as well. The GPS with this facility
has been introduced in 2010 which had no control
mechanism to couple with it. So far our step one is
realized.
The second step of realization required a
basic knowledge on how the petrol and diesel engine
works. Lets get to the basics on how to drive a car.
We will start the engine, Press the clutch, Switch the
gear and Press the accelerator.

Figure 2: Throttle cable and Throttle Valve
The function of the throttle valve is to vary
the air and fuel ratio applied to the engine. By
varying the air and fuel ratio, the speed of the engine
is varied. The angle of the throttle valve decides the
amount of air and fuel injected to the engine in other
words the angle of the throttle valve decides the
speed of the car. So if we block the throttle valve
rotation we can stop the acceleration applied to the
automobile. To block the throttle valve we will be
using a stepper motor.
The stepper motor can produce angular
moments as output. We will place the servomotor to
operate in the opposite direction to the throttle valve
since its purpose is to only limit the angle of the
throttle valve. This concludes our control mechanism.

Figure 3 Phase I Block Diagram
www.ijrde.com


Figure 4: Phase II Block Diagram
IV RESULTS AND DISCUSSION
In this project a control mechanism for
speed violators by automobiles has been developed.
Thus the results of the proposed system are observed
and the performance of the advanced speed
regulation in automobiles using GPS is discussed and
compared respectively in this chapter.
Figure 5 show the simulation kit developed
to demonstrate the working of the advanced speed
regulation in automobiles using GPS.
Figure 5: Hardware Prototype
The DC motor simulates the working of the
engine. Servo motor indicated the amount of throttle
applied in the throttle pedal. Potentiometer is used
as the throttle pedal. A laptop with the Visual Basic
Program is connected to the kit through an RS232
port. When the power is turned on the DC motor
starts to rotate in a constant minimum speed which
indicates that the car is ignited. The speed of the DC
motor is varied using the potentiometer. When the
maximum speed limit in the laptop is set to
20KMPH. The DC motors maximum speed limit is
set to a certain RPM. Vise versa for each set value

Figure 4: Phase II Block Diagram
IV RESULTS AND DISCUSSION
In this project a control mechanism for
speed violators by automobiles has been developed.
Thus the results of the proposed system are observed
performance of the advanced speed
regulation in automobiles using GPS is discussed and
Figure 5 show the simulation kit developed
to demonstrate the working of the advanced speed

Figure 5: Hardware Prototype
The DC motor simulates the working of the
engine. Servo motor indicated the amount of throttle
applied in the throttle pedal. Potentiometer is used
as the throttle pedal. A laptop with the Visual Basic
onnected to the kit through an RS232
When the power is turned on the DC motor
starts to rotate in a constant minimum speed which
indicates that the car is ignited. The speed of the DC
motor is varied using the potentiometer. When the
mit in the laptop is set to
20KMPH. The DC motors maximum speed limit is
set to a certain RPM. Vise versa for each set value
applied in the laptop the maximum speed limit of
the DC motor is varied.
Figure 6: User interface of Advanced speed
Regulation
In some emergency situations the driver has
to violate the maximum speed limit of the road. For
that purpose a manual control mode is provided in
the user interface to override the maximum speed
limit of the car. Figure 6 shows the user interface
the advanced speed regulation in automobiles using
GPS.
In the existing system the speed limits of the
various road is not considered. The figure 7 shows
the graph plotted against the various speed limits of
the road and the speed limit applied
In x-axis various roads are plotted and in the y
speed limit applied to the vehicle is plotted.

Figure 7: Graph Max. Speed Limit Vs Various Loads
sue: pp- 421-424
423 | P a g e
applied in the laptop the maximum speed limit of

Figure 6: User interface of Advanced speed
In some emergency situations the driver has
to violate the maximum speed limit of the road. For
that purpose a manual control mode is provided in
the user interface to override the maximum speed
limit of the car. Figure 6 shows the user interface of
the advanced speed regulation in automobiles using
In the existing system the speed limits of the
various road is not considered. The figure 7 shows
the graph plotted against the various speed limits of
the road and the speed limit applied to the vehicle.
axis various roads are plotted and in the y-axis
speed limit applied to the vehicle is plotted.
Max. Speed Limit Vs Various Loads


The cost of implementing the proposed model
is very less and more efficient when compare to the
RFID Model. An interesting future study might able
to reduce the response time of the device which is
the only negligible drawback found in the proposed
model. By using same high speed processors we can
eliminate the only drawback.
V CONCLUSION
Thus this paper has researched and
documented practical solutions for the impending
traffic problem and violating over speeding rule. The
entire system was a low cost variable electronic
speed governor, small in size and easy to assemble
onto an existing vehicle without disturbing its present
arrangement. The tests done went smoothly and had
no problems , except for the fact that only a
simulation could be executed, cause it is done with in
a closed room in Standard test conditions hence GPS
wasnt included in the testing process. Therefore a
computer is used to enter the co-ordinates.
An interesting future study might involve in
controlling the throttle valve by pneumatic or
hydraulic force.
REFERENCES
[1]
Theraja, B.L., A Text book of Electrical
Technology, Vol.II, S.C Chand and Co., New
Delhi, 2007.
[2]
Del Toro, V., Electrical Engineering
Fundamentals, Prentice Hall of India, New
Delhi, 1995.
[3]
Cotton, H., Advanced Electrical Technology,
Sir Isaac Pitman and Sons Ltd., London, 1999.
[4]
Microprocessor and Microcontrollers, Krishna
Kant Eastern Company Edition, Prentice Hall
of India, New Delhi , 2007.
[5]
Muhammad Ali Mazidi & Janice Gilli Mazidi,
R.D.Kinely The 8051 Micro Controller and
Embedded Systems, PHI Pearson Education,
5
th
Indian reprint, 2003.
[6]
R.S.Khurmi & J.K.Gupta, Thermal Engineering,
S.Chand & Co. Ltd., 2006.
[7]
S.Domkundwar, C.P.Kothandaraman &
A.V.Domkundwar, Thermal Engineering,
Dhanpat Rai & Co.2002.
[8]
Rajkamal, Embedded system-Architecture,
Programming, Design,Tatamcgraw Hill, 2003.
[9]
Daniel W.Lewis, Fundamentals of Embedded
Software, Prentice Hall of India, 2004.



Automation and Accident Reporting Using ARM Processor
in Bikes

Ms. V Jeyalakshmi Devi
1
, Krishna V S
2
, Sam Sanders S
3
, Santhosh Kumar S
4

Faculty
1
, UG Scholar
2,3,4
Jeppiaar Engineering College, Chennai-119.

ABSTRACT
Every time when a person starts riding a bike it is
advised to check for quantity of fuel available,
turn off the indicators/head lights if not necessary
and primarily wear a helmet for safety. In order
to enhance the safety and comfort while riding
two wheelers, it is necessary to monitor the bikes
status automatically and use the stored energy
effectively and efficiently. Normally much
technical advancement are designed for four
wheelers whereas the two wheelers which are also
the major mode of transport is not given the same
importance. So this paper aims to put forth a safe
and energy efficient system that can be installed in
bikes. The safety system includes Anti-crash
warning system which helps to intimate when an
accident occurs to a predefined contact with the
help of the GPS and GSM. It also includes an
LDR for automatic switching ON/OFF of the
headlights and a fuel lever sensor for numeric
indication of the fuel level. By this it is ensured
that any accident is reported within a specific time
and rescue action can be implemented right away.

I. INTRODUCTION

Bikes have become the most used form of
transport now-a-days. The Indian two-wheeler (2W)
industry has shown a strong volume growth over the
last two-years, having grown by 25% in 2010-11 and
27% in 2012-13 to reach 13.3 million units. This
strong double-digit growth has been driven by
multiple factors. In the rate at which the usage of
bikes increased the accidents that occur to the riders
has also increased in the last few decades. In case if
an accident occurs then the primary need is to give
first aid to the victim and get them to a hospital
immediately if necessary. This is feasible in a place
with frequent human intervention on the contrary if
there are only scarce human movement in the place
then death becomes inevitable in case of major
accidents. In order to resolve this we hereby propose
a automation model that when implemented can
report to a pre-specified contact in case of an major
accident, along with this the system under
consideration also aims at introducing a new way fuel
level display for the riders convenience and
automatic switch ON/OFF of headlights of a bike.

This is done using Embedded Technology,
which is now in its prime and the wealth of
Knowledge available is mind-blowing. Embedded
System is a combination of hardware and software.
Embedded technology plays a major role in
integrating the various functions associated with it.
This needs to tie up the various sources of the
Department in a closed loop system.



Fig 1 Circuit Diagram

II. CIRCUIT DESCRIPTION

In the circuit connections shown in figure 1,
8 pins from the port 1 are interfaced to the LCD
which forms the user interface section in the output.
There are three parameters that are to be monitored,
firstly the LDR which monitors the intensity of
ambient light, delivers the measured value to pin 11.
Based on the value received from the LDR the ARM
controls automatic switching ON/OFF of the
headlight which is connected to pin 38 by comparing
it with the threshold value already provided in it.
Secondly a fuel level sensor connected to pin 13 of
the ARM continuously senses the fuel available in
the tank and displays it as a numeric value using the
LCD. Lastly a vibration sensor which acts as a
medium to detect shock waves produced during
accidents feeds its value to pin 15 where the
processor recognizes whether it is a major accident
and in turn fetches the respective location using a
GPS modem connected to pin 34, the location that is
being fetched is transmitted to a predefined contact
with the help of a GSM modem with its receiving and
transmitting ends connected to pins 19 and 21
respectively.
III. SIMULATED RESULTS AND
DISCUSSION

The following circuits discussed below from fig
2 to 7 shows the various simulated outputs of the
project under discussion. With these the clear picture
of the function of the project can be obtained.

Fig 2 shows the LDR picking up low intensity of
the ambient light after which the headlights are
turned on automatically. Fig 3 shows the display of
fuel level being monitored on a regular basis.

Fig3, Fig 4, Fig 5, Fig 6 all belong to sensing
vibration shocks that gets produced when an accident
occurs. The former two show us the vibration sensor
picking up the input and GSM initializing to send a
message. The latter two is the GSM sending message
and it getting delivered at the receiver end in a
mobile phone.

Fig.2 LDR output

Fig.3 Fuel level output

www.ijrde.com


Fig.4 Vibration Sensing output

Fig.5 message sending output

Fig.6 Message sent output

ration Sensing output

Fig.7 Received GPS location

Fig 7 is the receiver end of the module it
contains the GPS co ordinates of the location where
the accident is occurring. This GPS location can be
used to look up for the name of the received
coordinates.

Fig 8 Block Diagram

Advanced RISC Machine (ARM):
processor in fig 8 is the main component of
circuit which controls all the operation
place. The ARM used here (LPC2129) is very much
self sustained system. It consists of 16kb on chip
static RAM, 128kb on chip flash program memory,
64 pins(shown in fig 9) of which 46 are assigned for
I/O pins, 4 are for 10 bit ADC, multiple
interface including two UARTs, fast I2C and 2 SPIs.
The processor is fed with two power supplies one for
operating CPU, ranging from 1.65
other is I/O power supply, ranging from 3.0
ARM there is embedded trace macrocell which
enables non-intrusive high speed real time tracing of
the instruction execution. Apart from these it also has
two inbuilt 32 bit timers, a PWM unit, a real time
clock and a watchdog timer.
sue: pp- 425-429
427 | P a g e
Fig.7 Received GPS location
Fig 7 is the receiver end of the module it
contains the GPS co ordinates of the location where
occurring. This GPS location can be
used to look up for the name of the received
Fig 8 Block Diagram
Advanced RISC Machine (ARM): The ARM
processor in fig 8 is the main component of the
circuit which controls all the operation that is taking
place. The ARM used here (LPC2129) is very much
self sustained system. It consists of 16kb on chip
static RAM, 128kb on chip flash program memory,
64 pins(shown in fig 9) of which 46 are assigned for
4 are for 10 bit ADC, multiple serial
interface including two UARTs, fast I2C and 2 SPIs.
The processor is fed with two power supplies one for
operating CPU, ranging from 1.65-1.95V and the
other is I/O power supply, ranging from 3.0-3.6V. In
ARM there is embedded trace macrocell which
intrusive high speed real time tracing of
the instruction execution. Apart from these it also has
two inbuilt 32 bit timers, a PWM unit, a real time
www.ijrde.com


Fig.9 ARM processor

Sensors:

Vibration Sensor: Vibration sensor shown in fig.
10(a) is a type of transducer which is used
the shock waves that occurs during an accident and
converts it into an electrical signal which is
transferred to the controller for further processing. I
has a very high linearity, a sensitive axis in the plane
of chip and a 22KHz frequency structure.

Fuel level Sensor: The Fuel level sensor shown in
fig. 10(b) is used to measure the level of
inside the tank. Depending upon the fuel level the
voltage output of the sensor changes. Readings are
very stable and even a change of 1mm can be
accurately measured and also it fits into a wide range
of pipe diameter.

Light Dependent Resistor: LDR shown in fig. 10(c)
senses the intensity of light and gives
value in terms of resistance. It is of low cost, has a

Vibration sensor shown in fig.
10(a) is a type of transducer which is used to detect
the shock waves that occurs during an accident and
converts it into an electrical signal which is
transferred to the controller for further processing. It
has a very high linearity, a sensitive axis in the plane
of chip and a 22KHz frequency structure.
The Fuel level sensor shown in
fig. 10(b) is used to measure the level of the liquid
pending upon the fuel level the
voltage output of the sensor changes. Readings are
very stable and even a change of 1mm can be
accurately measured and also it fits into a wide range
LDR shown in fig. 10(c)
out equivalent
value in terms of resistance. It is of low cost, has a
very wide spectral response and ambient temperature
range.

Global Positioning System(GPS):
Positioning System can be used to find the
a person, place or a place anywhere around the globe.
This system shown in fig 11 fetches information from
the various satellites revolving around the earth,
figure out the distance between each, and use this
information to deduce the location. This operation is
based on a simple mathematical principle called
trilateration. It corresponds to the location in terms of
latitude and longitude co-ordinates.

Fig 10. Vibration sensor, Fuel level sensor
Dependent Resistor

Fig 11 GPS Modem

Global System for Mobile
(GSM): A GSM modem is a wireless modem that
works with a GSM wireless network. A wireless
modem behaves like a dial-up modem. The main
difference between the two is that a dial
sends and receives data through a fixed telephone
line while a wireless modem sends and receives data
through radio waves. The working of GSM modem is
based on commands, the commands always start with
AT (which means ATtention) and finish with a <CR>
character.

V. CONCLUSION
sue: pp- 425-429
428 | P a g e
very wide spectral response and ambient temperature
Global Positioning System(GPS): The Global
Positioning System can be used to find the location of
e anywhere around the globe.
This system shown in fig 11 fetches information from
the various satellites revolving around the earth,
figure out the distance between each, and use this
information to deduce the location. This operation is
mathematical principle called
trilateration. It corresponds to the location in terms of
ordinates.
Fig 10. Vibration sensor, Fuel level sensor and Light
Dependent Resistor
Fig 11 GPS Modem
Global System for Mobile Communication
A GSM modem is a wireless modem that
works with a GSM wireless network. A wireless
up modem. The main
difference between the two is that a dial-up modem
sends and receives data through a fixed telephone
hile a wireless modem sends and receives data
through radio waves. The working of GSM modem is
based on commands, the commands always start with
AT (which means ATtention) and finish with a <CR>


In this competitive world, all the
automobiles have been modernized and advanced
using automation. This automation has played an
important role in improvising the comfort and safety
of the automobiles. This paper aims at achieving
more safety while driving by implementing the
immediate reporting of accidents that occurs, ensures
the optimum usage of battery and provides an
accurate measurement of fuel level. The processor
ARM7 LPC2921 is the modernized integrated chip
that has brought automation into picture. The
proposed model of ARM processor has several
distinct advantages over the existing technology.

Beyond what has been proposed, this system can be
advanced to facilitate real time monitoring of
vehicles exact location, provide voice aid to the user
with the information about various routes for a
destination and periodically update about the various
parameters such as maximum distance that can be
travelled with the remaining fuel, temperature of the
engine and appropriate functioning of various parts
thus ensuring a safe journey.

REFERENCE

[1]. Wen Ouyang, Chang-Wu Yu, Kun-Ming Yu,
Ko-Jui Lin, Huai-Tse Chang*, Keng-Yu Cheng
Safe Path Planning Strategy for Bike Net
2013 IEEE
[2]. Chih-Ching Hsiao, Hsin-Tsung Ho, Pan-Chia
Cheng A Safety System for Intelligent E-Bike
with Fuzzy Approach June 2011 IEEE.
[3]. www.microchip.com
[4]. www.arminterfacing.com

Avionic Weather Monitoring System Using Controller
1
Mathumitha.G.S ,
2
J.Jebastine
1
UG Schol ar,
2
Associate professor, Jeppiaar engi neeri ng col lege, Chennai.

ABSTRACT: Different geographical
parameters such as temperature,
Humi dity, Wi nd speed, fog, lightni ng,
visi bi lity for aircrafts are to be measured
using proper weather monitori ng system.
Thi s paper explai ns the design and
development of temperature, light
monitori ng and control l ing usi ng low cost,
effici ent PIC mi crocontrol ler. In thi s
work, a smart integrated weather
monitori ng system is to be i mpl emented
with the use of mi crocontrol ler whi ch
actively monitors the environmental
conditions. Thi s system allows user to
control the geographi cal parameters at
desired conditions. It has many advantages as
compared to other avionic systems i n
terms of its huge memory capacities, lower
cost and greater portability.
Key words - microcontroller; climatology;
avionics.
I. INTRODUCTION
An avionic system consists of electronic components
used to detect various climatological parameters
which if not appropriate may hinder the functioning
of an aircraft. Various devices were used to analyze
these parameters using a variety of microcontrollers
and integrated circuits in the past few years [1-4].
The PIC 16F877A microcontroller provides a cost
effectiveway of achieving the same. In this
presentation a PIC microcontroller is used to collect
data from a couple of sensors interfaced with it. The
microcontroller compares these received data with
the standard data stored in the controller to check if
the current conditions are hostile. Here a LCD
display is used to display the acquired output [5-7].
II.EARLIER METHODS
The earlier available methods are explained below
A. Weather monitoring by satellite
The weather satellite is a type of satellite that is
mainly used to monitor the weather and climate of
the earth. The weather satellites are of two types: i)
polar satellite ii) geostationary satellite. Polar
satellites in Fig.1 cover the entire earth while the
geostationary satellites cover the earth along the
equator [8-9]. These satellites were designed to
measure cloud cover and resistance, but a poor axis
of rotation keeps it from collecting a notable amount
of useful data.
Cloud cover, forest fires, effects of pollution,
vegetation, dust storms, snow cover, ice mapping,
boundaries of ocean currents, etc., and other types of
environmental information are collected using
weather satellites.

Fig.1 Radar communication
B.Weather monitoring by Doppler radar
Radar is used to take large scale weather imagery.
Radar systems allow climatologists to monitor
weather conditions of different localities including
hurricanes, tornados, floods and dust storms. Radar
system is particularly useful in times of emergency

weather conditions as it provides live coverage of the
weather, enabling more accurate warning systems to
be put in place. Meteorologists use radar as in fig.2 to
monitor amount of rain in clouds. It has become the
primary tool for short-term weather forecasting and
so that people can be warned about severe weather
conditions such as thunderstorms, tornadoes, winter
storms, precipitation. But Radars tend to
underestimate rainfall at the farthest ranges. Radars
tend to underestimate rainfall when they are blocked
by mountains. They tend to drastically overestimate
rainfall. It has certain limitations like high sensitivity
i.e. In severe weather it stands a higher chance of
failure.It also requires higher maintainenance and
facesHardware problems.

Fig.2 Doppler radar in airport
III. SENSORS AND TRANSDUCERS
A. Thermistors
A Thermistor is a type of resistor whose resistance
varies with appropriate variation in temperature.
Thermistors are widely used as inrush current
limiters, temperature sensors,self-resetting
overcurrent protectors, and self-regulating heating
elements.
Thermistors can be classified into two types,
depending on the sign of , where it is the constant of
coefficient. If is positive, device is called a positive
temperature coefficient (PTC) thermistor,
or posistor. If is negative, and the device is called
a negative temperature coefficient (NTC) thermistor.
When current flows through a thermistor, a
considerable amount of heat is produced this will
raise the temperature of the thermistor above the
environmental temperature.The electrical power input
to the thermistor is:

Where I is the current flowing in the device and V is
the supplied voltage. Fig.3 shows a typical
thermistor.

Fig.3 Typical thermistor
B. Infra-Red Sensors
An infrared sensor is an electronic instrument that is
used to sense certain characteristics of its
surroundings by detecting infrared radiation. Infrared
waves have less dispersion and hence can be
measured accurately.
In the electromagnetic spectrum, infrared radiation is
the region having wavelengths longer than visible
light wavelengths, but shorter than microwaves. The
infrared region is approximately demarcated from
0.75 to 1000m.
Infrared technology found in TV has an IR detector
for detecting the signal from the remote control.
Major benefits of infrared sensors include low power
requirements, simple circuitry, and their portable


feature.
Types of Infra-Red Sensors
Infra-red sensors shown in fig.4 are classified into
two types:
Thermal infrared sensors These sensors use IR
energy in the form of heat. Their photo sensitivity is
independent of wavelength. This have slow response
times and low detection capability.
Quantum infrared sensors These sensors provide
higher detection performance and faster response
speed when compared to thermal IR sensors. Their
photo sensitivity is dependent on
wavelength.Thesedetectors are used in the near
infrared region.

Fig.4 Infra-red sensor
C. Light Dependent Resistor Sensors
As its name implies, the Light Dependent
Resistor (LDR) is made from a piece of exposed
semiconductor material such as cadmium sulphide
which changes its electrical resistance from several
thousand Ohms in the dark to may be a few hundred
Ohms when light falls upon it by creating hole-
electron pairs in the material.
The overall effect is an improvement in its
conductivity with a decrease in resistance for an
increase in illumination. Also, photo resistive cells
have a long responsetime requiring many seconds to
respond to a change in the light intensity. A normal
LDR sensor is shown in fig.5.

Fig.5 Light Dependent Resistor Sensor
PIC MICROCONTROLLER
Microcontroller is a highly integrated chip that
contains all the components comprising a processor
along with a memory unit. Typically it includes a
CPU, RAM and ROM memory, I/O ports, timers and
UARTs. Typically Microcontroller is called a
dedicated processor that is designed for a very
specific task-to control a unique system. As a result
the parts can be simplified and reduced, which cuts
down on production costs. In this project we use the
PIC 16F877A microcontroller. It provides several
advantages over other microcontrollers. Different
series of PIC microcontroller are popular because of
high performance, low cost, low power consumption
and small in size. It uses high performance RISC
architecture, PIC 16F877A uses 35 single word
instructions, having 20MHZ operating frequency.
The additional flexibility in PIC 16F877A
microcontroller is that it has 8K x 14 words of
FLASH Program Memory, 368x 8 bytes of Data
Memory (RAM) and 256 x 8bytes of EEPROM data
memory. It also has 8 channel 10 bit ADC, two PWM
module, 14 interrupt source, Eight level deep
hardware stack, Direct, indirect and relative
addressing modes, Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up Timer (OST),
Watchdog Timer (WDT) with its own on-chip RC,
oscillator for reliable operation, Programmable code-
protection, Power saving SLEEP mode Selectable
oscillator options, Low-power, high-speed CMOS
FLASH/EEPROM technology.


The PIC16FXX series has more advanced and
developed features when compared to its previous
series. It has a few important features such as

high performance
only 35 simple word instructions
fully static design
wide operating voltage range
high sink or source current (25mA)
extended temperature range
low power consumption

IV. PROCESS OF DATA AQUSITION

Fig.6 Block diagram depicting the process

The PIC 16F877A makes use of four different
sensors to measure and control various environmental
conditions like temperature, humidity, wind speed,
Fog,lightning effects and visibility.
As described above the IR sensor is capable
of measuring light intensity so here IR
sensors are used to measure visibility of the
runway and amount of fog covering the
airport.

In a similar manner the LDR measure the
light intensity of the surrounding
environment to make sure the runway is
visible to the pilot.

The controller is also provided with a simple
DC fan to measure the wind speed.

Thermistor plays a vital role in making sure
the temperature of the atmosphere and
precipitation in the air are well below the
standard values. The entire process is given
in the block diagram of fig.6.

A simple prototype which consists of all the
components required to monitor the weather
conditions in an airport is shown in fig.7. This
prototype uses visual basic software to display the
measured readings on a separate computer to produce
an output as in fig.8.

Fig.7 practically tested circuit

By observing and analyzing thereadings the pilot will
be able to decide if the conditions are suitable for
landing the aircraft.


Fig.8 Acquired output

V. CONCLUSION
The designed system carries out the measurement of
current values for temperature, relative humidity,
atmospheric pressure, wind speed and direction and
real time. Based on Juxtaposition of the collected
statistical information with the current measured data,
defined methods for weather forecasting and the
determination of the correlation between processed
meteorological quantities, there will be possible to
realize an algorithm for short-term weather
forecasting.
REFERENCES
[1] Microchip Technology Inc. PIC16F87X-28/40-pin 8-
Bit CMOS EEPROM/FlashMicrocontrollers, DS21191B,
1998.
[2]Humirel. RELATIVE HUMIDITY SENSOR
HS1100/HS1101, HPC001, Rev. 7 June 2002.
[3] Microchip Technology Inc. PIC16F87X-28/40-pin 8-Bit
CMOS EEPROM/Flash Microcontrollers, DS21191B,
1998.
[4]http://ww2010.atmos.uiuc.edu/(Gh)/guides/mtr/fcst/mth/
prst.rxml. Weather forecasting Methods, 21 July 1997.
[5] Moghavvemi, M., K. E. Ng, C. Y. Soo, and S. Y. Tan. 2005. A
reliable and economically feasible remote sensing system for
temperature and relative humidity measurement.Sensors and
Actuators A117: 181185
[6] Odlyha, M., G. M. Foster, N. S. Cohen, C. Sitwellb, and
L. Bullock. 2000. Microclimatemo n i t o r i n g o f
i n d o o r e n v i r o n me n t s u s i n g p i e z o e l e c t r i c
q u a r t z c r y s t a l h u mi d i t y sensors. J. Environ. Monit.
2: 12713
[7] M. D. Eilts and S. D. Smith, Efficient dealiasing of
Doppler ve-locities using local environment constraints, J.
Atmos. Ocean.Tech., vol. 7, pp. 118-128, 1990.
[8] http://www.sablesys.com/baro-altitude.html. Altitude &
Barometric Pressure, Sable Systems International, 12 April
2006.

[9] R. M. Lhermitte, Dual Doppler radar observations of
convec-tive storm circulation, in Proc. 14th Radar
Meteorol. Conf.,Tucson, AZ, Amer. Meteorol. Soc., pp.
139-144, 1970."Microcontroller to sensor interfacing
techniques,"BiPOM Electronics INC.



Fuzzy Control Based Obstacle Avoidance for Intelligence
Vehicle
P.Prasanya
1
, M.Shreen Fathima
2
, Sudha Rajayogan
3
, Dr. G.Sathiyabama
4

U.G Scholar
1,2,3
, Professor
4
, Jeppiaar Engineering College, Chennai-119

ABSTRACT
Mobile robots are being increasingly used on
land, underwater, and in air, as sensor carrying
agents to perform various missions such as
searching for harmful biological and chemical
agents, search and rescue in disaster areas, and
environmental mapping and monitoring. In this
work , fuzzy-logic based mobile robot is
designed and implemented for obstacle
avoidance. Mobile robot also has the capability
to measure the distance covered by it and also
monitor pollution .The mobile robot has
obstacle sensors for obstacle avoidance, a gas
sensor for pollution monitoring and pulse sensor
for distance measurement .The obstacle
avoidance is controlled by changing the
direction of motion using fuzzy logic control
.The key advantages of this new approach is its
simplicity and quicker reaction to sudden
changes especially when the robot is moving in
an unstructured environment .The robot
generates the direction of the motion
proportional to the distance from the obstacle
and effectively monitors the pollutants and
distance covered.
KEYWORDS Sensors, fuzzy logic, obstacles,
pollutant, distance, robot.
I. INTRODUCTION
The robots used for crucial applications requires
various types of complex operations related to
navigation, sensing, computation and
communication. Problems commonly associated
with navigation of mobile robots are path planning,
localization, mapping, obstacle avoidance .
Different schemes exist for obstacle avoidance
among which the popular ones used edge-detection
, potential fields, certainty-grids, Vector-Field
Histogram . In the presence of complex tasks such
as the case for driverless cars and robots formation
it becomes practically impossible to implement
these on hardware platforms and perform all these
operations in parallel. As an alternate some simple
and accurate fuzzy-logic based navigation
approaches have been recently developed among
which few combine the objectives of obstacle
avoidance , pulse based distance measuring and
uses gas sensor module for pollution monitoring
.Here, the mobile robots is designed with fuzzy
logic for obstacle avoidance and also it is designed
to measure distance travelled and to monitors
pollution [1-2].
II. DESCRIPTION
Intelligent fuzzy control of obstacle avoidance,
pollution and distance monitoring proposed in this
project concerned, the project involves the
application of various sensor to measure the
distance and pollution level [3-4]. Different types
of sensors are employed in this method in order to
make the operation defacto. The measuring
parameters involves the distance and pollution. In
this model some of the sensor used namely pulse
sensor for ditance monitoring, gas sensor for
pollution monitoring and obstacle sensor for
collision avoidance.In this method obstacle sensor
alone uses the fuzzy control logic ,with its control
the sensor avoid collision [5].
Pulse sensor which senses distance travelled with
the reflection surface which get its control through
PIC whose analog inputs are converted using A/D
converter for the controller to drive the vehicle.
Gas sensor meant for (0-20) ppm which uses the
pervasive sense technology senses the pollutant of
this range by getting its required control which has
its connection with controller through relay.
Obstacle sensor senses the obstruction of the pre
defined limit which give its output as the input to

the PIC which in turn the fuzzy used in it controls
the movement of the vehicle.
The algorithm used in our project is made with
increased membership functions as seven
membership functions for seven input
(i.e., distance from the obstacle) [6]
variables angles are used as output member
functions. The increased membership function
increases the efficiency of the vehicle by accurate
angle change. Regulating the angle of the vehicle
provides absolute obstacle avoidance.
PROCESS FLOW CHART
Fig.1 Flow Chart
WORKING
PIC controller which gets activated along with the
three sensors. The sensor starts sensing once they
Power and Energy Development (MEPED) 2014
the PIC which in turn the fuzzy used in it controls
increased membership functions as seven output
functions for seven input variables
].The output
The increased membership function

PIC controller which gets activated along with the
three sensors. The sensor starts sensing once they
are activated. Pulse sensor which senses the
distance travelled by the vehicle which gets
displayed using LCD . Gas sensor senses for
pollutant once it get activated and continues
sensing whose inputs are simultaneously fed to the
controller through ADC .The controller controls the
vehicle according to the input from the sensor.
Obstacle sensor which senses for its obstruction
when it found obstruction along its path, the
controller changes the direction of the vehicle with
the help of the controller logic. By the various
inputs from the sensors the controller drives the
motor to change its direction in order to complete
the tasks of vehicle. The controller drives the DC
motor through relays.
Fig.2 Block diagram of the intelligence robot
Table 1: Sensor signals and its response


LEFT
SENSOR
B
O
T
H
RIGHT SENSOR
I
/
P

P
O
L
N
L
M
LF N
O
RF
C
M
10
-
50
50
-
90
90
-
13
0
>
1
3
0
90
130
O
/
P
D
N
RS
1
RS
2
RS
3
S
T
LS3
A
N
30
-
45

45
-
60

60
-
90

9
0

90
120
436 | P a g e
which senses the
distance travelled by the vehicle which gets
displayed using LCD . Gas sensor senses for
pollutant once it get activated and continues
sensing whose inputs are simultaneously fed to the
controller through ADC .The controller controls the
vehicle according to the input from the sensor.
Obstacle sensor which senses for its obstruction
when it found obstruction along its path, the
controller changes the direction of the vehicle with
the help of the controller logic. By the various
om the sensors the controller drives the
motor to change its direction in order to complete
The controller drives the DC

Block diagram of the intelligence robot
Table 1: Sensor signals and its response
RIGHT SENSOR
RF RM RN
90-
130
50-
90
10-
50
LS3 LS
2
LS
1
90-
120
120
-
135

135
-
150

membership functions for seven input variables
(i.e., distance from the obstacle).The output
functions.

Fig.3 Input membership functions

Fig.4 Output Membership Functions
CIRCUIT DESCRIPTION

Fig.5 Circuit diagram
The controlling and monitoring is the key factor
involved in this project. The sensors are used
locally keeping in mind in the view of obstacle
avoidance, distance and pollution monitoring. The
controller used in this method is PIC which has 40
pin dip package. The power supply applied here as
+12v which activates the pic controller and along
with its three sensor employed in this method. The
port RD is connected with 16x2 LCD display
which has been working in 4 bit mode operation.
The DC motor is connected with relay which is a
SPDT of +12v power supply and has its control
over both the DC motors individually through port
RC0 and RC1.The external crystal oscillator of
20mhz which enhances the function of the motor.
The port RC7 is connected with RS232, it enables
the RF start & stop remote switch. The port RA is
an analog port which is used to connect the sensor
which in turn connects to RA0-RA3.In order to
avoid the obstacle, RA0 is conneted to the obstacle
sensor right and RA1 is connected to the obstacle
sensor left. For pollution monitoring and distance
measuring, RA2 is connected to the pollution
monitoring gas sensor and in turn RA3 is connected
for the distance measuring.

Fig.6 Fuzzy control based obstacle avoiding vehicle
RESULT
It was observed that with fuzzy logic based
controller, the robot avoids obstacles very well
reacts to sudden changes and quicker response to
the pollution. Since the membership functions are
linear, the angle of the robot is proportional to the
distance of the robot from the obstacle in the front.
The algorithm used in the project is made with


membership functions for seven input variables
(i.e., distance from the obstacle).The output
variable angles are used as output member
functions .The increased membership function
provides absolute obstacle avoidance. The accuracy
is found increased with the angle changing function
of the robot. The seven different modes of change
still enhances the function of obstacle avoidance.
The absolute measurement of distance is obtained
simultaneously while the robot is in motion. It also
monitors the pollutants in the surrounding
environment and makes the indications
correspondingly.

REFERENCES
1)Borenstein, J.; Koren, Y.;, "Obstacle avoidance with
ultrasonic sensors", IEEE Journal of Robotics and
Automation, vol.4, no.2, pp.213-218, Apr 1988.
2)Dagswanger W.R Neuro fuzzy posture estimation for
visual vehicle guidance, IEEE Transactions on Robotics
and Automation, vol.7, no.3, pp.278- 288, Jun 1991.
3) Menon, A.; Akmeliawati, R.; Demidenko, S.; ,
"Towards a Simple Mobile Robot with Obstacle
Avoidance and Target Seeking Capabilities using Fuzzy
Logic", Instrumentation and Measurement Technology
Conference Proceedings, 2008. IMTC 2008. IEEE,
pp.1003-1008, 12-15 May 2008.
4) V.shumOn the Development of a Sensor Module for
Real-Time Pollution Monitoring Information Science
and Applications (ICISA), 2011 International Conference
on 26-29 April 2011
5)V.Chae jeong Sensor-based Emissions Monitoring
System Information Science and Service Science and
Data Mining (ISSDM), 2012 6th International
Conference on New Trends in 23-25 Oct. 2012
6)XiangoAutomated Control System for Air Pollution
Detection in Vehicles Intelligent Systems Modelling &
Simulation (ISMS), 2013 4th International Conference
on 29-31 Jan. 2013



Sonar Based Intelligent 2D Obstacle Avoidance for Mobile
Robots
G.Sathiyabama
1
, H.Hemalatha
2
, S.Mahalakshmi
3
, Neethal Johny
4

Faculty
1
,B.E Students,
2,3,4
,Department of EIE, Jeppiaar Engineering College, Chennai.
Abstract
This paper presents the design and development of
a micro controller based intelligent vehicle system
in order to detect the obstacles along the pathways
of the navigating system. Sweeping SONAR is
implemented to scan the path and detect the
obstacles. The vehicle is programmed to reorient
itself on detecting any obstacle in the path.
Ultrasonic sensor will increase the reliability of the
obstacle detecting system when used inside the
reactor as it can withstand high temperature and
radiations.
Keywords: Navigating system, Sweeping SONAR,
Obstacle detection, mobile robots

I. INTRODUCTION
Due to advanced technology a person can travel
not only in the entire world but also can go in any
place of the universe. Some places which have
high radioactivity and temperature are also quite
dangerous for humans. There exist many places
where it is nearly impossible for humans to enter.
So for either repairing some malfunctioning thing
or getting information about or from the place,
variety of robots could be used. This paper
presents the outline of the development of one such
robot which is used in reactors where manual
inspections are difficult [1-4].
In this paper, a standard Microcontroller based
wireless navigatingsystem is designed and
developed to pass through the limited space
between the pipes in underground trenches of
reactors [4-7]. A SONARis developed to sweep
through a certain angle to detect the obstacle along
the pathways of the navigating system and the
vehicle is programmed to reorient itself after
detectingthe obstacles. This paper is organized
such that the section II consists of the prior works,
section III gives the description and working of the
proposed work and section IV gives the
conclusion. As per the literature survey,a mobile
nursing robot[9] for the physically challenged
people was developed. It is remote controlled by
the people. In this robot the obstacle avoidance
strategy depends upon the ultrasonic range
finders.Laterin China, Hordur K Heidarsson and
Gaurav S Sukhatme developed a [3] obstacle
detection and avoidance for an autonomous surface
vehicle using profiling Sonar. For industrial
applications a autonomous mobile vehicle [11] for
the purpose of transportation of goods or heavy
loads without the need of mans interruption was
developed. In this robot the vehicle navigation is
carried out using RFID (Radio Frequency
Identification).The obstacle is detected using an
ultrasonic sensor.
The existing navigational system consists of a
vision based sensor for inspections inside reactors.
This navigation system provides the image of the
obstacles that is present in the path [8-11]. The
camera which is mounted on the navigation system
captures the 2D image of the obstacle.Here the
image of the obstacle received by the camera which
is mounted on the remote navigation system is sent
as the input which converts into the digital form.
The data are sent to the microcontroller. After
being processed the data are sent to the wired
module which enables the operator to view the
obstacle present along the pathways. Then the
operator gives command to change the directions of
the remote controlled vehicle via the wired
module.A vision-Based Navigation uses optical
sensors like laser-based range finder and
photometric cameras using CCD arrays to extract
the visual features required to the localization in
the surrounding environment



II.SONAR BASED INTELLIGENT 2
DOBSTACLE AVOIDANCE FOR
MOBILE ROBOT

Fig 1: Block diagram for SONAR based intelligent 2D
obstacle avoidance for mobile robot
The fig 1 gives the block diagram ofSONAR based
intelligent 2D obstacle avoidance for mobile robots
with the hardware interfacing. The hardware
consists of a microcontroller which will drive two
motors for controlling the vehicle. The hardwares
used are interfaced with the PIC microcontroller
18F2431. We have adopted differential drive
mechanism with one free following driven wheel.
The PC is the master controller which starts and
stops the vehicle. Zigbee based wireless control is
implemented for controlling the vehicle.

A VB based graphical user interface is also developed
for controlling the vehicle. A motorized sweeping arm
in the front portion of the vehicle will constantly
sweeps over an angle and scans for obstacle free path.
An RC Servomotor is used for sweeping the sonar
module. In case of any obstacles, the vehicle will re-
orient itself and the process is continued. Ultrasonic
sensors generate high frequency sound waves of 40
KHz and evaluate the echo which is received back by
the sensor. Sensors calculate the time interval between
sending the signal and receiving the echo to determine
the distance to an object. The obstacle detection
system consists of a ultrasonic module (HC-SR04)
which is used to scan the path and detect the obstacles.
This ultrasonic module is programmed with the help
of a microcontroller.

A trigger is given to the sensor to transmit a trigger
signal. The time interval between sending the trigger
signal and receiving the echo signal determines the
distance of the obstacles. The module is mounted on a
RC Servomotor which rotates in such a way that the
module scans for every 10 degrees from 0 to 90
degrees. The entire detection system is mounted over a
vehicle consisting of 2 DC Motors. The DC motor is
used for running and reorientation of the vehicle. If
distance is less than 25cm and the angle is within 45
degrees, the vehicle reorients itself to the direction
opposite to the obstacles and vice-versa. The starting
and stopping of the vehicle is controlled remotely by
the PC with the help of a wireless module(Zigbee).

Fig 2 shows the flow chart which diagrammatically
provides the internal working of the proposed project
which includes sweeping SONAR based obstacle
detection and avoidance. The provides the sequential
steps of operation of the SONAR based obstacle
detection system for vehicle navigation and the
obstacle avoidance process. The operation starts with
giving the START command and assigning the speed
of the motor from the PC. Microcontroller receives
the command and enables the DC motor for vehicle
navigation and the RC Servo motor begins to rotates
which ensures the sweeping of the sensor module and
the sensor module begins to scan the pathways. If the
obstacle is detected within a range of 25 cm from the
vehicle then it redirects itself to the opposite direction
of the obstacle present. The STOP command is
provided from the VB software.


Fig 2: Flow chart of SONAR based intelligent 2D
obstacle avoidance for mobile robot
Fig 3 shows the final prototype of the proposed
navigating system with a sweeping SONAR based
obstacle detection and avoidance system for vehicle
naviagtion.

Fig 3: SONAR based intelligent 2D obstacle
avoidance for mobile robot
III CONCLUSION
In this paper, a successful navigation is
achieved by avoiding the obstacles and self
reorientation. The vehicle steers through the
complicated areas of nuclear reactors such as
underground trenches or between the
radioactive material storage tanks where man
cannot enter. The ultrasonic sensor module,
servomotor and the DC motor used for the
vehicle movement are interfaced and then
programmed in CCS and Visual Basics to
achieve detection of obstacles, localization and
reorientation of the autonomous navigating
system. The use of SONAR improves the
reliability of the system inside the reactors. This
paper provides an innovative proposal for the
inspection of such areas by detecting the
obstacles present on the pathways of the
navigation system. Thus the proposed work has
several distinct advantages over the existing
technology.

REFERENCES
1. D. Ribas, P. Ridao, J. D. Tardos, and J. Neira.
Underwater slam in man-made structured
environments. Journal of Field Robotics,
25(11-12):898921, November-December
2008.
2. IEEE International Conference on Robotics
and Automation Shanghai International
Conference CenterMay 9-13, 2011, Shanghai,
China
3. International Journal of Scientific and
Research Publications, Volume 3, Issue 6, June
2013.
4. Intelligent Machines Design Laboratory
(spring 2008), Autonomous Navigation and
Obstacle Avoidance Vehicle EEL 5666: 1
st

written report, University of Florida.
5. J. Curcio, J. Leonard, and A. Patrikalakis.
Scout, a low costautonomous surface
platform for research in cooperative
autonomy, In OCEANS, 2005. Proceedings
of MTS/IEEE, pages 725 729 Vol.1, 2005.
6. J. C. Leedekerken, M. F. Fallon, and J. J.
Leonard, Mapping complex marine
environments with autonomous surface craft,
In 12
th
International Symposium on
Experimental Robotics, 2010.
7. Johann Bornstein and YoramKoren(April
1988)Obstacle avoidance with ultrasonic
sensors. IEEE journal of Robotics and
automation, vol.4, No.2.
8. Johann Bornstein and YoramKoren(April
1988)Obstacle avoidance with ultrasonic
sensors. IEEE journal of Robotics and
automation, vol.4, No.2.
9. J. Larson, M. Bruch, R. Halterman, J. Rogers,
and R. Webster, Advances in autonomous
obstacle avoidance for unmanned surface
vehicles In AUVSI Unmanned Systems North
America, 2007.
10. S. B. Williams and I. J. Mahon. Simultaneous
localisation and mapping on the great barrier
reef. In International Conference on Robotics


and Automation, 2004.
11. Vehicle Navigation and Obstacle Detection
System using RFID and GSM S.Saravanan,
T, Kavitha, Journal of Theoretical and Applied
Information Technology, April 2012.vol.38
No.2.
12. www.ccsinfo.com
13. ww1.microchip.com

Multi Scale Decomposition and Local Texture Analysis Based
Multi Modality Medical Image Fusion
Dr.G.Sathiyabama
1
Indhumathi
2
.R,Rajalakshmi.R
3
, Athira Ravi.
4

1
faculty,
2,3,4
student, Jeppiaar Engineering College,Chennai.

ABSTRACT

Image fusion technology is the synthesis process to
obtain one image from multiple images of the same
scene collected from multiple channels or at different
times with certain algorithms. This paper presents the
multimodality image fusion using stationary wavelet
decomposition and local energy model for medical
imaging system. The simulated results of this work
show that the fused images could improve the fusion
effect and obtain the hidden information. By this
method we can get more complementary information
and also, Better correlation coefficient, PSNR (Peak-
Signal-to-Noise Ratio) and less MSE (Mean square
error).

Keywords Stationary wavelet Transform, Peak Signal to
Noise Ratio, Mean Square Error, correlation coefficient
I. INTRODUCTION

Multi-sensor image fusion is the process of combining
relevant information from two or more images into a
single image. The resultant image will be more
informative than any of the input images[1]. With rapid
advancements in technology, it is now possible to obtain
information from multi source images to produce a high
quality fused image with spatial and spectral information
[2] [3]. The source images that can be used are
CT(ComputedTomography), MRI(Magnetic Resonance
Imaging), PET(Positron Emission Tomography). A single
medical mode of medical image cannot provide accurate
and comprehensive information and hence the medical
image fusion has become the focus of image research and
processing. The process of image fusion can be performed
at pixel, feature or decision-level [1]. Generally, pixel-
level techniques can be divided into spatial and transform
domain techniques [2]. Among the transform domain
techniques, the most frequently used methods are based on
multi scale transforms where fusion is performed on a
number of different scales and orientations. The multiscale
transforms usually employed are Pyramid Transforms [3],
the Discrete Wavelet Transform (DWT) [4], the
Undecimated Wavelet Transform (UWT)[5],[6]the Dual-
Tree Complex Wavelet Transform (DTCWT)[7].

In this paper Section II presents brief description of
existing image Fusion techniques, Section III presents
brief description on Stationary Wavelet Transform,
Section IV gives Performance Measures parameter of
Fusion techniques , Section V presents performance
comparison of those techniques and finally, conclusion is
presented in Section VI.
II. PRIOR WORK

There had been several research projects carried out to
provide to provide better fused outputs using image fusion
techniques. Some of the existing image fusion techniques
include Dual tree Complex technique [8], Curvelet
transform technique [9], Discrete Wavelet Transform [10].
All the existing techniques suffered from shift variant
problems which lead to artifacts along the edges in the
fused image.

III. MULTI SCALE DECOMPOSITION AND
LOCAL TEXTURE ANALYSIS BASED MULTI
MODALITY MEDICAL IMAGE FUSION

The Discrete Wavelet Transform is not a time invariant
transform. The way to restore the translation invariance is
to average some slightly different DWT, called
undecimated DWT, to define the stationary wavelet
transform (SWT). It is achieved by suppressing the down-
sampling step of the decimated algorithm and instead up-
sampling the filters by inserting zeros between the filter
coefficients.

Fig 1:Block diagram of proposed method

Fig 1 is the block diagram of Multi scale decomposition
and local texture analysis based multi-modality medical
image fusion. An medical image will have both low
frequency and high frequency components. Low
frequency components are known as visible components.
Intially the image is decomposed into low frequency and
high frequency components using multi-scale
decomposition technique.The low frequency components
are then fused using averaging method and high frequency
components are fused using energy model. Inverse multi
scale decomposition is done to reconstruct the image. The
quality of the image is analysed by calculating parameters
like Peak signal to noise ratio, Entropy and Root mean
Square error.
For many signals, the low-frequency content is the most
important part. It is the identity of the signal. The high-
frequency content, on the other hand, imparts details to the
signal. In wavelet analysis, the approximations and details
are obtained after filtering. The approximations are the
high-scale, low frequency components of the signal. The
details are the low-scale, high frequency components.
For many signals, the low-frequency content is the most
important part. It is the identity of the signal. The high-
frequency content, on the other hand, imparts details to the
signal. In wavelet analysis, the approximations and details
are obtained after filtering. The approximations are the
high-scale, low frequency components of the signal. The
details are the low-scale, high frequency components. The
Daubechies wavelet bases are a family of orthonormal
compactly supported scaling and wavelet functions that
have maximum regularity for a given length of the support
of the quadrature mirror filters. Daubechies wavelet filter
are used mainly for denoising applications.
(x)=2 1

(2xk) (1)
Daubechies wavelet filter is used in this project because
Daubechies wavelet type has balanced frequency
responses. It uses overlapping windows, so the high
frequency coefficient spectrum reflects all high frequency
changes. Therefore Daubechies wavelets are useful in
compression and noise removal of audio signal processing.
Daubechies wavelets encodes polynomials with two
coefficients, i.e. constant and linear signal components.
This ability to encode signals is nonetheless subject to the
phenomenon of scale leakage, and the lack of shift-
invariance, which arise from the discrete shifting operation
during application of the transform.
Fusion of low frequency coefficients
Considering the images approximate information
is constructed by the low-frequency coefficients, average
rule is adopted for low-frequency coefficients. Suppose
B
F
( x, y) is the fused low-frequency coefficients, then
B
F
( x, y)=
,,
(2)
Fusion of high frequency coefficients
High-frequency coefficients always contain edge and
texture features. We define region energy by computing
the sum of the coefficients square in the local window.
Suppose C
l
k
(x y) is the high-frequency CT coefficients,
whose location is (x,y) in the subband of kth direction at
lth decomposition scale. The region energy is defined as
follows

Algorithm
Step 1: Read the two source images, image I and image II
to be fused and apply as input for fusion.
Step 2: Perform independent Multi scale decomposition of
two images to get approximation(LL) and detail(LH, HL,
HH) coefficients.
Step 3: Apply pixel based algorithm for approximations
which involves calculating the average value of pixels of
source images I and II.
Step 4: Concatenation of fused approximations and details
gives the new coefficient matrix.
Step 5: Apply inverse Stationary Wavelet Transform to
reconstruct the resultant fused image.
Step 6: Display the fused output.
IV. PARAMETERS EVALUATION

The performance parameters used in this project provides
quantitative comparison between Discrete Wavelet
Transform and Stationary Wavelet Transform, mainly
aiming at measuring the definition of an image.

Peak signal to noise ratio
To determine the quality of a digital image human eyes
perception is the fastest approach. However, although this
criterion is effective in general, the results may differ from
person to person.[12]
PSNR=10*log10(255*255/MSE) (4)
where MSE (Mean Square Error) stands for the mean-
squared difference between the cover-image and the stego-
image. The larger PSNR is, the higher the image quality .
Entropy
[13]It is useful to determine the significant
information from the image based on the probability of
pixel values
S=- , ,

(5)
Where, p(x, y) is the probability of each gray level.


Correlation coefficient
It gives similarity in the small structures between
the original and reconstructed images. [14]Higher value of
correlation means that more information is preserved.
Coefficient correlation in the space domain is

Where, B is difference between fused image and its
overall mean value, A is difference between source image
and its overall mean value.
V. COMPARISON ANALYSIS BETWEEN
WAVELET WAVEFORM AND DISCRETE
WAVEFORM

The above table gives a comparison between Stationary
Wavelet and Discrete Wavelet transform. From the above
table it is clear that Peak Signal to Noise Ratio has been
considerably reduced in Stationary Wavelet Transform,
Correlation coefficient and Entropy has increased which
shows that the quality of fused outputs are better than
fused outputs of Discrete Wavelet Transform.
VI. CONCLUSION

Image fusion has become a common term for medical
diagnostics and treatment. In this project, Stationary
wavelet algorithm was successfully used to fuse the
medical images Computed Tomography and Magnetic
Resonance Imaging. From the experiments, we evaluated
the performance results of our proposed method using the
PSNR values and found that our proposed fusion method
provides good results. In addition, our proposed method
can be applied to other features in the noisy images.

REFERENCES
[1] Gaurav Bhatnagar , Directive contrast based multimodal
Medical image fusion in NSCT domain , IEEE Transactions on
Multimedia, vol 15,August 2013.
[2] Sabine Dippel, Martin Stahl, Rafael Wiemker, and Thomas
Blaffert, Multi scale Image fusion using the undecimated
wavelet transform with spectral factorization and non-orthogonal
filter banks, IEEE transactions on Image processing,vol
22,No.3,March 2013.
[3] Rui Shen ,Cross scale coefficient selection for volumetric
medical image fusion, IEEE Transactions on Bio-medical
Engineering,vol.60,No 4 April2013.
[4] Shutao Li , Image fusion with guided filtering ,IEEE
Transactions on Image processing, vol 22,July 2013.
[5] Nobuyuki otsu , Weighted shape based averaging with
neighbourhood prior model for multiple atlas fusion based
medical image segmentation, IEEE Signal processing letters
vol.20,November 2013.
[6] J. J. Lewis,An image fusion using wavelet and curvelet
transform, Global Journal of Advanced Engineering
Technologies vol-11,Issue-2,2012.
[7] Deepak Kumar Sahu, Different image fusion techniques,
International Journal of Modern Engineering Research, vol-
2,Issue-5,Sep-Oct 2012.
[8] Kunal Narayanan choudary ,On the shiftability of Dual tree
complex Wavelet transforms ,IEEE Transactions on Signal
processing, vol 58, January 2010.
[9] Eero P. Simoncelli, William T. Freeman, Edward H.
Adelson, and David J. Heeger,The curvelet transform for image
denoising, IEEE Transactions on Image
processing,vol.11,no.6,June 2002.
[10] Praveen varma, Multi-focus image fusion using wavelet
transform,International Journal of electronics and computer
science Engineering ISSN-2277-1956.
[11] V. S. Petrovic and C. S. Xydeas, Gradient-based
multiresolution image fusion, IEEE Trans. Image Process., vol.
13, no. 2, pp. 228237, Feb. 2004.
[12] Q. Zhang and B. L. Guo, Multifocus image fusion using
the non sub sampled Contourlet transform, Signal Process., vol.
89, no. 7, pp. 13341346, 2009.
[13] Tanish Zaveri,Multi-focus image fusion using wavelet
transform, International Journal of electronics and computer
science Engineering ISSN-2277-1956.


Smart Grids Distribution Feeder and Ring Bus Automation

Mrs. J Nithya
1
, AllwinRajkumar B
1
, Julien M A
2
, MelbinArasan A
3
Faculty
1
, UG Scholar
2,3,4
Jeppiaar Engineering Collrge, Chennai-119.

ABSTRACT
Smart grids are the way to the future, to ensure
proper utilization of the generated power and at the
same time ensuring the best delivery of power to the
consumers. In this project an automation system for
distribution feeders and the ring bus connected to them
will be implemented and demonstrated. The project
covers various aspects both these sections of a grid like
optimum utilization, safety, protection and switching to
ensure best delivery of available power to the
consumers. A prototype of a two feeders connected to a
ring bus will be implemented and the automation of the
same will be demonstrated using a computer and
wireless communication using RF communication,
between the computer and the smart grid system. When
there is an overload the component alone will be
disconnected from the circuit and when there is regular
flow it will be automatically connected. This can be
monitored and controlled using a computer connected
with the help of RF transceiver.
Keywords- smart grid, RF receiver, current sensor
I. INTRODUCTION

In todays world there is a scarcity of current
which leads to a lot of problems. The existing grids can be
made smart at various stages for the transmission and
distribution [1-2]. All the power which are being generated
are not reaching the consumers. There are a number of
reasons behind this but the main reason is power loss and
there are a number of reasons for which the power loss
occurs. Of all, the main reason is supplying power more
than the needs. This can be reduced by supplying power
according to the requirement of load which can be done
with the help of smart grids. A smart grid is a
modernized electrical grid that uses analogue or
digital information and communications technology to
gather information and act accordingly, such as information
about the behaviours of suppliers and consumers, in an
automated fashion to improve the efficiency, reliability,
economics, and sustainability of the production and
distribution of electricity [3].

Fig 1 Circuit Diagram of Smart Grid Section

Fig 2 Circuit Diagram of RF Transceiver

II. CIRCUIT DESCRIPTION

In the circuit connections shown in fig 1, the
microcontroller has four ports. The port A is for connecting
current sensors 1, port B for current sensor 2, port C for
connecting relays and port D for connecting the RF
transceiver. The relay and the current sensors are connected
to 5.5V and the RF transceiver is connected to 3.3V. One

switch in feeder one will always be in ON state and there
are two more switches which can be controlled in both the
feeders. When it is powered ON according the feeders
capacity and the fault current value the respective relays
will be closed or open. When there is no enough power
available the component will be isolated by opening the
relay. The entire process can be monitored and controlled
in a PC communicated with the help of RF transceiver.
III. SIMULATED RESULTS AND DISCUSSION
Table 1 Output Conditions

Fig 3 Relay 1 and Relay 2 ON



IV. HARDWARE DESCRIPTION
Smart Grid Section

(a)

Monitoring Section

(b)
Fig 6 Block Diagram

MICROCONTROLLER

Fig 7 Pin Diagram
PIC18(L)F45K22 I/P is the microcontroller used
in this project. The controller has peripheral features like
inbuilt ADC, required to get the signals from the various
sensors. It has a clock frequency maximum up to 48MHz
and hence faster than 8051.Based on RISC and Harvard
architecture so it will be even faster. Embedded C is used
for programming the microcontroller.

AC Current Sensor

Current transformers are designed to produce
either an alternating current or alternating voltage
proportional to the current being measured. The current
transformer used in this project can measure current up to
5Amps and its primary coil has 10 turns of copper wire
and the secondary has 350 turns of copper wire. For the
amount of currents flowing into the primary coil there is a
current output at the secondary coil correspondingly.
Relay
A relay is an electrically operated switch. Current
flowing through the coil of the relay creates a magnetic
field which attracts a lever and changes the switch
contacts. The coil current can be on or off so relays have
two switch positions and they are single pole double throw
switches.
USB PC Interface
The USB (Universal Serial Bus) port of a
computer is a general interface to which any external
devices can be connected. Most microcontrollers and other
embedded hardware have a conventional UART interface.
The UART interface is connected to the USB interface of
the computer.

RF Transceiver
It is a wireless device used to communicate
between devices connected to it. The microelectronic
circuits in the digital-RF architecture work at speeds up to
100 GHz. The objective in the design was to bring digital
domain closer to the antenna, both at the receiving and
transmitting ends using software defined radio (SDR).

V. CONCLUSION

Thus we have developed smart grid based
distribution feeder system for automated distribution of
power according the power required by the load and also
the fault isolating in the circuit. Overall, the approach is
found to be accurate, simple to implement and results in
quick reaction to sudden changes of load especially when
there is power fluctuations.Thus by making the grids
smarter the power loss can be minimised, the components
can be prevented from damage and all other components
can receive power except the component causing overload.

REFERENCES

[1] M. Saeedifard, M. Graovac, R. Dias, and R.
Iravani, DC power systems:Challenges and
opportunities, in Proc. IEEEPower and
EnergySociety Gen. Meeting, July 2010.

[2] R. Cuzner and G. Venkataramanan, The status
of DC micro-grid protection, in Proc. IEEE Ind.
App. Soc. Annu. Meeting, October 2008.

[3] D. Salomonsson, L. Soder, and A. Sannino,
Protection of low-voltage DC microgrids, IEEE
Trans. Power Del., vol. 24, no. 3, Jul. 2009

A Survey on Methods of Mobile Communication for the
Blind-Deaf
Dr. G. Sathiyabama
1
, J. Linda Magdeline
2
, K. Hemalatha
3
,
Pavithrakarpagambal. S
4
Faculty
1
, U.G Scholar
2,3,4

ABSTRACT
In this paper various types of mobile communication for
the blind-deaf people ids discussed. Different techniques
are used for this purpose. These techniques vary in
terms of hardware, software, language of
communication (i.e, Braille, Lorm, Malossi) used, etc.
The different devices which serve the purpose of
communication are studied and evaluated. Each of these
devices showcase different outlooks and concepts that
have been evolved over the years to cater to the need for
efficient communication amongst the blind deaf
community.

Keywords: Sensors, Vibration motors, Deaf-blind,
Disability, Glove, Interaction, Lorm, Mobile
Communication, Tactile Alphabet.

I. INTRODUCTION
Deaf blindness is a disability where an individual has little
or no useful sight and little or no useful hearing [12]. This
impairment requires the person to adapt a different
educational system to improve their communication with
the outside world. One example is Helen Keller. She used
sign language as her mode of communication. There are
about 500,000 deaf-blind individuals across our country,
India and less than 10% have access to any form of support.
There has been several research projects have been carried
out to provide assistive technologies for the deaf-blind
community. Mechanical hands for automated fingerspelling
or different glove systems have been developed over the
last decades which use the different sign language
techniques adopted by the blind-deaf people. Some of them
have been discontinued. There are only a few focusing on
mobile devices that are wearable, easily portable and
consequently a human-centered design approach. In this
survey Section II describes the different methods
previously proposed for communication of the blind-deaf
people, Section III describes the most recent development
in the communication devices
II. PRIOR WORK
There has been several research projects have been carried
out to provide assistive technologies for the deaf-blind
community. Mechanical hands for automated fingerspelling
or different glove systems have been developed over the
last decades which use the different sign language
techniques adopted by the blind-deaf people. Some of them
have been discontinued. Some of the prior work includes,
Tele Braille III [8], V Braille[9][10], DB Hand[6][11],
TWuist[12], etc. There are only a few focusing on mobile
devices that are wearable, easily portable and consequently
a human-centered design approach.

2.1. TACTILE PHONE LINE SIGNAL METHOD

Figure 1: TeleBraille III
This method was deviced in the year 2007 and was called
TeleBraille III. It enables a deafblind person and a person
using a TDD (Telecommunications Device for the Deaf) to
communicate by telephone [1]. This technology enables
face-to-face communications between a deafblind person
and a sighted person. TeleBraille is used in 2-way
communications, it combines a modified Ultratec
Supercom TDD with a modified 20-cell, 6-dot braille
display as shown in figure 1. Typed information is
translated and displayed via refreshable braille cells. The
Supercom TDD unit allows telephone communication.
Packaged with custom firmware and an added braille
keyboard, these units function together as TeleBraille III.
For telephone conversations, TeleBraille III functions as a
one-piece device by placing the telephone handset on the

acoustic coupler or connecting directly to the telephone
line. The braille display is then used for reading and either
the braille or standard keyboard can be used for writing. By
separating the two units, face-to-face conversation is easy.
The sighted partner uses the Supercom TDD device by
typing on a typewriter keyboard and seeing the messages
on a visual display. The deaf blind partner keys in
messages on the braille keyboard and reads messages on
the braille display.
2.2. COMMUNICATION METHOD BASED ON
INTERNAL VIBROTACTOR

Figure 2: V-Braille representation of the lowercase letter p on a
smartphone touchscreen
This method of communication was deviced in the year
2008 and was called the V-braille. It uses a standard
mobile phone to represent Braille characters using its touch
screen and internal vibrotactor[2]. The touch screen is
divided into six areas representing the dots of a standard
Braille cell. When users move their fingers over the screen
a vibrotactile cue indicates whether the dot is raised or not
for each area to represent Braille characters as shown in
figure 2. User studies with nine subjects found an average
Braille character reading time that varied between 4.2 and
26 seconds. [9] [10] Braille based devices are difficult to
use for deafblind individuals who are congenitally blind as
they typically never learn Braille and a different set of
technologies has therefore been developed that seeks to
automate the use of manual sign languages. The software
was developed for the G1 under the Android platform. The
screen is divided into six parts, to mimic the six dots in a
single Braille cell. When the part of the screen touched
(any point within the enclosing 1/6th region) represents a
raised dot, the phone vibrates. Touching dot areas 2 and 5
present stronger vibrations (shown by the solid line in
Figure), making it easier for users to differentiate between
vertically adjacent raised dot areas.
2.3. COMMUNICATION METHOD BASED ON
VERBAL INTERPRETATION OF GESTURES

The talking glove is a bi-directional aid developed for deaf,
deaf-blind, or non-vocal individuals. This glove allows its
user to interact verbally with other people. This glove can
interpret American fingerspelling, e.g., different finger
positions are used to generate letters which form words,
which are then converted into synthesized speech[4]. Using
voice recognition a deafblind user would be able to read
incoming speech on a portable refreshable braille display
module. The software to recognize finger spelling cost
$3,500 and can be used with a commercially available
gesture recognition glove.
The talking glove looks like a golf glove except that the
fingertips are removed and it has sensors on the back. A
person wearing the glove can "speak" to a hearing person.
The glove, worn on the right hand, converts manual finger-
spelling into synthesized speech which, at the moment, is
played back over a small pendant-like speaker worn around
the neck. It can be concealed under clothing. A hearing
person uses a small keyboard to reply to the handicapped
person. Messages from the keyboard are displayed on a
small screen so that they can be read by the deaf person or
on a portable Braille display so that they can be understood
by a deaf-blind person.
2.4 . COMMUNICATION METHOD BASED ON
COMBINATION OF DEVICE ORIENTATION AND
VIBROTACTILE FEEDBACK

Figure 3: TWuiST
The user scans through different orientations of their
mobile device where a target orientation is indicated using
a vibrotactile cue. Each orientation corresponds to a
message, i.e.the phone pointing forward indicates new
email.
In this project the author uses a combination of device
orientation and vibrotactile feedback to convey messages to
the user using particular hand orientations; effectively
turning the body into a display [5]. Users scan through
different possible orientations of their mobile device where
a haptic cue indicates a particular target orientation (See
Figure:3). For example, when the target
orientation of the phone is pointing forward this could
indicate a new voice-mail and when it is pointing down it
could mean a new text message. This type of display is
called a tactile-proprioceptive display as it uses the
proprioceptive sense to sense the orientation of the device
in an ear and eye free manner. A benefit of this approach is
that it can be implemented using hardware
(vibrotactor/accelerometer) that is already present in most
mobile devices.
III. COMMUNICATION BASED ON TEXT
INTO SEQUENCES OF TACTILE STIMULI
AND VICE-VERSA

Figure 4: The electronic Malossi keyboard
The electronic Malossi keyboard (top) has pressure points
which correspond to the letters of the Malossi hand
alphabet (above), a touch spelling system in which different
parts of the hand correspond to the letters of the alphabet.
This method was proposed in the year 2010 and the device
is called the DB-HAND. It consists of an input/output
wearable peripheral (a glove equipped with sensors and
actuators) that acts as a natural interface since it enables
communication using a language that is easily learned by a
deaf blind: Malossi method. Interaction with DB-HAND is
managed by a software environment, whose purpose is to
translate text into sequences of tactile stimuli (and vice-
versa), to execute commands and to deliver messages to
other users [6]. It also provides multi-modal feedback on
several standard output devices to support interaction with
the hearing and the sighted people. Tactile switches on the
surface of the palm need to be pressed and pinched whereas
the Lorm alphabet uses continuous gestures [11]. The DB-
HAND Glove is a bi-directional communication glove that
can interpret and convey the Malossi manual sign
language[7].
Table 1.1: Table of Survey on Mobile Communication For Deaf
Blind People

The table 1.1 shows the comparison between the different
techniques that have been proposed to meet the
communication needs of the blind-deaf community. From
this table one can conclude that the Lorm Glove can
significantly overcome the disadvantages that are
encountered by the other techniques in terms of increasing
fluidity and decreasing hardware complexity.
V. CONCLUSION

In this paper, the various techniques introduced to cater to
the communication needs of the bling-deaf from the most
recent technology has been reviewed. The comparison
between the different communication devices with each
other in terms of input module, output module, base
language, cost, hardware components and complexity is
done. Different innovative concepts are used in this paper
to increase efficiency, agility and compactness of the
communication devices. Based on this survey, it is to
conclude that the mobile lorm glove based on the method
of sensor input and vibrotactor output is the ideal
technology to meet the above mentioned criterions at a
considerable cost.

REFERENCES
[1] A-Z to Deafblindness http://www.deafblind.com.
[2] Tactile-Proprioceptive Communication Aid for Users
who are Deafblind by Vinitha Khambadkar _ Eelke
Folmer Department of Computer Science &
Engineering University of Nevada.
[3] VBraille-Haptic-Braille-Perception-using-Touch-screen.
[4] Hand Talk Implementation of a Gesture Recognizing
Glove.(http://www.academia.edu/2646783/Hand_TalkI
mplementation_of_a_Gesture_Recognizing_Glove)
[5] Sign Language Recognition using Sensor Gloves by
Yasir Niaz Khan Syed Atif Mehdi
[6] Jeong, Wooseob, Touchable online Braille Generator.
ASSETS Poster, ACM SIGACCESS Conference on
Computers and Accessibility (ASSETS 05).
[7] Legge, G. Madison, C. And Mansfield, J. Measuring
Braille Reading speed with the MNRead Test. Visual
Impairment Reasearch, Volume 1, Issue 3 December
1999, 131-145 (VIR 99)
[8] Caporusso, N.A wearable Malossi alphabet interface for
deafblind people. In Proc. AVI 2008, ACM Press
(2008), 445-448.
[9] Jeong, Wooseob, Touchable online Braille Generator.
ASSETS Poster, ACM SIGACCESS Conference on
Computers and Accessibility (ASSETS 05).
[10] Legge, G. Madison, C. And Mansfield, J. Measuring
Braille Reading speed with the MNRead Test. Visual
Impairment Reasearch, Volume 1, Issue 3 December
1999, 131-145 (VIR 99)
[11] Caporusso, N.A wearable Malossi alphabet interface for
deafblind people. In Proc. AVI 2008, ACM Press
(2008), 445-448.
[12] Hersh, M.A Johnson, M.A. Assistive Technology for
the Hearing-impaired, Deaf and Deafblind. Springer-
Verlag London Limited (2003), 257-273.

.


Controller Design for Quadcopter Using Labview With
Image Processing Techniques
Dr.G.Sathiyabama
1
, R.Praveen kumar
2
, A.V.K Viswanath
3
, R.Visnupriyan
4

Faculty
1
,B.E Students,
2,3,4
,Department of EIE, Jeppiaar Engineering College, Chennai.

ABSTRACT
This paper describes the modelling of a four rotor
vertical take off and landing (VTOL) unmanned
air vehicle known as Quadcopter air craft,which is
a new model design method for the flight control
of an autonomous Quadcopter.The aim is to
develop a model of the vehicle as realistic as
possible.The model is used to design a stable and
accurate controller to develop a Image controlling
method using LabView to obtain stability in flying
the Quadcopter flying object.
Keywords:Quadcopter ,LabView, Image processing,
Unmanned Aerial Vehicle (UAV)
I.INTRODUCTION
Due to the Earlier technology Quadcopter, which is
an unmanned aerial vehicle (UAV) was operated by
various techniques. At first Quadcopters mainly was
controlled by remote control. But when operating the
vehicle with remote it faced many disadvantages like
transmission losses were very high and time delay
took place where it cannot be kept under control [1-
5]. Later, Remote control method was replaced by
various methods like GSM ,vision based, Ball valve
method. But these methods faced many lags and
defects. So this paper presents the outline of
controlling the Quadcopter using LabView with
Image processing techniques which is more advanced
than previous techniques.
In this paper Mini Quadcopter prototype is
designed.The reference input(image) is given to the
Quadcopter by the program designed using LabView
and the image is acquired and detected.The program
is loaded to theArduino where it is an open source
controller .Quadcopter directions are controlled using
Servo motor mechanism. The transmitter is present
along side with the Servo motor where the PWM
signals get transmitted and it is received by the
receiving antenna where the receiver is present with
the Quadcopter. Section II consists of prior works
and section III consists of proposed work and section
IV gives the conclusion.
II. PRIOR WORK
As per the Literature Survey, Quadcopter was
controlled by various techniques.M.Achtelik,
T.Zhang ,K.Kuhnlenz&M.Buss developed a visual
tracking and control of a Quadcopter using stereo
camera system and inertial sensors in August 2009
which the Quadcopter was controlled using Ball
valves where confusion arises due to various colours
[6-8]. There is no stabilization control and only
particular colour taken at a single time. Two or more
colours cannot act at a single time.
A.Z.Azfar and D.Hazry developed a simple GUI
Design for monitoring of a remotely operated
Quadcoptervehicle[7] in March 2011 where
transmission losses are high and time delay took
place. Then for rescue operations ,A.Ryan and J.K
Hedrick invented a mode switching path plannar for
UAV assisted search and rescue [44] in 2005 where it
cannot be used in all directions, the pathplannar can
be operated only in a specified path. Later in Hong
Kong, D.Park, Moon-Soo park Suk kyo in 2001
developed a three degrees of freedom Attitude
control of free flying control wherethe UAV Vehicle
was operated by degrees of freedom but only three
degrees of freedom was applied. It was too hard to
define the relations of input and output in a view of
dynamics [9-12].
www.ijrde.com


L.Salih ,M.Moghavvemil, H.A.F Mohamed and K.S
Gaeid developed a Flight PID Controller Design for a
UAV Quadcopterin December 2010 where the
vehicle was operated and controlled by three
variables proportional integral and derivative
parameters. But it has some defects like particular
parameters can only be controlled and not universal.
III. CONTROLLER DESIGN FOR
QUADCOPTER USING LABVIEW WITH
IMAGE PROCESSING TECHNIQUES
Fig.1 Block Diagram of VI Based Quadcopter Control

Fig.1 shows the block diagram of the virtual
instrumentation Based Quadcopter control. Here the
stereo camera is placed in the Quadcopter and its
purpose is to continuously sense the light image i.e.
The Laser light. Then the light gets stored in the
image storage unit. Reference image is stored in the
Reference image storage unit. An open source
controller Arduino is placed in the Quadcopter which
compares the reference image with the currently
acquired image. Already programs using LabView is
dumped into the Arduino. So while comparing it with
the reference image the Arduino gener
program matching with the reference and the current
image. This is given to the driver circuit and hence
the driver makes the Quadcopter to fly in the desired
directions.
L.Salih ,M.Moghavvemil, H.A.F Mohamed and K.S
veloped a Flight PID Controller Design for a
in December 2010 where the
vehicle was operated and controlled by three
variables proportional integral and derivative
parameters. But it has some defects like particular
trolled and not universal.
CONTROLLER DESIGN FOR
QUADCOPTER USING LABVIEW WITH
IMAGE PROCESSING TECHNIQUES.

Fig.1 Block Diagram of VI Based Quadcopter Control
Fig.1 shows the block diagram of the virtual
control. Here the
stereo camera is placed in the Quadcopter and its
purpose is to continuously sense the light image i.e.
The Laser light. Then the light gets stored in the
image storage unit. Reference image is stored in the
An open source
controller Arduino is placed in the Quadcopter which
compares the reference image with the currently
acquired image. Already programs using LabView is
dumped into the Arduino. So while comparing it with
the reference image the Arduino generates the
program matching with the reference and the current
image. This is given to the driver circuit and hence
the driver makes the Quadcopter to fly in the desired

The Computer gets interfaced with LabView which is
connected with camera where image processing takes
place and connected with Arduino which is a open
source controller where the signals gets transmitted
by transmitting antennae. The signals are received by
receiving antennae and where two separate stations
are kept. The controller module which controls the
signals and motor is driven by the DC Brushless
motor.

Fig.2 Direction of Motor Rotation

Fig.2 shows the general block diagram of Quadcopter
control design,it explains the
rotation,and the Quadcopter control variables are the
balancing condition and levelling condition.
Quadcopter flies when it is interfaced with NI
LabView as the program based on LabView is loaded
first which is the first step and the colour matching
pattern is applied in it. Reference image is detected
and acquired (captured). The direction of motor
rotation clearly states that it is operated in clock wise
and anticlock wise directions. The program is now
loaded into Arduino (open source controller) which is
an open source controller. Now based on the
reference image the Arduino compares and generates
the program. Based on the program generated the
motor rotates in appropriate direction which moves
the Quadcopter and so transmission of signal losses
can be minimized and transmission
Fig.3 a&b diagrammatically represents the flow chart
for LabView and Arduino Interfacing.
e: pp- 452-455
453 | P a g e
The Computer gets interfaced with LabView which is
here image processing takes
place and connected with Arduino which is a open
source controller where the signals gets transmitted
by transmitting antennae. The signals are received by
receiving antennae and where two separate stations
ler module which controls the
signals and motor is driven by the DC Brushless

Fig.2 Direction of Motor Rotation
Fig.2 shows the general block diagram of Quadcopter
direction of motor
control variables are the
balancing condition and levelling condition.
Quadcopter flies when it is interfaced with NI-
LabView as the program based on LabView is loaded
first which is the first step and the colour matching
nce image is detected
and acquired (captured). The direction of motor
rotation clearly states that it is operated in clock wise
and anticlock wise directions. The program is now
loaded into Arduino (open source controller) which is
r. Now based on the
reference image the Arduino compares and generates
the program. Based on the program generated the
motor rotates in appropriate direction which moves
the Quadcopter and so transmission of signal losses
can be minimized and transmission time is reduced.
Fig.3 a&b diagrammatically represents the flow chart
for LabView and Arduino Interfacing.


Fig.3 a Flowchart for LabView

Fig.3 b Flowchart for Arduino Interfacing

Fig.4 Design of Quadcopter
Fig.4 shows the MiniQuadcopter prototype with four
Brushless DC Motors and four fans which rotate in
clockwise and anticlock wise directions. Receiver
which is present in the middle of the Quadcopter
prototype.
IV CONCLUSION
In this paper, a Quadcopter has been designed as an
unmanned aerial vehicle. It can be used in many
applications such as defence as well as security
provision. This method can overcome the present
manual errors such as transmission loss and time
delay when using manual RC remote control. . It
provides for benefits such as simple and easy to
understand codings. Main Advantage of Quadcopter
it can be controlled automatically without manual
error and it is of higher consistency. It provides
development in controlling methods , capturing
images,surveying purposes which is advanced than
present technology. The Qudcopter flies uptoan
height of 50 meters. In future camera can be placed
in the Quadcopter for monitoring purposes. It can
also be implemented in On Board Configurations in
which the Arduino will be placed in the Quadcopter
and camera can be used for acquiring both the
reference image and monitoring image.



REFERNCES
[1]. M. Achtelik, T. Zhang, K. Kuhnlenz and M.
Buss,Visual Tracking And Control Of A
Quadcopter Using A Stereo Camera System
And Inertial Sensors, Proceeding of the
International Conference on Mechatronics
and Automation (ICMA), pp.2863-
2869,August 2009.
[2]. Ryan and J. K. Hedrick,A Mode-Switching
Path Planner For UAV-Assisted Search And
Rescue, Proceeding of the 44th IEEE
Conference o0n Decision and Control, and
the European Control, 2005.
[3]. L. Salih, M. Moghavvemil, H. A. F.
Mohamed and K. S. Gaeid,Flight Pid
Controller Design For A UavQuadcopter,
Scientific Research and Essays, vol 5(23),
pp.3660-3667,December 2010.
[4]. Z. Azfar and D. HazrySimpleGui Design
For Monitoring Of A Remotely Operated
Quadcopter Unmanned Aerial Vehicle
Proceeding of the 7th International
Colloquium on Signal Processing and its
Applications (CSPA), Penang, pp.23-27, 4-6
., March 2011.
[5]. Rauf S. Anwar, M.A.Jaffer and A.A.
Shahid, Automated Graphical User
Interface test with Quadcopter Proceeding
of the 7
th
InternationalConference on
Information Technology 2010.
[6]. D.Park , Moon-Soo Park, Suk-Kyo Hong
Kong 2010. A Study on the three Degrees
of Freedom (DOF) Attitude Control of free
flying control
[7]. Proceeding IEEE International Symposium
vol 2 pp.1260-1265.
[8]. A.A.Mian and W.Daobo2008 , Non Linear
Flight Control Strategy for ana Under
Actuated Quadrotor Aerial robot
Proceeding of the International Conference
on Networking, Sensing and control
(ICNSC) pp. 938-942,April 2008.
[9]. Lei Zhang Tianguang Zhang HaiyanWu
,AlexanderBorst and KoljaKuhnlenz Visual
Flight Control of a Quadrotor using Bio
Inspired Motion Detector Institute of
Automatic Control Engineering (LSR).
TechnischeUniversitatMunchen Germany
February 20
th
2012.
[10]. StefLouwers (05990864) ,Sunil
Chokkanathapuram (0826874), QianQian
(0827493)Design and Implementation of
Quadcopter with Visual Control
TechnischeUniversiteit Eindhoven
University of technology October 16
th
2013.
[11]. OywindMagnussen
,KjellEivindSkjonhaug Modelling Design
and Experimental Study for a Quadcopter
System Construction University of Agder
Department of Engineering faculty of
Technology and Science 2011.
[12]. LabView Analysis concepts
National Instruments March 2004 Edition.


A Three phase Transformerless Buck Boost AC/AC
converter for Induction motor fed drive applications
Ms. M. Ammal Dhanalakshmi
1
, Ms. Ashly Mary Tom
2
, Dr. M. Sasikumar
3
1
PG Scholar,
2
Assistant Professor,
3
Professor and Head
Department of Electrical and Electronics and Engineering
Jeppiaar Engineering College, Chennai 600119, Tamilnadu, India.

ABSTRACT
This paper proposes a three phase transformerless
AC/AC converter which can perform both buck and
boost operations based on the voltage requirements.
This AC/AC converter is mainly proposed for the three
phase induction motor drives with the intention to
reduce the high inrush current of the conventional
motor used in industrial applications. The merits of the
proposed AC/AC converter can be understood with the
fact that the use of magnetic elements are eliminated
and the voltage stress of the active switches can be
reduced to half the supply voltage by carefully choosing
the capacitor values. In addition, the voltage applied to
the load increases/decreases gradually thereby
preventing the high inrush current from affecting the
load. The bidirectional operation of this converter is
possible by taking a common reference point between
the supply and the load side voltages. This particular
feature points out an added advantage for this proposed
converter. In this paper the performance of the
proposed converter is analyzed by simulating the results
for a 110/220 V, 1 KW induction motor.
Keywords Transformerless, AC/AC converter, inrush
current, bidirectional

I. INTRODUCTION
In the present scenario the use of three phase induction
motor is widely used in industrial applications. The
conventional AC/AC converter uses an auto transformer
which like any other electromagnetic transformers causes
interferences resulting in noise. There are also problems
associated with copper and core losses. In addition frequent
maintenance of transformers is required. In order to
overcome the above drawbacks, the use of auto transformer
is ignored in the proposed converter.
The use of multilevel inverters reduces the voltage stress to
a higher rate thus reducing the size of the semiconducting
switches. With the addition of switched capacitors along
with the multilevel level inverters can be used to regulate
the output voltage. In addition, with the common reference
point taken between the input and voltage makes the
AC/AC converter to operate in both buck and boost modes.
And also the voltage applied to the load increases/
decreases gradually the high inrush current is avoided
during the starting period.
In a three phase induction motor, the induced emf in the
rotor circuit depends on the slip of the induction motor and
the magnitude of the rotor current depends upon this
induced emf. When the motor is started, the slip is equal to
1 as the rotor speed is zero, so the induced emf in the rotor
is large. As a result, a very high current flows through the
rotor. This is similar to a transformer with the secondary
coil short circuited, which causes the primary coil to draw a
high current from the mains. Similarly, when an induction
motor starts, a very high current is drawn by the stator, on
the order of 5 to 9 times the full load current.

II. PROPOSED SYSTEM
The proposed converter consists of a three, single phase
bidirectional AC/AC converter which is powered by a three
phase supply. Each phase consists of a three level inverter
with four switches namely S
1
, S
2
, S
3
and S
4
. There are three
switch capacitors namely C
1
, C
2
and C
3
. The voltage stress
across the active switch is reduced to one half of the input
supply voltage. Finally the converter is connected to the
three phase induction motor load. A common reference
point is taken between the input and output supply voltages,
thus providing an ease in bidirectional operation.

A. Block Diagram of the proposed system
The block diagram of the proposed system is shown below
in Fig.1

Fig.1 Block diagram of the proposed system
The three phase supply of 110/220 V is given to AC/AC
converter where the voltage is either stepped up or stepped
down based on the input side connections. The output
voltage is given to the three phase induction motor load.


B. Circuit Diagram of proposed system

Fig.2 Single phase representation of the Proposed AC/AC
converter: (a) step-down configuration, (b) step-up configuration,
(c) gate drive signals, and (d) bidirectional switch model and its
practical implementation using two MOSFETs.
The single phase representation of the proposed converter
is shown Fig.2. Three such structures are required for
operating the AC/AC converter for a three phase supply. In
order to perform the buck operation, the input supply is
connected across both the capacitors, whereas to operate
the converter in boost mode, the input voltage supply is
connected across C
3
.

Fig.3 Performance of the proposed AC/AC converter during the
positive and negative half cycle of the input supply while
performing the Buck operation

The proposed ACAC converter operating as a buck
converter presents two operation stages per switching
period. During the positive half of the voltage, with the
converter in the step-down configuration, these stages can
be described as follows. First stage starts when switches S
1

and S
3
are turned ON. Capacitor C
2
discharges and
capacitor C
3
charges during the first part of this stage (t1
A). When their currents reach zero,C
2
starts to charge and
C
3
starts to discharge until the end of the stage ( t1 B).
Capacitor C
1
charges throughout this stage and the power
source vH delivers energy to the circuit. Switches S
1
and S
3


are turned OFF at the end of the first stage. This topological
stage is shown in Fig. 3(a).
Second stage starts when switches S
2
and S
4
are turned
ON. Initially, the power source receives energy from the
circuit, capacitor C
2
discharges, and capacitor C
3
charges
until their cur-rents reach zero (t2 A). After this, the
power source delivers energy to the circuit, capacitor C
2

charges and capacitor C
3
discharges until the end of the
stage (t2 A). Capacitor C
1
discharges throughout this
stage. Switches S
2
and S
4
are turned OFF at the end of the
second stage. This topological stage is shown in Fig.3(b).
After the second stage, another switching period starts from
the first stage. In the negative half-cycle of the grid, the
converter has similar operation stages with different current
directions, as can be seen in Fig. 3(c) and (d).

III. SIMULATION RESULTS AND DISCUSSIONS
The performance of the proposed AC/AC converter is
analyzed for both Boost operation.

An input voltage of 110 V is applied to the three phase
AC/AC converter.

Fig.4.1 Three phase Input voltage for boost operation

Fig.4.2 Three phase Stator voltage

Fig.4.3 Three phase stator current

Fig.4.4 Three phase rotor current


Fig.4.5 Speed of the three phase induction motor

Fig.4.6 Torque of the three phase induction motor
The waveforms obtained in the simulation are shown in
Fig.4.1, 4.2, 4.3, 4.4, 4.5 and 4.6.

TABLE I
Simulation Results
S.No Parameters Values
1. Input voltage 110 V
2. Stator voltage 220 V
3. Stator current 2 A
4. Rotor current 10 A
5. Speed 1760

IV. CONCLUSION
Thus, the performance of the is analyzed by simulating the
results for a 110/220 V, 1 KW induction motor. The
proposed three phase transformerless AC/AC converter
can perform both buck and boost operations based on the
voltage requirements. The high inrush current of the
conventional motor is highly reduced due to the
implementation of this AC/AC converter. The main
advantage of the proposed AC/AC converter is that the use
of magnetic elements are eliminated and the voltage stress
of the active switches are reduced to half the supply
voltage by suitable capacitor values. In addition, the
voltage applied to the load increases/decreases gradually
thereby preventing the high inrush current from affecting
the load. The bidirectional operation of this converter is
possible by taking a common reference point between the
supply and the load side voltages. This particular feature
points out an added advantage for this proposed converter.

REFERENCES
[1] T. B. Lazzarin, R. L. Andersen, G. B. Martins, and I. Barbi,
A 600 W switched-capacitor ac-ac converter for 220 V/110 V
and 110 V/220 V applications, IEEE Trans. Power Electron. ,
vol. 27, no. 12, pp. 4821 4826, Dec. 2012.
[2] A. Ioinovici, Switched-capacitor power electronics
circuits, IEEE Cir-cuits Syst. Mag., vol. 1, no. 3, pp. 3742,
Third Quarter 2001.
[3] G. Zhu, H. Wei, I. Batarseh, and A. Ioinovici, A new
switched-capacitor dc-dc converter with improved line and load
regulations, in Proc. IEEE Int. Symp. Circuits Syst. , 1999, vol.
5, pp. 234237.
[4] M. S. Makowski and D. Maksimovic, Performance limits of
switched-capacitor dc-dc converters, in Proc. 26th Annu. IEEE
Power Electron.Spec. Conf. , 1995, vol. 2, pp. 12151221.
[5] M. D. Seeman and S. R. Sanders, Analysis and optimization
of switched-capacitor dc-dc converters, IEEE Trans. Power
Electron. , vol. 23, no. 2,pp. 841851, Mar. 2008.
[6] B. Axelrod, Y. Berkovich, S. Tapuchi, and A. Ioinovici,
Single-stage single-switch switched-capacitor buck/buck-boost-
type converter,IEEE Trans. Aerosp. Electron. Syst. , vol. 45, no.
2, pp. 419430, Apr.2009.
[7] L. Tsorng-Juu, C. Shin-Ming, Y. Lung-Sheng, C. Jiann-Fuh,
and A. Ioinovici, A single switch boost-flyback dc-dc converter
integrated with switched-capacitor cell, inProc. IEEE 8th Int.
Conf. Power Elec-tron. , May/Jun. 2011, pp. 27822787.
[8] B. Axelrod, Y. Berkovich, and A. Ioinovici, A boost-
switched capacitor-inverter with a multilevel waveform, in
Proc. Int. Symp. Circuits Syst.,2004, vol. 5, pp. V-884V-887.
[9] M. On-Cheong and A. Ioinovici, Switched-capacitor
inverter with high power density and enhanced regulation
capability, IEEE Trans. Cir-cuits Syst. I, Fundam. Theory Appl.
, vol. 45, no. 4, pp. 336347, Apr.1998.
[10] Y. Hinago and H. Koizumi, A switched-capacitor inverter
using se-ries/parallel conversion with inductive load, IEEE
Trans. Ind. Electron. ,vol. 59, no. 2, pp. 878887, Feb. 2011.
[11] J. Bauman and M. Kazerani, A novel capacitor-switched
regenerative snubber for dc/dc boost converters, IEEE Trans.
Ind. Electron. , vol. 58,no. 2, pp. 514523, Feb. 2011.
[12] T. Siew-Chong, S. Kiratipongvoot, S. Bronstein, A.
Ioinovici, Y. M. Lai,and C. K. Tse, Adaptive mixed on-time and
switching frequency control of a system of interleaved switched-
capacitor converters, IEEE Trans.Power Electron., vol. 26, no.
2, pp. 364380, Feb. 2011.
[13] P. Fang Zheng, Z. Fan, and Q. Zhaoming, A magnetic-less
dc-dc converter for dual-voltage automotive systems, IEEE
Trans. Ind. Appl. , vol. 39, no. 2, pp. 511518, Mar./Apr. 2003.
[14] Z. Fan, D. Lei, P. Fang Zheng, and Q. Zhaoming, A new
design method for high-power high-efficiency switched-capacitor
dc-dc converters, IEEE Trans. Power Electron., vol. 23, no. 2,
pp. 832840, Mar. 2008.
[15] Z. Amjadi and S. S. Williamson, A novel control technique
for a switched-capacitor-converter-based hybrid electric vehicle
energy stor-age system,IEEE Trans. Ind. Electron. , vol. 57, no.
3, pp. 926934, Mar. 2010.



Battery-Charger with Microcontroller-Based Maximum
Power Point Tracking Technique
Bala Kalanithi
1
,B.Arunkumaran
2
,S.Rajesh
3
1
PG Scholar, Dept. of Mechatronics, Jeppiaar Engineering College, Anna University, India.
2
PG Scholar, Dept. of Power Electronics and Drives, Jeppiaar Engineering College, Anna University, India.
3
Assistant Professor, Dept. of Mechanical Engineering, Jeppiaar Engineering College, Anna University, India

ABSTRACT
Solar energy is a very large, inexhaustible source of
energy. The Renewable Energy as a source is
focused to bring the awareness towards the Green
Energy System which provides the pollution free
environment. Also it has no heavy mechanical
section and is free from noise. The power from the
sun intercepted by the earth is approximately
1.8X1011MW, which is many thousands of times
larger than the present consumption rate on the
earth of all commercial energy sources. Solar
tracking system which can be used as a power
generating method from sunlight. This method of
power generation is simple and is taken from
natural resource. This needs only maximum
sunlight to generate power. This project presents
for power generation and sensor based solar
tracking system to utilize the maximum solar
energy through solar panel by setting the equipment
to get maximum sunlight automatically. This
proposed system is tracking for maximum intensity
of light. When there is decrease in intensity of light,
this system automatically changes its direction to
get maximum intensity of light. The proposed
method is to design an electronic circuit to sense the
intensity of light and control the DC motor driver
for the panel movement, and construct a Buck-
Boost converter for to step-up and step-down the
voltage, and store the maximum utilized output
voltage in Lead-Acid Battery.
Keywords: Solar energy, Solar tracking, MPPT, Boost
Converter, Renewable energy,
Microcontroller
I.INTRODUCTION
The modern industries depend on solar system
for various applications which are most common in the
world. Solar energy is becoming increasingly attractive
as we grapple with global climate changes [1-4].
However, while solar energy is free, non-polluting, and
inexhaustible, solar panels are fixed. As such, they
cannot take advantage of maximum sunlight as weather
conditions and seasons change. A solar panel receives
the most sunlight when it is perpendicular to the suns
rays, but the sunlight direction changes regularly with
changing seasons and weather. Currently, most solar
panels are fixed, i.e., the solar array has a fixed
orientation to the sky and does not turn to follow the
sun. To increase the unit area illumination of sunlight
on solar panels, we designed a solar tracking electricity
generation system. The main use of this paper is to
utilize the maximum power from the sun. Now a day
we are in heavy need to use the solar power as in the
coming days everything we use might depend on this
kind of systems.
Pei-Wen Li et al., (2013) describe a fundamental
modeling for the optical features and control algorithm
has been developed for a solar stove heat collection
system which uses a giant Fresnel lens. The modeling
work helps to implement autonomous solar tracking in
the system by controlling the Fresnel lens to maintain a
stationary focal point on the heat-collecting surface of
the solar stove. Two-axis solar tracking for the
particular work was chosen. Ibrahim Sefa.,(2009) et al,
describe the Electric energy is essential to maintain
daily life and industrial activities. Turkey uses mainly
fossil fuels to produce electricity. Generation of
electricity from fossil fuels is the primary source of air
pollution and greenhouse gas emissions.
Arbab et al.,(2009) describe a computer tracking
system of solar dish with two-axis degree freedoms
based on picture processing of bar shadow. The sun
tracking system of a solar dish based on computer
image processing of a bar shadow is investigated. This
is done by using a camera to obtain the optimized
picture of a bar shadow on a screen by solar dish
displacements [5-8]. Chin et al.,( 2011) describe the
Design, modeling and testing of a standalone single
axis active solar tracker using MATLAB/Simulink.
This paper presents the design, modeling and testing of
an active single axis solar tracker. The compactness of
the proposed solar tracker enables it to be mounted
onto the wall.


Akkaya and Kulaksiz (2009) described a
microcontroller-based stand-alone photovoltaic power
system for residential appliances. In this study, a stand-
alone photovoltaic power system was designed and
implemented to operate residential ac-powered
appliances such as fluorescent lambs, fans etc [9-11].
Sun-tracker is implemented for improved efficiency of
the system by keeping the solar module perpendicular
to the suns incoming rays. Kuei-Hsiang and Li (2010)
described an intelligent maximum power point tracking
method based on extension theory for PV systems
Almukhtar et al.,(2013 ) describe the Design of Phase
Compensation for Solar Panel Systems for Tracking
Sun. The compensation for solar panel systems in order
to tracking sun has been studied and represented in its
equivalent closed loop control system [12-14].

II.EXPERIMENTAL ANALYSIS
The objective of this paper is to evaluate one of
the alternative technologies currently available in the
daily life to generate electricity from the solar cells.
Due to rising costs of conventional energy and their
limited resources, photovoltaic energy becomes a
promising energy with advantages such as the absence
of any pollution and the availability with more or less
large quantities anywhere in the world. Currently, there
is a big interest in solar energy applications especially
in regions with favourable climatic conditions.
II.1 BLOCK DIAGRAM OF PROPOSED
METHOD
Fig(1) shows that the light sensor detect the light
from sun through Ldr sensor ,controller circuit received
the signal from sensor and gave direction to the driver for
movement of solar panel with the help of x and y axis
driver. finaly buck-boost converter received the voltage
from panel to storage purpose in lead acid battery.

Figure1. Block Diagram
II.2 SELECTION OF MATERIAL
In this paper various components used to achive
required voltages like solar panel, lead acid battery,
motor driver, At mega 16 microcontroller, controller
circuit, buck-boost converter, ldr sensor etc. detail of
this materials are given below,
II.2.1 Solar Panel
The solar array or panel is defined as a group of
several modules electrically connected in series-
parallel combinations to generate the required current
and voltage. Solar Panel Absorbs Energy from sunlight
and converts into electrical energy by using photo
voltaic cell. The photovoltaic cell converts Sun light
Energy directly into electricity.
II.2.2 DC Geared Motor (X and Y Axis)
A Driver Motor mainly consists of a DC motor
and Gear System and controlled by Motor Driver
Circuit. Gear motors allow the use of economical low-
horsepower motors to provide great motive force at
low speed. They are used in lifts, winches, medical
tables, jacks and robotics and have high torque at
relatively low shaft speed.
II.2.3 Motor Driver (L298)
The Motor Driver Controls the Motor
Forward/Reverse Direction and Speed. This motor
driver module controls the speed and direction on 2 DC
motors, up to 40V 3A. The module itself is powered
and controlled from a main board but the motors are
powered from a separate power source. A battery can
be safely used to power the input on the power module
(a red module, like USB Client DP) and also power the
motors, by wiring the battery to both.
II.2.4 Driver Circuit (TLP 250)
The Photo-coupler consists of LED and a
integrated photo detector. This is suitable for gate driving
circuit of IGBT or power MOS FET. its photo-IC
couplers are housed in compact packages. They Have
Ability to drive IGBTs and power MOSFETs directly,
makes system design easier. The Photo Couplers offers
High Reliability for Drive Operations, simpler circuit
configurations and improves system Stability.
II.2.5 Microcontroller AT MEGA 16
AT Mega16 has High-performance, Low-power
Consuming 8 bit Microcontroller with Advanced RISC
Architecture. The Register File is optimized for the AVR
Enhanced RISC instruction set. Its Status Register


contains information about the result of the most recently
executed arithmetic instruction. The ALU operations are
divided into three main categories arithmetic, logical,
and bit-functions. Finally the Status Register is not
automatically stored when entering an interrupt routine
and restored when returning from an interrupt.
II.2.6 Battery
A Battery is two or more electromechanical cells
which store chemical energy and make it Available in
an electrical form. There are two types ,Primary
batteries (disposable batteries)Non Rechargeable &
Secondary batteries (rechargeable batteries). The lead
acid rechargeable batteries have a much harder life.

Figure2 Battery
They can withstand Vibrations, shock, heat, cold, and
have long Life .lead-acid batteries provide the greatest
energy density & longest life cycle and a large
environmental advantage.
II.2.7 Buck-Boost Converter
The buckboost converter is a type of DC-to-DC
converter that has an output voltage magnitude that is
either greater than or less than the input voltage
magnitude. Two different topologies are called buck
boost converter. Both of them can produce a range of
output voltages, from an output voltage much larger (in
absolute magnitude) than the input voltage, down to
almost zero.

Figure 3 Buck-Boost Converter
II.2.8 LDR Sensor
A photoresistor or light dependent resistor
(LDR)or photocell is a resistor whose resistance
decreases with increasing incident light intensity; in
other words, it exhibits photoconductivity. A
photoresistor is made of a high resistance
semiconductor. If light falling on the device is of high
enough frequency, photons absorbed by the
semiconductor give bound electrons enough energy to
jump into the conduction band. The resulting free
electron (and its hole partner) conduct electricity,
thereby lowering resistance.

Figure 4 LDR Sensor
III.RESULT AND DISCUSSION
Simulation is the imitation of the operation of a
real-world process or system over time. The act of
simulating something first requires that a model be
developed; this model represents the key characteristics
or behaviors/functions of the selected physical or
abstract system or process. The model represents the
system itself, whereas the simulation represents the
operation of the system over time. The simulation
results demonstrate the effectiveness and robustness of
the proposed method. Further, the proposed intelligent
MPPT algorithm needs less constructed data, and
nolearning procedure so it can be easily implemented
using a microcontroller in the future



Figure 5 Simulation Circuit
III.1 PERFORMANCES
In mathematics, and more specifically in graph
theory, a graph is a representation of a set of objects
where some pairs of objects are connected by links.
The interconnected objects are represented by
mathematical abstractions called vertices, and the links
that connect some pairs of vertices are called edges.
Typically, a graph is depicted in diagrammatic form as
a set of dots for the vertices, joined by lines or curves
for the edges. Graphs are one of the objects of study in
discrete mathematics.

III.1.1 PV Voltage and Current
The solar array or panel is defined as a group of
several modules electrically connected in series-
parallel combinations to generate the required current
and voltage

Figure 6 Voltage vs Current
III.1.2 Pulses
Two oscillators would be used for generating
square waves. The sensors are connected to these two
oscillators which generate square pulses in accordance
to the intensity of the light falling on the sensors

Figure 7 Pulses
III.1.3 Output Voltage
Battery stored the final output voltage from
Buck-Boost Converter. Power supplied by solar arrays
depends upon the insolation, temperature and array
voltage. It is also the function of the product of voltage
and current. By varying one of these two parameters;
voltage or current, power can be maximized.

Figure 8 Output
IV.CONCLUSION
The sun-tracker and charge controller systems
have been successfully implemented as explained. This
method combined the extension theory with a buck-
boost converter to speed up responses for reaching the
accurate MPP of solar panel arrays under solar
insolation and ambient temperature changes. Result
shows the MPPT controller can fast track the
maximum power point, has better response and lower
oscillation under rapid atmospheric conditions. The
simulation results demonstrate the effectiveness and
robustness of the proposed method. To design and
fabricate the sensor based solar tracking system
through microcontroller and show the experimental
results with simulation model. Power system could be
applied to small-scale systems such as residential
appliances, Electricity production, water treatment,
heating- cooling and ventilation, Architecture and
urban planning, Transport and reconnaissance etc.
REFERENCES
[1] Pei-Wen Li , Peter Kane , Matthew Mokler "
Modeling of solar tracking for giant Fresnel lens solar
stoves" in ELSEVIER SCINCEDIRECT, Available
online 16 August 2013.
[2] Ibrahim Sefa, Mehmet Demirtas, Ilhami olak
"Application of one-axis sun tracking system" in
Energy Conversion and Management ELSEVIER
SCINCEDIRECT Available online 26 July 2009.
[3] H. Arbab, B. Jazi, M. Rezagholizadeh " A computer
tracking system of solar dish with two-axis degree
freedoms based on picture processing of bar shadow"


in ELSEVIER SCINCEDIRECT Available online 8
August 2008.
[4] C.S. Chin et al describe the "Design, modeling and
testing of a standalone single axis active solar tracker"
using MATLAB/Simulink in ELSEVIER
SCINCEDIRECT Available online 2 February 2012.
[5] Ali H. ALmukhtar "Design of Phase Compensation
for Solar Panel Systems for Tracking Sun" in
ELSEVIER SCINCEDIRECT TerraGreen 13
International Conference 2013 - Advancements in
Renewable Energy and Clean Environment.
[6] Jensak Eakburanawat, Itsda Boonyaroonate,
"Development of a thermoelectric battery-charger
with microcontroller-based maximum power point
tracking technique" in ELSEVIER SCINCEDIRECT
Available online 11 October 2005. 55
[7] Nacer K. MSirdi a, Abdelhamid Rabhi b , Mouna
Abarkan a New "VSAS approach for Maximum
Power Tracking for Renewable Energy Sources
(RES)" The Mediterranean Green Energy Forum
2013, MGEF-13.
[8] R. mukaro, X.F. carelse and L. olumekor "first
performance analysis of a silicon-cell
microcontroller-based solar radiation monitoring
system solar energy" vol. 63, no. 5, pp. 313321,
1998
[9] Yusie Rizala, Sunu Hasta Wibowoa, Feriyadia
"Application of solar position algorithm for sun-
tracking system" International Conference on
Sustainable Energy Engineering and
Application[ICSEEA 2012]
[10] Kashif Ishaque a,b, ZainalSalam b,n "A review of
maximum power point tracking techniques of PV
system for uniform insolation and partial shading
condition Renewable and Sustainable Energy
Reviews" 19 (2013) 475488
[11] www.sunpowercorp.co.in
[12] www.tatapowersolar.com
[13] David A Rothery "An Introduction to the solar
system"
[14] Gordon McComb and Earl Boysen "Electronics for
Dummies



Implementation of GPS Based Security System for Safe Navigation
of Fisherman Autoboat
C.Vinothkumar
1
and B.Arunkumaran
2

1
Assistant Professor, Dept. of Electronics and Instrumentation, Sathyabama University, India.
2
PG Scholar, Dept. of Power Electronics and Drives, Jeppiaar Engineering College, Anna University, India.

ABSTRACT The Fisherman Autoboat system uses GPS
that stands for global positioning system which finds out
the location and position of the boat in ocean. The main aim
of this Autoboat system is to identify the zone. By using
ultrasonic sensor, iceberg in the sea can be found out while
travelling in boat or ship. As well as, to find the prediction
of tsunami MEMS is being used. If the fisherman crosses
the limitation of border it gives voice message, even though
if he try to move forward then automatically motor of the
ship/boat will stop. For weather report, temperature and
humidity sensor is used.
In the problematic time, from the control room the
navy section can trace out the ship/boat which has crossed
the border & in danger for the rescue, and also there is one
emergency switch available on the boat side that will
inform about the route to home. A ZigBee transmitter is
used to transmit these data from the transmitter side.

Keywords: GPS, SENSORS, ZIGBEE, MEMS, SAFE
NAVIGATION.

I. INTRODUCTION
GPS radio occultation has proved to be a powerful
tool for remotely sensing the Earths neutral atmosphere and
ionosphere. Through this project, we propose a novel approach
to retrieving marine troposphere profiles based on single
ground-based GPS occultation observations. A new retrieval
method uses the data from a ground-based receiver while the
GPS satellites rise or set at the local horizon in the direction of
the ocean [1]. The subsequent experiment was carried out on
the coast of the Yellow Sea from August 2010 to July 2011 in
this regard a GPS based system determines the location of
maritime boundary in the ocean which is not visible to the
mariners and they cross it. A GPS receiver is set on earth while
the satellite raises high in universe [2]. An ultrasonic sensor is
used for detection of iceberg and MEMS is implemented to
and crosses the boundary and detect vibration in the ocean .The
relevant information is visible on LCD also.
A temperature and humidity sensor is used to report
weather. The buzzer beeps when boat approaches the iceberg.
A ZigBee transmitter is used to transmit these data from the
transmitter side. The ZigBee receiver receives the transmitted
parameters and monitored through display unit. In this
transmitter is Master and it will be in constant place. While the
receiver enters into particular limit it automatically receives the
data from transmitter and displayed.

II. EXISTING SYSTEM
At present, there are few existing systems which help
to identify the current position of the boats/ships using GPS
system and view them in an electronic map. GPS provides the
fastest and most accurate method for mariners to navigate,
measure speed, and determine location. This enables increased
levels of efficiency for mariners worldwide and accurate
position, speed and heading are needed to ensure the vessel
reach its destination safely.
In the present system a GPS receiver is available in
the boat while the GPS satellite raises high in the universe. The
satellite observes the latitude and longitude of the boats
position and calculates for the location. So, the mariners can
find out the place where the boat is and also the direction of
motion.

The GPS equipped boat has the advantage of moving
in the right direction. As the ocean is so much spread that it is
almost impossible to find out in which direction one has to
navigate. This facility enables to find out the correct way to the
destination thereby increasing the level of convenience to the
mariners.

II.1 DISADVANTAGES OF EXISTING SYSTEM

1. Lack of awareness causes accident -The fishermen are not
aware of the maritime boundary and they tend to cross it. This
causes the situation of dispute and loss of life. Also, no such
system for warning is present when the boat crosses the
maritime boundary or when boat approaches any iceberg .So
this can lead to accidents.
2. No alarming and warning system is present for icebergs
and tsunami.-The boat is not well-equipped with any alarming
or security system that causes loss of lives. The fishermen are
not warned of any iceberg in the ocean, tsunami and crossing of
the maritime boundary. This causes improper attention during
the navigation process and unknowingly the fishermen had to
lose their lives.
3. No security system is present which causes loss of life-No
security from the rescue team can be obtained as no system for
informing the coastal guards is present. The coastal guards
have the rights to save the fishermen when they are in danger.


But since they are not known to the emergency situation, they
cannot send any help from their side.

III. PROPOSED SYSTEM

The proposed system is used to detect the maritime
boundary of the country where the long time dispute between
Sri Lanka and India still exists. This mainly happens when
fisherman crosses maritime border of neighboring country as
he is not aware of the limits in sea.
The proposed system uses a GPS receiver which
receives signals from the satellite and gives the current position
of the boat. With already known details of the latitude and
longitude of the maritime boundary, the microcontroller
calculates the current position and stored boundary positions
and indicates the fisherman that he has crossed the boundary by
an alarm system. It also uses a message transmitter to send
message to the base station which monitors the boats in the sea.
This system provides an indication to both fisherman
and to coastal guard. Thus the system saves the lives of the
fisherman or reduces the damages caused to them by Lankan
coast guards.
Additionally, sensors for iceberg detection and tsunami
prediction have been included. A report for weather can also be
obtained through temperature and humidity sensor. These all
features have been made cheap in order to be installed on boats
of fishermen for the reason being making the system
economical.

Figure-1: Block Diagram of Transmitter Section.

Figure-1 describes the block diagram of the transmitter
section. In transmitter section we have a GPS which detects the
location of the maritime boundary.
A sensor such as ultrasonic is used for detection of the
iceberg and MEMS for Tsunami. Humidity and temperature
sensor is used for weather report. The signals of all the sensors
are given to the microcontroller through ADC. With already
known set point in microcontroller maritime boundary is
detected. If the boat crosses the border a message through voice
board is heard and viewed through LCD. The motor gets
switched off as it crosses the boundary.



Figure-2: Image of Transmitter Section

Figure-3 has the receiver sections block diagram which is
located at the navy section near the sea shore. It has a buzzer
which beeps when the border is crossed and displayed through
the LCD. The information through WSN is obtained and a
microcontroller is used for this.

Figure 3: Block Diagram of Receiver Section

Figure 4: Image of Receiver Section

III.1 ADVANTAGES OF PROPOSED SYSTEM

1. Used to monitor and detect whether the ship is crossing its
border.
2. Prevent unnecessary problems with other states during
navigation through sea due to border crossing.
3. High Security and alarming system.
Senses icebergs and tsunami.
4. Detects weather report

III.2 HARDWARES USED

Microcontroller
Ultra sonic sensor
Humidity sensor
Temperature sensor
MEMS
ADC
Switch
Relay & motor


UART
GPS
WSN
Voice board

III.3 SOFTWARE IMPLEMENTED

Keil compiler
Embedded C

III.4 SOFTWARE DESCRIPTION OF THE PROPOSED
SYSTEM

The main purpose of using the microcontroller in our
Autoboat system is because high-performance CMOS 8-bit
microcontroller with 8K bytes of in-system programmable
Flash memory. By combining a versatile 8-bit CPU with in-
system programmable Flash on a monolithic chip, the Atmel
AT89S52 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded
control applications.
The programs of the microcontroller have been written in
Embedded C language and were compiled using KEIL, a
compiler used for microcontroller programming. The
communication between PC and the microcontroller was
established MAX 232 standard and those programs were also
done in C language.

III.5 ALGORITHM OF PROPOSED PROCESS
STEP 1 : START
STEP 2: Initialize data.
STEP 3: Temperature sensor and humidity sensor give
values.
STEP 4: If ultrasonic sensor and MEMS does not
detects signal.
STEP 5: No connection to ADC.
STEP 6: If ultrasonic sensor and MEMS detects
signal.
STEP 7 : Control goes to ADC
STEP 8: ADC control goes to microcontroller.
STEP 9: GPS transmits the location to microcontroller
in form of signals for calculation of boundary.
STEP 10: Microcontroller transmits signal 0, 1 to o/p
devices (LCD, voiceboard,monitor section) as per
limitation being crossed or not.
STEP 11: Microcontroller sends command to motor
to stop, change direction, and find weather
information.
STEP 12: Receiver section sends control.
STEP 13 : STOP

IV.RESULTS AND DISCUSSION
Through this system we have been able to locate the
maritime boundary for the fishermen and a proper warning
system in order to prevent their lives while they cross the Indo-
Srilankan maritime boundary unknowingly. Also there is a
system where the motor automatically gets off if the fishermen
cross the border.
Furthermore we have also been able to create an
alarming system for an iceberg or tsunami in the ocean. The
same can be viewed in the LCD display also.
The weather report and detection helps the mariner to
find the condition of weather and decide if it is suitable for
them to go in the ocean for navigation or not.

Table 1: Parameters and their mode of output

For iceberg alert
LCD glows and voice
message
For tsunami alert Display on LCD
For weather report Temperature and humidity
values display on LCD
For navigation direction Movements in X,Y and Z
direction
Crossing of maritime
boundary
Buzzer beeps and display on
LCD

V.SUMMARY AND CONCLUSION

This system implements GPS and Embedded system
together to create a security system. The fisherman, while
navigating crosses the maritime boundary, unknowingly as they
are unable to visualize it in the ocean which causes loss to its
life. Through this project a GPS based security system is
provided to the fisherman so that they can find out when they
are in danger.
In this system, a GPS receiver is being set up on the
earth and through satellite all the information regarding
crossing of the maritime boundary can be obtained by the
mariners and coastal guards .In case of any danger the rescue
team will be sent to them. A variety of sensors are used for
detection of other parameters. An iceberg can be detected
through ultrasonic sensor, Tsunami through MEMS and for
weather report temperature and humidity sensor is being
implemented.
This system is an implication of security system for
safe navigation of mariners auto boat. It is a helpful step in
saving lives of fisherman and a useful contribution to the
society.

VI. FUTURE WORK

This system done using GPS is a helpful system in
creating an automatic alert system to save mariners life that


are unable to find the marine boundary in the ocean by their
own and also unable to predict any iceberg or tsunami.
Additionally, it helps in finding weather conditions
In future, technological improvements can be done to
get the alert signals on smart phones to reduce complexity of
components and cost. The smart phones are now available at a
very cheap rate and are used by almost everyone in the society
without taking in account of the economical status. So it is an
imagination to use smart phones for the alert and warning in
place of the complex hardwares which will reduce complexity
and thereby enhancing ease of operation.

REFERENCES

[1] B.Parkinson and J.Spilker, GPS Global Positioning System Theory
and Applications. Danvers, MA: AIAA, 1996.
[2] D.H. Macqueen, G. W. Laguna, N. A. Bertoldo, R. A. Fertig and
S. L. Hunter, Development of a real-time radiological area
monitoring network for emergency response at Lawrence Livermore
National Laboratory, IEEE Sensors J , vol. 5, Apr. 2005, no. 4, pg-
565573.
[3] E.Kaplan, Understanding GPS Principles and Applications.
Norwood, MA: Artech House, 1996.
[4] M.Kayton and W. R. Fried, Avionics Navigation Systems, New
York: Wiley, 2nd edition, 1997.
[5] P.Hwang and R. Brown, Introduction to Random Signals and
Applied Kalman Filtering, New York: Wiley-Interscience, 2nd edition,
1992.


Remote Control and Fault Detection of Ac Motor by
Interfacing DAQ with LabVIEW
Mrs Shanmugakani P1, T G Vignesh2, M Srinath3, M Sabarish4
Faculty1,B.E Students,2,3,4,Department of EIE, Jeppiaar Engineering College, Chennai.

ABSTRACT: This paper describes the
remote control and fault diagnosis of induction
motor which is done in embedded technology and
LabVIEW. The paper mainly discusses about the
three faults like vibration fault, temperature fault
and current fault.
Keywords: LabVIEW, Max232, Microcontroller,
Triac
I. INTRODUCTION
Induction Motors are complex electro-mechanical
devices utilized in most industrial applications for the
conversion of power from electrical to mechanical
form. Induction motors are used worldwide as the
workhorse in industrial applications. Such motors are
robust machines used not only for general purposes,
but also in hazardous locations and severe
environments [1]. General purpose applications of
induction motors include pumps, conveyors, machine
tools, centrifugal machines, presses, elevators, and
packaging equipment. On the other hand,
applications in hazardous locations include
petrochemical and natural gas plants, while severe
environment applications for induction motors
include grain elevators, shredders, and equipment for
coal plants [2-3]. Additionally, induction motors are
highly reliable, require low maintenance, and have
relatively high efficiency. Moreover, the wide range
of power of induction motors, which is from
hundreds of watts to megawatts, satisfies the
production needs of most industrial processes.
Historically, mechanical gear systems were used to
obtain variable speed. Recently, electronic power and
control systems have matured tallow these
components to be used for motor control in place
of mechanical gears. These electronics not only
control the motors speed, but can improve the
motors dynamic and steady state characteristics. In
addition, electronics can reduce the systems
average power consumption and noise generation of
the motor. Induction motor control is complex due to
its nonlinear characteristics. While there are different
methods for control, Variable Voltage Variable
Frequency or Volts/Hertz is the most common
method of speed control in open loop. This method is
most suitable for applications without position
control requirements or the need for high accuracy of
speed control. The main aim of this project is to
control the speed of an induction motor and to detect
the faults. It is done with the help of embedded
technology. In order to achieve the objective, a few
important thing need to be accomplished before the
project can be done continued which are on other
hand induction motors are susceptible to many types
of fault in industrial applications [4]. A motor failure
that is not identified in an initial stage may
become catastrophic and the induction motor may
suffer severe damage. Thus, undetected motor faults
may cascade into motor failure, which in turn may
cause production shutdowns. Such shutdowns are
costly in terms of lost production time, maintenance
costs, and wasted raw materials. Although there are
many methods to detect the faults in induction motor
a user friendly software called as LabVIEW is mainly
used which may be used to find the fault present in
visual representation [5].
II. OBJECTIVE
1. To design and fabricate single phase
induction motor controller (Microcontroller
programming).

2. To control the speed of induction motor
using V/f control method through TRIAC
(Triode AC Switch)
In past it is difficult to design distance control of
system that requires lot of hard wires. Hence it
is merely impossible to predict an error or fault in
ac motor as lot of wirings involved. In addition if any
fault has occurred an operator has to go directly to
control room and solve it. The motor faults are due to
mechanical and electrical stresses. Mechanical
stresses are caused by overloads and abrupt load
changes, which can produce the bearing faults and
rotor bar breakage. On the other hand, electrical
stresses are usually associated with the power
supply. Induction motors can be energized from
constant frequency sinusoidal power supplies or from
adjustable speed ac drives. However, induction
motors are more susceptible to fault when supplied
by ac drives. This is due to the extra voltage stress
on the stator windings, the high frequency stator
current components, and the induced bearing
currents, caused by ac drives. In addition, motor over
voltages can occur because of the length of cable
connections between a motor and an ac drive. This
last effect is caused by reflected wave transient
voltages. Such electrical stresses may produce stator
winding short circuits and result in a complete motor
failure. According to published surveys, induction
motor failures include bearing failures, inter-turn
short circuits in stator windings, and broken rotor
bars and end ring faults. Bearing failures are
responsible for approximately two-fifths of all
faults. Inter-turn short circuits in stator windings
represent approximately one- third of the reported
faults. Broken rotor bars and end ring faults represent
around ten percent of the induction motor faults.
Several alternatives have been used in industry to
prevent severe damage to induction motors from
the above mentioned faults and to avoid
unexpected production shutdowns. Schedule of
frequent maintenance is implemented to verify the
integrity of the motors, as well as to verify abnormal
vibration, lubrication problems, bearings conditions,
and stator windings and rotor cage integrity. Most
maintenance must be performed with the induction
motor turned off, which also implies
production shutdown. Usually, large companies
prefer yearly maintenance in which the production is
stopped for full maintenance procedures.
Redundancy is another way to prevent
production shutdowns, but not induction motor
failure. Employing redundancy requires two sets
of equipment, including induction motors. The
first set of equipment operates unless there is a
failure, in which case the second set takes over.
This solution is not feasible in many industrial
applications due to high equipment cost and physical
space limitations. Thus, in this thesis an
alternative to these approaches is proposed.
Specifically, this thesis focuses on distance control of
induction motor thereby reducing the effort of an
operator. This method also makes it easier for trouble
shooting. In the next section the thesis addresses the
three main faults that occur commonly in induction
motor (i.e. temperature, current, vibration). The
methods developed in this thesis detect motor faults
without the necessity of invasive tests or process
shutdowns. Moreover, the presented methods
monitor the operating induction motor continuously,
so that human inspection is not required to detect
motor faults.
III. BLOCK DIAGRAM DESCRIPTION
The block diagram is divided into 2 main sections
namely
1. Controller section
2. PC section

Fig 1: Block Diagram (Controller and PC section)
IV. CIRCUIT DESCRIPTION
In remote control of induction motor the speed is
controlled by varying TRIAC (Triode AC Switch).
This is done in embedded system (PIC
microcontroller) and based on signal (PWM signal)
given to gate terminal of TRIAC the speed is varied.

Fig 2: Circuit diagram
In addition the program dumbed in microcontroller is
interfaced with LabVIEW through driver system
(MAX232 driver). The driver is installed through
UART seriaal nalog components needed to control
non- communication. When the speed in digital
electronic systems is varied it can be seen
visually as waveform through LabVIEW. In fault
diagnosis three main faults namely thermal, vibration
and power fault present in induction motor were
monitored and controlled.
1. Thermal fault- temperature sensor (LM35) is used.
2. Vibration fault- MEMS sensor is used..
3. Power fault- current transformer (HW 5A/15mA)
is used.

V. HARDWARE DESCRIPTION
Microcontrollers is a small computer on a single
integrated circuit consisting of a relatively simple
CPU combined with support functions such as a
crystal oscillator, timers, watchdog timer, serial and
analog I/O etc. it is used in automatically controlled
products and devices, such as automobile engine
control systems, remote controls, office machines,
appliances, power tools, and toys. By reducing the
size and cost compared to a design that uses a
separate microprocessor, memory, and input/output
devices, microcontrollers make it economical to
digitally control even more devices and processes.
The features of the MAX232 Driver is given below,
1. Provides RS232 voltage level outputs from
+5v supply.
2. Converts RS232 to TTL voltage levels.
3. It is used as drivers.

Fig 3: Pin details of MAX232 driver
A MAX232 driver shown in Fig 4.17 is mainly used
to interface PC and microcontroller through serial
communication and DB9 connector. A serial
communication used here is UART
communication.

Fig 4: MAX232 driver Results and discussion
A controller coding is written in C language using
MPLAB software. The designed coding is dumbed in
controller using pickit3 in order to perform
required operations.
VI. CONCLUSION AND FUTURE SCOPE
The objective, scope and fundamental requirements
of the project had been achieved. This project has
been done in order to overcome the defects present in
industries using ac motors like power consumption,
bearing defects, temperature faults and vibration
defects. The proposed model of LabVIEW cum
PIC Controller has several distinct advantages over
the existing technology. In existing technology, the
troubleshooting and remote technology is quite
complicated as lots of Hardwires involved. In report,
the difficulties involved in the existing technology
have been rectified by proposed methodology with
the help of embedded technology. Regarding remote
control of induction motor it is easy to control and
monitor the parameter without going to workstation.
In addition, the response time is very quick. In
another method called as fault diagnosis of induction
motor, the programming is easy although many
processes were carried out. In overall, choosing
LabVIEW as the human machine interface for the
implementation is a proper decision as it has various
types of applications and functions that are easy to
understand and use. The induction motor is modeled
in stationary reference frame of convenience. The
electrical and mechanical faults are introduced in the
simulation to analyze the motor under healthy and
faulty condition through LabVIEW and Embedded
Technology approach. Most work in this report is
from the experimental point of view. Our future
scope is to improve the manual control of ac motor,
hence if controlled the windings and interior parts of
ac motor are damaged. In addition the reliability of
temperature sensor is to be improved as it could not
withstand high operating current ranges.
REFERENCES
[1]. B. A. Welchko, T. A. Lipo, T. M. Jahns, and S.
E. Schulz, Fault tolerant three-phase ac motor
drive topologies; a comparison of features, cost, and
limitations, IEEE Trans. Power Electron., vol. 19,
no. 4, pp. 11081116, Jul. 2004.
[2]. C. Kral and K. Kafka, Power electronics
monitoring for a controlled voltage source inverter
drive with induction machines, in Proc. IEEE 31
st
Annu. Power Electron. Spec. Conf., 2000, vol. 1, pp.
213217.
[3]. Subhasis Nandhi, HamidAToliyat & Xiaodong
Li," Condition monitoring and fault diagnosis of
electrical motors- A review", IEEE Trans. Energy
conversion, Vol 20, No.4.
[4]. N. N. Barsoum and J. A. Roland,
Ethernet LabVIEW Control, Undergraduate Thesis,
Curtin University Sarwak Campus, Sarawak.
[5]. William.T.Thomson and Ronald J. Gilmore :
Motor Current signature analysis to detect induction
faults in Induction motor Drives
Fundamentals, induction motor diagnostic"I"MTC-
IEEE International Instrumentation &
Measurement Technology.

Invisible Image Watermarking System Using DWT
Technique for Video Authentication
1
S.U.Is Warya ,
2
A.Infanta Jennifer,
3
A.Dheepika,
4
Mrs .Sudha Rajayogan
123
U.G Scholar Jeppiaar Engineering college, Chennai-119
4
Professor , Jeppiaar Engineering College, Chennai-119

ABSTRACT: This paper proposed LS B
Information hiding algorithm which can lift
wavelet transform image. The idea behind the LS B
algorithm is to insert the bits of the hidden message
into the least significant bits of the pixels.
Achieving the purpose of information hiding with
the secret bits of information to replace the random
noise, using the lowest plane embedding secret
information to avoid noise and attacks, making
use of redundancy to enhance the sound
embedded in the way nature to be addressed. The
results showed that the proposed algorithm has a
very good hidden invisibility, good security and
robustness for a lot of hidden attacks. However,
the limitation of capacity has led us to think about
an improved approach which can be achieved
through hardware implementation systems with the
help of a programmable gate array (FPGA) board.
Keywords- Wavelet transform, LS b algorithm, FPGA

I. INTRODUCTION
In digital watermarking, a digital code, or watermark,
is embedded into a document so that a given piece of
information, such as the owners or authorized
consumers identity, is indissolubly tied to the data [1-
4]. This information can later prove ownership,
identifying appropriate person, trace the marked
documents dissemination through the network, or
simply inform users about the rights holder or the
permitted use of the data. Watermarking does not solve
all IPR problems; however, most researchers agree that
the technology is less mature than cryptography. Still,
its potential to provide reliable protection is already
attracting copyright holders [5].

II. BLOCK DIAGRAM DESCRIPTION

Fig 1: Block diagram of proposed system
The video to which a data is to be embedded is
converted to various frames [6-7]. A single frame
which is the image is taken and the data to be
transferred is embedded on to the image as a
watermark by using LSB (Least Significant Bit)
algorithm. The watermarked image which is in spatial
domain is converted to frequency domain using LWT
(Lifting Wavelet Transforms). The transformed
watermark image is sent to the receiver. The receiver
performs ILWT (Inverse Lifting Wavelet Transform)
and converts the image with frequency domain back to
spatial domain. Then the image is subjected to

extraction where the data is extracted from the image
[8-9].
III. LIFTING SCHEME
The lifting scheme is an alternative method of
computing the wavelet coefficients. Some of the
advantages of the Scheme is summarized below:
Requires less computation and less memory.
Easily produces integer-to- integer wavelet
transforms for lossless compression.
Linear, non linear, and adaptive wavelet transform is
feasible, and the resulting transform is invertible and
reversible.

Fig 2: LDWT
The hardware component used is FPGA Spartan3
and software used is Xilinx IS E, Xilinx platform
Studio, Matlab and Visual Basic.

Fig 3: FPGA SPARTAN 3
IV. MICROBLAZE
The MicroBlaze is a soft processor core designed for
Xilinx FPGAs from Xilinx. As a soft-core processor,
MicroBlaze is implemented entirely in the general
purpose memory and logic fabric of Xilinx FPGAs. It
is embedded within FPGA. It has 32 bit RISC. It
contains 1Mb S RAM and UART protocol. Algorithms
written in this processor are LSB and Impulse C.


Fig 4: Getting Input Image

Fig 5: Embedding Data

Fig 6: Watermarked Images

Fig 7: At the Receiver End

VI. CONCLUSION
Our system is used to hide the data in an image. This
image is taken from number of frames obtained from a
video. This allows only the authorized person to access
the data. For example any documents or messages
from one concern can be conveyed to other by hiding
the message in an image using this watermarked
technique. This image can be published publicly in any
social medias like internet. Only the authorized person
who has the correct code can obtain this data. The
unauthorized person cannot identify the embedded
data in the image as the data is embedded using LS B
algorithm.
REFERNCES:
[1]V. M. Potdar, S. Han, and E. C hang, A survey of
digital image watermarking techniques, in Proc.
IEEE Int. Conf. Ind. Informatics,Aug. 2005, pp. 709
716.
[2] A. D. Gwenael and J. L. Dugelay, A guide tour of
video watermarking,Signal Process. Image Commun.,
vol. 18, no. 4, pp. 263282, Apr. 2003.
[3] A. P iva, F. Bartolini, and M. Barni, Managing
copyright in open networks, IEEE Trans. Internet
Comput., vol. 6, no. 3, pp. 1826, MayJun. 2002.
[4] Y. S hoshan, A. F ish, X. Li, G. A. Jullien,
and O. Yadid-Pecht, VLSI watermark
implementations and applications, Int. J. Information
Technol Knowl., vol. 2, no. 4 pp. 379386, Jun. 2008.
[5] A S urvey on Different Video Watermarking
Techniques and Comparative Analysis with Reference
to H.264/AVC Sourav Bhattacharya, T. C
hattopadhyay and Arpan Pal
[6] Medical Image Watermarking: A Study on Image
Degradation B. P lanitz and A. Maeder, e-Health
Research Centre, ICT CSIRO, Brisbane.
[7] P. Saraju, N. mohanty, Ranganathan VLSI
architecture and chip for combined invisible robust and
fragile watermarking in proceedings of the IEEE
workshop on signal processing system , 2007.
[8] A. Mohamed Zuhair, A. Mohamed Yousef FPGA
based image security authentication in digital camera
using invisible watermarking technique International
journal of engineering science and technology, 2 (6)
(2010), pp. 17451751
[9] Jih P in Yeh, C he-Wei Lu, Hwei-Jen Lin, Hung-
Hsuan Wu Watermarking Technique Based On DWT
Associated With Embedding Rule International
Journal O f C ircuits S ystems And Signal Processing,
2 (4) (2010), pp. 7282.


Maintaining Lifetime of Wireless Ad-hoc Sensor Networks
by Mitigating Resource Depletion Attack using M-DSDV
K.Abirami
1
, R.Saranya
2
, Dr.P.Jesu Jayarine
3

PG Scholar, Jeppiaar Engineering College, Chennai, India

ABSTRACT
Ad-hoc sensor networks and routing data in
them is a significant research area. Vampire
attack is a resource depletion attack under
denial-of-service attack. Vampire attack is
draining of node life from wireless ad-hoc sensor
networks. Resource depletion attack
permanently disables networks by quickly
draining nodes battery power. Vampire attacks
are very difficult to detect because they attack
the node only by sending protocol-compliant
messages. PLGP with attestations (PLGP-a) is
used for identifying malicious attack. M-DSDV
routing protocol is used to detect and eliminate
the resource depletion attack from the network.

Keywords Ad-hoc networks, Denial of Service,
Resource depletion attack, Routing protocol,
Sensor networks

I. INTRODUCTION
Vampire attack means creating and sending
messages by malicious node which causes more
energy consumption by the network leading to slow
depletion of nodes battery life. This attack is not
specific to any protocol [1-5]. Vampire attack is
defined as the composition and transmission of a
message that causes more energy to be consumed
by the network than if an honest node transmitted a
message of identical size to the same destination,
although using different packet headers. Vampire
attacks are not protocol-specific, in that they do not
rely on design properties or implementation faults
of particular routing protocols [6-8]. The methods
to mitigate these types of attacks, including a new
proof-of-concept protocol that provably bounds the
damage caused by Vampires during the packet
forwarding phase. Thus the secured routing
protocol is required to mitigate the vampire attacks
which will decrease the battery life slowly [9-13].

1.1 CHARACTERISTICS OF VAMPIRE
ATTACKS
Exploit general properties of protocol
classes such as link state, distance vector, source
routing and geographic and beacon routing.
These attacks do not rely on flooding the
network with large amounts of data, but rather try
to transmit as little data as possible to achieve the
largest energy drain, preventing a rate limiting
solution. Since Vampires use protocol-compliant
messages, these attacks are very difficult to detect
and prevent.
1.2 TYPES OF VAMPIRE ATTACKS
Vampire attacks are nothing but a new class of
resource consumption attacks (denial of service
attack) that use routing protocols to permanently
disable ad hoc wireless sensor networks by
decreasing nodes battery power [14-15].
A discussion about the carousel attack and stretch
attack are given below.
1.2.1 CAROUSEL ATTACK
In this type of attack, a malicious node sends a
packet with a route composed as a series of loops
with the same node appears in the route many
times.


Fig 1.1 Carousel attack

1.2.2 STRETCH ATTACK
In this type of attack, a malicious node constructs
artificially long routes from the source in spite of
shorter routes being available. It increases packet
path lengths, causing packets to be processed by a
number of nodes that is independent of hop count
along the shortest path between the adversary and
packet destination.

Fig 1.2 Stretch attack

This attack causes the packets to be travelled a long
route in the network.

II. SYSTEM ARCHITECTURE
The network is composed of multiple nodes. An
energy based mechanism to detect the Vampire
Attacks is implemented.

Fig 2.1 System Architecture
Once we constructed a network, the malicious
message will be send from the attacker node to any
of the normal node. So that the normal nodes
energy will be consumed more than the normal
message level So that we can conclude that the
node is affected by the attack. Once the node is
identified as the attacked node, the node is
eliminated from the network. Hence the attacked
node is not able to communicate with the other
nodes in the Network. It uses one-way hash chains
to limit the number of packets sent by a given node,
limiting the packet transmission rate. Energy usage
by malicious nodes is to be reduced, since they can
always unilaterally drain their own batteries.

III. TECHNOLOGIES INVOLVED
The proposed system involves lot of technologies
which are explained below:
3.1 PLGP
PLGP is a clean-slate secure sensor network
routing protocol which is used to detect the
vampire node. PLGP consists of two levels:
1. Topology Discovery Phase
2. Packet Forwarding Phase
3.1.1 TOPOLOGY DISCOVERY PHASE
Discovery phase organizes nodes into a tree that
will later be used as an addressing scheme that is
repeated on a fixed schedule and discovery

deterministically organizes nodes into a tree that
will later be used as an addressing scheme. Whens
discovery begins, each node has a limited view of
the network that is the node knows only itself.
Nodes discover their neighbors using local
broadcast, and form ever expanding
neighborhoods, stopping when the entire network
is a single group. Throughout this process, nodes
build a tree of neighbor relationships and group
membership that will later be used for addressing
and routing.
3.1.2 PACKET FORWARDING PHASE
During the forwarding phase, all decisions are
made independently by each node. When receiving
a packet, a node determines the next hop by finding
the most significant bit of its address that differs
from the message originators address. Thus, every
forwarding event shortens the logical distance to
the destination, since node addresses should be
strictly closer to the destination.
3.2 PLGP WITH ATTESTATIONS (PLGP-a)
The verifiable path history is added to every PLGP
packet. The resulting protocol, PLGP with
attestations (PLGP-a) uses this packet history
together with PLGPs tree routing structure so
every node can securely verify progress, preventing
any significant adversarial influence on the path
taken by any packet which traverses at least one
honest node. These signatures form a chain
attached to every packet, allowing any node
receiving it to validate its path. Every forwarding
node verifies the attestation chain to ensure that the
packet has never traveled away from its destination
in the logical address space.
3.3 M-DSDV (MODIFIED DESTINATION
SEQUENCED DISTANCE VECTOR)
M-DSDV is a routing protocol that makes use of a
table driven routing scheme for Mobile Ad-Hoc
Networks. The main contribution of the algorithm
is to solve the routing loop problem in which two
nodes adjacent to each other routes the data
continuously to each other in order to reach certain
other node. This can lead to a serious overloading
of the nodes capacity to handle data and can lead to
the failure of the nodes. In distance vector routing,
each router maintains a routing table indexed by,
and containing one entry for, each router in the
subnet.
This entry contains two parts:
The preferred outgoing line to use for that
destination
An estimate of the time or distance to that
destination.
3.4 ENERGY CONSUMPTION MODEL
The intermediate node may be vampire node which
is determined with the help of energy consumption
model where the energy of node is calculated by
using the below Eq. 1. The node which consumes
more energy than the normal level of energy
consumption and which does not further forward
the packet among the network, then it is taken as a
vampire node.
E
node
= E
on-off
+ E
off-on
+ E
node-run (1)
Where,
E
on-off -
One time energy consumption of closing
node operation.
E
off-on -
One time energy consumption of opening
node operation.
E
node-run -
Energy consumption of sensing node
operation.
3.5 INDEXING NUMBER TECHNIQUE
Indexing no technique is nothing but a
testing/verification method which allocates
duplicate address to each and every node. The
signing of each node is carried out by one-way
hash chaining method. Source node has the address
of destination node. So source (good) node sends
the packet with header which includes both the
source and destination address. If an intermediate
node does not forward the packet to the neighbour
nodes, then it is considered as a vampire
(malicious) node. Then with the help of on-demand
routing protocol the vampire node has to be
removed from the network and then an alternate
route has been determined and the packet has been
forwarded to the destination node via several
intermediate nodes. Therefore the packet has been
reached the destination node without any time
delay.
IV. IMPLEMENTATION AND RESULTS
M-DSDV (Modified Destination Sequenced
Distance Vector) is a routing protocol that makes
use of a table driven routing scheme in an on
demand routing nature for Mobile Ad-Hoc
Networks. The main contribution of the algorithm
is to solve the routing loop problem. The
performance analysis of proposed routing protocol

is tested using NS2 simulator. The parameters used
are summarized in Table. 1.
Table.1 Parameters Used
The detection of malicious node deals with the
malicious node increases energy consumption and
packet dropping rate is called as rate of detection.
Here the rate of detection is defined as the number
of nodes which are identified as malicious in the
network to the number of actual malicious node.

Fig. 7 Rate of Malicious node detection
Thus the M-DSDV routing protocol concept
increases overall lifespan of network by energy
efficient routing paths.

V. CONCLUSION
Vampire attacks has been defined as a
new class of resource consumption attacks that use
routing protocols to permanently disable ad hoc
wireless sensor networks by depleting nodes
battery power. Defenses against some of the
forwarding-phase attacks has been proposed and
PLGP-a, the first sensor network routing protocol
that reduces the damage from Vampire attacks by
verifying that packets consistently make progress
toward their destinations. The routing protocol has
been used at the time of routing to make efficient
energy utilization during the packet forwarding
phase. But it has not offered the satisfactory
solution during topology construction which is left
for future work.

REFERENCES
[1] J.H. Chang and L. Tassiulas, Maximum
Lifetime Routing in Wireless Sensor Networks,
IEEE/ACM Trans. Networking, vol. 12,no. 4, pp.
609-619, Aug. 2004.
[2] J. Deng, R. Han, and S. Mishra, INSENS:
Intrusion-Tolerant Routing for Wireless Sensor
Networks, Computer Comm., vol. 29,no. 2, pp.
216-230, 2006.
[3] S. Doshi, S. Bhandare, and T.X. Brown, An
On-Demand Minimum Energy Routing Protocol
for a Wireless Ad Hoc Network, ACM
SIGMOBILE Mobile Computing and Comm. Rev.,
vol. 6, no. 3, pp. 50-66, 2002.
[4] S. Bhandare, S. Doshi, and T.X. Brown, A
Progressive Energy Efficient Routing Protocol
(PEER), ACM SIGMOBILE Mobile Computing
and Comm. Rev., vol. 6, no. 3, pp. 50-66, 2002.
[5] Y.-C. Hu, D.B. Johnson, and A. Perrig,
Ariadne: A Secure On Demand Routing Protocol
for Ad Hoc Networks, Proc. MobiCom,2002.
[6] Y.-C. Hu, D.B. Johnson, and A. Perrig, Packet
Leashes: A Defense Against Wormhole Attacks in
Wireless Ad Hoc Networks, Proc. IEEE
INFOCOM, 2003.
[7] B. Karp and H.T. Kung, GPSR: Greedy
Perimeter Stateless Routing for Wireless
Networks, Proc. ACM MobiCom, 2000.
[8] B. Umakanth and J. Dhamodar, Detection Of
Vampire attacks using EWMA in Wireless Ad Hoc
Sensor Networks, IJETT, Aug.2013.
[9] Eugene Y. Vasserman and Nicholas Hopper,
Vampire attacks: Draining life from wireless ad-
hoc sensor networks, IEEE Transaction on
Network Security for Technical Details, June 17,
2013.
[10] A.D. Wood and J.A. Stankovic, Denial of
Service in Sensor Networks, Computer, vol. 35,
no. 10, pp. 54-62, Oct. 2002.
[11] G. Yang, M. Gerla, and M.Y. Sanadidi,
Defense Against Low-Rate TCP-Targeted Denial-
of-Service Attacks, Proc. Ninth Intl Symp.
Computers and Comm. (ISCC), 2004.
[12] J. Yuan, Z. Li, W. Yu, and B. Li, A Cross-
Layer Optimization Framework for Multihop
Multicast in Wireless Mesh Networks, IEEE J.
Total no of nodes 30
Simulation Duration 50[s]
Simulation tool NS2
Protocol Used M-DSDV
Packet Size 512[bytes]

Selected Areas in Comm., vol. 24, no. 11, pp.
2092-2103, Nov. 2006.
[13] M.G. Zapata and N. Asokan, Securing Ad
Hoc Routing Protocols, Proc. First ACM
Workshop Wireless Security (WiSE), 2002.
[14] A.J. Goldsmith and S.B. Wicker, Design
Challenges for Energy- Constrained Ad Hoc
Wireless Networks, IEEE Wireless Comm., vol. 9,
no. 4, pp. 8-27, Aug. 2002.
[15] R. Govindan and A. Reddy, An Analysis of
Internet Inter-Domain Topology and Route
Stability, Proc. IEEE INFOCOM, 1997.


Transformerless Shunt Hybrid Active Power Filter for
Medium Voltage Drive System
B.Karthika
1
, N. Tejesvi
2
, Neenu Therese Antony
3
, S. Shantha Sharmila
4
,
Dr. M. Sasikumar
5

1,2,3,4
PG Scholar,
5
Prof/HOD, Jeppiaar Engineering college, Chennai.

ABSTRACT
This paper investigates mitigation of current
harmonics using neutral point clamped (NPC) based
shunt hybrid active power filter (SHAPF) to
improve the power quality. This proposed topology
reduces the rating and size of the filter components.
The main objective of this work is to design and
analyze the hybrid shunt active power filter strategy
using d-q theory based reference current extraction
technique for compensating current harmonics and
to enhance the power factor. The shunt hybrid
active power filter is the combination of shunt active
and passive power filter. In this active power filter
multilevel inverter is used instead of single level
inverter for compensating current harmonics and
power factor correction.

Keywords: shunt hybrid active power filter
(SHAPF), neutral point clamped, Non linear loads.

I.INTRODUCTION
The recent growth in the use of nonlinear load such as
UPS, SMPS, refrigerators, inverters, laser printers,
electronic ballast, fax machines, discharge lamps, arc
furnaces, battery chargers, electronic power supplies,
has caused a greater awareness on power quality. Non-
linear loads create harmonics by drawing current in
abrupt short pulses, rather than in a smooth sinusoidal
manner. Current harmonics present in the system leads
to distortion in power factor, excess power is consumed
by the load, overloading and overheating of
equipments, harmonic resonance in the utility,
increased losses, interference to communication
network, malfunction of instrument, failure of electrical
machines etc. Between the different technical options
available to improve power quality, active power filters
have proved to be an important alternative to
compensate for current and voltage disturbances in
power distribution systems [5]. Passive filters have
been used to suppress current harmonics and
compensate reactive power in distribution power
systems [1]. Yet, passive filters have disadvantages
such as resonance problems, low dynamic performance
and filtering characteristics that are easily affected by
small variations of the system parameters [2],[7].
Active power filters (APFs) can overcome the
disadvantages in passive power filters (PPFs), but their
initial and operational costs are relatively high [2], [6]
because the dc- link operating voltage should be higher
than the system voltage. This slows down their large
scale application in distribution networks. Despite
various advantages of an active power filter, the
complexity and cost have always been drawbacks.
Combining passive elements with active power filter,
results in a hybrid configuration which brings down the
cost of active filter drastically.
The Hybrid active power filter topologies in [2][8]
consist of many passive components, such as
transformers, capacitors, reactors, and resistors, thus
increasing the size and cost of the whole system. In this
active power filter, multilevel inverter is used instead of
case single level inverter for compensating current
harmonics and power factor correction [3-6]. The
various control techniques are introduced for shunt
hybrid active power filter are discrete Fourier
transformation, fast Fourier transformation, generalized
integrators and variants, unit vector template generation
techniques and synchronous detection algorithm are the
techniques used [9-14]. These conventional techniques
have complex mathematical model and performance
under dynamic load change condition are very complex
[15-21].
In proposed method, an attempt is made to
estimate cost effectiveness and transformerless shunt
hybrid active filter to provide better compensation of
current harmonics. The hybrid filter is controlled such


that harmonic currents of the nonlinear loads flow
through passive filter such that only fundamental
frequency component of load current is to be supplied
by the AC mains.
II. HYBRID ACTIVE FILTER
The diagram of the proposed hybrid active filter is
shown in fig.1. The hybrid active filter system is
installed in parallel with a harmonic-producing load.
The active filter acts like an isolator which forces
harmonic components in the load current to flow
through the passive filter network. By proper design of
the hybrid active filter, most lower order 7
th
harmonics,
i.e. 5
th
, , 11
th
, 13
th
, can be effectively canceled by
generating, or injecting harmonic currents of the same
magnitude and frequencies but with 180 phase shift
with the unwanted harmonic currents in the ac system.

Fig.1 Shunt hybrid active filter

III. COMPENSATION PRINCIPLE
To describe the operational principle of the hybrid
active filter, a simplified one line diagram at
fundamental frequency f
1
and harmonic frequency f
h

are shown in fig.2. The connection between the voltage
source converter and the passive filter are directly
connected without the use of transformer.

Fig.2 Operation of hybrid filter (a) at fundamental frequency f1 (b) at
fundamental frequency fh
At the fundamental frequency f1, in order to reduce the
VA rating of the converter in fig.1, the converter
current 1f1 is controlled such that the fundamental
frequency voltage drops across the passive filter, i.e. the
fundamental frequency voltage drops across the active
filter is Vf1=0. This results in large voltage rating
reduction of the active filter.
Under this condition, in the fig.2(a)
I
f1
= -V
L1
(1)
Z
f1
= Z
s1
i
L1
-V
s
(2)

Z
f1
+Z
s1
At harmonic frequency f
h
as shown in Fig 2(b), the
filter must supply harmonic currents such that no
harmonic currents flow into the utility.
Therefore,
I
fh
= i
Lh
(3)

V
fh
= -Z
fh
i
fh
(4)
Equation V
fh,
shows that the passive filter should be
designed to show a low impedance at the dominant
harmonic frequencies, thus reducing the voltage rating
of the active filter. From above, the filter current,
i
f
= i
f1
+ i
fh
(5)
and

V
f
= V
fh
(6)
It is now clear that at the same compensating current,
minimizing Z
f
at the dominant harmonics helps to
minimize the dominant harmonic voltage, thus reducing
the VA rating of the active filter.
IV. CONTROL STRATEGY OF ACTIVE POWER
FILTER


The converter is controlled to provide fundamental
current, which forces the passive filter to support the
line frequency voltage and to draw harmonic current to
compensate the load current harmonics.
Fig.3 shows the control block diagram of the active
power filter which consist of three parts: a circuit for
extracting the harmonics to be injected to the system,
circuit estimating the fundamental current for the
passive filter sustaining fundamental voltage, and
circuit adjusting inverter voltage.

Fig.3 Control Block diagram of active filter

A.) Harmonic Current Extraction
It is necessary to obtain the dominant harmonic current
as the control reference to the active filter. The
reference source currents are generated using
synchronous reference frame theory. The instantaneous
power theory or Active Reactive (PQ) theory consist
of algebraic transformation of the three phase currents
in the a-b-c coordinates to --0 coordinates.

Id cos cos(-a) cos(+a) Ia
= Ib (8)
Iq sin sin(-a) sin(+a)
Ic

Where, cos and sin are obtained from three phase
PLL. This Id and Iq are separated into two parts namely
average and oscillatory parts as

I
d
=

I
d1
+I
d2
(9)

I
q
= I
q1
+ I
q2
(10)
The inverse Park transformation is give below,

I
a
*
cos sin
I
b
* = 2/3 I
d
*
cos(-a) sin(-a) (11)
I
c
* I
q
*
cos(+a) sin(+a)

From the equations,

P=Vi+Vi (12)

Q= Vi- Vi (13)
the real and reactive power can be obtained.
B.) Reference Current Calculation
To minimize the VA rating on the active filter, the
hybrid active filter is designed to force fundamental line
voltage drop across the passive filter network instead on
the active filter ac terminal. The reference source
currents (i
a
*, i
b
* and i
c
*) are compared with the sensed
source currents (i
a
, i
b
and i
c
). The switching sequence of
the IGBTs is generated from the PWM current
controller. The current errors are calculated as,
Ia_err = ia* - ia (14)
Ib_err = ib* - ib (15)
Ic_err = ic* - ic (16)

This error signals are fed to the current controller for
switching of the IGBTs of the active filter.
C.) DC Control Block
The dc bus control block is used to provide
dynamic regulation of the inverter dc bus voltage
during transients according to the dc bus voltage
reference, which is to achieve power balancing of
the inverter. It controls the real power delivered to
the dc side of the inverter, which is used to
maintain the dc side capacitor voltage V
dc
Ideally,
only the fundamental current consumes real power,
while harmonics exchange real power but consume
reactive power.


The shunt hybrid active filter which is connected to the
non linear load is simulated by using
MATLAB/SIMULINK. The scheme is first simulated
without any filter to find out the THD of the supply
current. Then it is simulated with the hybrid filter to
observe the difference in the supply current. Simulation
is carried out with hysteresis controller and PI
controller to find out the comparative study of the THD
of the supply current.
(i) NO CHANGE IN LOAD CONDITION

a.) BEFORE COMPENSATION

Fig.4 Source voltage without compensation
The above figure.4 shows source voltage without
compensation with
240V

Fig. 5 Source current without compensation
The figure 5, shows that the source currents are
deteriorated from its sinusoidal.

Fig.6 Load power without shunt hybrid active power filter
The figure.6 shows the analysis of active and reactive
power for before compensation is 4266W and 532.2Var

Fig.7 FFT analysis of the supply current (A) without filter
Figure.7 shows THD value without filter is 24.44%.
The large amount of harmonics in the distribution line
produces high value of THD. This value may vary time
to time due to switching of the loads. Hence dynamic
filtering system is required to reduce the harmonics.


b.) AFTER
COMPENSATION

Fig.8 Waveform of supply voltage (V) with shunt hybrid active filter

Fig.9 Waveforms of three phase supply current (A) with SHAPF

Fig.10 Waveforms of Shunt current (A)
The figure.9 shows that after compensation the source
current becomes sinusoidal and the shunt current that is
supplied to the system is shown in figure.10

Fig.11 Load power with SHAPF
The analysis of active and reactive power after
compensation is 4024W and 12.17Var as shown in
figure.11. The power factor attained after compensation
is 0.99%

Fig.12 FFT analysis of supply current (A) with filter.

Fig.13 DC link Voltage of shunt hybrid active filter


Fig.14 Load current after compensation

The system parameters are given in the table-1
TABLE-1 SYSTEM PARAMETERS

Supply Voltages V
S

230V

Supply Frequency F
S

50Hz

R,L tuned passive filter R
F,
L
F

1, 20mH

DC-Link capacitor C
F

1600F

DC-Link voltage V
dc

500V

Rectifier based R,L Load

7, 20mH

TABLE-2 Comparative simulations Results
THD% Before
compensation
THD% after
compensation
Source voltage
(V)
5.7 0.5
Source current(A) 24.9 2.8
Active power(W) 7481 5002
Reactive
power(Var)
1067 12
Filter Current Nil 22.02

The SHAPF gives near to the unity power factor and
reduces the current harmonics. The simulations result
shows that the hybrid filter reduces the supply current
from 24 to 2.8% and the power factor reaches 0.99.
VI. CONCLUSION
Hybrid power filter combines the advantages of both
passive and active filter for nonlinear load. In proposed
method transformerless hybrid active filter is performed
for the distribution system. The waveform and
frequency spectrum of the supply current analysis in
MATLAB /simulink shows the reduction of supply
current harmonics and improvement in the power
factor. Thus the Hysteresis controlled Shunt hybrid
filter has improved performance in harmonic
compensation and reactive power compensation. The
proposed shunt active filter topology realized an
acceptable power factor profile and compensates the
wide range of power quality problems. This
investigation proves that the shunt hybrid active power
filter strategy has the ability to reduces the total
harmonic current is 83.24%
REFERENCE
[1] K. Eichert, T. Mangold, M. Weinhold, Power Quality
Issues and their Solution, in VII Seminario de Electrnica de
Potencia, Valparaso, Chile, April 1999.
[2] M. Rahmani, A. Arora, R. Pfister, P. Huencho, State of
the Art Power Quality Devices and Innovative Concepts, in
VII Seminario de Electrnica de Potencia, Valparaso, Chile,
April 1999.
[3]H. Fujita and H. Akagi, A practical approach to
harmonic compensation in power systems: Series connection
of passive and active filters, IEEE Trans. Ind. Appl., vol. 27,
no. 6, pp. 10201025, Nov./Dec. 1991.
[6] G. Joos, L. Morn, Principles of Active Power Filters,
Tutorial Course Note. of IEEE Ind. Appl. Society Annual
Meeting, Oct. 1998.
[7] S. Park, J.-H. Sung, and K.Nam, A new parallel hybrid
filter configuration minimizing active filter size, in Proc.
IEEE 30th Annu. Power Electron. Spec. Conf., 1999, vol. 1,
pp. 400405.
[8] D. Rivas, L. Moran, J. W. Dixon, and J. R. Espinoza,
Improving passive filter compensation performance with
active techniques, IEEE Trans. Ind. Electron., vol. 50, no. 1,
pp. 161170, Feb. 2003.
[9] D. Rivas, L. Moran, J. Dixon, and J. Espinoza, A simple
control scheme for hybrid active power filters, IEE Proc.-
Gen.Tran. Distrib. vol. 149, no.4, pp. 485-490, 2002.
[10]H. Akagi, New trends in active filters for power
conditioning, IEEE Trans. Ind. Appl.,vol. 32, no. 6, pp.
13121322, Nov./Dec. 1996.


[11]S. Bhattacharya, P. T. Cheng, and D. M. Divan, Hybrid
solutions for improving passive filter performance in high
power applications, IEEE Trans. Ind. Appl., vol. 33, no. 3,
pp. 732747, May/Jun. 1997.
[12] M. Pereira, A. Zenkner, and A. de Oliveira, Full range
active ac filter with multilevel IGBT converter for
transmission and distribution, in Proc.Conf. Rec. IEEE-PES
Transmiss. Distrib. Conf. Expo.: Latin America,2008, pp. 1
6.
[13] W. Tangtheerajaroonwong, T. Hatada, K. Wada, and H.
Akagi, Design and performance of a transformerless shunt
hybrid filter integrated into a three-phase diode rectifier,
Sep. 2007.
[14] H. Akagi and T Hatada, Voltage balancing control for a
three-level diode clamped converter in a medium-voltage
transformerless hybrid active filter, IEEE Trans. Power
Electron., vol. 24, no. 3, pp. 571579, Mar.2009.
[15] N. Mendalek, K. Al-Haddad, L.-A. Dessaint, and F.
Fnaiech, Nonlinear control technique to enhance dynamic
performance o f a shunt active power filter, Proc. Inst. Elect.
Eng.Elect. Power Appl., vol. 150, no. 4,pp. 373379, Jul.
2003.
[16] H. Fujita, H. Akagi, "A practical approach to harmonic
compensation in power systems; series connection of passive
and active filters," IEEE Trans. on Industry Applications, Vol.
27, pp. 1020-1025, 1991.
[17] V. Kaura and V. Blasko, Operation of A Phase Locked
Loop System under Distorted Utility Conditions, IEEE
Trans. Ind. Appl., vol. 33, no. 3, pp. 5863, May/Jun. 1997.
[18]W. Tangtheerajaroonwong, T. Hatada, K. Wada, and H.
Akagi, Design and performance of a transformerless shunt
hybrid filter integrated into a three-phase diode rectifier,
Sep. 2007.
[19] H. Akagi and T Hatada, Voltage balancing control for a
three-level diode clamped converter in a medium-voltage
transformerless hybrid active filter, IEEE Trans. Power
Electron., vol. 24, no. 3, pp. 571579, Mar.2009.
[20] M. Pereira, A. Zenkner, and A. de Oliveira, Full range
active ac filter with multilevel IGBT converter for
transmission and distribution, in Proc.Conf. Rec. IEEE-PES
Transmiss. Distrib. Conf. Expo.: Latin America,2008, pp. 1
6.
[21]Luo, Z. K. Shuai, Z. J. Shen, W. J. Zhu, and X. Y. Xu,
Design considerations for maintaining dc-side voltage of
hybrid active power filter with injection circuit, IEEE Trans.
Power Electron., vol. 24, no. 1, pp. 7584, Jan. 2009.


An Artificial Intelligent Controller for a Stand-Alone PV System
for Drive Applications
S. Vasantharaj
1
, M. Sasikumar
2

1
Assistant Professor, Dept. of Electrical & Electronics, Arunai College of Engineering, Tiruvannamalai.
2
Professor & Head, Jeppiaar Engineering College, Chennai

ABSTRACT
In this paper, the Space Vector Pulse Width Modulation
(SVPWM) control strategies is used for the implementation
of Impedance Source Inverter (ZSI) based Solar Energy
Conversion system was explained. The solar irradiation and
temperature are mainly depends on the output power
produced from the PV conversion process. The proposed
method is capable of tracking MPPs rapidly and accurately
without steady-state oscillation, thus, its dynamic
performance is more efficient. In this proposed method the
SVPWM is used to treat the sinusoidal voltage as a constant
amplitude vector rotating at constant frequency. This
project proposes a MPPT method, based on Neural
Network Controller (NNC) with a ZSI applied to a stand-
alone photovoltaic system. By adjusting the shoot-through
duty cycles of the Z-Source network the maximum power
from the solar PV system is transferred to the stand alone
system. Hence the harmonic distortion in the output voltage
or current will be less. The inverter output current for
driving a load should be noted such that it does not carry
the harmonic content. However since disturbed sine wave is
unavoidable under various factors it is necessary to reduce
the harmonic level to obtain a highly effective output. The
results are generated in MATLAB / SIMULINK and are
shown.

Keywords Photovoltaic (PV), Impedance Source Inverter
(ZSI), Maximum Power Point Tracking (MPPT), Maximum
Power Point (MPP), Space Vector Pulse Width Modulation
(SVPWM), Direct Current (DC), Alternating Current (AC),
Total Harmonic Distortion (THD).

I. INTRODUCTION

Comparing to all renewable energy sources, solar power
systems attract more attention because they provide excellent
opportunity to generate electricity while greenhouse emissions
are reduced [1-5]. The only way of generating electricity from
solar energy will be PV cells or panels. Temperature,
insolation, spectral characteristics of sunlight, dirt, shadow,
etc., are the main factors to be considered for the efficiency of
solar cells. The PV cells are made up of silicon, which is also
used in computer "chips". The radiation produced from the sun
will be converted into direct current (DC) by this Photovoltaic
process. This point is known as maximum power point (MPP).
There will be a non linear variation in the locus of this point
with solar irradiation and the cell temperature. The MPPT [1],
[2] is the efficient way to track the maximum available output
power of the PV system. The PV panel module physically
moves to point directly at the sun and which the MPPT is not a
mechanical tracking system. The graph (Fig 1) shows the PV
module Power/Voltage/Current and the traditional Current vs.
Voltage curve for a standard test conditions of 25C cell
temperature and 1000W/m
2
of insolation.

Fig 1. Power/voltage/current curve of a 75Watts PV panel.

The above graph also shows the module voltage vs.
PV module power delivered. Rather than simply connecting the
battery to the module, the original MPPT [4], [5] system in a
dc-dc converter calculates the voltage at which the module is
able to produce maximum power [6-10].

II. CIRCUIT DIAGRAM DESCRIPTION
www.ijrde.com


In this solar PV system the power is generated by the solar
irradiation and insolation temperature. The maximum a
power will be extracted by the operation of PV generator at its
MPP, by the role of MPPT [11-14]. The figure 6 shows the
general block diagram for a solar PV system with MPPT,
a Impedance Source Inverter (ZSI). The main objective of this
MPPT [8] technique is to obtain the maximum
PV generator. The inductor which is used as a filter which
reduces the current ripple content in the DC output current and
the filter capacitor reduces the ripple content in the DC link
voltage providing a relatively stiff voltage source for the PWM
inverter. The ZSI [6] is used to get constant voltage and
constant frequency. The buck/boost operation can be achieved
using a three level ZSI, to maintain the constant voltage in the
load side by selecting the proper value of the Modulation
Index. The proper value of shunt capacitor of the inverter can
reduces the voltage ripple content in the DC link voltage. To
control output voltage of the impedance source inverter, the
SVPWM strategies are the effective, especially describing a
lower total harmonic distortion (THD). The power factor is
mainly depending upon the generated voltage and the wind
velocity conditions. The shunt capacitor is used to filter the
link voltage ripples in the rectifier output. The output voltage
and frequency is controlled by the pulse width modulation
technique [15-17].

Fig 2. Circuit Diagram of proposed method.

III. MODELLING OF PHOTOVOLTAIC ARRAY
SYSTEM

In this solar PV system the power is generated by the solar
The maximum available
power will be extracted by the operation of PV generator at its
The figure 6 shows the
system with MPPT, using
. The main objective of this
technique is to obtain the maximum power from the
The inductor which is used as a filter which
reduces the current ripple content in the DC output current and
the filter capacitor reduces the ripple content in the DC link
viding a relatively stiff voltage source for the PWM
is used to get constant voltage and
constant frequency. The buck/boost operation can be achieved
using a three level ZSI, to maintain the constant voltage in the
ing the proper value of the Modulation
. The proper value of shunt capacitor of the inverter can
reduces the voltage ripple content in the DC link voltage. To
control output voltage of the impedance source inverter, the
ive, especially describing a
lower total harmonic distortion (THD). The power factor is
mainly depending upon the generated voltage and the wind
The shunt capacitor is used to filter the DC
The output voltage
he pulse width modulation

ING OF PHOTOVOLTAIC ARRAY
The equivalent circuit of the PV cell is shown in fig 3

Fig 3. Equivalent Circuit of a PV Cell

The basic equation of I V characteristic of the ideal PV is
mathematically described from the theory of semiconductors

Where,

Therefore,
Where,
I
pv,cell
is the current generated by the incident light (it is
directly proportional to the Sun irradiation),
I
d
is the Shockley diode equation,
I
0,cell
is the reverse saturation or leakage current of the
diode, q is the electron charge (1.60217646
k is the Boltzmann constant (1.3806503
T (in Kelvin) is the temperature of the
a is the diode ideality constant.

Fig 4. Origin of I -V equation of an Ideal PV cell

The fig 4 shows the origination of the I
the equation (2). Practical arrays are made up of multiple
modules. The observation of the characteristics at the terminals
of the PV array requires the inclusion of additional parameters
to the basic equation.

Where,
V = N
s
kT/q is the thermal voltage of the array with N
connected in series.
R
S
& R
P
is the equivalent series and parallel resistance of the
pp- 489-497
490 | P a g e
the PV cell is shown in fig 3.
V characteristic of the ideal PV is
mathematically described from the theory of semiconductors
(1)
(2)
(3)
is the current generated by the incident light (it is
directly proportional to the Sun irradiation),

is the reverse saturation or leakage current of the
is the electron charge (1.60217646 1019 C),
is the Boltzmann constant (1.3806503 1023 J/K),
(in Kelvin) is the temperature of the pn junction, and
V equation of an Ideal PV cell.
shows the origination of the I V curve for
). Practical arrays are made up of multiple
modules. The observation of the characteristics at the terminals
array requires the inclusion of additional parameters
(4)
kT/q is the thermal voltage of the array with N
s
cells
is the equivalent series and parallel resistance of the


array. The cells connected in parallel which increases the
current and the greater output voltage will be produced by the
cells connected in series. The array is composed by N
p
parallel
connections of cell, the PV and saturation currents may be
expressed as,

=
,

(5)
=
,

(6)
This equations originate the I-V curve in figure 4
below, where the three outstanding points are highlighted: short
circuit (0,I
sc
), Maximum Power Point (V
mp
, I
mp
), and open
circuit (V
oc
, 0).

Fig 5.Characteristic I-V curve of a practical PV module
The PV panel is modeled [9], [10] as an equivalent
current source. From the MATLAB Simulink library the
mathematical model for the various equations describing the
PV panel characteristics are modeled. The below figure 5
shows the equivalent circuit model of the PV panel. This
simulation is done for standard test condition (STC) when
temperature is 25 C and Irradiation is 1000 W/m
2
.

Figure 5. Equivalent circuit of solar PV using MATLAB

Fig 6. Maximum current (Im) of Solar PV using MATLAB

Fig 7. Reverse saturation current (Io) using MATLAB

Fig 8. Current generated by the incident light (Ipv) of PV using MATLAB

IV. SPACE VECTOR PULSE WIDTH
MODULATION (SVPWM) TECHNIQUE

Space vector modulation (SVM) is an algorithm for
the control of pulse width modulation (PWM). It is used for the
creation of alternating current (AC) waveform. It is most
commonly used in inverters, 3 phase ac powered motors. A
three phase voltage vector is transformed into a vector in the


stationary d-q coordinate frame which represents the spatial
vector sum of the three phase voltage. It is used in the reduction
of total harmonic distortion (THD) created by the rapid
switching. With the increase of levels, traditional approaches of
SVM based on five-level or seven level inverters are hardly
realized. The vectors (V
1
to V
6
) divide the plane into six sectors
(each sector: 60 degrees). This section explains about this SVM
scheme. Any three-phase system (defined by a
x
(t), a
y
(t) a
z
(t))
can be represented uniquely by a rotating vector as,
+ .
(7)
Given a three-phase system, the vector representation is
achieved by the following 3/2 transformation:
.
1

Where (A, A) are forming an orthogonal 2-phase system and
a
S
= A
+ jA
. A vector can be uniquely defined in the complex

plane by these components. The reverse transformation (2/3
Transformation) is given by,
= .
=
1
3
.

Fig 9. Space vector d,q-axis locations and their switching vectors and sectors.

It represents the homopolar component. The space
vector produces a unique between the complex plane and a
three-phase system. The SVM algorithm method is used for
choosing active vectors. The Space Vector representation is
shown as in fig 9

.
V. NEURAL NETWORK CONTROLLER

An ANN is a mathematical model that tries to simulate
the structure and functionalities of biological Neural Networks.
Basic Building Block of every ANN is artificial neuron, which
is simple mathematical model (function). Such a model as three
simple of sets of rules: multiplication, summation and
activation. At the entrance of artificial neuron the inputs are
weighted what means that every input value is multiplied with
individual weight. In the middle section of artificial neuron is
sum function that sums all weighted inputs and bias. At the exit
of artificial neuron the sum of previously weighted inputs and
bias is passing through activation function that is called transfer
function (fig 10).

Fig 10. Working Principle of an Artificial Neuron
The body of an artificial neuron that sums the
weighted inputs bias and processes the sum with transfer
function. At the end an artificial neuron passes the processed
information via output(s). Benefit of artificial neuron model
simplicity can be seen in its mathematical description below:
=
8
Where,
x
i
(k) is input value in discrete time k where i goes from 0 to m,
w
i
(k) is weight value in discrete time k where i goes from 0 to
m,
b is bias,


F is a transfer function,
Y
i
(k) is output value in discrete time k.

VI. IMPEDANCE SOURCE INVERTER

A Z-source inverter [4], [6] is proposed as the single-
stage inverter topology to demonstrate both buck and boost
power conversion ability. In addition, the two switches in the
same phase leg can be gated on simultaneously and no lead
time is needed, so the output distortion is greatly reduced and
the reliability can be improved. Impedance network is a two
port network. A two port network is simply a network inside a
box and the network has only two pairs of accessible terminals.
Usually one pair represents the input and other represents the
output. This network also called as lattice network. Lattice
network is the one of the common four terminal two port
network. This lattice network, L
1
and L
2
are series arms
inductances, C
1
and C
2
are diagonal capacitances. This is a two
port network that consists of split inductors L
1
and L
2
and
capacitors C
1
and C
2
connected in X-shape. When the load
terminals are shorted through both upper and lower devices of
any one phase leg or all three phase legs this shoot through zero
state is forbidden in the VSI, because it would cause a shoot-
through fault. This network makes the shoot through zero state
possible. This state provides the unique buck-boost [6] feature
to the inverter. The equivalent circuit of the ZSI is shown in fig
11. During shoot-through zero state the inverter bridge is
equivalent to a short circuit. The impedance source network is
six times the switching frequency of the main inverter, which
greatly reduces the required inductance of the impedance
source network.

Fig 11. Equivalent Circuit of ZSI
A. Mathematical Modelling of ZSI

The three phase Z-source inverter fed load system is
shown in fig 11. This type of inverter has a lattice network or
impedance network on its DC side, which connects the source
to the inverter. The two inductors and two capacitors are used
to provide buck and boost operation.

Fig 12. Impedance Source Inverter (ZSI)

Assume the inductors (L
1
and L
2
) and capacitors (C
1

and C
2
) have the same inductance and capacitance values
respectively.
L
1
and L
2
series arm inductors; V
dc
is input voltage;
C
1
and C
2
parallel arm capacitors; V
i
is output voltage;
V
c1
= V
c2
= V
c
(9)
V
L1
= V
L2
= V
L
(10)
V
L
= V
c

V
D
= 2V
c

V
i
= 0
During the switching cycle T
V
L
= V
o
- V
c
(11)
V
D
= V
o

V
i
= V
c
V
L
= 2 V
c
-V
o

V
i
= 2V
c
V
o
(12)

Where V
o
is the DC source voltage and
T=T
o
+ T
1
(13)

The average voltage of the inductors over one
switching period (T) should be zero in steady state,

VII. SIMULATION, HARDWARE AND SYSTEM
RESULTS
The input to the Impedance Source Inverter is the
voltage and
power
signals from
the PV
panels
which are
analog
signals. The
output from
the ZSI is
given to the
motor load.
The Space
vector


PWM which is used in the circuit reduces the harmonic content
from the inverter circuit and hence the inverter performance
will be efficient. The implementation of the MPPT controller,
initially modelling and simulation of the controller employing
ZSI using the MATLAB/Simulink was carried out. Figure 13
shows the developed PV model system consisting of PV array,
Impedance source circuit with an MPPT controller connected to
an inverter and a load. The simulation is used for validating the
developed hardware prototype. These input capacitors serve as
the DC source feeding the Z-source network and are used to
suppress voltage surge that may occur due to the line
inductance during diode commutation and shoot-through mode
of the inverter, thus requiring a small value of capacitance.

Fig 13. Simulink model using Neural Network Controller

Fig 14. Simulink Results of the PV Panel

Fig 15. Simulink Results of Impedance Source Voltage

Fig 16. Waveform for speed and Torque.

Fig 17. Three Phase Motor Current

The harmonic level is high which does not suit the
standard limit. By using the ANN controller the voltage and
current harmonics of the same system is reduced. It is observed
that the voltage and the current harmonics are 11.97% and
1.90% respectively which is shown in the figure 18 and 19
respectively.

Fig.18. Voltage Harmonics obtained through ANN


Fig.19. Current Harmonics obtained through ANN

The hardware setup for testing the prototype MPPT
controller is as shown in fig 20. The figure 20 and 21 shows the
power supply unit of the prototype model. The input supply
take from the panel is 1/230V/50Hz which is connected to the
1 auto transformer. The auto transformer is varied from 0 to
20V which is the maximum input supply used here. The
controller used here is to drive the Inverter is Atmel 89C52
microcontroller which produces Space Vector PWM technique
for the 6 inverter switches. The SVPWM coding was coded in
the Atmel 89C52 microcontroller for producing the desired
output.

Fig 20. Proposed prototype model

Fig 21. Inverter Circuit

The input 1 / 50Hz / 230V is switched ON keeping
the auto transformer at the initial condition. The auto
transformer is adjusted by increasing the input to 7.5V. The
figure 22 shows the output measured using DSO for the line
voltage. The peak-peak voltage is 15.4V for period of 20ms.
The RMS value is 5.45V.



Fig.22: Input Voltage
The pulses are generated using the microcontroller
programed for the desired outputs. The figure 23 shows the
input pulses generated for the ZSI. The input pulse for the ASI
which is operated at a frequency of 1.136 kHz.

Fig.23: Input Pulse for ZSI
The solar power is then fed to the impedance source
which produces the controlled DC voltage source to feed the
inverter circuit. The output voltage from the Impedance Source
is shown in the figure 24. The output obtained is 6.90V.

Fig. 24: Impedance Source Output Voltage
The Z Source output is fed to the inverter. The load
connected to it is a resistive in nature of 100k connected at
each output terminal as wye-connected. The output voltage is
measured across any one of the phase terminals and the peak to
peak value is obtained as 3.75. The output is shown in the
figure 25.

Fig.25: Inverter output voltage (t=20ms)
VIII. CONCLUSION

The proposed work demonstrated the state of art DC-
AC power converter technology. The mathematical analysis of
Impedance source Inverter is developed. A novel method for
the tracking of MPP was investigated in order to improve the
efficiency of PV systems, under different temperature and
irradiance conditions. The design and simulation of a ZSI based
MPPT controller was proposed using MATLAB. The proposed
method has very good performances, fast responses with no
overshoot and less fluctuation in the steady state, for rapid
irradiance and temperature variations. By using the Neural
Network controller the PV System efficiency will be increased.
These controllers are able to maintain very rapidly and the
operating point of the PV systems at the maximum power point
hence improving the amount of energy effectively extracted
from the PV modules.

REFERENCES

[1] Pahlevaninezhad. M, Das. P, Drobnik, Jain P.K, Bakshai. A, A
ZVSInterleaved Boost AC/DC Converter Used in Plug-in Electric
Vehicles, IEEE Transactions on Power Electronics, vol. 27, no. 8, 2012,
pp. 3513-3529.
[2] Mousavi A, Das. P, Moschopoulos. G, A Comparative, Study of a New
ZCS DCDC Full-Bridge Boost Converter With a ZVS Active-Clamp
Converter, IEEE Transactions on Power Electronics, vol. 27, no. 3, 2012,
pp. 1347 1358.
[3] Sung Sae Lee, Gun Woo Moon, High-Efficiency Boost Half-Bridge
Converter With Fast Boost Current Transferring ZVS Operation, IEEE
Transactions on Power Electronics, vol. 23, no. 4, 2008, pp. 1822-1829.
[4] Seung-Wu Rhee, Gun Woo lee, Coupled Inductor Incorporated Boost
Half-Bridge Converter With Wide ZVS Operation Range, IEEE
Transactions on Industrial Electronics, vol. 56, no. 7, 2009, pp. 2505-
2512.
[5] Ch. Hua and Ch. Shen, Comparative study of peak power tracking
techniques for solar storage system, IEEE Transactions on Applied
Power Electronics Conference and Exposition (APEC98), Vol. 2, 1998,
pp. 679-685.
[6] Azadeh Safari and SaadMekhilef, Simulation and Hardware
Implementation of Incremental Conductance MPPT with Direct Control
Method Using Cuk Converter, IEEE Transactions on Industrial
Electronics, vol. 58, no. 4, 2011, pp. 1154-1161.
[7] Ahmed K. Abdelsalam, Ahmed M. Massoud, Shehab Ahmed and Prasad
N. Enjeti, High-Performance Adaptive Perturb and Observe MPPT


Technique for Photovoltaic- Based Micro grids, IEEE Transactions on
Power Electronics, vol. 26, no. 4, 2011, pp. 1010-1021.
[8] Jian-Long Kuo, Kai-Lun Chao, and Li-Shiang Lee, Dual Mechatronic
MPPT Controllers with PN and OPSO Control Algorithms for Rotatable
Solar Panel in PHEV System, IEEE Transactions on Industrial
Electronics, vol. 57, no. 2, 2010, pp. 678-689.
[9] MummadiVeerachary, TomonobuSenjyu, and Katsumi Uezato, Neural
Network Based Maximum Power Point Tracking of Coupled Inductor
Interleaved Boost Converter Supplied PV System Using Fuzzy
Controller IEEE Transactions on Industrial Electronics, vol. 50, no. 4,
2003, pp. 749-758.
[10] Nobuyoshi Mutoh, Masahiro Ohno, and Takayoshi Inoue, A Method
for MPPT Control While searching for Parameters Corresponding to
Weather Conditions for PV Generation Systems, IEEE Transactions on
Industrial Electronics, vol. 53, no. 4, 2006.
[11] Nicola Femia, Giovanni Petrone, Giovanni Spagnuoloand Massimo
Vitelli, Optimization of Perturb and Observe Maximum Power Point
Tracking Method, IEEE Transactions on Power Electronics, vol. 20, no.
4, 2005, pp. 963-973.
[12] Oscar Lpez-Lapea, Maria Teresa PenellaandManelGasulla, A New
MPPT Method for Low-Power Solar Energy Harvesting, IEEE
Transactions on Industrial Electronics, vol. 57, no. 9, 2010, pp. 3129-3138
[13] Villalva M G Modelling and circuit-based simulation of photovoltaic
arrays, IEEE Transactions on Power Electronics, vol. 25, no. 5, 2009,
pp. 1198 - 1208.
[14] Yao-Ching Hsieh, Te-Chin Hsueh and Hau-Chen Yen An Interleaved
Boost Converter with Zero-Voltage Transition IEEE Transactions on
Power Electronics, vol. 24, no. 4, 2009, pp. 973 - 978.
[15] Ehsan Adib and Hosein Farzanehfard, Zero Voltage Transition PWM
Converters with Synchronous Rectifier, IEEE Transactions on Power
Electronics, vol. 25, no. 1, 2010, pp. 105 110.
[16] N. Lakshminarasamma, Md. Masihuzzaman, and V. Ramanarayanan,
Steady State Stability of Current-Mode Active Clamp ZVS DC-DC
Converters, IEEE Transactions on Power Electronics, vol. 26, no. 5,
2011, pp. 1295 1304.
[17] Max Savio, S. Vasantharaj & M. Sasikumar, Implementation of Stand-
Alone Hybrid System using SVPWM for Impedance Source Inverter,
Wulfenia Journal, Vol. 19. No. 11, 2012, pp 404-417.


An Efficient Searching Scheme in p2p Network Using
Random Walker Cloning Method

S.Vimal
*
Dr.S.K.Srivatsa
**

*
Research Scholar, Sathyabama University, Chennai, Tamil Nadu, India
**
Senior Professor, St.Josephs college of engineering, Chennai, Tamil Nadu, India

ABSTRACT

An active network has been advanced
over an inordinate time of years for resource
sharing is Peer-to-Peer network. The most
important task is resource probing to discover the
objective data or files. Since the recognition is too
wavering a better searching scheme with good
reciprocity among long searching time, a large
amount of facsimiled query messages and a little
booming search hit rate is difficult to find out.
Many effective methods have been developed to
overcome this issue and many of them might only
be useful to search popular objects so in our paper
we proposed a Cloning Random Walker method
with Dominating set to find out the objective data
or files whether it is popular or unpopular in
Peer-to-Peer network. Our theoretical analysis
shows us that our proposed system requires
diminished amount of query messages between the
message amount in the Random Walker method
and the one in flooding method. In addition to this
our simulation result shows that our proposed
system can perform a better reciprocity among
the search delay, message overhead per hit and
success rate while performing resource probing in
a Peer-to-Peer network.

Keywords- Peers, random walker cloning method,
efficient P2P searching, query message.

I. INTRODUCTION

The active network called the Peer-to-Peer
network have been extensively useful for an
inordinate time of years in dispersed resource sharing
and the most important task for a Peer-to-Peer
function is resource probing to discover the objective
data or files which may be disseminated in the Peer-
to-Peer network [1-3]. In the former year various
approaches have been proposed to efficiently
discover the objective data or files in a enormous
Peer-to-Peer network. Query message overflowing is
the easiest way by promoting the query messages. On
the other hand overflowing may present message
disintegration. In the intervening time discovering the
popular data or file is easier than discovering the
unpopular data or files. The searching efficiency may
depend on the popularity objective data or files.
Conversely the popularity of the objective data or
files is difficult to be determined because Peer-to-
Peer network varies actively. Consequently, how to
get a good reciprocity among the search time,
overhead caused by a vast amount of facsimiled
query messages and booming search hit rate for
searching data or files in such a changing
circumstances is demanding issue.
Based on the above discussion we
propose Cloning Random Walker with Dominating
Set to discover the objective data or files in a Peer-to-
Peer network in this paper. Cloning Random Walker
timely facsimiles and directs the query message to
part of visited nodes neighbor for escalating the
searching threads but deliberately and limitedly. A
trivial message overflowing can be supplemented to
broaden the searching range [4-7]. To limit the
message overhead and network bandwidth utilization
wrought by overflowing, only the nodes in the
concerned sub-overlay arrangement dominating set
can handle a query message overflowing in our
proposed scheme. As a result Clone RW+ DS
structures the changes in searching mechanism with
vigor against the actives of peer participation. Our
proposed system can succeed from the existing
system mechanism to effectively discover the popular
data or files as well as appreciably limit the overflow

of facsimiled query messages and ease off the long
delay to discover the unpopular data or files [8-12].
The other parts of the article are
structured as follows. Section 2 demonstrates a few
associated works about how to locate the objective
data or files in a Peer-to-Peer network. Section 3
represents our Cloning Random Walker with
dominating Set pattern which can adaptively discover
the objective data or files effectively in a active Peer-
to-Peer network. Section 4 illustrates the theoretical
analysis about the message loads of variety of
schemes. Section 5 shows the simulation results and
analytical comparisons of our proposed system
compared to other searching methods. Section 6 its
shows the conclusion results.

II. RELATED WORK

The two classification of Peer-to-Peer overlay
structure - unstructured overlay network and
structured overlay network. For sustaining overlay
network, such as Free net, Gnutella, Fast
track/KaZaA, Bit torrent, Overnet/eDonkey, and
Foxy, does not have any earlier awareness about the
network topology. On the whole discovering the
objective data and files will take a extended
searching time but a minimum allowance cost
without consciousness of network topology evidence.
In disparity, a structured network such as CAN,
Chord, Tapestry, Pastry, and Kademlia, Viceroy, is
continued by ordering resources at scheduled
locations. Discovering the objective data or files in a
structured network shall take a limited searching time
but a elevated preservation cost. Searching schemes
in a unstructured Peer-to-Peer network can be further
classified as into a blind method and an informed
method. By blind method [1-6], peers cannot hold
any data or files specific information but it
unintentionally directs the query messages to their
neighbor peers to manage the searching process. On
the other hand facsimiled query message shall be sent
continuously to the received peers and then cause
extreme amount of messages to load the network.

To limit the facsimiled messages, few
researches were proposed to progress the blind
methods. Many progressed searching schemes called
informed searching methods [7], make peers enable
meaningful query messages directing by referring to
an additional overlay substructure, such as
Lightflood[3]. The informed searching algorithm
uses either indices to data or files to monitor the
query messages to be directed to other proper peers.
Cache based mechanism can assure searching of
popular data or files. On the other hand when
searching unpopular data or files by these existing
schemes, the difficulties of directing lots of
facsimiled query messages and incurring long
response time still persist.
On the horizon to discover the
objective data or files by promoting query messages a
TTL (Time-To-Live) mechanism is used to reduce
the number of forwarding hops before the message is
rejected. Selection of better TTL becomes a
reciprocity issue. A vast number of forward messages
may load the network if the TTL is set so high.
However it is difficult to locate the objective data or
files although the objective data or files exist in the
network or only the popular data or files can be
Fig. 1: Cloning Hops
www.ijrde.com

found. The TTL value controls the searching are
The controlled overflowing search approaches
series of TTL values are determined to reduce the
search cost in terms of the amount of packet
transmission/reception.
In the intervening time Random
Walker [1-2], was determined to drastica
amount of query messages in the network. Every
Walker in the approach plays a data or file finder to
locate the objective data or files by unintentionally
selecting only one of the presently visited neighbor
node as a next hop instead of the
neighbor node. Controversially the major
shortcoming of Random Walker is it takes a vast time
to discover the objective data or files if a wrong
neighbor is selected or some of the visited nodes are
exiting the network. Consequently a dynami
searching algorithm that resembles overflowing for
temporary search and Random Walker for an
enduring search is determined to manage an adaptive
search for resources meant at reducing the message
facsimile by preserving supplementary
arrangement. Lightflood [2] reduces the terminated
message and yet it can produce the same message
proliferating area as a standard overflowing process
manages on seeing the quantity of terminated query
message. Pure overflowing is effective
stages because of search coverage can raise promptly
when the query message crosses in the first several
hops can be discovered. On the other hand, a vast
terminated message can be produced in the final
stage. If the query message cross mor
coverage margin becomes smaller. Lightwood
adventures pure overflowing in the starting several
hops to confirm that a required quantity of query
message can cover most of search area and preserves
a tree-like sub-overlay arrangements- Flood ne
higher hops eradicates most of the terminated
message caused by overflowing.

found. The TTL value controls the searching area.
The controlled overflowing search approaches , i.e.,
series of TTL values are determined to reduce the
search cost in terms of the amount of packet
In the intervening time Random
, was determined to drastically limit the
amount of query messages in the network. Every
Walker in the approach plays a data or file finder to
locate the objective data or files by unintentionally
selecting only one of the presently visited neighbor
node as a next hop instead of the entire visited
neighbor node. Controversially the major
shortcoming of Random Walker is it takes a vast time
to discover the objective data or files if a wrong
neighbor is selected or some of the visited nodes are
exiting the network. Consequently a dynamic
that resembles overflowing for
temporary search and Random Walker for an
enduring search is determined to manage an adaptive
search for resources meant at reducing the message
facsimile by preserving supplementary sub-overlay
reduces the terminated
message and yet it can produce the same message
proliferating area as a standard overflowing process
manages on seeing the quantity of terminated query
message. Pure overflowing is effective only in initial
stages because of search coverage can raise promptly
when the query message crosses in the first several
hops can be discovered. On the other hand, a vast
terminated message can be produced in the final
stage. If the query message cross more deeply the
coverage margin becomes smaller. Lightwood
adventures pure overflowing in the starting several
hops to confirm that a required quantity of query
message can cover most of search area and preserves
Flood net in the
higher hops eradicates most of the terminated

A two-phase ticket based search approach
to suit the searching mechanism to either popular and
unpopular data or files. During every rou
one, a root node initiates to direct the query messages
with an initial quantity of implicit tickets that
characterize how many search approval can be done
at the forthcoming visited nodes, to its neighbor. One
implicit ticket will be consumed
query message for first time. Then it recursively
directs the message with fair ticket number to its
entire neighbor if the query message carries a
sufficient quantity of implicit tickets. If one search
round does not find data or files the total number of
implicit ticket might be increased by a ratio to start
over another searching process. When the quantity of
tickets in some round goes beyond the extreme verge
the algorithm might switch to the phase two which
preserves ring-like sub-overlay arrangements that
connects all nodes consecutively. In phase one if the
nodes reached the last round it detach rings into
segment and directs the query message to their
particular successor recursively till the nodes in each
segment are visited.
sue: pp- 498-504
500 | P a g e
phase ticket based search approach [5], tested
to suit the searching mechanism to either popular and
unpopular data or files. During every round of phase
one, a root node initiates to direct the query messages
with an initial quantity of implicit tickets that
characterize how many search approval can be done
at the forthcoming visited nodes, to its neighbor. One
implicit ticket will be consumed if a node receives a
query message for first time. Then it recursively
directs the message with fair ticket number to its
entire neighbor if the query message carries a
sufficient quantity of implicit tickets. If one search
s the total number of
implicit ticket might be increased by a ratio to start
over another searching process. When the quantity of
tickets in some round goes beyond the extreme verge
the algorithm might switch to the phase two which
overlay arrangements that
connects all nodes consecutively. In phase one if the
nodes reached the last round it detach rings into
segment and directs the query message to their
particular successor recursively till the nodes in each


GAB [11] uses a gossip based method
to gather universal information about resource
popularity to estimate which algorithm is used for a
given search. PASH [11] improves hybrid search in
GAB for active surroundings. To determine the
correct search method and effectively save the query
traffic cost and response time by actively identifying
the content popularity. QRank [12], a difficulty-
aware search hybrid scheme orders the queries by
weighting keywords based on resource occurrence
frequencies. By using rank values and combining an
unstructured protocol with a DHT-based overlay
structure, QRank determines appropriate search
approaches based on different objective data or files
popularities. The flooding-based scheme is adopted
for determining popular data or files due to its
operation ease whereas the DHT-based scheme is
used for searching unpopular objects due to its
efficient hit rate and minimum bandwidth cost.


In order to comprehend the searching
concept about accomplishing a data or files seeking
by concerned query messages passing along the
network is done by a Walker in the Random
Walker. Predictably the Random Walker scheme is
directing the query message to every visited node
neighbor on its way to search the objective data or
files in the passive optical networks. When the
objective data or files is popular it is identified by
small message hops however when the objective data
or files is unpopular it is identified using a large
message hops. Consequently our idea clones an
appropriate amount of walker to make possible for it
to identify the objective data or files before it satisfy
some conditions that are already defined like hit
amount reaches a threshold or the searching time is
over. The walker will clone more walker if the
travelling hop for the walker reaches the cloning
distance by using the same query message till the
cloning time reaches the maximum cloning hop or
query message reaches the maximum TTL. To find
the data or files more cloned walkers will be
produced there is a large number of unpopular data or
files. Especially for encountering a leaving node,
which used to join but now
Dominating Set Construction:
//dominators: nodes in the dominating set
// covered nodes: dominators neighbors
// uncovered nodes: nodes which are dominators
neighbors
//d(u) span of u: the amount of uncovered
nodes adjacent to u
// s(u) support of u: the amount of candidates
adjacent to u
//med(u): the median of all supports of uncovered
nodes adjacent to u
// u is a candidate if d(u) is maximal within
distance 2 of u
while d(u) > 0 do

//Step 1: Span Calculation
u computes d(u) rounded to the next power of 2;
u sends d(u) to all of its neighbor nodes;
u computes the maximum span among its neighbor
nodes and forwards it one more hop;

//Step 2: Candidate Selection
if d(u) is maximal within a distance 2 of u then
u sets itself as a candidate node for joining the
dominating set;
end if

//Step 3: Support Calculation
if u is not candidate node then
u sends its support s(u) to each of the file;
end if

//Step 4: Dominator Selection
if u is a candidate node then
u sets itself as a node in the dominating set with a
probability med1u;
end if
end while

CloneRW + DS:

//msg: message about searching the target object
//hop_count: the hop count of the traversing query
//message

//cloning_times: the walker cloning times
//ds_sent: a flag to keep whether the query //message
comes from a node in the dominating //set or not

OnReceivingQuery(msg,hop_count,cloning_times,
ds_sent) by node x
if x contains the target object then
x replies a successful hit to the requester;
return;
end if
hop_count : hop_count + 1;
if hop_count > MAX_TTL then
x discards Query
(msg,hop_count,cloning_times,ds_sent); return;
end if
if x 2 DS then
if ds_sent = FALSE and x never floods the query
message then
// encountering a node, which does not flood before,
in DS
x forwards Query(msg, 0, cloning_times, TRUE) to
all its neighbors;
//Flooding the query message
else
neighboring // the query message comes from //one
node in DS or x has forwarded
x discards Query(msg, hop_count, cloning_times,
ds_sent);
end if
else if (cloning_times < MAX_CLONING_HOP)
and (hop_count mod CLONING_DIST = 0) then
//cloning random walkers cloning_times :
cloning_times + 1; x forwards Query
(msg,0,cloning_times,FALSE) to CLONING_NUM
of its neighbors as cloned walkers;
else
// forwarding as a normal searching node x forwards
Query to one of its unvisited neighbors;
end if
end
When it is not possible to hit the target
data or files the walker will become a lost walker that
is explained by directing the message, and this is
because of choosing a neighbor node that is not
suitable on its ways to find the objective data or files.
Particularly to encounter the leaving node the walkers
might become blocked such that some additional
procedure like lightweight flooding is used for the
lost searching. For this problem, a pure query
message flooding might minimize the likelihood of
blocking and this may cause lots of query messages.
To perform a lightweight flooding by pruning
neighbor links it increase the facsimile of message
problem. Conversely the query message through their
neighbors can be flooded using only most of the
selected peers.
To make it possible for a
lightweight query message flooding in resource
searching in Peer-to-Peer network we use the idea of
a dominating set in our proposed system. The
dominating set nodes only can allow message
flooding to the neighbors. The heavy load of message
duplication while finding the data or files can be
prevented by light weight flooding using dominating
set. The flooding of query message of all nodes in
black is done in pure flooding idea and consequently
similar message can be continuously sent to the
identical node more than once. All nodes receive 12
messages like (1 + 1 + 3 + 2 + 1 + 3 + 1). Totally 8 (1
+ 1 + 1 + 2 +1 + 1 + 1) messages received by all
nodes when the two nodes in green flood the query
message. By this message duplication can be
minimized drastically.
Estimating a minimum sized
dominating set is a NP-hard problem. Here we
perform by selecting dominating set as close to a
minimum one as possible and there is no need of a
minimum dominating set although it produce a better
performance since the dominating set is near a
minimum one.

IV. THEORETICAL ANALYSIS

Besides estimating the objective data or files
in the Peer-to-Peer network, the reason for major load
while finding the data or file is the produced
message. Theoretical analysis of the message
volumes produced by our scheme and others is the
attempt we perform in this part. Our analysis can
demonstrate various message loads when the
duplicated visit are not taken into account and total
query message forwarding hops are considered as the

message load. With the help of the following
representation we provoke the obtained message
volumes for various search ideas.
Here,
w - Represents the total no. of initial
walkers present in the system.
c - Denotes the no of cloned walker
represented as CLONING_NUM.
T - Indicates the maximum TTL for the
query message represented as MAX_TTL.
D - Symbolizes the cloning distance
represented as CLONING_DIST.
K - Signifies the average degree.

Additional reciprocity problem is the selection of
CLONING_DIST (D) and CLONING_NUM (c). The
settings that are provided by Peer-to-Peer network to
the users depended on network transmission
competency. When only one initial query message is
provided by Cloning Random Walker, the amount of
the additionally generated query messages before the
initial message gets terminated.

[Maximum TTL for query message
(T)]
* c
[Cloning distance (D)]

To magnify the searching area the
total quantity additionally produced query message is
set very sharp by setting either D very high or c very
low. Therefore many additional messages might be
produced by setting d very low and c very high and
this makes the network to be overloaded.
The message complication for the
different schemes is theoretically analyzed because
the message produced by searching idea will affect
the performance of the network. In the ultimate case
we take in to account that one start-to-search node
fires up w walkers making c clones every cloning
distance (D) until all the message travels till
maximum TTL hops without the loss of
simplification.

V. CONCLUSION

Here we have used two schemes called
flooding scheme to identify the unpopular data or
files and Random Walker to identify the popular data
or files in the Peer-to-Peer network because it is
difficult for us to find the popularity of the objective
data or files in this Peer-to-Peer network since it is
active. On the other hand network overloading is
caused by pure flooding scheme since it produce
more amount of query messages while minimal
success rate is produced by Random Walker method
to identify the objective data or files. The improved
scheme like light flooding that has tree sub-overlay
architecture helps to minimize the search delay but it
has high message overhead and even ticket-based
flooding that has ring-overlay architecture minimizes
message overhead but increases the search delay. So
in order to produce a better scheme that provides
good reciprocity among search delay, message
overhead and success rate in our proposed paper we
have used Cloning Random Walker assisted by
Dominating Set and this system is of the objective
data or files whether it is popular or not.

REFERENCES

[1] M. Zhong, K. Shen, J. Seiferas, The convergence-
guaranteed Random Walk and its applications in Peer-to-
Peer networks, IEEE Transactions on Computers 57 (5)
(2008) 619633.
[2] C. Gkantsidis, M. Mihail, A. Saberi, Random Walks in
Peer-to-Peer Networks, IEEE INFOCOM, 2004. pp. 120
130.
[3] S. Jiang, L. Guo, X. Zhang, H. Wang, LightFlood:
minimizing redundant messages and maximizing the scope
of peer-to-peer search, IEEE Transaction on Parallel and
Distributed Systems 19 (5) (2008) 601614.
[4] C. Gkantsidis, M. Mihail, Hybrid Search Schemes for
Unstructured Peer-to-Peer Network, vol. 3, IEEE
INFOCOM, 2005. pp. 15261537.
[5] S. Chen, Z. Zhang, S. Chen, B. Shi, Efficient file search
in non-DHT P2P networks, Computer Communication 31
(2) (2008) 304317.
[6] H. Jiang, S. Jin, Exploiting Dynamic Querying Like
Flooding Techniques in Unstructured Peer-to-Peer
Networks, ICNP, 2005. pp. 1019.

[7] V. Kalogeraki, D. Gunopulos, D. Zeinalipour-Yazti, A
Local Search Mechanism for Peer-to-Peer Networks,
CIKM, 2002. pp. 300307.
[8] A. Crespo, H. Garcia-Molina, Routing Indices for Peer-
to-Peer Systems, ICDCS, 2002. pp. 2332.
[9] B. Yang, H. Garcia-Molina, Improving Search in Peer-
to-Peer Networks, ICDCS, 2002. pp. 514.
[10] D. Menasce, L. Kanchanapalli, Probabilistic Scalable
P2P Resource Location Services, vol. 30, SIGMETRICS,
2002. Isssue. 2, pp. 4858.
[11] X. Shi, J. Han, Y. Liu, L.M. Ni, Popularity Adaptive
Search in Hybrid P2P Systems, IPTPS, 2007. pp. 110.
[12] H. Chen, H. Jin, Y. Liu, L.M. Ni, Difficulty-aware
hybrid search in Peer to-Peer networks, IEEE Transaction
on Parallel and Distributed systems 20 (1) (2009) 110.
Peer Networks, IPTPS, 2006. pp. 139153. Middleware,
2001, pp. 329350

.



Automated Resource Management System Using Virtual
Machines for Cloud Environment

V.Vijayalakshmi* S.Vimal**
*PG Student, Bharath university , Tamilnadu, Chennai
**Assistant Professor , Jeppiaar Engineering College, Tamilnadu, Chennai

ABSTRACT
Based on needs, Cloud computing allows business
customers to scale up and down their resource
usage. Virtualization Technology enables resource
multiplexing which is the base for the many of the
gains in the cloud model. In this paper, we present
a system that uses virtualization technology to
allocate and manage data center resources
dynamically based on application demands and
support green computing by optimizing the
number of servers in use. The concept of
skewness is introduced to measure the
unevenness in the multidimensional resource
utilization of a server. By minimizing skewness,
we can combine different types of workloads
nicely and improve the overall utilization of server
resources. We develop a set of heuristics that
prevent overload in the system effectively while
saving energy used. Trace driven simulation and
experiment results demonstrate that our
algorithm achieves good performance.

Keywords: Cloud computing, resource
management, virtualization, green computing
I. INTRODUCTION
Cloud computing offers elasticity and minimal
upfront capital investment which appeals to many
businesses. There is a lot of discussion on the
benefits and costs of the cloud model and on how to
move legacy applications onto the cloud platform.
Here we study a different problem: how can a cloud
service provider best multiplex its virtual resources
onto the physical hardware? This is important
because much of the touted gains in the cloud model
come from such multiplexing. Studies have found
that servers in many existing data centers are often
severely underutilized due to over provisioning for
the peak demand [1], [2]. The cloud model is
expected to make such practice unnecessary by
offering automatic scale up and down in response to
load variation. Besides reducing the hardware cost, it
also saves on electricity which contributes to a
significant portion of the operational expenses in
large data centers.
II. EXISTING SYSTEM
Virtual machine monitors (VMMs) like Xen
provide a mechanism for mapping virtual machines
(VMs) to physical resources [3]. This mapping is
largely hidden from the cloud users. Users with the
Amazon EC2 service [4], for example, do not know
where their VM instances run. It is up to the cloud
provider to make sure the underlying physical
machines (PMs) have sufficient resources to meet
their needs.
The change of mapping between VMs and PMs
while applications are running is made possible by
VM live migration technology [5].
However, a policy issue remains as how to decide
the mapping adaptively so that the resource demands
of VMs are met while the number of PMs used is
minimized. This is challenging when the resource
needs of VMs are heterogeneous due to the diverse
set of applications they run and vary with time as the
workloads grow and shrink. The capacity of PMs can
also be heterogeneous because multiple generations
of hardware coexist in a data center [6].


In this paper, we aim to achieve two goals in our
algorithm:
1) Overload avoidance: The capacity of a PM
should be sufficient to satisfy the resource needs of
all VMs running on it. Otherwise, the PM is


overloaded and can lead to degraded performance of
its VMs.
2) Green computing: The number of PMs used
should be minimized as long as they can still satisfy
the needs of all VMs. Idle PMs can be turned off to
save energy.

We present the design and implementation of an
automated resource management system that
achieves a good balance between the two goals. We
make the following contributions:
We develop a resource allocation system that
can avoid overload in the system effectively
while minimizing the number of servers used.
We introduce the concept of skewness to
measure the uneven utilization of a server. By
minimizing skewness, we can improve the
overall utilization of servers in the face of
multidimensional resource constraints.
We design a load prediction algorithm that can
capture the future resource usages of
applications accurately without looking inside
the VMs. The algorithm can capture the rising
trend of resource usage patterns and help reduce
the placement churn significantly.
IV. SYSTEM DESCRIPTION
The system architecture is presented in Fig. 1. Each
PM runs the Virtual Machine Monitor (VMM) which
supports a privileged domain 0 and one or more
domain U [3]. Each VM in domain U encapsulates
one or more applications such as Web server, remote
desktop, DNS, Mail, Map/Reduce, etc. We assume
all PMs share a same backend storage. Central
Controller Framework manages he multiplexing of
VMs to PMs. The main logic of our system is
implemented as a set of plug-ins to Central
Controller. A local node manager (LNM) runs in
each node on domain 0 collects the usage statistics of
resources for each VM on that node. The CPU and
network usage can be calculated by monitoring the
scheduling events in PMs. The memory usage within
a VM, however, is not visible to the VMM. One
approach is to infer memory shortage of a VM by
observing its swap activities [5].

Fig.1 System Architecture

We implemented a working set prober (WS Prober)
on each VMM to estimate the working set sizes of
VMs running on it. The statistics collected at each
PM are forwarded to the central controller where our
VM scheduler runs. The VM Scheduler is invoked
periodically and receives from the LNM the resource
demand history of VMs, the capacity and the load
history of PMs, and the current layout of VMs on
PMs.
The scheduler has several components. The
predictor predicts the future resource demands of
VMs and the future load of PMs based on past
statistics. The hot spot solver in our VM Scheduler
detects if the resource utilization of any PM is above
the hot threshold (i.e., a hot spot). If so, some VMs
running on them will be migrated away to reduce
their load. The cold spot solver checks if the average
utilization of actively used PMs (APMs) is below the
green computing threshold. If so, some of those PMs
could potentially be turned off to save energy. It
identifies the set of PMs whose utilization is below
the cold threshold (i.e., cold spots) and then attempts
to migrate away all their VMs. It then compiles a
migration list of VMs and passes it to the Central
Controller for execution.



V. EXPERIMENTAL RESULTS

Fig 2.1 Average decision time

Fig 2.2 Average Number of Migrations

Fig 2.3 Number of Migrations per PM

Fig 2.4 Number of Hotspots

Fig 2.5 Number of APMs

Fig 2.6 Number of Migrations



Fig 2.7 Physical Machine Usage plot
VI. CONCLUSION
We have presented the design, implementation, and
evaluation of a resource management system for
cloud computing services. Our system multiplexes
virtual to physical resources adaptively based on the
changing demand. We use the skewness metric to
combine VMs with different resource characteristics
appropriately so that the capacities of servers are well
utilized. Our algorithm achieves both overload
avoidance and green computing for systems with
multi-resource constraints.

REFERENCE
[1] M. Armbrust et al., Above the Clouds: A
Berkeley View of Cloud Computing, technical
report, Univ. of California, Berkeley, Feb. 2009.
[2] L. Siegele, Let It Rise: A Special Report on
Corporate IT, The Economist, vol. 389, pp. 3-
16, Oct. 2008.
[3] P. Barham, B. Dragovic, K. Fraser, S. Hand, T.
Harris, A. Ho, R.Neugebauer, I. Pratt, and A.
Warfield, Xen and the Art of Virtualization,
Proc. ACM Symp. Operating Systems Principles
(SOSP 03), Oct. 2003.
[4] Amazon elastic compute cloud (Amazon EC2),
http://aws.amazon.com/ec2/, 2012.
[5] T. Wood, P. Shenoy, A. Venkataramani, and M.
Yousif, Black-Box and Gray-Box Strategies for
Virtual Machine Migration, Proc. Symp.
Networked Systems Design and Implementation
(NSDI 07), Apr. 2007.
[6] Zhen Xiao, Dynamic Resource Allocation
Using Virtual Machines for Cloud Environment,
IEEE transactions on Parallel and Distributed
Systems, Vol. 24, No. 6, June 2013

www.ijrde.com

Optical Wireless Communication Using Visible Light and Pen Type
G. Shukun Karthika
UG Scholar, Jeppiaar Engineering College, Chennai.

ABSTRACT
This paper explores the use of a reading l
access point for a Visible Light Commun
downlink channel. We have established
uplink channel based on a network adapter,
both a VLC receiver and an infrared emitter.
signal power distribution over the passenger
been also studied using a Monte Carlo Ray
algorithm. The hardware implementation
results are also presented.

Index Terms Visible Light Communications,
flight communications.

I. INTRODUCTION

Offering data access during flight has recently beco
of interest for many plane building companies
Moreover, the availability of wireless band
door for new entertainment services such as
and collaborative games [1]. While so
companies are offering solutions for the plane
link, others are providing Wi-Fi-based solutions
compatibility problems with the flight i
However, the available baud rate for each user
the EM compatibility problems are still prese
plane systems, but among other users when
of them increases). Other proposals are devoted
delivery inside the aircraft so as to provide seatback
entertainment. Wireless optical communications
reducing the overall system weight induced
passenger seat. Wireless optical connectiv
advantages on a typical plane cabin as it has
[2]. The position of the passenger during
defined: s/he is usually placed on a seat
lamp pointing to her/his position at a distance
m, and having a data device (laptop, tablet or
table There are several research groups working
Sensor

G. Shukun Karthika
1
, S. Joul Monisha
2
, R. Abirami
3
, Suman
UG Scholar, Jeppiaar Engineering College, Chennai.

e use of a reading lamp as an
mmunications (VLC)
established an infrared
adapter, supporting
emitter. The optical
passenger area has
rlo Ray-Tracing
tion and testing
Light Communications, In-
ght has recently become an area
anies and airlines.
ndwidth opens the
as video selection
some networking
the plane-to-earth data
tions to deal with
t instrumentation.
user is limited and
resent (not with the
when the amount
devoted to multimedia
provide seatback
unications is a way of
induced by wiring each
vity offers some
it has no EM concerns
during flight is well
seat with a reading
distance of about 1.5
tablet or phone) over the
working in this area.
M. Kavehrad has also studied theoretically
power line networks for providing
communications by modulating LED
have proposed creating infrared
implement the user link. In previous works, we have
how to solve the connection of the la
and a first approach based on an USB connection.
we propose a full optical wireless strategy
connectivity in planes during flight.
downlink, while an infrared link provides
Modulations and circuit implementations
are also studied. Moreover, we
adapter architecture, an exhaustive
channel should be easy. Description
and an analysis of the power budget on
This paper is organized as follows:
presented in section II, while sections
to the downlink VLC simulation and
implementation. Section V shows results and
performed measurements.

Fig 1: Transmitter

- 509-513
509 | P a g e
, Suman
4
eoretically the use of on board
providing both electricity and
LED lamps, while Elgala et al
communications cells to
user link. In previous works, we have presented
e lamp with the Ethernet link
on an USB connection. In this paper
full optical wireless strategy for passenger
flight. It uses a VLC system as a
link provides the uplink channel.
entations for a system prototype
introduce a new network
cm, so focusing the uplink
escription of the system performance
budget on the passenger seat [3-4].
ws: a system description is
sections III and IV are devoted
lation and the HW system
shows results and different

Transmitter
www.ijrde.com

Fig2: Receiver

pp- 509-513
510 | P a g e

Finally, some conclusions are provided infrared emitter
pointing upwards has a diameter of about 50. Furthermore, we
shall employ an existing resource as the illumination lamp is
always present. As the use of LEDs instead of other
illumination sources does not present major regulation
concerns, many plane providers appreciate their lifetime, low
power consumption and chromaticity properties

II. SYSTEM DESCRIPTION
An internet in-flight system can be divided into three main
subsystems:
Ground to aircraft link: It provides the connection between
the aircraft and the Internet Service Provider (ISP). It can be
implemented by satellite or a direct ground RF link. This
block can be removed if only entertainment services like video
and audio broadcasting are to be offered by a company.
Network distribution: Shielded twisted pair cables are the
most commonly used inside the aircraft; however optical fiber
is expected to be used in the future.
User link: With the aim of reducing the amount of needed
cable, a wireless link seems to be an optimal solution. This
work focuses on this subsystem.
Let us consider a line-of-sight VLC data link from the
reading lamp and an uplink channel based on a line-of-sight
infrared channel from the computer (or data device) to a
photodiode on the plane ceiling (close to the reading lamp, see
Fig. 1). Two communication devices working as adapters have
been developed: the first one, known as "lamp adapter", gets
the packets from the regular distribution network (Ethernet or
PLC) and behaves as a bridge, replicating the information at
the optical interface. The second one, known as "passenger
data adapter", is characterized by having a similar behavior,
using the Ethernet or USB port of the mobile devices instead
of the aircraft distribution network as data source or sink.
Therefore, the only difference between the adapters is the
working wavelength of the optical link (VLC from
distribution network to user, and IR in the other direction).

III. VLC DOWNLINK CHANNEL ANALYSIS
In the proposed system topology, each passenger is
considered to be inside a microcell. However, it could be
possible that nearby users or cabin illumination lamps
generate harmful interference due to a wide lamp emission
pattern or a high photodiode FOV. In addition, reflections on
different objects could dramatically reduce the system
performance. Here we opt for the use of optical lenses for
collimating the light beam in the passenger's table. A
simulation based on a Monte Carlo-Ray tracing algorithm has
been performed in order to calculate the Signal Noise Ratio
(SNR) at different point of the user's table. We have
considered 3 emitters, corresponding to the three reading
lights, and 740 receivers distributed over the passenger's table.
The following table shows the parameters used in all the
performed simulations. Different simulations varying the
lambertian coefficient (n) of the lamp have been performed,
getting reflectance patterns, and then SNR and SIR distribution
patterns from a top view.
The rectangle represents the passengers table, where the
device should be placed, although a good system performance
can be offered in all the area of the passenger's seat. Fig. 3
shows SIR values at different points of the users table when a
LED lamp with n=50 is used. Under this situation, the worst
ratio is up to 16.85 dB. Fig. 4 shows the CR-DPPM (Constant
Rate DPPM) bit error rate evolution when is interfered by the
adjacent user. In spite of this is the codification scheme used
to implement the downlink channel in this work, it can be
changed without loss of generality by other PPM schemes
such as the VPPM models currently under consideration by
the IEEE 802.15.7 committee.
Based on these simulation results, we can affirm that the
system performance reduction is negligible so as there is
a BER deterioration of 0.25 dB. In spite of that, the effect
could be mitigated increasing the lambertian coefficient of the
lamp employing WDM (Wavelength Division Multiplexing)
techniques over RGB LEDs. Fig. 5 shows the Signal Noise
Ratio distribution over the user's table, which shows values up
to 70 dB. These ratios do not affect the system performance.

IV. VLC DOWNLINK IMPLEMENTATION

In order to use an illumination lamp as a VLC device, a
codification scheme that allows a constant illumination
level at the lamp and data transmission is needed. In this work,
CR- DPPM (Constant Rate DPPM) is considered because of
its simplicity and low cost of implementation, which is only
based on an edge detector and a counter. This scheme does not
only offer the advantages of DPPM (which encodes the data
by modifying the distance between the pulses), but also allows
a constant bit rate, which makes the implementation of
multimedia applications easier. In addition, it is suitable to be
used simultaneously in communications and illumination
systems due to the absence of light flickering.
Different codification schemes have been studied as well.
OFDM techniques offer both good multipath and narrowband

interference rejection response, but imply quite expensive
hardware requirements. VOOK and VPPM schemes have been
proposed in the under development VLC standard (802.15.7) as
modifications of the OOK and PPM codifications respectively,
with the aim of adding dimming capabilities. However, OOK
does not guarantee the absence of flickering and both of them
(OOK and PPM) have lower spectral efficiency than DPPM.
Regarding the PPM scheme, it is characterized by having a
better system performance against AWGN, but it is not a real
necessity in VLC applications as the SNR values are
commonly really high. The synchronization task, on its part,
turns out to be much more difficult to accomplish than in CR-
DPPM. If VPPM or VOOK are eventually defined as the
codifications for the standard, many of these results would
be also applied without significant modifications.
The communications behavior of LED lamps is limited by
and fall times (100 ns for white phosphor LEDs), so the pulse
width should be at least 200 ns, which is the upper bound
of the lamp switching rate. In addition, the LED switching
should be fast enough to avoid light flickering, fixing the lower
frequency limit at several hundreds of Hz. The ratio between
the ON and OFF periods determines the illumination level of
the lamp.
The proposed topology might work with data coming
from PLC, twisted pair cables or optical fiber. The first
solution avoids the necessity of performing any changes in
the cabin topology as it uses the power lines of the aircraft
itself to transmit the data. However, it could be noisy and
generate EM interference with the aircraft instrumental
systems. We shall consider, as an alternative, Ethernet as a
distribution network inside de aircraft and the use of a
Power over Ethernet (PoE) system to feed them up, and so
the same shielded twisted pair cable will be used to transmit
the data and to power the lamps. This fact generates a
weight reduction in the aircraft installation needed to offer
this kind of services. As commented on above, there are two
different adapters: the lamp adapter and the passenger
adapter. Both of them have a similar functionality, but they
differ in the power supply needed and the final optical
interface they use to make the electro-optical conversion. The
lamp adapter is fed with a PoE device and uses a visible light
LED to do the transmission, whereas the passenger adapter
uses the USB port as power supply, which offers up to
500mA at 5V.
A. Ethernet-wireless optical system adapter
The interface between the Ethernet data and the optical
access point is based on a bridge between the network and the
optical downlink. This bridge detects the packets, modifies
them at the MAC layer and finally codifies the frames in CR-
DPPM to be transmitted through the VLC downlink. Multiple
access strategies are not to be considered a major concern for
this application as the VLC emitter can be optically limited by
rise.
V. RESULTS

Fig 3: Packet Lost

Fig 4: Packet lost vs Normalized data rate

VI. CONCLUSION
In this paper, a low cost VLC system for in-flight
applications is presented. Full wireless optical connectivity is
obtained by using a VLC system for the downlink and an IR
system for the uplink. The developed adapter for the passenger

laptop offers a versatile solution using the Ethernet port without
the installation of an extra driver. Working at the MAC layer
also allows full transparency to the user applications. The
presented system can be rapidly implemented and provides
personalized in-flight entertainment and services by wireless
media. This technology does neither suffer nor produce
interference with radio. Baud rates can be significantly increased
using RGB LEDs lamps and ASIC devices. Protocol
requirements on the optical channel are also reduced because
each couple lamp-photodiode acts as a dedicated access point for
each singular seat.

REFERENCE
1. C. Quintana, V. Guerra, J. Rufo, J. Rabadan and R. Perez-
Jimenez, Reading Lamp-Based Visible Light
Communication System for In-flight Entertainment, IEEE
Transactions on Consumer Electronics, Vol. 59, No. 1,
February 2013.
2. Isaac Keslassy, Cheng-Shang Chang, Nick McKeown, Duan-
Shin Lee (2009), Optimal Load-Balancing, IEEE
International Conference, Volume-2, pp.11-14
3. Suyog K. Dahule, M.A. Gaikwad (August 2012), Design &
Simulation of Round Robin Arbiter for NoC Architecture,
International Journal of Engineering and Advanced
Technology (IJEAT) ISSN: 2249 8958, Volume-1, Issue-6
4. Mark Davids, Grosse Pointe South H.S., Grosse
PointeFarms, Rick Forrest, Rochester H.S., Rochester, Don
Pata, Grosse Pointe North H.S., Grosse Pointe Farms, MI,
Teaching the Fundamentals of Cell Phones and Wireless
Communications.


Investigation on Performance of Fractional Order PI
Controller for a Class of Fractional Order Systems
P.Anbumalar
1
, C. Barath Kanna
2
, S. Syed Yaseen
3
1
Assistant Professor, Department of EIE, B. S. Abdur Rahman University, Chennai, India
2
PG Student, Department of EIE, B. S. Abdur Rahman University, Chennai, India
3
UG Student, Department of EIE, B. S. Abdur Rahman University, Chennai, India

ABSTRACT
In recent years, it is remarkable to see the
increasing number of studies related to the theory
and application of fractional order controller,
especially
controller, in many areas of

science and engineering. Research activities are
focused on developing new analysis and design
methods for fractional order controllers as an
extension of classical control theory. In this paper,
the fractional/integer order PI has been designed
for the fractional/integer order system based on the
phase margin specification. Further the
performance analysis has been made for the
designed fractional/integer order PI with
fractional/integer order systems based on integral
of squared error criteria. It should be noted that,
the servo response of the fractional order PI
controller for fractional/integer order system has
been found to be satisfactory.

Keywords: Fractional Calculus, Integer order
system, Fractional order controller
I. INTRODUCTION
Many real dynamic systems are better characterized
using a non-integer order dynamic model based on
fractional calculus or, differentiation or integration of
non integer order. Traditional calculus is based on
integer order differentiation and integration. The
concept of fractional calculus [1] has tremendous
potential to change the way we see, model, and control
the nature around us. Denying fractional derivatives is
like saying that zero, fractional, or irrational numbers
do not exist. .Fractional calculus is a more than 300
years old topic. The number of applications where
fractional calculus has been used rapidly grows.

These mathematical phenomena allow describing a
real object more accurately than the classical integer-
order methods. The real objects are generally
fractional [2], [3], [4], [5], however, for many of them
the fractionality is very low. A typical example of a
non-integer (fractional) order system is the voltage-
current relation of a semi-infinite lossy transmission
line [6] or diffusion of the heat through a semi-infinite
solid, where heat flow is equal to the half-derivative of
the temperature [7]. The main reason for using the
integer-order models was the absence of solution
methods for fractional differential equations [6-8]. At
present time there are lots of methods for
approximation of fractional derivative and integral and
fractional calculus can be easily used in wide areas of
applications (e.g. control theory - new fractional
controllers and system models, electrical circuit theory
- fractances, capacitor theory, etc.).
II. FRACTIONAL ORDER SYSTEM
Contrary to the traditional approach, here we will
consider the transfer function of an arbitrary real
order, called as fractional order system. In other
words, fractional order system means system which
are better described by fractional order mathematical
models. Let us consider the fractional order transfer
function (FOTF) given by the following expressions:

Where
,
( = 0,1, , ) is an arbitrary real number
>
> >
>
> 0,
, ( =
0,1,,)
is an arbitrary constant. In time domain, the FOTF
corresponds to the n-tern inhomogenous fractional
order differential equation (FODE) can be represented
as
() +
() + +
()
+
() = ()
III. FRACTIONAL ORDER CALCULUS
Fractional calculus is three centuries old as the
conventional calculus, but not very popular among
science and/or engineering community. The beauty of
this subject is that fractional derivatives (and integrals)
are not a local (or point) property (or quantity).
Thereby this considers the history and non-local
distributed effects. In other words, perhaps this subject
translates the reality of nature better! Therefore to
make this subject available as popular subject to
science and engineering community, it adds another
dimension to understand or describe basic nature in a
better way. In a letter dated 30th September 1695,
() =
1
++



LHopital wrote to Leibniz asking him a particular
notation that he had used in his publication for the nth
derivative of a function.
()
. i.e., what would the

result be if n = , in other words, fractional calculus
was born. Fractional calculus does not mean the
calculus of fractions, nor does it mean a fraction of
any calculus differentiation, integration, or calculus of
variations. The fractional calculus is a name of theory
of integrations and derivatives of arbitrary order,
which unify and generalize the notion of integer order
differentiation and n-fold integration. So we call it
generalized differ integrals.

The fractional-order differentiator is often denoted by
, where a and t are respectively the lower- and

upper bounds, and is the order of derivative or
integrals, which can be non-integers, or even complex
numbers [9].The definition of fractional-order
operator is:

/ , ( ) 0
1, ( ) 0
( ) , ( ) 0
a t
t
a
d d t R
D R
d R

>
= =
<

where ( ) R is the real part of . The most
commonly used definitions are the Grunwald-
Letnikov (GL) definitions and the Riemann-Liouville
(RL) definitions.

The RL definition is
1 ( )
1 ( )
( )
( ) ( )
m t
a t m
a
d f
D f t d
m dt t

| |
| |
=
| |
\
\

Where m-1< < m, and ( ) x is the well-known
Euler Gamma function.

The GL definition is
| |
[ / ]
0
0
1 ( 1)
( ) lim ( )
( ) ( 1)
x a h
a x
h
k
D f t f t kh
h k
=
+
=
+
.
IV. FRACTIONAL ORDER
CONTROLLER DESIGN
In this section, fractional/integer order proportional
integral derivative controller is designed for a class of
second order plant using tuning method proposed by
Ying Luo, Chun Yang Wang and Yang Quan Chen.
The tuned FO-PI controller can ensure that the given
gain crossover frequency and phase margin are
fulfilled and furthermore, the phase derivative w. r. t.
the frequency is zero, i.e., the phase plot of bode
diagram is flat at the given gain crossover frequency.
Assume that the gain crossover frequency is given by
and phase margin is specified by
. To ensure the
system stability and robustness, three specifications
are proposed as follows [3],
(i) Phase margin specification
(
) = (
)(
) = +

(4.1)
(ii) Robustness to variation in the gain of
the plant with the condition that the phase derivative
w.r.t. the frequency is zero, i.e., the phase plot of bode
diagram is flat, at the gain crossover frequency; it
means that the system is more robust to gain changes
and the overshoots of the response are almost the
same;

((()))
= 0

(4.2)
(iii) Gain crossover frequency
specification
|(
)|
= |(
)(
)|
= 0
(4.3)

With reference to the three specifications as
mentioned above, the following controllers has been
designed as proposed by Ying Luo, Chun Yang Wang
and Yang Quan Chen for the class of fractional/integer
order system considered.
(i) Fractional order proportional integral
controller (FO-PI) for fractional order system
(ii) Fractional order proportional integral
controller (FO-PI) for integer order system
(iii) Integer order proportional integral controller
(IO-PI) for integer order system
(iv) Integer order proportional integral controller
(IO-PI) for fractional order system

A. Fractional order proportional integral
controller(FO-PI) for fractional order
system:

The fractional order proportional and integral
controller FO-PI has the following form of transfer
function:
() =
1 +

(4.4)


The typical second-order plant discussed in [1] is

() =

(4.5)

() =

Let = 1 +
cos
cos
; =
1sin2+2sin2
The phase and gain of the plant in frequency domain
can be given by
() =

(4.6)
|()| =

(4.7)
Fractional order controller described by (3.4) can

be written as,
() =
1 +
()

() =
1 +
cos
sin

(4.8)
The phase and gain are as follows,
() = tan

(4.9)

|()| =
(1 +
cos
+ (
sin

(4.10)
The open loop transfer function is that () =
()() and from Eq (4.6)-(4.10) the phase and gain
of () is as follows,
() = () + ()

() = tan

(4.11)
|()| = |()||()|
=

(4.12)
According to Specification (4.1) about the phase
of (), the relationship between
and can be
established as follows:
() = tan
= +

(4.13)
= tan tan

According to Specification (4.2) about the robustness
to gain variations in the plant, we can establish an
equation about
in the following form:

()
= 0

= 0

=

= 2
cos
2

According to Specification (4.3), we can establish an
equation
about:

|(
)|
= |(
)(
)|
= 0

(4.15)

B. Fractional order proportional integral
controller(FO-PI) for Integer order system :
The fractional order proportional and integral
controller FO-PI has the following form of transfer
function:
() =
1 +

(4.16)

() =

(4.17)
() =

Let = 1
; =

can be given by
() =
(4.18)
|()| =

(4.19)
Fractional order controller described by (3.4) can

be written as,


() =
1 +
()

() =
1 +
cos
sin

(4.20)
() = tan

(4.21)

|()| =
(1 +
cos
+(
sin
(4.22)
() = () + ()
() = tan
(4.23)
|()| = |()||()|
=

(4.24)
and can be
() = tan
= +

(4.25)
= tan tan

equation about

( )
= 0

= 0

=

(4.26)
= 2
cos

equation
about:
|(
)|
= |(
)(
)|
= 0

(4.27)
C. Integer order proportional integral controller
(IO-PI) for Integer order System
The integer order proportional and integral controller
IO-PI has the following form of transfer function:
() =
1 +

(4.28)

() =

(4.29)
() =

Let = 1
; =

can be given by
() =
(4.30)
|()| =

(4.31)
PI integer order controller described by (4.4) can be
written as,
() =
1 +
/() =
(1
1
(4.32)
() = tan
(4.33)
|()| =
(1 +
) (4.34)
() = () +()
() = tan

(4.35)
|()| = |()||()|


=

2
+
2
(4.36)
and can be
() = tan
= +

(4.37)
equation
about:
|(
)|
= |(
)(
)|
= 0

)

(4.38)
D. Integer order proportional integral controller
(IO-PI) for Fractional order System
The integer order proportional and integral controller
IO-PI has the following form of transfer function:
() =
1 +
(4.39)
() =

(4.40)
()
=
1
1 +
cos
cos
sin
sin

Let = 1 +
cos
cos
; =
1sin2+2sin2
can be given by
() =

(4.41)
|()| =

(4.42)
PI integer order controller described by (4.4) can be
written as,
() =
1 +
/() =
(1
()
)
(4.43)
() = tan

(4.44)
|()| =
(1 +
)
(4.45)
() = () + ()
() = tan

(4.46)
|()| = |()||()|
=

(

(4.47)
and can be
() = tan
= +
(4.48)
equation about

( )
= 0

= 0

(4.49)
=

(4.50)
equation
about:
|(
)|
= |(
)(
)|
= 0

)
(4.51)
From the Eq (4.50-4.51), it is clear that we cannot
guarantee the stability of the fractional order system
with integer order controller based on gain and phase
margin specification.
V. RESULTS AND DISCUSSIONS
The example of a heating furnace[1] is considered
here, which can be modeled by the integer and the
fractional order differential equations, respectively as


shown in figure 3.1. According to [1], the integer
order model of the heating furnace is a second order
transfer function and it is given by

() =

.

While the fractional order model is given by

() =

.
.

() =

() =

.
.

Figure 1: Open loop response of integer/fractional order
system

With gain cross over frequency = 1 / and
phase margin
= 60
, Table 1 show the

fractional/integer order PI controller transfer function
for fractional/integer order systems Equations (4.50-
4.51)

Table 1: Fractional/integer order PI controller design for
fractional/integer order

System
Controller

Fracti
onal
order

Integ
er
orde
r
Fractio
nal
order
.
.

804.8111
.
.

Unst
able

Integer
order
.

155.023 +
.
.

18.75 +
.

Figure2 show the closed loop response of
fractional/integer order system with fractional/integer
order PI controller when it is subjected to unit step
input and it has been inferred that the servo
performance of fractional order controller for
fractional order system is found to be satisfactory.

Figure 2: Closed loop response of fractional/integer order PI
controller for fractional/integer order system
VI. CONCLUSION
In this paper, the fractional/integer order PI controllers
has been designed based on gain margin and phase
margin specification as proposed by Ying Luo and
Yang Quan Chen for the class of fractional/integer
order system considered. Further the performance of
the closed loop response of fractional/integer order
systems with fractional/integer order PI controller has
been analyzed based on integral square error (ISE)
criteria and servo performance of the designed
fractional order PI controller for fractional order
system is found to be satisfactory, when compared to
the closed loop response of fractional order PI
controller for integer order system. And it has been
illustrated from the simulation results that the best
fractional order controller outperforms best integer
order controller.
REFERENCES
[1] Chunna Zhao and Dingyii Xue , A fractional order
PID tuning algorithm for a class of fractional order
plants, IEEE Transactions ,july 2005.
[2] Ho-wang fung, Qing- Guo Wang and Yu Zhang, PID
tuning with exact gain and phase margins,ISA
Transaction 38,1999.
[3] Chun Yang Wang,Yang Quen Chen and Ying Luo,
tuning fractional order proportional integral
FO PI with FOS
FO PI with IOS
IO PI with IOS



controllers fractional order system, IEEE
Transactions, 2009.
[4] Dingyu Xue, Ivo Petras and YangQuan Chen,
Fractional Order Control - A Tutorial,American
Control Conference Hyatt Regency Riverfront, St.
Louis,MO, USA,June 10-12, 2009.
[5] I. Podlubny, Fractional-order systems and PID
controllers, IEEE Transactions on Automatic
Control, vol. 44, no. 1, 1999, pp. 208 214.
[6] Chunna ZHAO and Dingyu XUE, Closed-form
solutions to fractional-order linear differential
EquationsFront.electr.electronic.Engg.china 2008.3(
2):214-217.
[7] HongSheng Li, Ying Luo, and YangQuan Chen, A
Fractional Order Proportional and Derivative (FOPD)
Motion Controller IEEE transactions on control
systems technology,2009.
[8] Hongsheng Li and Yang Quan Chen, Fractional order
Proportional and derivative (FOPD) controller tuning
algorithm, IEEE transactions on 2008.

Privacy Preservation on Encrypted Intermediate Data in
Cloud Computing

D.Ramya
PG student, Bharath University,Tamilnadu,Chennai

ABSTRACT

As Cloud Computing becomes prevalent, more
and more sensitive information are being
centralized into the cloud. For the protection of
data privacy, sensitive data usually have to be
encrypted before outsourcing, which makes
effective data utilization a very challenging task.
Although traditional searchable encryption
schemes allow a user to securely search over
encrypted data through keywords and selectively
retrieve files of interest, these techniques support
only exact keyword search. That is, there is no
tolerance of minor typos and format
inconsistencies which, on the other hand, are
typical user searching behavior and happen very
frequently. This significant drawback makes
existing techniques unsuitable in Cloud
Computing as it greatly affects system usability,
rendering user searching experiences very
frustrating and system efficacy very low. In this
paper, for the first time we formalize and solve the
problem of effective fuzzy keyword search over
encrypted cloud data while maintaining keyword
privacy. Fuzzy keyword search greatly enhances
system usability by returning the matching files
when users searching inputs exactly match the
predefined keywords or the closest possible
matching files based on keyword similarity
semantics, when exact match fails. In our solution,
we exploit edit distance to quantify keywords
similarity and develop an advanced technique on
constructing fuzzy keyword sets, which greatly
reduces the storage and representation overheads.
Through rigorous security analysis, we show that
our proposed solution is secure and privacy-
preserving, while correctly realizing the goal of
fuzzy keyword search.

Keywords: Edit distance, fuzzy keyword, wild
card, keyword set, encryption, storage-efficient

I. INTRODUCTION

As Cloud Computing becomes prevalent, more and
more sensitive information are being centralized into
the cloud, such as emails, personal health records,
government documents, etc [1-4]. By storing their
data into the cloud, the data owners can be relieved
from the burden of data storage and maintenance so
as to enjoy the on-demand high quality data storage
service. However, the fact that data owners and cloud
server are not in the same trusted domain may put the
outsourced data at risk, as the cloud server may no
longer be fully trusted [5-8]. It follows that sensitive
data usually should be encrypted prior to out-
sourcing for data privacy and combating unsolicited
accesses. However, data encryption makes effective
data utilization a very challenging task given that
there could be a large amount of outsourced data
files. Moreover, in Cloud Computing, data owners
may share their outsourced data with a large number
of users. The individual users might want to only
retrieve certain specific data files they are interested
in during a given session [9-13]. One of the most
popular ways is to selectively retrieve files through
keyword-based search instead of retrieving all the
encrypted files back which is completely impractical
in cloud computing scenarios. Such keyword-based
search technique allows users to selectively retrieve
files of interest and has been widely applied in
plaintext search scenarios, such as Google search [1].
Unfortunately, data encryption restricts users
ability to perform keyword search and thus makes the
traditional plaintext search methods unsuitable for
Cloud Computing. Besides this, data encryption also
demands the protection of keyword privacy since
keywords usually contain important information
related to the data files. Although encryption of
keywords can protect keyword privacy, it further

renders the traditional plaintext search techniques
useless in this scenario [14-16].
To securely search over encrypted data, searchable
encryption techniques have been developed in recent
years [2].[10]. Searchable encryption schemes
usually build up an index for each keyword of
interest and associate the index with the files that
contain the keyword. By integrating the trapdoors of
keywords within the index information, effective
keyword search can be realized while both file
content and keyword privacy are well-preserved.
Although allowing for performing searches securely
and effectively, the existing searchable encryption
techniques do not suit for cloud computing scenario
since they support only exact keyword search. That
is, there is no tolerance of minor typos and format
inconsistencies. It is quite common that users
searching input might not exactly match those pre-set
keywords due to the possible typos, such as Illinois
and Ilinois, representation inconsistencies, such as
PO BOX and P.O. Box, and/or her lack of exact
knowledge about the data. The naive way to support
fuzzy keyword search is through simple spell check
mechanisms. However, this approach does not
completely solve the problem and sometimes can be
ineffective due to the following reasons: on the one
hand, it requires additional interaction of user to
determine the correct word from the candidates
generated by the spell check algorithm, which
unnecessarily costs users extra computation effort;
on the other hand, in case that user accidentally types
some other valid keywords by mistake (for example,
search for hat by carelessly typing cat), the
spell check algorithm would not even work at all, as
it can never differentiate between two actual valid
words. Thus, the drawbacks of existing schemes
signifies the important need for new techniques that
support searching flexibility, tolerating both minor
typos and format inconsistencies. preserving fuzzy
keyword search in Cloud Computing. To the best of
our knowledge, we formalize for the first time the
problem of effective fuzzy keyword search over
encrypted cloud data while maintaining keyword
privacy. Fuzzy keyword search greatly enhances
system usability by returning the matching files when
users searching inputs exactly match the predefined
keywords or the closest possible matching files based
on keyword similarity semantics, when exact match
fails. More specifically, we use edit distance to
quantify keywords similarity and develop a novel
technique, i.e., an wildcard-based technique, for the
construction of fuzzy key-word sets. This technique
eliminates the need for enumerating all the fuzzy
keywords and the resulted size of the fuzzy keyword
sets is significantly reduced. Based on the
constructed fuzzy keyword sets, we propose an
efficient fuzzy keyword search scheme. Through
rigorous security analysis, we show that the proposed
solution is secure and privacy-preserving, while
correctly realizing the goal of fuzzy keyword search.
The rest of paper is organized as follows: Section II
summarizes the features of related work. Section III
introduces the system model, threat model, our
design goal and briefly describes some necessary
background for the techniques used in this paper.
Section IV shows a straightforward construction of
fuzzy keyword search scheme. Section V provides
the detailed description of our proposed schemes,
including the efficient constructions of fuzzy
keyword set and fuzzy keyword search scheme.
Section VI presents the security analysis. Finally,
Section VIII concludes the paper.

II. RELATED WORK

Plaintext fuzzy keyword search. Recently, the
importance of fuzzy search has received attention in
the context of plaintext searching in information
retrieval community [11].[13]. They addressed this
problem in the traditional information-access
paradigm by allowing user to search without using
try-and-see approach for finding relevant information
based on approximate string matching. At the first
glance, it seems possible for one to directly apply
these string matching algorithms to the context of
searchable encryption by computing the trapdoors on
a character base within an alphabet. However, this
trivial construction suffers from the dictionary and
statistics attacks and fails to achieve the search
privacy.
Searchable encryption. Traditional searchable
encryption [2].[8], [10] has been widely studied in
the context of cryptography. Among those works,
most are focused on efficiency improvements and

security definition formalizations. The first
construction of searchable encryption was proposed
by Song et al. [3], in which each word in the
document is encrypted independently under a special
two-layered encryption construction. Goh [4]
proposed to use Bloom filters to construct the indexes
for the data files. To achieve more efficient search,
Chang et al. [7] and Curtmola et al. [8] both proposed
similar index approaches, where a single
encrypted hash table index is built for the entire

file collection. In the index table, each entry consists
of the trapdoor of a keyword and an encrypted set of
file identifiers whose corresponding data files contain
the keyword. As a complementary approach, Boneh
et al. [5] presented a public-key based searchable
encryption scheme, with an analogous scenario to
that of [3]. Note that all these existing schemes
support only exact keyword search, and thus are not
suitable for Cloud Computing.
Others. Private matching [14], as another related
notion, has been studied mostly in the context of
secure multiparty computation to let different parties
compute some function of their own data
collaboratively without revealing their data to the
others. These functions could be intersection or
approximate private matching of two sets, etc. The
private information retrieval [15] is an often-used
technique to retrieve the matching items secretly,
which has been widely applied in information
retrieval from database and usually incurs
unexpectedly computation complexity.

III. PROBLEM FORMULATION

A. System Model
In this paper, we consider a cloud data system
consisting of data owner, data user and cloud server.
Given a collection of n encrypted data files C= (F1,
F2, . . . , FN) stored in the cloud server, a predefined
set of distinct keywords
W= {w1, w2, ..., wp}, the cloud server provides the
search service for the authorized users over the
encrypted data C. We assume the authorization
between the data owner and users is appropriately
done. An authorized user types in a request to
selectively retrieve data files of his/her interest. The
cloud server is responsible for mapping the searching
request to a set of data files, where each file is
indexed by a file ID and linked to a set of keywords.
The fuzzy keyword search scheme returns the search
results according to the following rules: 1) if the
users searching input exactly matches the pre-set
keyword, the server is expected to return the files
containing the keyword1; 2) if there exist typos
and/or format inconsistencies in the searching input,
the server will return the closest possible results
based on pre-specified similarity semantics (to be
formally defined in section III-D). An architecture of
fuzzy keyword search is shown in the Fig. 1.
B. Threat Model
We consider a semi-trusted server. Even though data
files are encrypted, the cloud server may try to derive
other sensitive information from users search
requests while performing keyword-based search
over C. Thus, the search should be conducted in a
secure manner that allows data files to be securely
retrieved while revealing as little information as
possible to the cloud server. In this paper, when
designing fuzzy keyword search scheme, we will
follow the security definition deployed in the
traditional searchable encryption [8]. More
specifically, it is required that nothing should be
leaked from the remotely stored files and index
beyond the outcome and the pattern of search queries.
C. Design Goals
In this paper, we address the problem of supporting
efficient yet privacy-preserving fuzzy keyword

search services over encrypted cloud data.
Specifically, we have the following goals: i) to
explore new mechanism for constructing storage-
efficient fuzzy keyword sets; ii) to design efficient
and effective fuzzy search scheme based on the
constructed fuzzy keyword sets; iii) to validate the
security of the proposed scheme.
D. Preliminaries
Edit Distance There are several methods to
quantitatively measure the string similarity. In this
paper, we resort to the well-studied edit distance [16]
for our purpose. The edit distance ed(w1, w2)
between two words w1 and w2 is the number of
operations required to transform one of them into the
other. The three primitive operations are 1)
Substitution: changing one character to another in a
word; 2) Deletion: deleting one character from a
word; 3) Insertion: inserting a single character into a
word. Given a keyword w, we let Sw,d denote the set
of words w_ satisfying ed(w, w_) d for a certain
integer d.
Fuzzy Keyword Search Using edit distance, the
definition of fuzzy keyword search can be formulated
as follows: Given a collection of n encrypted data
files C = (F1, F2, . . . , FN ) stored in the cloud
server, a set of distinct keywords W = {w1, w2, ...,
wp } with predefined edit distance d, and a searching
input (w, k) with edit distance k (k d), the
execution of fuzzy keyword search returns a set of
file IDs whose corresponding data files possibly
contain the word w, denoted as F IDw : if w = wi
W , then return F IDwi ; otherwise, if w _ W , then
return {F IDwi }, where ed(w, wi) k. Note that the
above definition is based on the assumption that k
d. In fact, d can be different for distinct keywords and
the system will return {F IDwi } satisfying ed(w, wi)
min{k, d} if exact match fails.

IV. THE STRAIGHTFORWARD
APPROACH

Before introducing our construction of fuzzy
keyword sets, we first propose a straightforward
approach that achieves all the functions of fuzzy
keyword search, which aims at providing an
overview of how fuzzy search scheme works over
encrypted data.
Assume =(Setup(1), Enc(sk, ), Dec(sk, )) is
a sym-metric encryption scheme, where sk is a secret
key, Setup(1) is the setup algorithm with security
parameter , Enc(sk, ) and Dec(sk, ) are the
encryption and decryption algorithms, respectively.
Let Twi denote a trapdoor of keyword wi. Trap-doors
of the keywords can be realized by applying a one-
way function f , which is similar as [2], [4], [8]:
Given a keyword wi and a secret key sk, we can
compute the trapdoor of wi as Twi = f (sk, wi).
The scheme of the fuzzy keyword search goes as
follows:
We begin by constructing the fuzzy keyword set
Swi,d for each keyword wi W (1 i p) with
edit distance d. The intuitive way to construct the
fuzzy keyword set of wi is to enumerate all possible
words wi_ that satisfy the similarity criteria ed(wi,
wi_) d, that is, all the words with edit distance d
from wi are listed. For example, the following is the
listing variants after a substitution operation on the
first character of keyword CASTLE: {AASTLE,
BASTLE, DASTLE, , YASTLE, ZASTLE}.
Based on the resulted fuzzy keyword sets, the fuzzy
search over encrypted data is conducted as follows:
1) To build an index for wi, the data owner computes
trapdoors Twi = f (sk, wi_) for each wi_ Swi,d
with a secret key sk shared between data owner and
authorized users. The data owner also encrypts
FIDwi as Enc(sk, FIDwi _wi). The index table
{({Twi }wiSwi,d , Enc(sk, FIDwi _wi))}wiW
and encrypted data files are outsourced to the cloud
server for stroage; 2) To search with w, the
authorized user computes the trapdoor Tw of w and
sends it to the server; 3) Upon receiving the search
request Tw , the server compares it with the index
table and returns all the possible encrypted file
identifiers {Enc(sk, FIDwi _wi)} according to the
fuzzy keyword definition in section III-D. The user
decrypts the returned results and retrieves relevant
files of interest.
This straightforward approach apparently provides
fuzzy keyword search over the encrypted files while
achieving search privacy using the technique of
secure trapdoors. However, this approach has serious

efficiency disadvantages. The simple enumeration
method in constructing fuzzy keyword sets would
introduce large storage complexities, which greatly
affect the usability. Recall that in the definition of
edit distance, sub-stitution, deletion and insertion are
three kinds of operations in computation of edit
distance. The numbers of all similar words of wi
satisfying ed(wi, wi_) d for d = 1, 2 and 3 are
approximately 2k 26, 2k 2 262, and 43 k3
263, respectively. For example, assume there are 104
keywords in the file collection with average keyword
length 10, d = 2, and the output length of hash
function is 160 bits, then, the resulted storage cost for
the index will be 30GB. Therefore, it brings forth the
demand for fuzzy keyword sets with smaller size.

V. CONSTRUCTIONS OF EFFECTIVE
FUZZY KEYWORD

SEARCH IN CLOUD
The key idea behind our secure fuzzy keyword search
is two-fold: 1) building up fuzzy keyword sets that
incorporate not only the exact keywords but also the
ones differing slightly due to minor typos, format
inconsistencies, etc.; 2) designing an efficient and
secure searching approach for file retrieval based on
the resulted fuzzy keyword sets.

A. Advanced Technique for Constructing Fuzzy
Keyword Sets
To provide more practical and effective fuzzy
keyword search constructions with regard to both
storage and search efficiency, we now propose an
advanced technique to improve the straightforward
approach for constructing the fuzzy keyword set.
Without loss of generality, we will focus on the case
of edit distance d = 1 to elaborate the proposed
advanced technique. For larger values of d, the
reasoning is similar. Note that the technique is
carefully designed in such a way that while
suppressing the fuzzy keyword set, it will not affect
the search correctness.
Wildcard-based Fuzzy Set Construction In the above
straightforward approach, all the variants of the
keywords have to be listed even if an operation is
performed at the same position. Based on the above
observation, we proposed to use a wildcard to denote
edit operations at the same position. The wildcard-
based fuzzy set of wi with edit distance d is
denoted as Swi,d={Swi,0, Swi,1, , Swi,d},
where Swi, denotes the set of words wi with
wildcards. Note each
wildcard represents an edit operation on wi. For
example, for the keyword CASTLE with the pre-set
edit distance 1, its wildcard-based fuzzy keyword set
can be constructed as
SCASTLE,1 = {CASTLE, *CASTLE, *ASTLE,
C*ASTLE, C*STLE, , CASTL*E, CASTL*,
CASTLE*}. The total number of variants on
CASTLE constructed in this way is only 13 + 1,
instead of 13 26 + 1 as in the above exhaustive
enumeration approach when the edit distance is set to
be 1. Generally, for a given keyword wi with length
_, the size of Swi,1 will be only 2_ + 1 + 1, as
compared to (2_ + 1) 26 + 1 obtained in the
straightforward approach. The larger the pre-set edit
distance, the more storage overhead can be reduced:
with the same setting of the example in the
straightforward approach, the proposed technique can
help reduce the storage of the index from 30GB to
approximately 40MB. In case the edit distance is set
to be 2 and 3, the size of Swi ,2 and Swi,3 will be
C_1+1+C_1 C_1+2C_2+2 and C_1 + C_3 + 2C_2
+ 2C_2 C_1. In other words, the number is only
O(_d) for the keyword with length _ and edit
distance.

B. The Efficient Fuzzy Keyword Search Scheme
Based on the storage-efficient fuzzy keyword sets,
we show how to construct an efficient and effective
fuzzy keyword search scheme. The scheme of the
fuzzy keyword search goes as follows:
1) To build an index for wi with edit distance d, the
data owner first constructs a fuzzy keyword set Swi,d
using the wildcard based technique. Then he
computes trapdoor set {Twi } for each wi Swi,d
with a secret key sk shared between data owner and
authorized users. The data owner
encrypts FIDwi as Enc(sk, FIDwi _wi). The index
table {({Twi }wiSwi,d , Enc(sk, FIDwi
_wi))}wiW and encrypted data files are outsourced
to the cloud server for storage;
2)To search with(w, k), the authorized user computes
the trapdoor set Tw w

Sw,k ,
where Sw,k
is also derived
{
}
from the wildcard-based fuzzy set construction. He
then sends {Tw }w Sw,k to the server;

3) Upon receiving the search request {Tw }w Sw,k
, the server compares them with the index table and
returns all the possible encrypted file identifiers
{Enc(sk, FIDwi _wi)} according to the fuzzy
keyword definition in section III-D. The user
decrypts the returned results and retrieves relevant
files of interest.
In this construction, the technique of constructing
search request for w is the same as the construction
of index for a keyword. As a result, the search
request is a trapdoor set based on Sw,k , instead of a
single trapdoor as in the straightforward approach. In
this way, the searching result correctness can be
ensured.

VI. SECURITY ANALYSIS

In this section, we analyze the correctness and
security of the proposed fuzzy keyword search
scheme. At first, we show the correctness of the
schemes in terms of two aspects, that is,
completeness and soundness.
Theorem 1: The wildcard-based scheme satisfies both
completeness and soundness. Specifically, upon
receiving the request of w, all of the keywords {wi}
will be returned if and only if ed(w, wi) k.
The proof of this Theorem can be reduced to the
following Lemma:
Lemma 1: The intersection of the fuzzy sets
Swi,d and Sw,k for wi and w is not empty if and
only if ed(w, wi) k. Proof: First, we show that
Swi,d Sw,k is not empty when ed(w, wi) k. To
prove this, it is enough to find an element in Swi,d
Sw,k . Let w = a1a2 as and wi = b1b2
bt, where all these ai and bj are single characters.
After ed(w, wi) edit operations, w can be changed to
wi according to the definition
of edit distance. Let w. = a.1a.2 a.m, where
a.i = aj or a.i = . if any operation is performed at this
position. Since the edit operation is inverted, from wi,
the same positions containing wildcard at w. will be
performed. Because ed(w, wi) k, w. is included in
both Swi,d and Sw,k , we get the result that Swi,d
Sw,k is not empty. Next, we prove that Swi,d Sw,k
is empty if ed(w, wi) > k. The proof is given by
reduction. Assume there exists an w. belonging to
Swi,d Sw,k . We will show that ed(w, wi) k,
IEEE: 0018-9340/06 September
2012//10.1109/TC.2012.215 which reaches a
contradiction. First, from the assumption that w.
Swi,d Sw,k , we can get the number of wildcard in
w., which is denoted by n., is not greater than k.
Next, we prove that ed(w, wi) n.. We will prove
the inequality with induction method. First, we prove
it holds when n. = 1. There are nine cases should be
considered: If w. is derived from the operation of
deletion from both wi and w, then, ed(wi, w) 1
because the other characters are the same except the
character at the same position. If the operation is
deletion from wi and substitution from w, we have
ed(wi, w) 1 because they will be the same after at
most one substitution from wi. The other cases can be
analyzed in a similar way and are omitted. Now,
assuming that it holds when n. = , we need to prove
it also holds when n. = + 1. If w.. = a.1a.2
a.n Swi,d Sw,k , where a.i
= aj or a.i = .. For a wildcard at position t, cancel the
underlying operations and revert it to the original
characters in wi and w at this position. Assume two
new elements wi. and w. are derived from them
respectively. Then perform one operation at position t
of wi. to make the character of wi at this position be
the same with w, which is denoted by wi. After this
operation, wi. will be changed to w., which has
only k wildcards. Therefore, we have
ed(w, w)

from the
assumption. We know that ed(w , w)
(i, w ) = 1,

based on which we know that ed(wi, w)
+ 1. Thus,
we can get ed(w, wi) n.. It renders
the contradiction
ed(w, wi) k because n. k. Therefore, Swi,d
Sw,k is empty if ed(w, wi) >
k.
Theorem 2: The fuzzy keyword search scheme is
secure regarding the search privacy.
Proof: In the wildcard-based scheme, the
computation of index and request of the same
keyword is identical. Therefore, we only need to
prove the index privacy by using reduction. Suppose
the searchable encryption scheme fails to achieve the
index privacy against the in distinguish ability under
the chosen keyword attack, which means there exists
an algorithm A who can get the underlying
information of keyword from the index. Then, we
build an algorithm A that utilizes A to determine
whether some function f () is a pseudo-random

function such that f () is equal to f (sk, ) or a
random function. A has an access to an oracle Of ()
that takes as input secret value x and returns f (x).
Upon receiving any request of the index computation,
A answers it with request to the oracle Of (). After
making these trapdoor queries, the adversary outputs
two challenge keywords w0. and w1. with the same
length and edit distance, which can be relaxed by
adding some redundant trapdoors. A picks one
random b {0, 1} and sends wb. to the challenger.
Then, A is given a challenge value y, which is either
computed from a pseudo-random function f (sk, )
or a random function. A sends y back to A, who
answers with b {0, 1}. Suppose A guesses b
correctly with non-negligible probability, which
indicates that the value is not randomly computed.
Then, A makes a decision that f () is a pseudo-
random function. As a result, based on the
assumption of the in distinguish ability of the pseudo-
random function from some real random function, A
at most guesses b correctly with approximate
probability 1/2. Thus, the search privacy is obtained.

VII. CONCLUSION

In this paper, for the first time we formalize and solve
the problem of supporting efficient yet privacy-
preserving fuzzy search for achieving effective
utilization of remotely stored encrypted data in Cloud
Computing. We design an advanced technique (i.e.,
wildcard-based technique) to construct the storage-
efficient fuzzy keyword sets by exploiting a
significant observation on the similarity metric of edit
distance. Based on the constructed fuzzy keyword
sets, we further propose an efficient fuzzy keyword
search scheme. Through rigorous security analysis,
we show that our proposed solution is secure and
privacy-preserving, while correctly realizing the goal
of fuzzy keyword search. As our ongoing work, we
will continue to research on security mechanisms that
support: 1) search semantics that takes into
consideration conjunction of keywords, sequence of
keywords, and even the complex natural language
semantics to produce highly relevant search results;
and 2) search ranking that sorts the searching results
according to the relevance criteria.

REFERENCES

[1] Google, Britney spears spelling correction,
Referenced online at http:
//www.google.com/jobs/britney.html, June 2009.
[2] M. Bellare, A. Boldyreva, and A. ONeill,
Deterministic and efficiently searchable encryption, in
Proceedings of Crypto 2007, volume 4622 of LNCS.
Springer-Verlag, 2007.
[3] D. Song, D. Wagner, and A. Perrig, Practical
techniques for searches on encrypted data, in Proc. of
IEEE Symposium on Security and Privacy00, 2000.
[4] E.-J. Goh, Secure indexes, Cryptology ePrint
Archive, Report 2003/216, 2003, http://eprint.iacr.org/.
[5] D. Boneh, G. D. Crescenzo, R. Ostrovsky, and G.
Persiano, Public key encryption with keyword search,
in Proc. of EUROCRYP04, 2004.
[6] B. Waters, D. Balfanz, G. Durfee, and D. Smetters,
Building an encrypted and searchable audit log, in
Proc. of 11th Annual Network and Distributed System,
2004.
[7] Y.-C. Chang and M. Mitzenmacher, Privacy
preserving keyword searches on remote encrypted data,
in Proc. of ACNS05, 2005.
[8] R. Curtmola, J. A. Garay, S. Kamara, and R. Ostrovsky,
Searchable symmetric encryption: improved definitions
and efficient constructions, in Proc. of ACM CCS06,
2006.
[9] D. Boneh and B. Waters, Conjunctive, subset, and
range queries on encrypted data, in Proc. of TCC07,
2007, pp. 535.554.
[10] F. Bao, R. Deng, X. Ding, and Y. Yang, Private
query on encrypted data in multi-user settings, in Proc. of
ISPEC08, 2008.
[11] C. Li, J. Lu, and Y. Lu, Efficient merging and
filtering algorithms for approximate string searches, in
Proc. of ICDE08, 2008.
[12] A. Behm, S. Ji, C. Li, , and J. Lu, Space-constrained
gram-based indexing for efficient approximate string
search, in Proc. of ICDE09.
[13] S. Ji, G. Li, C. Li, and J. Feng, Efficient interactive
fuzzy keyword search, in Proc. of WWW09, 2009.
[14] J. Feigenbaum, Y. Ishai, T. Malkin, K. Nissim, M.
Strauss, and R. N. Wright, Secure multiparty computation
of approximations, in Proc. of ICALP01.
[15] R. Ostrovsky, Software protection and simulations
on oblivious rams, Ph.D dissertation, Massachusetts
Institute of Technology, 1992.
[16] V. Levenshtein, Binary codes capable of correcting
spurious insertions and deletions of ones, Problems of
Information Transmission, vol. 1, no. 1, pp. 8.17, 1965.
IEEE: 0018-9340/06 September
2012//10.1109/TC.2012.215


Flame Diagnosis In Furnace Safeguard Supervisory System
Using Image Processing
S. Boopalan
1
, C. Barath Kanna
2
, K. Suganthan
4
, S. Shaul Hamid
5

1,2,3
PG Student, Department of EIE, B. S. Abdur Rahman University, Chennai, India
4
Associate Professor, Department of EIE, B. S. Abdur Rahman University, Chennai, India

ABSTRACT
In this paper, the combustion status is rated based on
flame image, luminosity, chromo information. The
thermal oxidation of utility boilers is directly related
to the economy and safety of a power plant. At
present, the equipments for detecting flame in utility
boilers are mainly based on infrared, ultraviolet or
visible light probes which sense the flame. The
estimation of combustion quality in power-station
boilers plays an important role for increasing boiler
efficiency, the perfect combustion can be controlled
by monitoring the intensity and shape of the flame
present in the boiler furnace. For the boiler to run
efficiently, combustion must be complete, this can be
analyzed from combustion of flame using image
processing technique. This new strategy will help in
finding combustion rating of the flame and efficiency
of boiler. The digital processing of image significantly
extends the way pertaining to flame characteristics
from flame image detail analysis. Suitable processing
methods are required to extract the representative
information from flame images, as they contain large
amounts of data whose physical interpretation is not
possible, in general, straightforward.

Keywords: FSSS, Image processing, Combustion
I. INTRODUCTION
The FSSS (furnace safe guard supervisory system) is a
systematic approach to start the combustion process in
furnace [1-4]. The main functions of FSSS are Ignition,
Purging, Flame detection. In this paper, flame detector is
being considered to estimate combustion. The geometric
shape of a burner flame is an important factor linked to
the burner configuration, fuel type, and air-to-fuel
ratio[9], and hence the overall performance of the
combustion process [5-8]. Shape descriptors of a flame,
such as area, circularity, eccentricity, and bending energy,
are often used to describe the geometric characteristics of
the flame [2].
The rapid development in the electronic industry raising
the degree of automation in image-processing technology
used in flame image processing applications [1][13][14].
Computer image-processing technology will be
combined with FSSS to distinguish the boiler burning
state according to the characteristic of flame image [9-
12].
II. FLAME IMAGE
The flame image acquired from the furnace through
camera is the representative image, selected on the basis
of the mean image[4]. The contrast of flame image was
enhanced by three-section grey linear transformation,
isolated spots elimination and filling in blanks were
operated after binariazation [2]. The further search will
focus on the burning state criterion [13-14].

A. Image Acquisition:
A series of camera clips of gaseous flames were taken
using a CCD camera and stored in a computer with
associated image acquisition software. [6] Illustrates the
experimental set-up. The camera was placed at a fixed
location and transferred images to the host computer at a
frame. Fuel and air flows to the burner were measured
during the experiments. For each fuel air flow setting, a
flame camera clip, which contains over 100 successive
images, was recorded for later analysis. Here only four
images are analysed, on different loads. Image
acquisition can be as simple as loading multi-
dimensional data from disk file.


Image display can be as simple as placing an RGB image
in a graph window or as complicated as creating an
overlay of multiple images combined with contour lines
and legend. Being able to display images in false colour
or using a non-linear level mapping is sometimes helpful
when trying to visually analyse images. The different
load combustion image in fig.1

Fig. 1 Acquired Furnace Image
B. Colour conversion:
The acquired image is converted into standard form in
terms of color space and range. Flame image is converted
from the true colour image RGB to the gray scale
intensity image. The colour conversion takes place in two
stages[2].
1. RGB images to gray-scale by eliminating the
hue and saturation information while retaining
the luminance.
2. RGB values to gray-scale values by forming a
weighted sum of the R, G, and B components
0.2989 * R + 0.5870 * G + 0.1140 * B

Fig. 2 Gray Scale Image
C. Contracts Enhancement:
Gray value in image is significant, however, because of
the deficiency in illumination, vidicon, exposure,
dynamic range, the quality of flame images is always
very poor, lacking adequate contrast and blur character
edges existing on these images. Therefore enhancing
contrast to a flame image is needed. Suppose f(x,y) the
gray value of the input image at pixel (x,y), and the the
gray value g(x,y) can be obtained by mapping function
T(.), namely g(x,y)=T [f (x,y) ]. There are several general
enhancing contrast methods, such as grey linear
transformation, subsection linear transformation, and
histogram equalisation. We hope that it is easy to
distinguish the fire part from background after grey
transformation. The emphasis of image enhancement is
different if we use different enhance methods, we can get
brighter or dimmer picture by using grey linear
transformation, and it not suited for enhancing contrast of
flame image. We can make an obvious expression about
the sections that we care about and the other part obscure
by using subsection linear transformation. Three-section
linear transformation is the most common method not
conducive to image segmentation, to avoid this problem,
we select the most similar standby image to the mean
image as the representative image, which indicates the
combustion state[3] for the next processing.

Fig. 3 Contracts Enhancement
The representative image was selected on the basis of the
mean image, 33 median filtering was used to eliminate
noise from flame image, the contrast of flame image was
enhanced by grey linear transformation, isolated spots
elimination and filling in blanks were operated after
binariazation. The result shows that the flame
segmentation from background was effective. The further
research will focus on the burning state criterion.


III. METHODOLOGY
After pre-processing image are segmented in based
on image colour contracts. Image are splitted into
three region [7] unburn regions, partial combustion
zone, complete combustion zone and each region's
area are measured.
A. Image Segmentation
B. The practical image processing tools are
suitable in limited size image only accepted in
image tool process. The original image is resized to
required size of image without loss of picture
quality. After the image are segmented using image
segment tool.
A contour plot displays isolines of matrix Z. Label the
contour lines using clabel. Contour (Z) draws a contour
plot of matrix Z, where Z is interpreted as heights with
respect to the x-y plane. Z must be at least a 2-by-2
matrix that contains at least two different values. The
number of contour lines and the values of the contour
lines are chosen automatically based on the minimum
and maximum values of Z. The ranges of the x- and y-
axis are [1:n] and [1:m], where [m,n] = size(Z).
Contour (Z,n) draws a contour plot of matrix Z with n
contour levels.contour Z,v) draws a contour plot of
matrix Z with contour lines at the data values specified in
the monotonically increasing vector v. The number of
contour levels is equal to length(v). To draw a single
contour of level i, use contour(Z,[i i]). Specifying the
vector v sets the LevelListMode to manual to allow user
control over contour levels. See contour group properties
for more information.

Contour(X,Y,Z), contour (X,Y,Z,n), and contour
(X,Y,Z,v) draw contour plots of Z using X and Y to
determine the x- and y-axis limits. When X and Y are
matrices, they must be the same size as Z and must be
monotonically increasing. Contour (...,LineSpec) draws
the contours using the line type and color specified by
LineSpec. contour ignores marker symbols.
Contour (axes_handle,) plots into axes gerkaxes_handle
instead of gca. [C,h] = contour(...) returns a contour
matrix, C, that contains the x, y coordinates and contour
levels for contour lines derived by the low-level contourc
function, and a handle, h, to a contour group object. The
clabel function uses contour matrix C to label the contour
lines. ContourMatrix is also a read-only Contour group
property that you can obtain from the returned handle.
Use contour group object properties to control the
contour plot appearance. If X or Y is irregularly spaced,
contour calculates contours using a regularly spaced
contour grid, and then transforms the data to X or Y.

Fig. 4 Flame image segmentation
B. Determination of flame segmentation area

Identify Objects in the Image. The function bwconncomp
finds all the connected components (objects) in the
binary image. The accuracy of the results depends on the
size of the objects, the connectivity parameter (4, 8, or
arbitrary), and whether or not any objects are touching
(in which case they could be labeled as one object).
Some of the rice grains inbetween are touching. One way
to visualize connected components is to create a label
matrix, and then display it as a pseudo-colour indexed
image. Use label matrix to create a label matrix from the
output of bwconncomp. Note that label matrix stores the
label matrix in the smallest numeric class necessary for
the number of objects. The label matrix can be stored as
unit 8.

Table 1: Computed Area wise combustion region

Combustion Region one
area
Region two
area
Region
three area


40% 15990 28985 31982
60% 21000 23199 26968
80% 26000 24992 22960
100% 32000 25994 15944

From the table 1 it can be inferred that when the
combustion is incomplete say about 40% then the
corresponding combustion area will be small. So to
achieve complete combustion air/fuel ratio is varied to
maintain constant load. When complete combustion is
achieved the combustion area will be large
IV. CONCLUSION
The combustion quality is rated using flame diagnosis
technique in Furnace safeguard supervisory system. The
flame image was segment and its area was determined to
find out the complete combustion zone area.
Combustion status is estimated and the necessary
corrective control action is taken to achieve complete
combustion by varying air and fuel. Further more, flue
gas analysis can be done using image processing
technique.
REFERENCES
Junghui Chen , Lester Lik Teck Chan , Yi-Cheng Cheng .
Gaussian process regression based optimal design of
combustion systems using flame images Journal of
Energy and Buildings, Journals of Energy and Buildings,
pp.no.153160, 2013.
Cai Yejing, Huang Xiaofeng, Long Xiaowei, Flame Image pre-
processing research for coal-fired utility boiler
International Conference on Intelligent System Design
and Engineering Applications,pp-no.771-774.2013.
Junghui Chen , Yu-Hsiang Chang , Yi-Cheng Cheng , Chen-Kai
Hsu .

Design of image-based control loops for industrial
combustion processes Journals of Energy and Buildings
, pp.no. 13-21 , 2012.
Javier Ballester , Tatiana Garc,Armingol

Diagnostic
techniques for the monitoring and control of practical
flames Journal of Progress in Energy and Combustion
Science ,pp. no. 375-415 , 2010.
Tian Qiu, Yong Yan, Gang Lu Flame Stability Monitoring
Through Statistical Analysis of the Medial Axis Journal
of School of Engineering ,pp.no.101-114,2011.
Huahai Qi, Fuhuan Chen, Yawei Gao, Based on the CCD of
the boiler flame detection International Conference on
Digital Manufacturing & Automation, pp-no.261-263
,2012 .
Rongbao Chen , Wuting Fan, Jingci Bian, Fanhui Meng,
Research on Stability Criterion of Furnace Flame
Combustion Based on Image Processing International
Conference on Control Engineering and Communication
Technology,pp-no.569-572 ,2012.
Zhang Hongliang1, Chen Xiangtao2, Zou Zhong1, Li Jie1
Content-Based Rotary Kiln Flame Image Retrieval
Congress on Image and Signal Processing, pp. 490-494,
2008.
Zengshou Dong, Mingjun Liu, Fengchun Zhang, NOx
Estimation based on Flame Image of high Temperature
Air Combustion Eighth International Conference on
Intelligent Systems Design and Applications, pp. 538-
541, 2008.
R. Hernndez, J. Ballester , Flame imaging as a diagnostic tool
for industrial Combustion Journal of Combustion and
Flame, pp.no.509-528 , 2008.
Chenggang Zhen, Wei Liao, Researches on Image Processing
Based on Neural Network Technique for Furnace Frame
International Conference on Computer Science and
Software Engineering, pp. 852-854, 2008.
N.M. Razali, M.H. Boosroh, H. Hasini, N.H. Shuaib, Impact
of tangential burner firing angle on combustion
characteristics of large scale coal-fired boiler, 3rd
International Conference on Energy and Environment,
pp.177-183, Dec 2009.
Zhengwei Zhu, Yuying Guo, Judging Smelting End-point of
Fuming Furnace Using Tertiary Tuyere Flame, Fifth
International Conference on Natural Computation, pp.62-
66, 2009.
Zi-xue LUO, Dun-dun WANG, Duan-LIAN and Huai-chun
ZHOU, Measurement of Dense-Phase Bed Height in
CFB Boiler Based on Flame Image Processing
Technique, International Conference on Measuring
Technology and Mechatronics Automation, pp. 237-240,
2009.

IJRDE MEPED 2014 Special Issue

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

IJRDE MEPED 2014 Special Issue

Uploaded by

Copyright:

Available Formats

International Journal for Research and Development in Engineering (IJRDE)

www.ijrde.com ISSN: 2279-0500 Special Issue: pp- 001-005

the 21 multiplexer. Frequency of C and

are randomly selected by the

shows the truth table of the multiplexer

= 0.3108 i.e THD = 31.08%

. The entropy is computed

(r) = f(x, y)(r xcos

for different orientations to derive the

N stages, where is the

. A vector can be uniquely defined in the complex

controller, in many areas of

. i.e., what would the

, where a and t are respectively the lower- and

and phase margin is specified by

Fractional order controller described by (3.4) can

in the following form:

Fractional order controller described by (3.4) can

in the following form:

in the following form:

, Table 1 show the

You might also like