Exercise #9:

Arithmetic Circuits: Four-bit Adder/Subtractor

Revised:11_03_09

I am submitting my own work, and I am aware of the penalties for Print Name: Upadesh Acharya
cheating that may be assessed if I submit work that is not my own.

_Upadesh Acharya_____________________11/11/09_____ ID#: ua16 Section: 06

_____________
Sign Name Date
For lab assistant use: I observed the student designing, implementing, and demonstrating the circuits and/or other work
for this lab, or the student demonstrated adequate knowledge of their submitted work (otherwise, circle “no demo” and
deduct points as appropriate).
This lab was (circle one) circle if
Overall score (do not deduct late points):
ON TIME LATE (-20%) NO DEMO

Lab assistant signature Date Time

Lab Datasheet

Lab Exercise 1 – A One-bit Half Adder

Write the minimum SOP equations and draw the two-level and-or circuit.
Sum = X’Y + XY’ = X⊕Y
CarryOut = XY

Lab Exercise 1b – A One-bit Full Adder

Write the minimum SOP equations and draw the two-level and-or circuit.

SUM = C’X’Y + C’XY’ + CX’Y’ + CXY = X ⊕ Y ⊕ C

CarryOut = CX + CY + XY
Lab Exercise 2 – A One-bit Full Adder in Verilog
Create screenshots of your code for the one-bit adder. You should have a module for the adder
as well as a top-level module associating the inputs/outputs of the adder to the pins.
TA Inspection of circuit and code ______________________________________________

Lab Exercise 3 – Four-Bit Full Adder Verilog Circuit using instantiations of the one-bit
module
Create screenshots of your project (each source). You do not need to show the module for the
clk7segment module as this was done in a previous lab. You should show the top-level module
that calls each module.

Lab Exercise 4 – A One-bit Half Subtractor

Write the minimum SOP equations and draw the two-level and-or circuit.
Difference = X’Y+XY’
Borrower = X’Y

Lab Exercise 4b – A One-bit Full Subtractor

Write the minimum SOP equations and draw the two-level and-or circuit.
Difference = B’X’Y + B’XY’ + BX’Y’ + BXY = X ⊕ Y ⊕ B
BorrowOut = BX + BY + XY

Lab Exercise 4c – Questions concerning A One-bit Full Subtractor

What is the relationship between the full adder circuit and the full subtractor circuit – how are
they the same? how are they different?
The full adder circuit is same as the full subtractor circuit. They have the same SOP equation

Lab Exercise 5 – A One-bit Full Adder/Subtractor in Verilog

Create screenshots of your code for the one-bit adder/subtractor. You should have a module for
the adder/subtractor as well as a top-level module associating the inputs/outputs of the
adder/subtractor to the pins.
Lab Exercise 5b – Four-Bit Full Adder/Subtractor Verilog Circuit using instantiations of
the one-bit module
Create screenshots of your project (each source). You do not need to show the module for the
clk7segment module as this was done in a previous lab. You should show the top-level module
that calls each module.