SUBJECT: MICROPROCESSOR AND MICROCONTROLLER CODE: EC 2304

UNIT I
INTRODUCTION TO 8 BIT AND 16 BIT MICROPROCESSORS H/W ARCHITECTURE
COMPUTER AND ITS ORGANIZATION
A Computer is a programmable machine. It responds to a specific set of instructions in a well-defined
manner. It can execute a prerecorded list of instructions (a program ).Modern computers are electronic
and digital. The actual machinery wires transistors and circuits is called hardware. The instructions
and data are called software.
All general-purpose computers re!uire the following hardware components"
M!"#$" #nables a computer to store at least temporarily data and programs.
M%&& &'"#%( )*+," Allows a computer to permanently retain large amounts of data. Common mass
storage de$ices include dis% dri$es and tape dri$es.
I-./' )*+," &sually a %eyboard and mouse are the input de$ice through which data and instructions
enter a computer.
O/'./' )*+," A display screen printer or other de$ice that lets you see what the computer has
accomplished.
C-'#%0 .#",&&+-( /-+' 1CPU2: The heart of the computer this is the component that actually
executes instructions.
In addition to these components many others ma%e it possible for the basic components to wor%
together efficiently.
'or example e$ery computer re!uires a bus that transmits data from one part of
the computer to another.
Computers can be generally classified by si(e and power as follows though there is considerable
o$erlap"
P#&"-%0 ,"!./'#" A small single-user computer based on a microprocessor. In addition to the
microprocessor a personal computer has a %eyboard for entering data a monitor for displaying
information and a storage de$ice for sa$ing data.
W"#3+-( &'%'+"-" A powerful single-user computer. A wor%station is li%e a personal computer but it
has a more powerful microprocessor and a higher!uality monitor.
M+-+,"!./'#" A multi-user computer capable of supporting from )* to hundreds of users
simultaneously.
M%+-4#%!" A powerful multi-user computer capable of supporting many hundreds or thousands of
users simultaneously.
S/.#,"!./'#: An extremely fast computer that can perform hundreds of millions of instructions
per second.
M+-+,"!./'#"
A midsi(ed computer. In si(e and power minicomputers lie between wor%stations and mainframes.
A minicomputer a term no longer much used is a computer of a si(e intermediate between a
microcomputer and a mainframe.
Typically minicomputers ha$e been stand-alone computers (computer systems with attached terminals
and other de$ices) sold to small and mid-si(e businesses for general business applications and to large
enterprises for department-le$el operations.
W"#3&'%'+"-:
A type of computer used for engineering applications (CA+,CAM) des%top publishing software
de$elopment and other types of applications that re!uire a moderate amount of computing power and
relati$ely high !uality graphics capabilities.
-or%stations generally come with a large high- resolution graphics screen at least ./ M0 (mega
bytes) of 1AM built-in networ% support and a graphical user interface.
M+,#","!./'#: The term microcomputer is generally synonymous with personal computer or a
computer that depends on a microprocessor.
Microcomputers are designed to be used by indi$iduals whether in the form of 2Cs wor%stations or
noteboo% computers.
A microcomputer contains a C2& on a microchip (the microprocessor) a memory
system (typically 13M and 1AM) a bus system and I,3 ports typically housed in a motherboard.
INTRODUCTION TO MICROPROCESSOR
M+,#".#",&&"#" A silicon chip that contains a C2&. In the world of personal
Computers the terms microprocessor and C2& are used interchangeably. A !+,#".#",&&"#
(sometimes abbre$iated 5P) is a digital electronic component with miniaturi(ed transistors on a single
semiconductor integrated circuit (IC).3ne or more microprocessors typically ser$es as a central
processing unit (C2&) in a computer system or handheld de$ice. Microprocessors made possible the
ad$ent of the microcomputer. At the heart of all personal computers and most wor%ing stations sits a
microprocessor.
Microprocessors also control the logic of almost all digital de$ices from cloc% radios to fuel-in4ection
systems for automobiles.
Three basic characteristics differentiate microprocessors"
I-&'#/,'+"- &'" The set of instructions that the microprocessor can execute.
B%-)6+)'7" The number of bits processed in a single instruction.
C0",3 &.)" 5i$en in megahert( (M6() the cloc% speed determines how many instructions per
second the processor can execute.
M+,#","-'#"00#:
A highly integrated chip that contains all the components comprising a controller. Typically this
includes a C2& 1AM some form of 13M I,3 ports and timers. &nli%e a general-purpose computer
which also includes all of these components a microcontroller is designed for a $ery specific tas% - to
control a particular system.
A microcontroller differs from a microprocessor which is a general-purpose chip that is used to create
a multi-function computer or de$ice and re!uires multiple chips to handle $arious tas%s. A
microcontroller is meant to be more self-contained and independent and functions as a tiny dedicated
computer.
The great ad$antage of microcontrollers as opposed to using larger microprocessors is that the parts-
count and design costs of the item being controlled can be %ept to a minimum. They are typically
designed using CM37 (complementary metal oxide semiconductor) technology an efficient
fabrication techni!ue that uses less power and is more immune to power spi%es than other techni!ues.
Microcontrollers are sometimes called embedded microcontrollers, which 4ust means that they are part
of an embedded system that is one part of a larger de$ice or system
E!8))) &$&'!"
An #mbedded 7ystem is a speciali(ed computer system that is part of a larger system or machine.
Typically an embedded system is housed on a single microprocessor board with the programs stored
in 13M. 8irtually all appliances that ha$e a digital Interface- watches microwa$es 8C1s cars
-utili(e embedded systems. 7ome embedded systems include an operating system but many are so
speciali(ed that the entire logic can be implemented as a single program.
A))#&& B/&9 D%'% B/& %-) C"-'#"0 B/&
The preferred method for data,information transfer between system components is by a common data
bus. -here point-to-point data transfer is re!uired the digital format is the preferred method
C"-'#"0 B/&
The control bus is used by the C2& to direct and monitor the actions of the other functional areas of
the computer. It is used to transmit a $ariety of indi$idual signals (read write interrupt
ac%nowledge and so forth) necessary to control and coordinate the operations of the
computer. The indi$idual signals transmitted o$er the control bus and their functions are co$ered in
the appropriate functional area description.
A))#&& B/&
The address bus consists of all the signals necessary to define any of the possible memory address
locations within the computer or for modular memories any of the possible memory address locations
within a module. An address is defined as a label symbol or other set of characters used to designate
a location or register where information is stored. 0efore data or instructions can be written into or
read from memory by the C2& or I,3 sections an address must be transmitted to memory o$er the
address bus.
D%'% B/&
The bidirectional data bus sometimes called the memory bus handles the transfer of all )%'% and
+-&'#/,'+"-& 8'6- functional areas of the computer. The bi directional data bus can only transmit
in one direction at a time. The data bus is used to transfer instructions from memory to the C2& for
execution. It carries data (operands) to and from the C2& and memory as re!uired by instruction
translation. The data bus is also used to transfer data between memory and the I,3 section during
input,output operations
T#+&'%' 8/&
T7#:&'%' '#+:&'%' or 3:&'%' logic allows an output port to assume a high impedance state in
addition to the * and ) logic le$els effecti$ely remo$ing the output from the circuit. This allows
multiple circuits to share the same output line or lines (such as a bus).
Three-state outputs are implemented in many registers bus dri$ers and flip-flops in
the 9/** and /*** series as well as in other types but also internally in many integrated circuits. 3ther
typical uses are internal and external buses in microprocessors memories and peripherals. Many
de$ices are controlled by an acti$e-low input called 3# (3utput #nable) which dictates whether the
outputs should be held in a high-impedance state or dri$e their respecti$e loads (to either *- or )-
le$el).
C0",3 (-#%'+"-
A ,0",3 (-#%'"# is a circuit that produces a timing signal (%nown as a cloc% signal and beha$es as
such) for use in synchroni(ing a circuit:s operation. The signal can range from a simple
symmetrical s!uare wa$e to more complex arrangements. The basic parts that all cloc% generators
share are a resonant circuit and an amplifier.
The resonant circuit is usually a !uart( pie(o-electric oscillator although simpler tan% circuits and
e$en 1C circuits may be used.
The amplifier circuit usually in$erts the signal from the oscillator and feeds a portion bac% into the
oscillator to maintain oscillation.
The generator may ha$e additional sections to modify the basic signal. The ;*;; for example used a
<,= duty cycle cloc% which re!uired the cloc% generator to incorporate logic to con$ert the >*,>* duty
cycle which is typical of raw oscillators.
3ther such optional sections include fre!uency di$ider or cloc% multiplier sections. 2rogrammable
cloc% generators allow the number used in the di$ider or multiplier to be changed allowing any of a
wide $ariety of output fre!uencies to be selected without modifying the hardware.
The cloc% generator in a motherboard is often changed by computer enthusiasts to control the speed of
their C2& '70 52& and 1AM. Typically the programmable cloc% generator is set by the 0I37 at
boot time to the $alue selected by the enthusiast? although some systems ha$e dynamic fre!uency
scalingthat fre!uently re-program the cloc% generator.
C"--,'+-( M+,#".#",&&"# '" I/O )*+,&
M!"#$:!%..) I/O (MMIO) and ."#' I/O (also called +&"0%') I/O or ."#':!%..)
I/O abbre$iated PMIO) are two complementary methods of performing input,output between
the C2& andperipheral de$ices in a computer. An alternati$e approach not discussed in this article is
using dedicated I,3 processors @ commonly %nown as channels on mainframe computers @ that
execute their own instructions.
Memory-mapped I,3 (not to be confused with memory-mapped file I,3) uses the same address bus to
address both memory and I,3 de$ices - the memory and registers of the I,3 de$ices are mapped to
(associated with) address $alues. 7o when an address is used by the C2& it may refer to a portion of
physical 1AM or it can instead refer to memory of the I,3 de$ice. Thus the C2& instructions used to
access the memory are also used for accessing de$ices. #ach I,3 de$ice monitors the C2&:s address
bus and responds to any of the C2&:s access of address space assigned to that de$ice connecting
the data bus to a desirable de$ice:s hardware register. To accommodate the I,3 de$ices areas of the
addresses used by the C2& must be reser$ed for I,3 and not be a$ailable for normal physical memory.
The reser$ation might be temporary @ the Commodore ./ could ban% switch between its I,3 de$ices
and regular memory @ or permanent.
2ort-mapped I,3 uses a special class of C2& instructions specifically for performing I,3. This is
generally found on Intel microprocessors specifically the IA and 3&T instructions which can read and
write one to four bytes (outb outw outl) to an I,3 de$ice. I,3 de$ices ha$e a separate address space
from general memory either accomplished by an extra BI,3B pin on the C2&:s physical interface or an
entire bus dedicated to I,3. 0ecause the address space for I,3 is isolated from that for main memory
this is sometimes referred to as isolated I,3.
A de$ice:s direct memory access (+MA) is not affected by those C2&-to-de$ice communication
methods especially it is not affected by memory mapping. This is because by definition +MA is a
memory-to-de$ice communication method that bypasses the C2&.
6ardware interrupt is yet another communication method between C2& and peripheral de$ices.
6owe$er it is always treated separately for a number of reasons. It is de$ice-initiated as opposed to
the methods mentioned abo$e which are C2&-initiated. It is also unidirectional as information flows
only from de$ice to C2&. Castly each interrupt line carries only one bit of information with a fixed
meaning namely Ban e$ent that re!uires attention has occurred in a de$ice on this interrupt lineB.
DATA TRANS;ER SCHEMES
S$-,7#"-"/& D%'% T#%-&4#:
7ynchronous means Dat the same timeE. In this format of data transfer transmitter and recei$er de$ice
are synchroni(ed with the same cloc% pulse.
This type of data transfer format is used in between the de$ices that match in speed. This method is
in$ariably used in between memory and microprocessor as they are compatible.
A&$-,7#"-"/& D%'% T#%-&4#: :
Asynchronous means Dat a regular inter$alE. In this method data transfer is not based on
predetermined timing pattern in this techni!ue the status of the I3 de$ice is chec%ed by the
microprocessor before the data is transferred. This method is in$ariably used in between
microprocessor and I3 de$ices
MODES O; DATA TRANS;ER
T6# MIC13213C#7731 recei$es or transmits binary data in either of two mode"-
PARALLEL MODE"-In a parallel mode the entire word is transferred at one time .the de$ice
commonly used for data transfer are %eyboards se$en segment C#+s data con$erters and memory.
SERIAL MODE::In the serial mode data are transferred one bit at a time o$er a single line between
the microprocessors and a peripheral. It is commonly used with peripherals such as C1T terminals
printers cassette tapes and modems for telephone<
DMA:
+irect Memory Access (+MA) is a method of allowing data to be mo$ed from one location to another
in a computer without inter$ention from the central processor (C2&).
The way that the +MA function is implemented $aries between computer architectures so this
discussion will limit itself to the implementation and wor%ings of the +MA subsystem on the I0M
2ersonal Computer (2C) the I0M 2C,AT and all of its successors and clones.
The 2C +MA subsystem is based on the IntelF ;<=9 +MA controller. The ;<=9 contains four +MA
channels that can be programmed independently and any one of the channels may be acti$e at any
moment. These channels are numbered * ) < and =. 7tarting with the 2C,AT I0M added a second
;<=9 chip and numbered those channels / > . and 9.
The original +MA controller (* ) < and =) mo$es one byte in each transfer. The second +MA
controller (/ > . and 9) mo$es ).-bits from two ad4acent memory locations in each transfer with the
first byte always coming from an e$en-numbered address. The two controllers are identical
components and the difference in transfer si(e is caused by the way the second controller is wired into
the system.
The ;<=9 has two electrical signals for each channel named +1G and -+ACH. There are additional
signals with the names 61G (6old 1e!uest) 6C+A (6old Ac%nowledge) -#32 (#nd of 2rocess)
and the bus control signals -M#M1 (Memory 1ead) -M#M- (Memory -rite) -I31 (I,3 1ead) and
-I3- (I,3 -rite).
The ;<=9 +MA is %nown as a Dfly-byE +MA controller. This means that the data being mo$ed from
one location to another does not pass through the +MA chip and is not stored in the +MA chip.
7ubse!uently the +MA can only transfer data between an I,3 port and a memory address but not
between two I,3 ports or two memory locations.
8086 MICROPROCESSOR
IIt is a ).-bit Jp.
I;*;. has a <* bit address bus can access up to <<* memory locations () M0).
IIt can support up to ./H I,3 ports.
IIt pro$ides )/ ). -bit registers.
IIt has multiplexed address and data bus A+*- A+)> and A). K A)L.
IIt re!uires single phase cloc% with ==M duty cycle to pro$ide internal timing.
I;*;. is designed to operate in two modes Minimum and Maximum.
IIt can prefetches upto . instruction bytes from memory and !ueues them in order to
speed up instruction execution.
IIt re!uires N>8 power supply.
IA /* pin dual in line pac%age
M+-+!/! %-) M%=+!/! M")&"
IThe minimum mode is selected by applying logic ) to the MA , MO input pin. This is a
single microprocessor configuration.
IThe maximum mode is selected by applying logic * to the MA , MO input pin. This is a
multi micro processors configuration.
I-'#-%0 A#,7+','/# "4 8086
I;*;. has two bloc%s 0I& and #&.
IThe 0I& performs all bus operations such as instruction fetching reading and writing operands for
memory and calculating the addresses of the memory operands. The instruction bytes are transferred to
the instruction !ueue.
I#& executes instructions from the instruction system byte !ueue.
I0oth units operate asynchronously to gi$e the ;*;. an o$erlapping instruction fetch and execution
mechanism which is called as 2ipelining. This results in efficient use of the system bus and system
performance.
I0I& contains Instruction !ueue 7egment registers Instruction pointer Address adder.
I#& contains Control circuitry Instruction decoder AC& 2ointer and Index register 'lag register.
BUS INTER;ACR UNIT:
IIt pro$ides a full ). bit bidirectional data bus and <* bit address bus.
IThe bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions"
IInstruction fetch Instruction !ueuing 3perand fetch and storage Address relocation and 0us control.
IThe 0I& uses a mechanism %nown as an instruction stream !ueue to implement a pipeline
architecture.
IThis !ueue permits prefetch of up to six bytes of instruction code. -hen e$er the !ueue of the 0I& is
not full it has room for at least two more bytes and at the same time the #& is not re!uesting it to read
or write operands from memory the 0I& is free to loo% ahead in the program by prefetching the next
se!uential instruction.
IThese prefetching instructions are held in its 'I'3 !ueue. -ith its ). bit data bus the 0I& fetches
two instruction bytes in a single memory cycle.
IAfter a byte is loaded at the input end of the !ueue it automatically shifts up through the 'I'3 to the
empty location nearest the output.
IThe #& accesses the !ueue from the output end. It reads one instruction byte after the other from the
output of the !ueue. If the !ueue is full and the #& is not re!uesting access to operand in memory.
IThese inter$als of no bus acti$ity which may occur between bus cycles are %nown as Idle state.
IIf the 0I& is already in the process of fetching an instruction when the #& re!uest it to read or write
operands from memory or I,3 the 0I& first completes the instruction fetch bus cycle before initiating
the operand read , write cycle.
IThe 0I& also contains a dedicated adder which is used to generate the <*bit physical address that is
output on the address bus. This address is formed by adding an appended ). bit segment address and a
). bit offset address.
I'or example: The physical address of the next instruction to be fetched is formed by combining the
current contents of the code segment C7 register and the current contents of the instruction pointer I2
register.
IThe 0I& is also responsible for generating bus control signals such as those for memory read or write
and I,3 read or write.
E>ECUTION UNIT
The #xecution unit is responsible for decoding and executing all instructions.
IThe #& extracts instructions from the top of the !ueue in the 0I& decodes them generates operands
if necessary passes them to the 0I& and re!uests it to perform the read or write bys cycles to memory
or I,3 and perform the operation specified by the instruction on the operands.
I+uring the execution of the instruction the #& tests the status and control flags and updates them
based on the results of executing the instruction.
IIf the !ueue is empty the #& waits for the next instruction byte to be fetched and shifted to top of the
!ueue.
I-hen the #& executes a branch or 4ump instruction it transfers control to a location corresponding to
another set of se!uential instructions.
I-hene$er this happens the 0I& automatically resets the !ueue and then begins to fetch instructions
from this new location to refill the !ueue.
S+(-%0 D&,#+.'+"- "4 8086IThe Microprocessor ;*;. is a ).-bit C2& a$ailable in different cloc%
rates and pac%aged in a /* pin C#1+I2 or plastic pac%age.
IThe ;*;. operates in single processor or multiprocessor configuration to achie$e high performance.
The pins ser$e a particular function in minimum mode (single processor mode) and other function in
maximum mode configuration (multiprocessor mode ).
IThe ;*;. signals can be categorised in three groups. The first are the signal ha$ing common
functions in minimum as well as maximum mode.
IThe second are the signals which ha$e special functions for minimum mode and third are the signals
ha$ing special functions for maximum mode.
T7 4"00"6+-( &+(-%0 )&,#+.'+"-& %# ,"!!"- 4"# 8"'7 !")&<
IAD1?:AD0" These are the time multiplexed memory I,3 address and data lines.
I Address remains on the lines during T) state while the data is a$ailable on the data bus during T<
T= Tw and T/.
IThese lines are acti$e high and float to a tristate during interrupt ac%nowledge and local bus hold
ac%nowledge cycles.
IA1@/S69A18/S?9A1A/S49A16/S3: These are the time multiplexed address and status lines.
I+uring T) these are the most significant address lines for memory operations.
I+uring I,3 operations these lines are low. +uring memory or I,3 operations status information is
a$ailable on those lines for T<T=Tw and T/.
IThe status of the interrupt enable flag bit is updated at the beginning of each cloc% cycle.
IThe 7/ and 7= combinedly indicate which segment register is presently being used for memory
accesses as in below fig.
IThese lines float to tri-state off during the local bus hold ac%nowledge. The status line 7. is always
low.
IThe address bit are separated from the status bit using latches controlled by the AC# signal.
BHE /SA: The bus high enable is used to indicate the transfer of data o$er the higher order ( +)>-+; )
data bus as shown in table. It goes low for the data transfer o$er +)>- +; and is used to deri$e chip
selects of odd address memory ban% or peripherals. 06# is low during T) for read write and interrupt
ac%nowledge cycles whene$er a byte is to be transferred on higher byte of data bus. The status
information is a$ailable during T< T= and T/. The signal is acti$e low and tristated during hold. It is
low during T) for the first pulse of the interrupt ac%nowledges cycle.
IRDR%): This signal on low indicates the peripheral that the processor is performing memory or I,3
read operation. 1+ is acti$e low and shows the state for T< T= Tw of
any read cycle. The signal remains tristated during the hold ac%nowledge.

IREADB" This is the ac%nowledgement from the slow de$ice or memory that they ha$e completed the
data transfer. The signal made a$ailable by the de$ices is synchroni(ed by the ;<;/A cloc% generator
to pro$ide ready input to the ;*;.. the signal is acti$e high.
IINTR:I-'##/.' RC/&'" This is a triggered input. This is sampled during the last cloc% cycles of
each instruction to determine the a$ailability of the re!uest. If any interrupt re!uest is pending the
processor enters the interrupt ac%nowledge cycle.
IThis can be internally mas%ed by resulting the interrupt enable flag. This signal is acti$e high and
internally synchroni(ed.
ITESTThis input is examined by a P-AITQ instruction. If the T#7T pin goes low execution will
continue else the processor remains in an idle state. The input is synchroni(ed internally during each
cloc% cycle on leading edge of cloc%.
ICLD- Cloc% Input" The cloc% input pro$ides the basic timing for processor operation and bus control
acti$ity. Its an asymmetric s!uare wa$e with ==M duty cycle.
IMN/M>" The logic le$el at this pin decides whether the processor is to operate in either
minimum or maximum mode.
ET7 4"00"6+-( .+- 4/-,'+"-& %# 4"# '7 !+-+!/! !") ".#%'+"- "4 8086<
IM/IO M!"#$/IO" This is a status line logically e!ui$alent to 7< in maximum mode.
-hen it is low it indicates the C2& is ha$ing an I,3 operation and when it is high it
indicates that the C2& is ha$ing a memory operation. This line becomes acti$e high in
the pre$ious T/ and remains acti$e till final T/ of the current cycle. It is tristated during
local bus Dhold ac%nowledge D.
I INTA I-'##/.' A,3-"60)(" This signal is used as a read strobe for interrupt
ac%nowledge cycles. i.e. when it goes low the processor has accepted the interrupt.
IALE A))#&& L%',7 E-%80" This output signal indicates the a$ailability of the $alid
address on the address,data lines and is connected to latch enable input of latches. This
signal is acti$e high and is ne$er tristated.
IDT/ R D%'% T#%-&!+'/R,+*" This output is used to decide the direction of data
flow through the transrecei$ers (bidirectional buffers). -hen the processor sends out
data this signal is high and when the processor is recei$ing data this signal is low.
IDEN D%'% E-%80" This signal indicates the a$ailability of $alid data o$er the
address,data lines. It is used to enable the transrecei$ers ( bidirectional buffers ) to
separate the data from the multiplexed address,data signal. It is acti$e from the middle of
T< until the middle of T/. This is tristated during P hold ac%nowledgeQ cycle.
IHOLD9 HLDA: A,3-"60)(" -hen the 63C+ line goes high it indicates to the
processor that another master is re!uesting the bus access.
IThe processor after recei$ing the 63C+ re!uest issues the hold ac%nowledge signal on
6C+A pin in the middle of the next cloc% cycle after completing the current bus
cycle.IAt the same time the processor floats the local bus and control lines. -hen the
processor detects the 63C+ line low it lowers the 6C+A signal. 63C+ is an
asynchronous input and is should be externally synchroni(ed.
IIf the +MA re!uest is made while the C2& is performing a memory or I,3 cycle it will
release the local bus during T/ pro$ided"
).The re!uest occurs on or before T< state of the current cycle.
<.The current cycle is not operating o$er the lower byte of a word.
=.The current cycle is not the first ac%nowledge of an interrupt ac%nowledge se!uence.
/. A Coc% instruction is not being executed.
IThe following pin function are applicable for maximum mode operation of 8086.
IS29 S19 S0 S'%'/& L+-&" These are the status lines which reflect the type of operation
being carried out by the processor. These become acti$ity during T/ of the pre$ious cycle
and acti$e during T) and T< of the current bus cycles.
G-#%0 B/& O.#%'+"-:
IThe ;*;. has a combined address and data bus commonly referred as a time multiplexed
address and data bus.
IThe main reason behind multiplexing address and data o$er the same pins is the
maximum utilisation of processor pins and it facilitates the use of /* pin standard +I2
pac%age.
IThe bus can be demultiplexed using a few latches and transrecei$ers when e$er
re!uired.
I0asically all the processor bus cycles consist of at least four cloc% cycles. These are
referred to as T) T< T= T/. The address is transmitted by the processor during T). It is
present on the bus only for one cycle.
IThe negati$e edge of this AC# pulse is used to separate the address and the data or status
information. In maximum mode the status lines 7* 7) and 7< are used to indicate the
type of operation.
I7tatus bits 7= to 79 are multiplexed with higher order address bits and the 06# signal.
Address is $alid during T) while status bits 7= to 79 are $alid during T< through T/.
MINIMUM MODE 8086 SBSTEM
IIn a minimum mode ;*;. system the microprocessor ;*;. is operated in minimum
mode by strapping its MA,MO pin to logic ).
IIn this mode all the control signals are gi$en out by the microprocessor chip itself.
There is a single microprocessor in the minimum mode system.
IThe remaining components in the system are latches transrecei$ers cloc% generator
memory and I,3 de$ices. 7ome type of chip selection logic may be re!uired for selecting
memory or I,3 de$ices depending upon the address map of the system.
ICatches are generally buffered output +-type flip-flops li%e 9/C7=9= or ;<;<. They are
used for separating the $alid address from the multiplexed address,data signals and are
controlled by the AC# signal generated by ;*;..
G-#%0 B/& O.#%'+"- C$,0 +- M%=+!/! M")
ITransrecei$ers are the bidirectional buffers and some times they are called as data
amplifiers. They are re!uired to separate the $alid data from the time multiplexed
address,data signals.
IThey are controlled by two signals namely +#A and +T,1.
IThe +#A signal indicates the direction of data i.e. from or to the processor. The system
contains memory for the monitor and users program storage.
I&sually #213M are used for monitor storage while 1AM for users program storage. A
system may contain I,3 de$ices.
IThe wor%ing of the minimum mode configuration system can be better described in
terms of the timing diagrams rather than !ualitati$ely describing the operations.
IThe opcode fetch and read cycles are similar. 6ence the timing diagram can be
categori(ed in two parts the first is the timing diagram for read cycle and the second is
the timing diagram for write cycle.
IThe read cycle begins in T) with the assertion of address latch enable (AC#) signal and
also M , I3 signal. +uring the negati$e going edge of this signal the $alid address is
latched on the local bus.
IThe 06# and A* signals address low high or both bytes. 'rom T) to T/ the M,I3
signal indicates a memory or I,3 operation.
IAt T< the address is remo$ed from the local bus and is sent to the output. The bus is
then tristated. The read (1+) control signal is also acti$ated in T<.
IThe read (1+) signal causes the address de$ice to enable its data bus dri$ers. After 1+
goes low the $alid data is a$ailable on the data bus.
IThe addressed de$ice will dri$e the 1#A+R line high. -hen the processor returns the
read signal to high le$el the addressed de$ice will again tristate its bus dri$ers.
IA write cycle also begins with the assertion of AC# and the emission of the address. The
M,I3 signal is again asserted to indicate a memory or I,3 operation. In T< after sending
the address in T) the processor sends the data to be written to the addressed location.
IThe data remains on the bus until middle of T/ state. The -1 becomes acti$e at the
beginning of T< (unli%e 1+ is somewhat delayed in T< to pro$ide time for floating).
IThe 06# and A* signals are used to select the proper byte or bytes of memory or I,3
word to be read or write.
IThe M,I3 1+ and -1 signals indicate the type of data transfer as specified in table
below.
-rite Cycle Timing +iagram for Minimum Mode
IHold Response seuence" The 63C+ pin is chec%ed at leading edge of each cloc%
pulse. If it is recei$ed acti$e by the processor before T/ of the pre$ious cycle or during
T) state of the current cycle the C2& acti$ates 6C+A in the next cloc% cycle and for
succeeding bus cycles the bus will be gi$en to another re!uesting master.
IThe control of the bus is not regained by the processor until the re!uesting master does
not drop the 63C+ pin low. -hen the re!uest is dropped by the re!uesting master the
6C+A is dropped by the processor at the trailing edge of the next cloc%.
0us
1e!uest and 0us 5rant Timings in Minimum Mode 7ystem
M%=+!/! M") 8086 S$&'! IIn the maximum mode the ;*;. is operated by
strapping the MA,MO pin to ground.
IIn this mode the processor deri$es the status signal 7< 7) 7*. Another chip called bus
controller deri$es the control signal using this status information.
IIn the maximum mode there may be more than one microprocessor in the system
configuration.
IThe components in the system are same as in the minimum mode system.
IThe basic function of the bus controller chip IC;<;; is to deri$e control signals li%e 1+
and -1 ( for memory and I,3 de$ices) +#A +T,1 AC# etc. using the information by
the processor on the status lines.
IThe bus controller chip has input lines 7< 7) 7* and CCH. These inputs to ;<;; are
dri$en by C2&.
IIt deri$es the outputs AC# +#A +T,1 M1+C M-TC AM-C I31C I3-C and
AI3-C. The A#A I30 and C#A pins are specially useful for multiprocessor systems.
IA#A and I30 are generally grounded. C#A pin is usually tied to N>8. The significance
of the MC#,2+#A output depends upon the status of the I30 pin.
IIf I30 is grounded it acts as master cascade enable to control cascade ;<>LA else it
acts as peripheral data enable used in the multiple bus configurations.
IIATA pin used to issue two interrupt ac%nowledge pulses to the interrupt controller or to
an interrupting de$ice.
II31C I3-C are I,3 read command and I,3 write command signals respecti$ely. These
signals enable an I3 interface to read or write the data from or to the address port.
IThe M1+C M-TC are memory read command and memory write command signals
respecti$ely and may be used as memory read or write signals.
IAll these command signals instructs the memory to accept or send data from or to the
bus.
I'or both of these write command signals the ad$anced signals namely AI3-C and
AM-TC are a$ailable.
I6ere the only difference between in timing diagram between minimum mode and
maximum mode is the status signals used and the a$ailable control and ad$anced
command signals.
I1* 7) 7< are set at the beginning of bus cycle.;<;; bus controller will output a pulse
as on the AC# and apply a re!uired signal to its +T , 1 pin during T).
IIn T< ;<;; will set +#AS) thus enabling transcei$ers and for an input it will acti$ate
M1+C or I31C. These signals are acti$ated until T/. 'or an output the AM-C or
AI3-C is acti$ated from T< to T/ and M-TC or I3-C is acti$ated from T= to T/.
IThe status bit 7* to 7< remains acti$e until T= and become passi$e during T= and T/<
IIf reader input is not acti$ated before T= wait state will be inserted between T= and T/.
M!"#$ R%) T+!+-( +- M%=+!/! M")
MINIMUM MODE INTER;ACE
I-hen the Minimum mode operation is selected the ;*;. pro$ides all control signals
needed to implement the memory and I,3 interface.
Memory -rite Timing in Maximum mode.
IThe minimum mode signal can be di$ided into the following basic groups" address,data
bus status control interrupt and +MA.
IA))#&&/D%'% B/&" these lines ser$e two functions. As an address bus is <* bits long
and consists of signal lines A* through A)L. A)L represents the M70 and A* C70. A
<*bit address gi$es the ;*;. a )Mbyte memory address space. More o$er it has an
independent I,3 address space which is ./H bytes in length.
IThe ). data bus lines +* through +)> are actually multiplexed with address lines A*
through A)> respecti$ely. 0y multiplexed we mean that the bus wor% as an address bus
during first machine cycle and as a data bus during next machine cycles. +)> is the M70
and +* C70.
I-hen acting as a data bus they carry read,write data for memory input,output data for
I,3 de$ices and interrupt type codes from an interrupt controller.
UNIT II 16 BIT MICROPROCESSOR INSTRUCTION SET AND ASSEMBLB LANGUAGE
PROGRAMMING
The Intel ;*;. Instruction 7et
ADDRESSING MODES
IImplied - the data $alue,data address is implicitly associated with the instruction.
IRegister - references the data in a register or in a register pair.
IImmediate - the data is pro$ided in the instruction.
IDirect - the instruction operand specifies the memory address where data is located.
IRegister indirect - instruction specifies a register containing an address where data is
located. This addressing mode wor%s with 7I +I 0O and 02 registers.
IBased"- ;-bit or ).-bit instruction operand is added to the contents of a base register
(0O or 02) the resulting $alue is a pointer to location where data resides.
IIndexed"- ;-bit or ).-bit instruction operand is added to the contents of an index register
(7I or +I) the resulting $alue is a pointer to location where data resides
IBased Indexed"- the contents of a base register (0O or 02) is added to the contents of
an index register (7I or +I) the resulting $alue is a pointer to location where data resides.
IBased Indexed with displacement"- ;-bit or ).-bit instruction operand is added to the
contents of a base register (0O or 02) and index register (7I or +I) the resulting $alue is
a pointer to location where data resides.
IIAT instruction - brea%point interrupt. This is a type = interrupt.
IIAT Tinterrupt numberU instruction - any one interrupt from a$ailable <>. interrupts.
IIAT3 instruction - interrupt on o$erflow
I7ingle-step interrupt - generated if the T' flag is set. This is a type ) interrupt. -hen the
C2& processes this interrupt it clears T' flag before calling the interrupt processing
routine.
Arithmetic Instructions
The 80x86 provides many arithmetic operations: addition, subtraction, negation, multiplication, division/modulo
(remainder), and comparing two values The instructions that handle these operations are add, adc, sub,
sbb, mul, imul, div, idiv, cmp, neg, inc, dec, xadd, cmpxchg, and some miscellaneous
conversion instructions: aaa, aad, aam, aas, daa, and das The !ollowing sections describe these
instructions in detail
The generic !orms !or these instructions are
add dest, src dest := dest + src
adc dest, src dest := dest + src + C
SUB dest, src dest := dest - src
sbb dest, src dest := dest - src - C
mul src acc := acc * src
imul src acc := acc * src
imul dest, src1, imm_src dest := src1 * imm_src
imul dest, imm_src dest := dest * imm_src
imul dest, src dest := dest * src
div src acc := xacc -m!d src
idiv src acc := xacc -m!d src
cmp dest, src dest - src "and set #lags$
neg dest dest := - dest
inc dest dest := dest + 1
dec dest dest := dest - 1
xadd dest, src "see text$
cmpxchg !perand1, !perand% "see text$
cmpxchg& ax, !perand "see text$
aaa "see text$
aad "see text$
aam "see text$
aas "see text$
daa "see text$
das "see text$
6.5.1 The Addition Instructions: ADD, ADC, INC, XADD, AAA, and DAA
These instructions ta"e the !orms:
add reg, reg
add reg, mem
add mem, reg
add reg, immediate data
add mem, immediate data
add eaxaxal, immediate data
adc #!rms are identical t! '(()
inc reg
inc mem
inc reg1*
xadd mem, reg
xadd reg, reg
aaa
daa
#ote that the aaa and daa instructions use the implied addressing mode and allow no operands
6.5.1.1 The ADD and ADC Instructions
The syntax o! add and adc (add with carry) is similar to m!v $i"e m!v, there are special !orms !or the axeax
register that are more e!!icient %nli"e m!v, you cannot add a value to a segment register with these instructions
The add instruction adds the contents o! the source operand to the destination operand &or example, add ax,
bx adds bx to ax leaving the sum in the ax register 'dd computes dest :=dest+s!urce while adc
computes dest :=dest+s!urce+C where C represents the value in the carry !lag There!ore, i! the carry !lag is
clear be!ore execution, adc behaves exactly li"e the add instruction
'oth instructions a!!ect the !lags identically They set the !lags as !ollows:
The over!low !lag denotes a signed arithmetic over!low
The carry !lag denotes an unsigned arithmetic over!low
The sign !lag denotes a negative result (ie, the () bit o! the result is one)
The *ero !lag is set i! the result o! the addition is *ero
The auxiliary carry !lag contains one i! a '+, over!low out o! the $) nibble occurs
The parity !lag is set or cleared depending on the parity o! the $) eight bits o! the result -! there are
an even number o! one bits in the result, the .,, instructions will set the parity !lag to one (to denote even parity)
-! there are an odd number o! one bits in the result, the .,, instructions clear the parity !lag (to denote odd parity)
The add and adc instructions do not a!!ect any other !lags
The add and adc instructions allow eight, sixteen, and (on the 80/86 and later) thirty0two bit operands 'oth
source and destination operands must be the same si*e 1ee +hapter #ine i! you want to add operands whose
si*e is di!!erent
1ince there are no memory to memory additions, you must load memory operands into registers i! you want to add
two variables together The !ollowing code examples demonstrate possible !orms !or the add instruction:
+ ,:= - + .
m!v ax, -
add ax, .
m!v ,, ax
-! you want to add several values together, you can easily compute the sum in a single register:
+ , := - + . + / + 0
m!v ax, -
add ax, .
add ax, /
add ax, 0
m!v ,, ax
-! you want to reduce the number o! ha*ards on an 80286 or 3entium processor, you can use code li"e the
!ollowing:
m!v bx, -
m!v ax, .
add bx, /
add ax, 0
add ax, bx
m!v ,, ax
)ne thing that beginning assembly language programmers o!ten !orget is that you can add a register to a memory
location 1ometimes beginning programmers even believe that both operands have to be in registers, completely
!orgetting the lessons !rom +hapter &our The 80x86 is a +-1+ processor that allows you to use memory
addressing modes with various instructions li"e add -t is o!ten more e!!icient to ta"e advantages o! the 80x864s
memory addressing capabilities
+ , := - + ,
m!v ax, - +1his 2!r3s because additi!n is
add ,, ax + c!mmutative4
+ 5#ten, beginners 2ill c!de the ab!ve as !ne !# the #!ll!2ing t2! se6uences)
+ 1his is unnecessar74
m!v ax, , +8eall7 B'( 2a7 t! c!mpute
m!v bx, - + , := , + -)
add ax, bx
m!v ,, ax
m!v ax, , +Better, but still n!t a g!!d 2a7 t!
add ax, - + c!mpute , := , + -
m!v ,, ax
)! course, i! you want to add a constant to a memory location, you only need a single instruction The 80x86 lets
you directly add a constant to memory:
+ , := , + %
add ,, %
There are special !orms o! the add and adc instructions that add an immediate constant to the al, ax, or eax
register These !orms are shorter than the standard add reg, immediate instruction )ther instructions also
provide shorter !orms when using these registers5 there!ore, you should try to "eep computations in the
accumulator registers (al, ax, and eax) as much as possible
add bl, % +1hree b7tes l!ng
add al, % +12! b7tes l!ng
add bx, % +9!ur b7tes l!ng
add ax, % +1hree b7tes l!ng
etc)
.nother optimi*ation concerns the use o! small signed constants with the add and adc instructions -! a value is in
the range 0678,,8679, the add and adc instructions will sign extend an eight bit immediate constant to the
necessary destination si*e (eight, sixteen, or thirty0two bits) There!ore, you should try to use small constants, i!
possible, with the add and adc instructions
6.5.1.2 The INC Instruction
The inc (increment) instruction adds one to its operand :xcept !or the carry !lag, inc sets the !lags the same way
as add !perand, 1 would
#ote that there are two !orms o! inc !or 66 or /7 bit registers They are the inc reg and inc reg1*
instructions The inc reg and inc mem instructions are the same This instruction consists o! an opcode byte
!ollowed by a mod0reg0r/m byte (see .ppendix , !or details) The inc reg1* instruction has a single byte
opcode There!ore, it is shorter and usually !aster
The inc operand may be an eight bit, sixteen bit, or (on the 80/86 and later) thirty0two bit register or memory
location
The inc instruction is more compact and o!ten !aster than the comparable add reg, 1 or add mem, 1
instruction -ndeed, the inc reg1* instruction is one byte long, so it turns out that two such instructions are
shorter than the comparable add reg, 1 instruction5 however, the two increment instructions will run slower on
most modern members o! the 80x86 !amily
The inc instruction is very important because adding one to a register is a very common operation -ncrementing
loop control variables or indices into an array is a very common operation, per!ect !or the inc instruction The !act
that inc does not a!!ect the carry !lag is very important This allows you to increment array indices without a!!ecting
the result o! a multiprecision arithmetic operation ( see +hapter #ine !or more details about multiprecision
arithmetic)
6.5.1.3 The XADD Instruction
;add (:xchange and .dd) is another 80286 (and later) instruction -t does not appear on the 80/86 and earlier
processors This instruction adds the source operand to the destination operand and stores the sum in the
destination operand (owever, <ust be!ore storing the sum, it copies the original value o! the destination operand
into the source operand The !ollowing algorithm describes this operation:
xadd dest, s!urce
temp := dest
dest := dest + s!urce
s!urce := temp
The xadd sets the !lags <ust as the add instruction would The xadd instruction allows eight, sixteen, and thirty0
two bit operands 'oth source and destination operands must be the same si*e
6.5.1.4 The AAA and DAA Instructions
The aaa (.1+-- ad<ust a!ter addition) and daa (decimal ad<ust !or addition) instructions support '+, arithmetic
'eyond this chapter, this text will not cover '+, or .1+-- arithmetic since it is mainly !or controller applications, not
general purpose programming applications '+, values are decimal integer coded in binary !orm with one decimal
digit (0=) per nibble .1+-- (numeric) values contain a single decimal digit per byte, the () nibble o! the byte
should contain *ero
The aaa and daa instructions modi!y the result o! a binary addition to correct it !or .1+-- or decimal arithmetic &or
example, to add two '+, values, you would add them as though they were binary numbers and then execute the
daa instruction a!terwards to correct the results $i"ewise, you can use the aaa instruction to ad<ust the result o! an
.1+-- addition a!ter executing an add instruction 3lease note that these two instructions assume that the add
operands were proper decimal or .1+-- values -! you add binary (non0decimal or non0.1+--) values together and
try to ad<ust them with these instructions, you will not produce correct results
The choice o! the name >.1+-- arithmetic> is un!ortunate, since these values are not true .1+-- characters .
name li"e >unpac"ed '+,> would be more appropriate (owever, -ntel uses the name .1+--, so this text will do so
as well to avoid con!usion (owever, you will o!ten hear the term >unpac"ed '+,> to describe this data type
'aa (which you generally execute a!ter an add, adc, or xadd instruction) chec"s the value in al #!r '+,
over!low -t wor"s according to the !ollowing basic algorithm:
i# " "al and :9h$ ; < !r "'uxC =1$ $ then
i# "&:&& !r &:&*$ then
al := al + *
else
ax := ax + *
endi#
ah := ah + 1
'uxC := 1 +Set auxilliar7 carr7
Carr7 := 1 + and carr7 #lags)
else
'uxC := : +Clear auxilliar7 carr7
Carr7 := : + and carr7 #lags)
endi#
al := al and :9h
The aaa instruction is mainly use!ul !or adding strings o! digits where there is exactly one decimal digit per byte in
a string o! numbers This text will not deal with '+, or .1+-- numeric strings, so you can sa!ely ignore this
instruction !or now )! course, you can use the aaa instruction any time you need to use the algorithm above, but
that would probably be a rare situation
The daa instruction !unctions li"e aaa except it handles pac"ed '+, (binary code decimal) values rather than the
one digit per byte unpac"ed values aaa handles .s !or aaa, daa4s main purpose is to add strings o! '+, digits
(with two digits per byte) The algorithm #!r daa is
i# " "'= and :9h$ ; < !r "'uxC = 1$$ then
al := al + *
'uxC := 1 +Set 'uxilliar7 carr7)
endi#
i# " "al ; <9h$ !r "Carr7 = 1$$ then
al := al + *:h
Carr7 := 1+ +Set carr7 #lag)
endi#
6.5.2 The Sutraction Instructions: S!", S"", D#C, AAS, and DAS
The sub (subtract), sbb (subtract with borrow), dec (decrement), aas (.1+-- ad<ust !or subtraction), and das
(decimal ad<ust !or subtraction) instructions wor" as you expect Their syntax is very similar to that o! the add
instructions:
sub reg, reg
sub reg, mem
sub mem, reg
sub reg, immediate data
sub mem, immediate data
sub eaxaxal, immediate data
sbb #!rms are identical t! sub)
dec reg
dec mem
dec reg1*
aas
das
The sub instruction computes the value dest := dest - src The sbb instruction computes dest := dest
- src - C #ote that subtraction is not commutative -! you want to compute the result !or dest := src -
dest you will need to use several instructions, assuming you need to preserve the source operand)
)ne last sub<ect worth discussing is how the sub instruction a!!ects the 80x86 !lags register The sub, sbb, and
dec instructions a!!ect the !lags as !ollows:
They set the *ero !lag i! the result is *ero This occurs only i! the operands are e?ual !or sub and sbb
The dec instruction sets the *ero !lag only when it decrements the value one
These instructions set the sign !lag i! the result is negative
These instructions set the over!low !lag i! signed over!low/under!low occurs
They set the auxiliary carry !lag as necessary !or '+,/.1+-- arithmetic
They set the parity !lag according to the number o! one bits appearing in the result value
The sub and sbb instructions set the carry !lag i! an unsigned over!low occurs #ote that the dec
instruction does not a!!ect the carry !lag
The aas instruction, li"e its aaa counterpart, lets you operate on strings o! .1+-- numbers with one decimal digit
(in the range 0=) per byte @ou would use this instruction a!ter a sub or sbb instruction on the .1+-- value This
instruction uses the !ollowing algorithm:
i# " "al and :9h$ ; < !r 'uxC = 1$ then
al := al - *
ah := ah - 1
'uxC := 1 +Set auxilliar7 carr7
Carr7 := 1 + and carr7 #lags)
else
'uxC := : +Clear 'uxilliar7 carr7
Carr7 := : + and carr7 #lags)
endi#
al := al and :9h
The das instruction handles the same operation !or '+, values, it uses the !ollowing algorithm:
i# " "al and :9h$ ; < !r "'uxC = 1$$ then
al := al -*
'uxC = 1
endi#
i# "al ; <9h !r Carr7 = 1$ then
al := al - *:h
Carr7 := 1 +Set the Carr7 #lag)
endi#
1ince subtraction is not commutative, you cannot use the sub instruction as !reely as the add instruction The
!ollowing examples demonstrate some o! the problems you may encounter
+ , := - - ,
m!v ax, - +1his is a nice tr7, but it c!mputes
sub ,, ax + , := , - -, subtracti!n isn>t
+ c!mmutative4
m!v ax, - +C!rrect s!luti!n)
sub ax, ,
m!v ,, ax
+ , := , - "- + .$ -- (!n>t #!rget this is e6uivalent t! , := , - - - .
m!v ax, - +C!mputes '? := - + .
add ax, .
sub ,, ax +C!mputes , := , - "- + .$
m!v ax, , +'n!ther s!luti!n, th!ugh less
sub ax, - +@##icient
sub ax, .
m!v ,, ax
#ote that the sub and sbb instructions, li"e add and adc, provide short !orms to subtract a constant !rom an
accumulator register (al, ax, or eax) &or this reason, you should try to "eep arithmetic operations in the
accumulator registers as much as possible The sub and sbb instructions also provide a shorter !orm when
subtracting constants in the range 06788679 !rom a memory location or register The instruction will automatically
sign extend an eight bit signed value to the necessary si*e be!ore the subtraction occurs 1ee .ppendix , !or the
details
-n practice, there really isn4t a need !or an instruction that subtracts a constant !rom a register or memory location 0
adding a negative value achieves the same result #evertheless, -ntel provides a subtract immediate instruction
.!ter the execution o! a sub instruction, the condition code bits (carry, sign, over!low, and *ero) in the !lags register
contain values you can test to see i! one o! sub4s operands is e?ual, not e?ual, less than, less than or e?ual,
greater than, or greater than or e?ual to the other operand 1ee the cmp instruction !or more details
6.5.3 The C$% Instruction
The cmp (compare) instruction is identical to the sub instruction with one crucial di!!erence 0 it does not store the
di!!erence bac" into the destination operand The syntax !or the cmp instruction is very similar to sub, the generic
!orm is
cmp dest, src
The speci!ic !orms are
cmp reg, reg
cmp reg, mem
cmp mem, reg
cmp reg, immediate data
cmp mem, immediate data
cmp eaxaxal, immediate data
The cmp instruction updates the 80x864s !lags according to the result o! the subtraction operation (dest 0 src) @ou
can test the result o! the comparison by chec"ing the appropriate !lags in the !lags register &or details on how this
is done, see >The >1et on +ondition> -nstructions> and >The +onditional Aump -nstructions>
%sually you4ll want to execute a conditional <ump instruction a!ter a cmp instruction This two step process,
comparing two values and setting the !lag bits then testing the !lag bits with the conditional <ump instructions, is a
very e!!icient mechanism !or ma"ing decisions in a program
3robably the !irst place to start when exploring the cmp instruction is to ta"e a loo" at exactly how the cmp
instruction a!!ects the !lags +onsider the !ollowing cmp instruction:
cmp ax, bx
This instruction per!orms the computation ax-bx and sets the !lags depending upon the result o! the computation
The !lags are set as !ollows:
B: The *ero !lag is set i! and only i! ax = bx This is the only time ax-bx produces a *ero result (ence, you can
use the *ero !lag to test !or e?uality or ine?uality
1: The sign !lag is set to one i! the result is negative .t !irst glance, you might thin" that this !lag would be set i! ax
is less than bx but this isn4t always the case -! axC9&&&h and bxC06 (0&&&&h) subtracting ax !rom bx produces
8000h, which is negative (and so the sign !lag will be set) 1o, !or signed comparisons anyway, the sign !lag
doesn4t contain the proper status &or unsigned operands, consider axC0&&&&h and bxC6 'x is greater than bx
but their di!!erence is 0&&&:h which is still negative .s it turns out, the sign !lag and the over!low !lag, ta"en
together, can be used !or comparing two signed values
): The over!low !lag is set a!ter a cmp operation i! the di!!erence o! ax and bx produced an over!low or
under!low .s mentioned above, the sign !lag and the over!low !lag are both used when per!orming signed
comparisons
+: The carry !lag is set a!ter a cmp operation i! subtracting bx !rom ax re?uires a borrow This occurs only when
ax is less than bx where ax and bx are both unsigned values
The cmp instruction also a!!ects the parity and auxiliary carry !lags, but you4ll rarely test these two !lags a!ter a
compare operation Diven that the cm& instruction sets the !lags in this !ashion, you can test the comparison o! the
two operands with the !ollowing !lags:
cmp 5prnd1, 5prnd%
Condition Code Settin's A(ter C$%
!nsi'ned o&erands: Si'ned o&erands:
B: e?uality/ine?uality B: e?uality/ine?uality
+: )prnd6 E )prnd7 (+C6) )prnd6 FC )prnd7 (+C0) +: no meaning
1: no meaning 1: see below
): no meaning ): see below
&or signed comparisons, the 1 (sign) and ) (over!low) !lags, ta"en together, have the !ollowing meaning:
-! ((1C0) and ()C6)) or ((1C6) and ()C0)) then )prnd6 E )prnd7 when using a signed comparison
-! ((1C0) and ()C0)) or ((1C6) and ()C6)) then )prnd6 FC )prnd7 when using a signed comparison
To understand why these !lags are set in this manner, consider the !ollowing examples:
5prnd1 minus 5prnd% S 5
------ ------ - -
:9999 "-1$ - :999@ "-%$ : :
:&::: - ::::1 : 1
:999@ "-%$ - :9999 "-1$ 1 :
:A999 "B%A*A$ - :9999 "-1$ 1 1
Gemember, the cmp operation is really a subtraction, there!ore, the !irst example above computes (06)0(07) which
is (86) The result is positive and an over!low did not occur so both the 1 and ) !lags are *ero 1ince (1 xor )) is
*ero, )prnd6 is greater than or e?ual to )prnd7
-n the second example, the cmp instruction would compute (0/7968)0(86) which is (0/796=) 1ince a 660bit signed
integer cannot represent this value, the value wraps around to 9&&&h (8/7969) and sets the over!low !lag 1ince
the result is positive (at least within the con!ines o! 66 bits) the sign !lag is cleared 1ince (1 xor )) is one here,
)prnd6 is less than )prnd7
-n the third example above, cmp computes (07)0(06) which produces (06) #o over!low occurred so the ) !lag is
*ero, the result is negative so the sign !lag is one 1ince (1 xor )) is one, )prnd6 is less than )prnd7
-n the !ourth (and !inal) example, cmp computes (8/7969)0(06) This produces (8/7968), setting the over!low !lag
&urthermore, the value wraps around to 8000h (0/7968) so the sign !lag is set as well 1ince (1 xor )) is *ero,
)prnd6 is greater than or e?ual to )prnd7
6.5.4 The C$%XC)*, and C$%XC)*+" Instructions
The cmpxchg (compare and exchange) instruction is available only on the 80286 and later processors -t supports
the !ollowing syntax:
cmpxchg reg, reg
cmpxchg mem, reg
The operands must be the same si*e (eight, sixteen, or thirty0two bits) This instruction also uses the accumulator
register5 it automatically chooses al, ax, or eax to match the si*e o! the operands
This instruction compares al, ax, or eax with the !irst operand and sets the *ero !lag i! they are e?ual -! so, then
cmpxchg copies the second operand into the !irst -! they are not e?ual, cmpxchg copies the !irst operand into the
accumulator The !ollowing algorithm describes this operation:
cmpxchg !perand1, !perand%
i# "CalaxeaxD = !perand1$ then
Eer! := 1 +Set the Eer! #lag
!perand1 := !perand%
else
Eer! := : +Clear the Eer! #lag
CalaxeaxD := !perand1
endi#
Cmpxchg supports certain operating system data structures re?uiring atomic operations and semaphores )!
course, i! you can !it the above algorithm into your code, you can use the cmpxchg instruction as appropriate
#ote: unli"e the cmp instruction, the cmpxchg instruction only a!!ects the 80x86 *ero !lag @ou cannot test other
!lags a!ter cmpxchg as you could with the cmp instruction
The 3entium processor supports a 62 bit compare and exchange instruction 0 cmpxchg&b -t uses the syntax:
cmpxchg&b ax, mem*F
This instruction compares the 62 bit value in edx:eax with the memory value -! they are e?ual, the 3entium
stores ecx:ebx into the memory location, otherwise it loads edx:eax with the memory location This instruction sets
the *ero !lag according to the result -t does not a!!ect any other !lags
6.5.5 The N#* Instruction
The neg (negate) instruction ta"es the two4s complement o! a byte or word -t ta"es a single (destination) operation
and negates it The syntax !or this instruction is
neg dest
-t computes the !ollowing:
dest := : - dest
This e!!ectively reverses the sign o! the destination operand
-! the operand is *ero, its sign does not change, although this clears the carry !lag #egating any other value sets
the carry !lag #egating a byte containing 0678, a word containing 0/7,968, or a double word containing
07,629,28/,628 does not change the operand, but will set the over!low !lag /eg always updates the ., 1, 3, and B
!lags as though you were using the sub instruction
The allowable !orms are:
neg reg
neg mem
The operands may be eight, sixteen, or (on the 80/86 and later) thirty0two bit values
1ome examples:
+ , := - ,
neg ,
+ , := --
m!v ax, -
neg ax
I-&'#/,'+"- M%-+-( N"'&
AAA A7CII %d4ust AC after %ddition used with unpac%ed binary coded decimal
AA+ A7CII %d4ust AO before )i$ision
;*;.,;*;; datasheet documents only base )*
$ersion of the AA+ instruction (opcode *x+>
*x*A) but any other base will wor%. Cater
Intel:s documentation has the generic form too.
A#C 8<* and 8=* (and possibly other A#C 8-
series C2&s) always use base )* and ignore the
argument causing a number of incompatibilities
AAM A7CII %d4ust AO after
!ultiplication
3nly base )* $ersion is documented see notes
for AA+
AA7 A7CII %d4ust AC after &ubtraction
A+C A)d with ,arry destination "S destination N source N carryVflag
A++ Add
AA+ Cogical AA+
CACC Call procedure
C0- Con$ert 8yte to 6ord
CCC C0ear , arry flag
CC+ C0ear )irection flag
CCI C0ear +nterrupt flag
CMC Co!plement ,arry flag
CM2 Co!.are operands
CM270 Co!.are bytes in memory
CM27- Co!.are words
C-+ Con$ert 6ord to )oubleword
+AA Decimal %d4ust AC after %ddition (used with pac%ed binary coded decimal)
+A7 Decimal %d4ust AC after &ubtraction
+#C D,rement by )
+I8 &nsigned )+*ide
#7C &sed with floating-point unit
6CT #nter 7a0' state
I+I8 7+gned )+*ide
IM&C 7+gned !/0tiply
IA I-put from port
IAC I-,rement by )
IAT Call to +-' errupt
IAT3 Call to +-'errupt if "$erflow
I1#T R'urn from +nterrupt
Wxx Jump if condition
(JA, JAE, JB, JBE, JC, JCXZ, JE, JG, JGE, JL,
JLE, JNA, JNAE, JNB, JNBE, JNC, JNE, JNG,
JNGE, JNL, JNLE, JNO, JNP, JNS, JNZ, JO,
JP, JPE, JPO, JS, JZ)
WM2 Ju!.
CA6' Load 4lags into AH register
C+7 Load pointer using DS
C#A Load Effecti$e Address
C#7 Load ES with pointer
C3CH Assert 0&7 LOCDX signal (for multiprocessing)
C3+70 L"a) &igned 8yte
C3+7- L"a) &igned 6ord
C332,C332x L"". control (LOOPE, LOOPNE, LOOPNZ, LOOPZ)
M38 M"*e
M3870 M"*e 8yte from &tring to string
M387- M"*e word from &tring to &tring
M&C &nsigned !/0tiply
A#5 Two:s complement -(ation
A32 No ".eration opcode (*xL*) e!ui$alent to OC65 #AO #AO
A3T Aegate the operand logical NOT
31 Cogical OR
3&T O/'put to port
232 P". data from stac%
232 C7 (opcode *x*') wor%s only on
;*;.,;*;;. Cater C2&s use *x*' as a prefix for
newer instructions.
232' P". data into 4 lags register
2&76 P/&7 data onto stac%
2&76' P/&7 4lags onto stac%
1CC Rotate 0eft (with ,arry)
1C1 Rotate #ight (with ,arry)
1#2xx
R.eat
M387,7T37,CM27,C3+7,7CA7
(REP, REPE, REPNE, REPNZ, REPZ)
1#T R'urn from procedure
1#TA R'urn from -ear procedure
1#T' R'urn from 4ar procedure
13C R"tate 0eft
131 R"tate #ight
7A6' Store AH into 4lags
7AC
S hift A rithmetically 0eft (signed
shift left)
7A1
Shift Arithmetically #ight (signed
shift right)
700 Su8traction with 8orrow
7CA70 Comp%re 8yte &tring
7CA7- Comp%re 6ord &tring
76C S7 ift 0eft (unsigned shift left)
761 S7ift #ight (unsigned shift right)
7TC Se' ,arry flag
7T+ Se' )irection flag
7TI Se' +nterrupt flag
7T370 S'"re 8yte in &tring
7T37- S'"re 6ord in &tring
7&0 S/8traction
T#7T Cogical compare (AA+)
-AIT W%+' until not busy
-aits until 0&7RX pin is inacti$e (used with
floating-point unit)
OC65 #=,7an(e data
OCAT Table loo%-up translation
O31 # = clusi$e OR
UNIT III
MICROPROCESSOR PERIPHERAL INTER;ACING
DMA C"-'#"00# ;%'/#&
5eneral-purpose direct-memory access (+MA) controller
&p to ). +MA channels
7upports both synchronous and asynchronous +MA transfers
+esigned for peripheral component interconnect (2CI) and other central processing
unit (C2&) bus systems
DMA C"-'#"00# B0",3 D+%(#%!
'igure ) shows the bloc% diagram for the +MA controller mega function.
!igure ". #$% &ontroller 'loc( #iagram
DMA C"-'#"00# D&,#+.'+"-
The +MA controller megafunction is designed for data transfer in different system en$ironments.
Two module types@type * and type )@are pro$ided and the user can choose the number of each
module type. Type * modules are designed to transfer data residing on the same bus and Type )
modules are designed to transfer data between two different buses. #ach module can support up to /
+MA channels? the megafunction supports up to ). total +MA channels.
#ach +MA channel can be programmed for $arious features such as transfer si(e synchroni(ed and
unsynchroni(ed transfer control transfer priority interrupt generation memory and I,3 address
space and address change direction. This megafunction is designed to wor% with =<-bit and ./-bit
bus systems including the 2CI bus 2ower2C bus and other C2& host buses. It can also be
integrated with other mega functions to form a complete functional bloc%.
This mega function is a$ailable in Altera 6ardware +escription Canguage (A6+C) 8erilog 6+C
86+C and netlist format.
82?@A PROGRAMMABLE INTERRUPT CONTROLLER
The Intel ;<>LA 2rogrammable Interrupt Controller handles up to eight $ectored priority interrupts
for the C2&. It is cascadable for up to ./ $ectored priority interrupts without additional circuitry. It
is pac%aged in a <;-pin +I2 uses AM37 technology and re!uires a single a>8 supply. Circuitry is
static re!uiring no cloc% input.
The ;<>LA is designed to minimi(e the software and real time o$erhead in handling multi-le$el
priority interrupts.
It has se$eral modes permitting optimi(ation for a $ariety of system re!uirements. The ;<>LA is
fully upward compatible with the Intel ;<>L. 7oftware originally written for the ;<>L will operate
the ;<>LA in all ;<>L e!ui$alent modes (MC7-;*,;> Aon-0uffered and #dge Triggered).
;UNCTIONAL DESCRIPTION
Interrupts in Microcomputer 7ystems Microcomputer system design re!uires that I.3 de$ices such
as %eyboards displays sensors and other components recei$e ser$icing in a an efficient manner so
that large amounts of the total system tas%s can be assumed by the microcomputer with little or no
effect on throughput. The most common method of ser$icing such de$ices is the 2olled approach.
This is where the processor must test each de$ice in se!uence and in effect Das%E each one if it needs
ser$icing. It is easy to see that a large portion of the main program is looping through this continuous
polling cycle and that such a method would ha$e a serious detrimental effect on system throughput
thus limiting the tas%s that could be assumed by the microcomputer and reducing the cost
effecti$eness of using such de$ices.
A more desirable method would be one that would allow the microprocessor to be executing its main
program and only stop to ser$ice peripheral de$ices when it is told to do so by the de$ice itself. In
effect the method would pro$ide an external asynchronous input that would inform the processor
that it should complete whate$er instruction that is currently being executed and fetch a new routine
that will ser$ice the re!uesting de$ice. 3nce this ser$icing is complete howe$er the processor
would resume exactly where it left off.
This method is called Interrupt. It is easy to see that system throughput would drastically increase
and thus more tas%s could be assumed by the microcomputer to further enhance its cost
effecti$eness. The 2rogrammable Interrupt Controller (2IC) functions as an o$erall manager in an
Interrupt-+ri$en system en$ironment. It accepts re!uests from the peripheral e!uipment determines
which of the incoming re!uests is of the highest importance (priority) ascertains whether the
incoming re!uest has a higher priority $alue than the le$el currently being ser$iced and issues an
interrupt to the C2& based on this determination. #ach peripheral de$ice or structure usually has a
special program or YYroutine:: that is associated with its specific functional or operational
re!uirements? this is referred to as a YYser$ice routine::. The 2IC after issuing an Interrupt to the
C2& must somehow input information into the C2& that can YYpoint:: the 2rogram Counter to the
ser$ice routine associated with the re!uesting de$ice. This YYpointer:: is an address in a $ectoring
table and will often be referred to in this document as $ectoring data.
IAT#11&2T 1#G&#7T 1#5I7T#1 (I11) AA+ IA-7#18IC# 1#5I7T#1 (I71)
The interrupts at the I1 input lines are handled by two registers in cascade the Interrupt 1e!uest
1egister (I11) and the In-7er$ice (I71). The I11 is used to store all the interrupt le$els which are
re!uesting ser$ice? and the I71 is used to store all the interrupt le$els which are being ser$iced.
21I31ITR 1#73C8#1
This logic bloc% determines the priorites of the bits set in the I11. The highest priority is selected
and strobed into the corresponding bit of the I71 during IATA pulse.
IAT#11&2T MA7H 1#5I7T#1 (IM1)
The IM1 stores the bits which mas% the interrupt lines to be mas%ed. The IM1 operates on the I11.
Mas%ing of a higher priority input will not affect the
interrupt re!uest lines of lower !uality.
IAT (IAT#11&2T)
This output goes directly to the C2& interrupt input. The 836 le$el on this line is designed to be
fully compatible with the ;*;*A ;*;>A and ;*;. input le$els.
IATA (IAT#11&2T ACHA3-C#+5#)
IATA pulses will cause the ;<>LA to release $ectoring information onto the data bus. The format of
this data depends on the system mode (m2M) of the ;<>LA.
+ATA 0&7 0&''#1
This =-state bidirectional ;-bit buffer is used to interface the ;<>LA to the system +ata 0us. Control
words and status information are transferred through the +ata 0us 0uffer.
1#A+,-1IT# C3AT13C C35IC
The function of this bloc% is to accept 3&Tput commands from the C2&. It contains the
Initiali(ation Command -ord (IC-) registers and 3peration Command -ord (3C-) registers
which store the $arious control formats for de$ice operation. This function bloc% also allows the
status of the ;<>LA to be transferred onto the +ata 0us.
C7 (C6I2 7#C#CT)
A C3- on this input enables the ;<>LA. Ao reading or writing of the chip will occur unless the
de$ice is selected.
-1 (-1IT#)
A C3- on this input enables the C2& to write control words (IC-s and 3C-s) to the ;<>LA.
1+ (1#A+)
A C3- on this input enables the ;<>LA to send the status of the Interrupt 1e!uest 1egister (I11)
In 7er$ice 1egister (I71) the Interrupt Mas% 1egister (IM1) or the Interrupt le$el onto the +ata
0us.
A*
This input signal is used in con4unction with -1 and 1+ signals to write commands into the $arious
command registers as well as reading the $arious status registers of the chip. This line can be tied
directly to one of the address lines.
IAT#11&2T 7#G&#AC#
The powerful features of the ;<>LA in a microcomputer system are its programmability and the
interrupt routine addressing capability. The latter allows direct or indirect 4umping to the specific
interrupt routine re!uested without any polling of the interrupting de$ices. The normal se!uence of
e$ents during an interrupt depends on the type of C2& being used.
The e$ents occur as follows in an MC7-;*,;> system"
). 3ne or more of the IAT#11&2T 1#G&#7T lines (I19Z*) are raised high setting the
corresponding I11 bit(s).
<. The ;<>LA e$aluates these re!uests and sends an IAT to the C2& if appropriate.
=. The C2& ac%nowledges the IAT and responds with an IATA pulse.
/. &pon recei$ing an IATA from the C2& group the highest priority I71 bit is set and
the corresponding I11 bit is reset. The ;<>LA will also release a CACC instruction code
())**))*)) onto the ;-bit +ata 0us through its +9Z* pins.
>. This CACC instruction will initiate two more IATA pulses to be sent to the ;<>LA
from the C2& group.
.. These two IATA pulses allow the ;<>LA to release its preprogrammed subroutine
address onto the +ata 0us. The lower ;-bit address is released at the first IATA pulse and the
higher ;-bit address is released at the second IATA pulse.
9. This completes the =-byte CACC instruction released by the ;<>LA. In the A#3I
mode the I71 bit is reset at the end of the third IATA pulse. 3therwise the I71 bit remains
set until an appropriate #3I command is issued at the end of the interrupt se!uence. The
e$ents occurring in an ;*;. system are the same until step /.
;. &pon recei$ing an IATA from the C2& group the highest priority I71 bit is set and
the corresponding I11 bit is reset. The ;<>LA does not dri$e the +ata 0us during this cycle.
L. The ;*;. will initiate a second IATA pulse. +uring this pulse the ;<>LA releases an
;-bit pointer onto the +ata 0us where it is read by the C2&.
)*. This completes the interrupt cycle. In the A#3I mode the I71 bit is reset at the end of
the second IATA pulse. 3therwise the I71 bit remains set until an appropriate #3I
command is issued at the end of the interrupt subroutine. If no interrupt re!uest is present at
step / of either se!uence (i.e. the re!uest was too short in duration) the ;<>LA will issue an
interrupt le$el 9. 0oth the $ectoring bytes and the CA7 lines will loo% li%e an interrupt le$el
9 was re!uested. -hen the ;<>LA 2IC recei$es an interrupt IAT becomes acti$e and an
interrupt ac%nowledge cycle is started. If a higher priority interrupt occurs between the two
IATA pulses the IAT line goes inacti$e immediately after the second IATA pulse. After an
unspecified amount of time the IAT line is acti$ated again to signify the higher priority
interrupt waiting for ser$ice. This inacti$e time is not specified and can $ary between parts.
The designer should be aware of this consideration when designing a system which uses the
;<>LA. It is recommended that proper asynchronous design techni!ues be followed.
The IAT#C ;<9L is specially de$eloped for interfacing %eyboard and display de$ices to
;*;>,;*;.,;*;; microprocessor based system. The important features of ;<9L are
). 7imultaneous %eyboard and display operations.
<. 7canned %eyboard mode.
=. 7canned sensor mode.
/. ;-character %eyboard 'I'3.
>. ) .-character display.
.. 1ight or left entry ) .-byte display 1AM.
9. 2rogrammable scan timing.
Heyboard section"
The %eyboard section consists of eight return lines 1C* - 1C9 that can be used to
form the columns of a %eyboard matrix.
It has two additional input" shift and control,strobe. The %eys are automatically
debounced.
The two operating modes of %eyboard section are <-%ey loc%out and A-%ey rollo$er.
In the <-%ey loc%out mode if two %eys are pressed simultaneously only the first %ey
is recogni(ed.
In the A-%ey rollo$er mode simultaneous %eys are recogni(ed and their codes are
stored in 'I'3.
The %eyboard sections also ha$e an ; x ; 'I'3 ('irst In 'irst 3ut) 1AM.
The 'I'3 can store eight %ey codes in the scan %eyboard mode. The status of the shift
%ey and control %ey are also stored along with %ey code. The ;<9L generate an interrupt
signal when there is an e'I'3.
0loc% diagram of ;<9L"
The functional bloc% diagram of ;<9L is shown.
In sensor matrix mode the condition (i.e. open,close status) of ./ switches is stored
in 'I'3 1AM. If the condition of any of the switches changes then the ;<9L asserts I1G as
high to interrupt the processor.
+isplay section"
The display section has eight output lines di$ided into two groups A*-A= and 0*-0=.
The output lines can be used either as a single group of eight lines or as two groups of
four lines in con4unction with the scan lines for a multiplexed display.
The output lines are connected to the anodes through dri$er transistor in case of
common cathode 9-segment C#+s.
The cathodes are connected to scan lines through dri$er transistors.
The display can be blan%ed by 0+ (low) line.
The display section consists of ). x ; display 1AM. The C2& can read from or write
into any location of the display 1AM.
7can section"
The scan section has a scan counter and four scan lines 7C* to 7C=.
In decoded scan mode the output of scan lines will be similar to a <-to-/ decoder.
In encoded scan mode the output of scan lines will be binary count and so an
external decoder should be used to con$ert the binary count to decoded output.
The scan lines are common for %eyboard and display.
The scan lines are used to form the rows of a matrix %eyboard and also connected to
digit dri$ers of a multiplexed display to turn 3A,3''.
C2& interface section"
The C2& interface section ta%es care of data transfer between ;<9L and the processor.
This section has eight bidirectional data lines +0* to +09 for data transfer between
;<9L and C2&.
It re!uires two internal address A S* for selecting data buffer and A S ) for selecting
control register of;<9L.
The control signals -1 (low) 1+ (low) C7 (low) and A* are used for read,write to
;<9L.
It has an interrupt re!uest line I1G for interrupt dri$en data transfer with processor.
The ;<9L re!uire an internal cloc% fre!uency of )** %6(. This can be obtained by
di$iding the input cloc% by an internal prescaler.
The 1#7#T signal sets the ;<9L in ).-character display with two -%ey loc%out
%eyboard modes.
S#+%0 P#+.7#%0 I-'#4%, B/&
O.#%'+"-
The 72I bus can operate with a single master de$ice and with one or more sla$e de$ices.
If a single sla$e de$ice is used the 77 pin m! be fixed to logic low if the sla$e permits it. 7ome
sla$es re!uire the falling edge (high[low transition) of the sla$e select to initiate an action such as
the Maxim MAO)</< A+C which starts con$ersion on said transition. -ith multiple sla$e de$ices
an independent 77 signal is re!uired from the master for each sla$e de$ice.
Most sla$e de$ices ha$e tri-state outputs so their MI73 signal becomes high impedance
(BdisconnectedB) when the de$ice is not selected. +e$ices without tri-state outputs can:t share 72I
bus segments with other de$ices? only one such sla$e could tal% to the master and only its chip
select could be acti$ated.
D%'% '#%-&!+&&+"-
A typical hardware setup using two shift registers to form an inter-chip circular buffer
To begin a communication the master first configures the cloc% using a fre!uency less than or e!ual
to the maximum fre!uency the sla$e de$ice supports. 7uch fre!uencies are commonly in the range of
)K9* M6(.
The master then pulls the sla$e select low for the desired chip. If a waiting period is re!uired (such
as for analog-to-digital con$ersion) then the master must wait for at least that period of time before
starting to issue cloc% cycles.
+uring each 72I cloc% cycle a full duplex data transmission occurs"
the master sends a bit on the M37I line? the sla$e reads it from that same line
the sla$e sends a bit on the MI73 line? the master reads it from that same line
Aot all transmissions re!uire all four of these operations to be menin"#ul but they do happen.
Transmissions normally in$ol$e two shift registers of some gi$en word si(e such as eight bits one
in the master and one in the sla$e? they are connected in a ring. +ata are usually shifted out with the
most significant bit first while shifting a new least significant bit into the same register. After that
register has been shifted out the master and sla$e ha$e exchanged register $alues. Then each de$ice
ta%es that $alue and does something with it such as writing it to memory. If there is more data to
exchange the shift registers are loaded with new data and the process repeats.
Transmissions may in$ol$e any number of cloc% cycles. -hen there are no more data to be
transmitted the master stops toggling its cloc%. Aormally it then deselects the sla$e.
Transmissions often consist of ;-bit words and a master can initiate multiple such transmissions if it
wishes,needs. 6owe$er other word si(es are also common such as ).-bit words for touchscreen
controllers or audio codecs li%e the T7C<)*) from Texas Instruments? or )<-bit words for many
digital-to-analog or analog-to-digital con$erters.
#$ery sla$e on the bus that hasn:t been acti$ated using its sla$e select line must disregard the input
cloc% and M37I signals and must not dri$e MI73. The master must select only one sla$e at a time.
C0",3 ."0%#+'$ %-) .7%&
A timing diagram showing cloc% polarity and phase
In addition to setting the cloc% fre!uency the master must also configure the cloc% polarity and
phase with respect to the data. 'reescale:s 72I 0loc% 5uide
\)]
names these two options as C23C and
C26A respecti$ely and most $endors ha$e adopted that con$ention.
The timing diagram is shown to the right. The timing is further described below and applies to both
the master and the sla$e de$ice.
At C23CS* the base $alue of the cloc% is (ero
! 'or C26AS* data are captured on the cloc%:s rising edge (low[high
transition) and data are propagated on a falling edge (high[low cloc% transition).
! 'or C26AS) data are captured on the cloc%:s falling edge and data are
propagated on a rising edge.
At C23CS) the base $alue of the cloc% is one (in$ersion of C23CS*)
! 'or C26AS* data are captured on cloc%:s falling edge and data are
propagated on a rising edge.
! 'or C26AS) data are captured on cloc%:s rising edge and data are propagated
on a falling edge.
That is C26AS* means sample on the leading (first) cloc% edge while C26AS) means sample on
the trailing (second) cloc% edge regardless of whether that cloc% edge is rising or falling. Aote that
with C26AS* the data must be stable for a half cycle before the first cloc% cycle. 'or all C23C and
C26A modes the initial cloc% $alue must be stable before the chip select line goes acti$e.
Also note that Bdata is readB in this document more typically means Bdata m! be readB. The M37I
and MI73 signals are usually stable (at their reception points) for the half cycle until the next cloc%
transition. 72I master and sla$e de$ices may well sample data at different points in that half cycle.
UNIT IF 8 BIT MICROCONTROLLER: H/W ARCHITECTURE9 INSTRUCTION
SET AND PROGRAMMING
80?1 ;%!+0$


The ;*>) is 4ust one of the MC7->) family of microcontrollers de$eloped by Intel. The design of
each of the MC7->) microcontrollers are more or less the same. The differences between each
member of the family is the amount of on-chip memory and the number of timers as detailed in
the table below.


M+,#","-'#"00#
O-:,7+. C")
M!"#$
O-:,7+. D%'%
M!"#$
T+!#&
;*>) /H 13M )<; bytes <
;*=) * )<; bytes <
;9>) /H #213M )<; bytes <
;*>< ;H 13M <>. bytes =
;*=< * <>. bytes =
;9>< ;H #213M <>. bytes =

#ach chip also contains"

four ;-bit input,output (I,*) ports
serial interface
./H external code memory space
./H external data memory space
0oolean processor
<)* bit-addressable locations
/us multiply,di$ide



The diagram abo$e shows the ;*>) pinout. The chip is a /*-pin pac%age.


P"#' 0 - pins =< to =L ma%e up the ;-bit I,3 port *. 6owe$er if external memory is used these
lines are used as a multiplexed address and data bus.
P"#' 1 - pins ) to ; ma%e up the ;-bit I,3 port ).

P"#' 2 - pins <) to <; ma%e up the ;-bit I,3 port <. 6owe$er if external memory is used these
lines ma%e up the high-byte of the external address (A; to A)>).

P"#' 3 - pins )* to )9 ma%e up the ;-bit I,3 port =. 6owe$er each of these eight pins also has an
alternate function as detailed in the table below.


P+- N%!
B+'
A))#&&
;/-,'+"-
2=.* 1O+ 0*6 1ecei$e data for serial port
2=.) TO+ 0)6 Transmit data for serial port
2=.<
IAT*-
bar
0<6 #xternal interrupt *
2=.=
IAT)-
bar
0=6 #xternal interrupt )
2=./ T* 0/6
Timer,counter * external
input
2=.> T) 0>6
Timer,counter ) external
input
2=.. -1-bar 0.6
#xternal data memory write
strobe
2=.9 1+-bar 096
#xternal data memory read
strobe


RST - the reset input is on pin L. This pin is used for resetting the ;*>) (ie? loading the 2C with
the correct startup $alue).

EA:8%# - the external access on pin =) is used for enabling or disabling the on-chip 13M. -hen
tied high (>8) the ;*>) executes instructions in internal 13M when executing in the lower /H
(;H for the ;*><) of memory. If tied low the ;*>) will always execute instructions in external
memory. The ;*=) and ;*=< should always ha$e pin =) tied low as there is no internal code
memory.

ALE - the address latch enable is on pin =*. The AC# is used for latching the low byte of the
address into an external register. -e will deal with this at a later date.

PSEN:8%# - the program store enable is an output signal on pin <L. This signal is used for
fetching instructions from external code memory. -e will also deal with this at a later date.


80?1 M!"#$ O#(%-+&%'+"-

I-'#-%0 ROM

The ;*>) has /H (/*L. locations) of on-chip 13M. This is used for storing the system
program. <
)<
S /*L. therefore the internal 13M address bus is )< bits wide and internal 13M
locations go from ***6 to '''6.


I-'#-%0 RAM


There are <>. bytes of internal 1AM on the ;*>). <
;
S <>. therefore the internal 1AM
address bus is ; bits wide and internal 1AM locations go from **6 to ''6.

The first )<; locations (**6 to 9'6) of internal 1AM are used by the programmer for storing
data while the second )<; locations (;*6 to ''6) are the 7pecial 'unction 1egisters (7'1s)
which we will deal with later.

The diagram below is a summary of the ;*>) on-chip 1AM.


R(+&'# B%-3&

There are four register ban%s from **6 to )'6. 3n power-up registers 1* to 19 are located at
**6 to *96. 6owe$er this can be changed so that the register set points to any of the other
three ban%s (if you change to 0an% < for example 1* to 19 is now located at )*6 to )96).

B+':%))#&&%80 L",%'+"-&

The ;*>) contains <)* bit-addressable locations of which )<; are at locations <*6 to <'6
while the rest are in the 7'1s. #ach of the )<; bits from <*6 to <'6 ha$e a uni!ue number
(address) attached to them as shown in the table abo$e. The ;*>) instruction set allows you to
set or reset any single bit in this section of 1AM.
-ith the general purpose 1AM from =*6 to 9'6 and the register ban%s from **6 to )'6 you
may only read or write a full byte (; bits) at these locations.
6owe$er with bit-addressable 1AM (<*6 to <'6) you can read or write any single bit in this
region by using the uni!ue address for that bit. -e will later see that this is a $ery powerful
feature.

S.,+%0 ;/-,'+"- R(+&'#& 1S;R&2

Cocations ;*6 to ''6 contain the special function registers. As you can see from the diagram
abo$e not all locations are used by the ;*>) (ele$en locations are blan%). These extra locations
are used by other family members (;*>< etc.) for the extra features these microcontrollers
possess.

Also note that not all 7'1s are bit-addressable. Those that are ha$e a uni!ue address for each
bit.

-e will deal with each of the 7'1s as we progress through the course but for the moment you
should ta%e note of the accumulator (ACC) at address #*6 and the four port registers at
addresses ;*6 for 2* L*h for 2) A* for 2< and 0* for 2=.
-e will later see how easy this ma%es ready from and writing to any of the four ports.

T7 M+&&+-( R(+&'#&

The two registers not shown in the table abo$e are the instruction register and the program
counter. These two $ery important registers are not placed in 1AM because it is not necessary
to ma%e them directly accessible to the programmer. The instruction register gets its data from
the execution cycle while the program counter is manipulated by the operation of these
instructions.


I-&'#/,'+"- S' S/!!%#$


Instructions tell the processor which operation to carry out. 'or example M38 A X>#6 tells the
processor to mo$e the data >#6 to the accumulator.

Instructions result in the processor performing some operation on some data (the data being X>#6
in the example abo$e). The instruction abo$e is an example of what:s %nown as immedite
ddressin". The reason for this is because the data immediately follows the instruction in code
memory.

6owe$er it is not always ade!uate to store the data in code memory itself. If we needed to read
the information from a %eyboard for example we would need to use something other than
immediate addressing.
There are eight different addressing modes in the ;*>).

O.,") %-) O.#%-)

The first byte of an instruction is %nown as the opcode (operation code) because this is the byte
that is decoded by the processor - from this code the processor can wor% out what operation it
must perform.
'or a one-byte instruction there is only the opcode.

'or a two-byte instruction the second byte is the operand. The operand can be data or an ;-bit
address.

'or a three-byte instruction the second and third bytes ma%e up the operand. A two-byte operand
is usually a ).-bit address as we shall see when we loo% at long addressing.

A))#&&+-( M")&
The eight addressing modes are"

Immediate
1egister
+irect
Indirect
1elati$e
Absolute
Cong
Indexed

I!!)+%' A))#&&+-(
If the operand is a constant then it can be stored in memory immediately after the opcode.
1emember $alues in code memory (13M) do not change once the system has been programmed
and is in use in the e$eryday world. Therefore immediate addressing is only of use when the data
to be read is a constant. 'or example if your program needed to perform some calculations based
on the number of wee%s in the year you could use immediate addressing to load the number ><
(=/6) into a register and then perform arithmetic operations upon this data.
M38 1* X=/

The abo$e instruction is an example of immediate addressing. It mo$es the data =/6 into 1*. The
assembler must be able to tell the difference between an address and a piece of data. The has
symbol (X) is used for this purpose (whene$er the assembler sees X before a number it %nows this
is immediate addressing).
This is a two-byte instruction.


R(+&'# A))#&&+-(

3ften we need to mo$e data from a register into the accumulator so that we can perform
arithmetic operations upon it. 'or example we may wish to mo$e the contents of 1> into the
accumulator.
M38 A 1>

This is an example of register addressing. It mo$es data from 1> (in the currently selected
register ban%) into the accumulator.

A++ A 1.

The abo$e is another example of register addressing. It adds the contents of 1. to the
accumulator storing the result in the accumulator. Aote that in both examples the destination
comes first. This is true of all instructions.


D+#,' A))#&&+-(

+irect addressing is used for accessing data in the on-chip 1AM. 7ince there are <>. bytes of
1AM ()<; bytes general storage for the programmer and another )<; bytes for the 7'1s). That
means the addresses go from **6 to ''6 any of which can be stored in an ;-bit location.
M38 A .9

The abo$e instruction mo$es the data in location .96 into the accumulator. Aote the difference
between this and immediate addressing. Immediate addressing uses the data which is
immediately after the instruction. -ith direct addressing the operand is an address. The data to
be operated upon is stored in that address. The assembler realises this is an address and not data
because there is no hash symbol before it.
A++ A *.

The abo$e instruction adds the contents of location *.6 to the accumulator and stores the result
in the accumulator. If the selected register ban% is ban% * then this instruction is the same as A++
A 1..


I-)+#,' A))#&&+-(
1egister addressing and direct addressing both restrict the programmer to manipulation of data in
fixed addresses. The address the instruction reads from (M38 A =*6) or writes to (M38 =*6
A) cannot be altered while the program is running.

There are times when it is necessary to read and write to a number of contiguous memory
locations. 'or example if you had an array of ;-bit numbers stored in memory starting at address
=*6 you may wish to examine the contents of each number in the array (perhaps to find the
smallest number). To do so you would need to read location =*6 then =)6 then =<6 and so on.

This can be achie$ed using indirect addressing. 1* and 1) may be used as pointer registers. -e
can use either one to store the current memory location and then use the indirect addressing
instruction shown below.
M38 A ^1i
where Ri is either 1* or 1).
Aow we can read the contents of location =*6 through indirect addressing"
M38 1* X=*6
M38 A ^1*

The first instruction is an example of immediate addressing whereby the data =*6 is placed in
1*. The second instruction is indirect addressing. It mo$es the contents of location =*6 into the
accumulator.
If we now wish to get the data in location =)6 we use the following"

IAC 1*
M38 A ^1*

3nce we see how to write a loop in assembly language we will be able to read the entire contents
of the array.


R0%'+* A))#&&+-(

1elati$e addressing is used only with certain 4ump instructions. The system executes a 4ump by
changing the contents of the 2C to the address of the next instruction to be executed. 'or
example if we wished to 4ump to the instruction stored at location /#6 in code memory the 2C
would be loaded with /#6. Then during the next execution cycle the contents of the 2C (/#6)
are placed on the address bus and the instruction at /#6 is retrie$ed.

A relati$e address (or offset) is an ;-bit signed $alue which is added to the 2C to form the
address of the next instruction to be executed.

-ith ;-bit signed numbers the M70 is used to determine whether the number is positi$e or
negati$e. If the M70 is * then the number is positi$e while if the M70 is ) the number is
negati$e.
The instruction below shows how to 4ump six locations ahead.
7WM2 *.6
SJ$%P is an unconditional 4ump and is a <-byte instruction. The number following it is an offset
address. If this instruction were stored in code memory at locations )**6 and )*)6 as shown
below"

&''( 80H
&'&( 06H

The opcode for SJ%P is ;*6. The operand is the offset address. If this instruction were executed
the 2C would get the $alue )*;6. This is what happens"

The 2C contains )**6 therefore the instruction ;*6 is read into the I1.
The instruction is decoded as the <-byte 7WM2 instruction.
The 2C is incremented so that the operand may be retrie$ed.
The operand is read from code memory and the 2C is incremented again (because this is a
<-bye instruction).
The operand (*.6) is added to the 2C ()*<6 N *.6 S )*;6).
The next instruction (at )*;6) is executed.

3nce we deal with <:s compliment and how negati$e numbers are dealt with in the C2& we will
loo% at a bac%ward 4ump.

The S in SJ%P stands for s)ort. The range of signed ;-bit numbers is -)<9 to )<;. (Clic% here to
see how signed numbers are stored in a microcontroller.) Therefore using 7WM2 allows us to
4ump )<9 locations forward or )<; locations bac%ward. 6ence the name short 4ump.

-hen writing assembly programs we do not need to calculate the offset when using 7WM2.
Instead we use labels. If we wished to 4ump to the instruction at )*;6 we would simply label the
instruction with an appropriate name for example *(ERE. -e would then write the assembly
code SJ%P *(ERE. The assembler does the wor% of replacing the label with the correct offset.


A8&"0/' A))#&&+-(
Absolute addressing is only used with the ACACC and AWM2 instructions.
ACACC - subroutine call (< byte instruction)
AWM2 - unconditional 4ump (< byte instruction)
These instructions allow you to mo$e to any instruction within the same <H of memory.

-e will loo% at the AWM2 instruction only (at a later date when we begin dealing with
subroutines we will deal with the ACACC instruction).

The operation of the AWM2 instruction is detailed below"

AWM2 address
(2C) T- (2C) N <
(2C
)*
-2C
*
) T- address
)*
- address
*


Aote that only the ele$en least significant bits of the 2C are altered. The fi$e most significant bits
remain the same. This means the AWM2 will only allow you to 4ump to a location in the same <H
page as the instruction directly after the 4ump.

'or example"

If the label T6#1# represents an instruction at address *'/.6 and the instruction AJ%P *(ERE
is in memory at locations *L**6 and *L*)6 the assembler will encode the instruction as
)))****) &st b!te +A&' , A- . opcode/
*)***))* 0nd b!te +A1 , A'/

The underlined bits are the low-order )) bits of the destination address *'/.6 S
****))))*)***))*0. The upper fi$e bits in the program counter will not change when this
instruction executes. Aote that both the AWM2 instruction and the destination are within the <H
page bounded by *;**6 and *'''6 and therefore ha$e the upper fi$e address bits in common.



N"': +' +& -"' +!."#'%-' '" #!!8# '7 )+44#-' 3+-)& "4 %))#&&+-( !")& %-) 67+,7
+-&'#/,'+"-& 80"-( '" 67+,7 !")< I' +& 4%# !"# +!."#'%-' '" /-)#&'%-) 7"6 '" (' )%'%
4#"! "- .0%, '" %-"'7# %-) 7"6 '" .#4"#! ".#%'+"-& /."- '7 )%'%< B"/ 6+00 -*# 8
%&3) '" !!"#+& % .#",&&"#G& +-&'#/,'+"- &'< T7+& 6+00 %06%$& 8 .#"*+))< H"6*#9 %&
6 &7%00 & 67- 6 &'%#' 6#+'+-( .#"(#%!&9 +' +& +!."#'%-' '" 8 %80 '" /& '7 +-&'#/,'+"-
&'<

M"&' "4 "/# %#0$ .#"(#%!& 6+00 )%0 6+'7 !"*+-( )%'% +-'" %-) "/' "4 '7 %,,/!/0%'"#9
.#4"#!+-( %#+'7!'+, ".#%'+"-& %-) H/!.+-( '" )+44#-' .%#'& "4 '7 .#"(#%!<

T7 S.,+%0 ;/-,'+"- R(+&'#& 1S;R&2


The 7'1s are in locations ;*6 to ''6 of the on-chip 1AM. In the ;*>) not all locations are used.
These extra locations are used by other family members (;*>< etc.) for the extra features these
microcontrollers possess.


As you can see some of the 7'1s are bit addressable including the four ports 2* 2) 2< and 2=.

P#"(#%! S'%'/& W"#) 1PSW2

The 27- is at location +*6 and is bit addressable. The table below describes the function of each
bit.


B+' S$!8"0 A))#&& D&,#+.'+"-
27-.9 CR +96 Carry flag
27-.. AC +.6 Auxiliary carry flag
27-.> '* +>6 'lag *
27-./ 17) +/6 1egister ban% select )
27-.= 17* +=6 1egister ban% select *
27-.< 38 +<6 3$erflow flag
27-.) -- +)6 1eser$ed
27-.* 2 +*6 #$en parity flag


C%##$ ;0%(
The carry flag has two functions.

'irstly it is used as the carry-out in ;-bit addition,subtraction. 'or example if the
accumulator contains '+6 and we add = to the contents of the accumulator (A++ A X=) the
accumulator will then contain (ero and the carry flag will be set. It is also set if a subtraction
causes a borrow into bit 9. In other words if a number is subtracted from another number smaller
than it the carry flag will be set. 'or example if A contains =+6 and 1= contains /06 the
instruction 7&00 A 1= will result in the carry bit being set (/06 is greater than =+6).
The carry flag is also used during 0oolean operations. 'or example we could AA+ the
contents of bit =+6 with the carry flag the result being placed in the carry flag - AAC C =+6

R(+&'# B%-3 S0,' B+'&

0its = and / of the 27- are used for selecting the register ban%. 7ince there are four register ban%s
two bits are re!uired for selecting a ban% as detailed below.

27-./ 27-.=
1egister
0an%
Address
of
1egister
0an%
* * *
**6 to
*96
* ) )
*;6 to
*'6
) * <
)*6 to
)96
) ) = );6 to
)'6

'or example if we wished to acti$ate register ban% = we would use the following instructions -

7#T017)
7#T0 17*


If we then mo$ed the contents of 1/ to the accumulator (M38 A 1/) we would be mo$ing the
data from location )C6 to A.


;0%( 0
'lag * is a general-purpose flag a$ailable to the programmer.


P%#+'$ B+'

The parity bit is automatically set or cleared e$ery machine cycle to ensure e$en parity with the
accumulator. The number of )-bits in the accumulator plus the parity bit is always e$en. In other
words if the number of )s in the accumulator is odd then the parity bit is set to ma%e the o$erall
number of bits e$en. If the number of )s in the accumulator is e$en then the parity bit is cleared to
ma%e the o$erall number of bits e$en.

'or example if the accumulator holds the number *>6 this is **** *)*) in binary SU the
accumulator has an e$en number of )s therefore the parity bit is cleared. If the accumulator holds
the number '<6 this is )))) **)* SU the accumulator has an odd number of )s therefore the
parity bit is set to ma%e the o$erall number of )s e$en.

As we shall see later in the course the parity bit is most often used for detecting errors in
transmitted data.


B R(+&'#
The 0 register is used together with the accumulator for multiply and di$ide operations.
The M&C A0 instruction multiplies the $alues in A and 0 and stores the low-byte of the
result in A and the high-byte in 0.
! 'or example if the accumulator contains '>6 and the 0 register contains *<6 the
result of M&C A0 will be A S #A6 and 0 S *)6.
The +I8 A0 instruction di$ides A by 0 lea$ing the integer result in A and the remainder
by 0.
! 'or example if the accumulator contains *96 and the 0 register contains *<6 the
result of +I8 A0 will be A S *=6 and 0 S *)6.
The 0 register is also bit-addressable.


S'%,3 P"+-'#

The stac% pointer (72) is an ;-bit register at location ;)6. A stac% is used for temporarily storing
data. It operates on the basis of last in first out (CI'3). 2utting data onto the stac% is called
Bpushing onto the stac%B while ta%ing data off the stac% is called Bpopping the stac%.B

The stac% pointer contains the address of the item currently on top of the stac%. 3n power-up or
reset the 72 is set to *96. -hen pushing data onto the stac% the 72 is first increased by one and
the data is then placed in the location pointed to by the 72. -hen popping the stac% the data is
ta%en off the stac% and the 72 is then decreased by one.

7ince reset initialises the 72 to *96 the first item pushed onto the stac% is stored at *;6
(remember the 72 is incremented first then the item is placed on the stac%). 6owe$er if the
programmer wishes to use the register ban%s ) to = which start at address *;6 he,she must mo$e
the stac% to another part of memory. The general purpose 1AM starting at address =*6 is a good
spot to place the stac%. To do so we need to change the contents of the 72.
M38 72 X<'6.
Aow the first item to be pushed onto the stac% will be stored at =*6.

A0.7%8'+,%0 L+&' "4 I-&'#/,'+"-&
ACALL " Absolute Call
ADD9 ADDC " Add Accumulator (-ith Carry)
AJMP " Absolute Wump
ANL " 0itwise AA+
CJNE " Compare and Wump if Aot #!ual
CLR " Clear 1egister
CPL " Complement 1egister
DA " +ecimal Ad4ust
DEC " +ecrement 1egister
DIF " +i$ide Accumulator by 0
DJNZ " +ecrement 1egister and Wump if Aot _ero
INC " Increment 1egister
JB " Wump if 0it 7et
JBC " Wump if 0it 7et and Clear 0it
JC " Wump if Carry 7et
JMP " Wump to Address
JNB " Wump if 0it Aot 7et
JNC " Wump if Carry Aot 7et
JNZ " Wump if Accumulator Aot _ero
JZ " Wump if Accumulator _ero
LCALL " Cong Call
LJMP " Cong Wump
MOF " Mo$e Memory
MOFC " Mo$e Code Memory
MOF> " Mo$e #xtended Memory
MUL " Multiply Accumulator by 0
NOP " Ao 3peration
ORL " 0itwise 31
POP " 2op 8alue 'rom 7tac%
PUSH " 2ush 8alue 3nto 7tac%
RET " 1eturn 'rom 7ubroutine
RETI " 1eturn 'rom Interrupt
RL " 1otate Accumulator Ceft
RLC " 1otate Accumulator Ceft Through Carry
RR " 1otate Accumulator 1ight
RRC " 1otate Accumulator 1ight Through Carry
SETB " 7et 0it
SJMP " 7hort Wump
SUBB " 7ubtract 'rom Accumulator -ith 0orrow
SWAP " 7wap Accumulator Aibbles
>CH " #xchange 0ytes
>CHD " #xchange +igits
>RL " 0itwise #xclusi$e 31
U-)4+-) " &ndefined Instruction
UNIT F
SBSTEM DESIGN USING MICRO PROCESSOR I
MICROCONTROLLER
TRA;;IC LIGHT CONTROL
The traffic light control using ;*>) is represented in the following circuit diagram.
P#"(#%!
INCLUDE REGJ?2<PD;
NR EKU P3<?
NB EKU P3<4
NG EKU P3<3
SR EKU P1<2
SB EKU P1<3