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LESSON PLAN
Name: G.Sathya
Designation/Dept: Lecturer/ECE
Sub. Code: CS2202
Faculty Code: ECE13
Sub. Name: Digital Principles and System Design Sem /Year: III/II CSE A
S.No
Week
Date
Period
Topics to be covered
No
UNIT I BOOLEAN ALGEBRA AND LOGIC GATES
1.
20.07.09
1, 5
Introduction
2.
21.07.09
3, 6
3.
22.07.09
4.
5.
23.07.09
Binary arithmetic
6.
24.07.09
Binary codes
7.
27.07.09
1, 5
8.
28.07.09
3, 6
29.07.09
Boolean functions
10.
30.07.09
11.
31.07.09
Simplifications of Boolean
functions using Karnaugh
map
Tabulation methods
12.
03.08.09
1, 5
04.08.09
3, 6
Logic gates
05.08.09
Logic gates
9.
2
13.
14.
UNIT II
15.
16.
17.
18.
19.
20.
19
21.
20
22.
21
23.
22
COMBINATIONAL LOGIC
06.08.09
Introduction- Combinational
circuits
Combinational circuits
07.08.09
10.08.09
1, 5
Combinational circuits
11.08.09
3, 6
12.08.09
17.08.09
18.08.09
Code conversion
20.08.09
1, 5
Code conversion
21.08.09
3, 6
Code conversion
Remarks
24.
23
Introduction to Hardware
Description Language
(HDL)
25.
24
26.
5
22.08.09
24.08.09
27.
25.08.09
Introduction to Hardware
Description Language
(HDL)
Problems
27.08.09
Problems
29.
28.09.09
3, 6
Problems
30.
29.08.09
Problems
28.
S.No
31.
27
32.
29
33.
30
34.
31
35.
32
36.
33
37.
Week
Date
No
UNIT III
Period
Topics to be covered
DESIGN WITH MSI DEVICES
31.08.09
Decoders
01.09.09
Encoder
03.09.09
1, 5
7
3
04.09.09
Multiplexers
Demultiplexers
Demultiplexers
05.09.09
07.09.09
38.
08.09.09
40.
10.09.09
1, 5
41.
11.09.09
3, 6
42.
12.09.09
43.
14.09.09
Problems
15.09.09
Problems
44.
UNIT IV
45.
47.
49.
17.09.09
1, 5
Sequential circuits
18.09.09
3, 6
Flip flops
19.09.09
Remarks
50.
22.09.09
State reduction
51.
23.09.09
State reduction
25.09.09
State assignment
53.
26.09.09
3, 6
State assignment
54.
29.09.09
30.09.09
Shift registers
56.
01.10.09
Shift registers
57.
06.10.09
1, 5
Counters
07.10.09
3, 6
Counters
08.10.09
Counters
60.
09.10.09
62.
10.10.09
Date
Period
52.
55.
59.
S.No
10
11
12
Week
No
UNIT V
63.
13.10.09
1, 5
64.
14.10.09
65.
Topics to be covered
13
66.
15.10.09
67.
16.10.09
68.
20.10.09
Design of asynchronous
sequential circuits
Design of asynchronous
sequential circuits
Reduction of state and flow tables
69.
22.10.09
1, 5
23.10.09
70.
14
72.
24.10.09
3
6
3
73.
26.10.09
27.10.09
Hazards.
28.10.09
Hazards.
74.
75.
15
Remarks
76.
29.10.09
3, 6
ASM chart
77.
31.10.09
ASM chart
TEXT BOOKS
1. M.Morris Mano, Digital Design, 3rd edition, Pearson Education, 2002.
REFERENCES
1. Charles H.Roth, Jr. Fundamentals of Logic Design, 4 th Edition, Jaico Publishing House,
2000.
2. Donald D.Givone, Digital Principles and Design, Tata McGraw-Hill, 2003.
Assignment
No.
Topics
Date of
Submission
Problems
11.08.09
Problems
15.09.09
29.09.08
13.10.09
23.10.09
Signature of Faculty
Signature of HOD