Hardware / Software Optimizations for

Efficient Embedded Digital Signal Processing

in Wireless Body Sensor Nodes
ObeSense
RTD 2013
Rubn Braojos, Giovanni Ansaloni, David Atienza
Embedded Systems Laboratory, EPFL
Overhead 3L-MF 3LMMD RPCLASS
Code size 2,6 % 0,9 % 0,7 %
Run-time 1,7 % 1,0 % 0,6 %
Lxper|menta| kesu|ts
3L-MF
SC MC
0
25
50
75
100 3L-MMD RP-CLASS
P
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(

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Clock Tree
D-Crossbar
I-Crossbar
Cores & logic
Data Mem.
Prog. Mem.
SC MC SC MC
Mulu-core W8Sn are more energy emclenL Lhan slngle-core
equlvalenLs lf Lhey are proper|y synchron|zed
!up Lo 40 |ess power consumpnon (3L-Ml)
!Very |ow overhead (< 3) due Lo synchronlzauon
Synchronlzauon + 8roadcasnng = Memory energy emclency
! 40 |ess accesses Lo lM and 3.7 |ess accesses Lo uM
SlMu + Workload dlvlslon ! Lower clock consLralnL ! VIS
! 1S keducnon of System V
DD

W|re|ess 8ody Sensor Nodes (W8SNs) |n nea|thcare
Input
Bio-signals
Output
Diagnosis
luslon Analysls lllLer
Consecutive phases! Parallelism?
Multiple inputs
! Parallelism?
W8SNs are mlnlaLurlzed devlces able Lo
acqulre, process and LransmlL blo-slgnals (LCC,
LMC, blood pressure movemenLs.)
" Wearable, unobLruslve, lnexpenslve
# LlmlLed resources and auLonomy
Cn-board ulglLal Slgnal rocesslng (uS) ls
employed Lo lmprove energy emclency.
Can a|gor|thm|c para||e||sm be exp|o|ted?
New 1rend: Mu|n-core W8SN for Lmc|ent DS
Multi-core WBSN
lnsL.
memory
(lM)
uaLa
memory
(uM)
Core Core
Core Core
Core Core
erlpherals
Application partition
Parallelism
P
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Workload ls dlvlded lnLo subLasks by
plpellnlng phases and performlng
SlMu execuuon over several blo-slgnals
! Lach subLask ls execuLed ln a core
! Vo|tage frequency sca||ng (VIS)
Challenges
uaLa-dependenL branches (SlMu)
uaLa and conLrol ow among phases
Lack of emclenL mechanlsm for
8e-synchronlzauon Lo maxlmlze SlMu
roducer-consumer noucauon
8LlL8LnCLS:

[1] uogan, eL al., Low- power processor archlLecLure explorauon for onllne blomedlcal slgnal analysls," lL1-CuS 2012.
[2] 8ahlml, eL al. A fully-synLheslzable slngle-cycle lnLerconnecuon neLwork for Shared-L1 processor clusLers" uA1L'11
[3] ?. Sun eL al., LCC slgnal condluonlng by morphologlcal lLerlng," CompuLers ln 8lology and Medlclne, 2002.
[4] l. 8lncon eL al., uevelopmenL and evaluauon of mululead waveleL-based LCC dellneauon algorlLhms for embedded
wlreless sensor nodes," lnformauon 1ech. ln 8lomedlclne, 2011.
[3] 8rao[os eL al., A meLhodology for embedded classlcauon of hearLbeaLs uslng random pro[ecuons," ln uA1L'13

Conc|us|ons
1wo consldered sysLems:
Synchronlzed mulu-core
W8Sn (MC)
LqulvalenL slngle-core
W8Sn (SC)
Lvaluauon lramework
81L lmplemenLauon
SysLemC cycle-accuraLe
slmulaLor
CusLom compllauon
Lool-chaln
ower model derlved from
posL-layouL slmulauons
roposed So|unon: L|ghtwe|gth nW ] SW Mechan|sm for Code Synchron|zanon
Cores
l
n
1
L
8
C
C
n
n
L
C
1

l
n
1
L
8
C
C
n
n
L
C
1

#0
#1
#2
#3
#4
#n

IM DM
rlvaLe #0
rlvaLe #1
rlvaLe #2
rlvaLe #3
rlvaLe #4
Shared

Synchron|zer
SLeps Lo adapL exlsung blo-
medlcal appllcauons

1. arnnon|ng: ldenufy
algorlLhmlc phases (producer-
consumer) and poLenual
parallel compuLauons (SlMu)
2. Instrucnon |nsernon:
lmplemenL re-synchronlzauon
and producer-consumer
relauons wlLh Lhe speclc lSL
3. Code mapp|ng: Cores
performlng SlMu share Lhe
shame lM bank
Synchronizer unit:
Stalls and wakes-up cores to
orchestrate execution
Guaranties re-synchronization
Synchronization points:
Store run-time information for each
synchronization event
Reserved space in shared memory
Instruction Set Extension (ISE):
SLEEP, SINC, SDEC and SNOP
Mark synchronization events and
modify synchronization points
Mulu-core W8Sn (based on [1])
8lSC ulLra-low power
processors
Mu|n-banked lM and uM +
shared and pr|vate uM
! Mlnlmlze memory conlcLs
LogarlLhmlc comblnauonal
lnLerconnecL [3] wlLh
arblLrauon capablllues
8roadcasnng: SlmulLaneous
requesL of Lhe same address
are merged lnLo a slngle
memory access
! Memory energy emclency
lLerlng
lLerlng
lLerlng
lL.
lL.
lL.
Comblnauon uellneauon
lL.
lL.
lL.
Comblnauon uellneauon
classlcauon
Mu|n-|ead LCG h|ter|ng (3L-MI) [3]
8emove unwanLed arufacLs (persplrauon,
muscular acuvlLy,.) from muluple LCC slgnals
Mu|n-|ead LCG de||neanon (3L-MMD) [4]
Comblnes muluple lLered slgnals and nds
onseL, peak and end of Lhe maln LCC waves
neart-beat c|ass|her (k-CLASS) [S]
erforms mulu-lead dellneauon only ln
Lhe presence of abnormallues
8enchmarks: Lmbedded L|ectrocard|ogram (LCG) App||canons for W8SNs
Only
SIMD execution
SIMD execution +
Producer-consumer
SIMD execution + Producer-
consumer + complex control
activation