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Class: 11ES

Group 1:
L Vn V An
Trn Phc T Tm
Nguyn Mnh T


1. Introduction
In this report, we will handle the first part of the Lab as required. It is
Part 1: Modeling, Simulating, and Testing a Digital Comparator. To
begin with, we show the Verilog codes for implementation. Then based
on the screenshots of simulation, we answer the questions to complete
part 1 of the lab.



2. Implementation
Verilog Code of the circuit:






Answer the questions:
1. Draw a logic diagram using the logic gates that were used to
build the digital circuit in the Verilog source code.


In the diagram, basically, we used a three inputs AND gate, four two
inputs AND gates and a five inputs OR gate.


2. Draw a truth table for the circuit.



3. When you run the simulation, does the output of the Verilog
program agree or disagree with your truth table?
Answer: It does not. At first, the Verilog code indicates that there
is a delay time of the gates (delay=10 time units) and a delay time
for input signals changing (stimDelay=15 time units), which
makes the result different from the values of our truth table. To
illustrate more about this, we will explain later in the answer of
question 4.

4. Please explain the apparently incorrect order in which the
results in the output log are printed; specifically when the
output line Producing Glitch prints.



Answer: Since the time delay for each gate is 10, it takes 30 time
units (30 ps in simulation) for input signals to go through NOT,
AND, OR gates and produce values for the output. At the time
30ps, the input signal changes (from 0000 to 0001) and output
receives the value of 1. We can see the issue is that the output
value should be 0 (for input signal 0001) instead of 1. The reason
is that the output still gets the old value of input signal (0000) and
it has to wait for another 30ps to get a new value.



As we can see, the value of output should be 1 corresponding to
the input signal 1010. However, the output unexpectedly has a
value 0 at time 515ps and the value changes back to 1 at time
525, which produces glitch. That means in general, the output
still receives the correct value related to certain input signal, but
in a very short time, it changes to another value (from 1 to 0 or 0
to 1) and go back to original one, which affects little the result.

5. Change the value of the delay in the program from 10 to 0.
Rerun the simulation. Does the output of the Verilog program
agree or disagree with your truth table? Please explain any
differences.

Answer: The simulation shows correct values and matches the
result of our truth table. Again, at the time 30ps when the input
signal changes from 0000 to 0001, the output accordingly
receives value 0. The reason is that as there is no delay time for
the gates, the output can get the value right after the input signal
changes.


6. Change the delay in the program back to 10 time units.
Change the stimDelay in the test module to 5 time units. What
affect does this change have on the outputs of your simulation?


Answer: In this way, the overall result is different from the one of
our truth table, though there are some accidentally correct values
(for example, at time 30ps, input signal is 0101 and output value
is 1. However, the value 1 is produced from input 0000, not
0101). The cause of the difference is similar to the reason in
question 4 as the input signal changes so fast that the output
cannot keep up.
7. What advantages are there to using a program like Verilog?
Name three or more.
Verilog allows programmers to implement circuits in many ways
such as: behavioral, RTL or structural.
Verilog has the ability to express concurrency, which is very hard
for programmers to implement in other language like C or C++.
Compared with other HDL, Verilog simulates faster because the
simulator does not provide a lot of runtime checks. Only wires
and ports are resolved.