System-level design of mixed-signal ASICs using Simulink:

Efficient transitions to EDA environments

This work presents an approach for automated transitions from analog and digital parts
of Simulink models representing mixed-signal ASICs to mixed-signal design
environments.
Andreas Mauderer, Jan-Hendrik Oetjens (Robert Bosch GmbH) and Wolfgang
Rosenstiel (University of Tuebingen)
(May 30, 2012)
Abstract
Simulink models are used as executable specifications in commonly used design flows
for mixed-signal ASICs. Based on these specifications, analog and digital components
are directly implemented in mixed-signal design environments. This step constitutes a
large leap of abstraction. In this work, we address this aspect by showing and
discussing an approach for automated transitions from Simulink models representing
analog and digital components to HDL descriptions using HDL Coder. On the one hand,
we translate analog Simulink components into continuous-value discrete-time HDL
descriptions that can serve as reference behavioral models in the mixed-signal design
environment. On the other hand, for digital Simulink components, we developed
optimizations for Simulink models in order to achieve resource-efficient HDL
descriptions. Both solutions in the analog and digital domain were integrated into
Simulink Model Advisor. An evaluation of the presented design flow, as applied to an
automotive hardware design, is shown.

Introduction
Electronic Control Units (ECUs) in the field of automotive electronics generally interact
with the physical environment by using sensors and actuators. Thereby, mixed-signal
ASICs (Application Specific Integrated Circuits) are needed as an interface between
microcontrollers and sensors as well as actuators. In this work, we focus on ASICs
connected to sensors, whereby the sensor is often enclosed with the ASIC into a
system-in-package (SiP). In the most general case, mixed-signal ASICs consist of
analog, non-programmable digital and programmable digital components.
The increasing integration density of ASICs allows more and more functionality, which
leads to more complex ASIC designs. These require a holistic view on a high
abstraction level at the beginning of the design. Therefore, a system-level (SL) design
methodology is needed, where all ASIC components and the associated sensor are
modeled in a common SL design environment.
In standard flows, the design starts by developing an SL model that serves as
executable functional specification. Based on this specification, the particular ASIC
components are designed on implementation level (IL) isolated from the overall system
and without any reuse of the design effort performed at SL. The isolation between SL
and IL constitutes a gap in the design flow, which leads to redundant implementation
efforts and consistency problems between SL and IL.
Furthermore, the isolation of components from the overall system during implementation
leads to lost optimization potential. That is why in [1], we proposed a seamless SL
design methodology, which uses automated transitions from SL to IL models in order to
reduce the effort of design transfer between SL and IL (see Figure 1).


Figure 1: SL design methodology using automated transitions
Assisted refinement of SL model components with respect to the surrounding system
and automated top-down transitions from SL to IL are suggested in order to transfer
design effort from SL to IL. SL and IL are defined as follows: At SL, the whole ASIC and
its connected sensor is considered in a common design environment, whereby the ASIC
SL model consists of analog, digital and software partitions.
Then again, there are IL models, which describe a system component of a single
domain in its domain-specific language and design environment. IL models are later
refined down to a physical implementation either in a manual or an automated design
flow that depends on the particular domain. After we provided approaches for top-down
transitions from MATLAB/Simulink both in the digital and the analog domain (see [2]
and [3], in this article, we present the combination of both approaches and their
application to an automotive mixed-signal hardware design.

System-level design environment: Simulink
For heterogeneous systems, SL design environments have to support the description of
system components from different domains. We use MATLAB/Simulink (see [4] as SL
design environment, which constitutes a de facto standard for signal processing design
in automotive applications.
Simulink is a graphical multi-domain design environment and supports multiple models
of computation like continuous-time, discrete-time and electrical modeling. Thereby,
Simulink models can include blocks from the Simulink library as well as blocks
described in different languages like MATLAB, Stateflow and Simscape, and
programming languages like C and C++.
Simulink library blocks allow the description of analog circuits both as continuous-time
and discrete-time signal-flow models. Simscape offers the possibility to model systems
as physical networks. It can be used for the modeling and simulation of electrical
systems whereby these systems obey Kirchhoff's laws. With Simscape, Simulink is also
suited for the description of analog components and sensors as electrical and
mechanical systems.
Transitions in the digital domain
The current design-flow of digital automotive ASIC parts commonly starts on register-
transfer level (RTL) using VHDL or Verilog (henceforth referred to as HDL descriptions).
Therefore, we define these models as IL models in the digital domain. For transitions
between Simulink models and these HDL descriptions, there are two different kinds of
solutions, which are depicted in Figure 2.



Figure 2: Transitions in the digital domain.
One kind of solutions are high-level synthesis (HLS) transitions (see arrow 1 in Figure
2), which refine a behavioral description of an SL model into a cycle-accurate
description of an IL model by performing scheduling, allocation and binding. The other
kind of solutions are mapping transitions (see arrow 2 in Figure 2), which transform an
SL model that is already refined down to an RTL description into an IL model without
performing any refinement. We focus on mapping transitions, because high-level
synthesis transitions make it difficult to formally verify resulting HDL descriptions (see
[2].
A mapping transition from Simulink models described on RTL to HDL is realized by
MathWorks HDL Coder. HDL Coder is compatible with Simulink models containing a
subset of the standard Simulink blockset, Stateflow models and MATLAB Code.
Additionally, HDL Coder offers the possibility to explore the trade-off between area and
timing. Therefore, different implementations for Simulink blocks are provided on the one
hand. On the other hand, HDL Coder can modify the SL model by applying distributed
pipelining, streaming and resource sharing to subsystems.

Optimizations
We want to assist the developer in developing Simulink designs that result in efficient
HDL designs. Therefore, we developed two optimization approaches. They were
derived from our experience in developing Simulink SL models representing datapath-
oriented applications. These optimizations showed a significant improvement of our SL
design flow.

Timing optimization
Signals in digital signal processing designs are often processed at different sample
rates: While for example analog signals are sampled at a very high rate for the
improvement of the signal-to-noise ratio, the internal computation at lower rates reduces
the computational effort in the design. Transitions between different sample rates are
realized by decimation and interpolation of signals. Such systems containing multiple
sample rates are called multirate systems.
Simulink is capable of modeling multirate systems. Decimation or interpolation of
signals can be achieved for example by using rate transition blocks or counters and
switches. While developers often model decimation and interpolation of signals correctly
based on their signal processing knowledge, it might occur that sample rates of blocks
are higher than the sample rates of the connected signals. Because HDL Coder
translates Simulink sample rates directly into clock rates, this results in unnecessarily
high clock rates in the HDL description.
For avoiding too high clock rates, we developed Timing Optimization, which checks a
Simulink model for blocks whose connected signals change at a lower rate than the
blocks' sample rates. When the sample rate of blocks is adjusted to the alteration rate of
the connected signals, then HDL Coder runs the resulting HDL components at a
corresponding lower clock rate. This results in relaxed timing constraints for logic
synthesis and reduced power consumption.
Furthermore, if a block such as a derivation block contains delay blocks and its sample
rate can be reduced by a certain factor, then the number of delays can be decreased by
the same factor. This leads to fewer registers in the HDL description. The alteration rate
of signals is determined by simulation. After changing the sample rates, an automated
verification is executed by simulating the model and comparing the systems outputs.
This is necessary since some combinations of blocks might lead to a different behavior
when their sample rate is reduced.
Figure 3 shows an example of a system of two Simulink blocks. The value R is the rate
at which a signal changes, which is also depicted in the signal sequences next to the
signals. S represents the sample rate of a block that results in the used clock rate in the
HDL description. The decimation block reduces the incoming signal rate by a factor of 2.
The processing block then receives a signal with a change rate of 5 kHz and outputs a
signal with the same rate, yet this block is executed with a sample rate of 10 kHz.
Therefore, the processing block's sample rate can be reduced by a factor of 2.


Figure 3: Timing Optimization
This optimization identifies characteristics of Simulink models which lead to inefficient
HDL descriptions and improves these characteristics. The optimization depends on
signals' sample rates occurring during simulation. Thus it is crucial that the testbench
stimuli of the SL model are sufficient for covering all possible scenarios that are
specified. Furthermore, this optimization enables the quick assembling of an SL model
using existing Simulink subsystems and the adaption of the subsystem to the alteration
rates of the incoming signals.

Word-length optimization
At the beginning of a common system-level design flow, Simulink models representing
digital hardware often use floating-point signals. For a resulting efficient hardware
implementation, a fixed-point representation of the design is needed, which supports the
needed value ranges and precisions for every signal.
MathWorks Fixed-Point Tool part of Simulink Fixed Point assists the developer in
the adaption of signals integer bits to the used value ranges. We extend this
functionality by providing an optimization that reduces the fractional bits of signals.
Since the modification of fractional bits of signals influences their precision, we consider
the impact on the output behavior of the overall system. This also allows the
identification and reduction of blocks that have little or no impact on the system's
behavior. We are looking for the most efficient hardware implementation that doesnt
change the systems behavior.
For this purpose, we use the stochastic optimization method Simulated Annealing. We
explore the solution space by increasing and decreasing the integer and fractional bits
of randomly chosen blocks. The resulting solution specifies word-lengths for every block
while the resource consumption should be minimal and no deviation of the system's
output signals is allowed.
In Figure 4 the Simulated Annealing algorithm for our specific problem is shown: We
start with an initial SL model that contains signal values that lead to the desired signal
processing behavior. This behavior will be used in further optimization as reference
behavior. In the following, the model is rated by estimating the resulting hardware
resource consumption of the digital component. After that, it will be decided if the
solution will be accepted. Better solutions are always accepted, and depending on the
current temperature, worse solutions are accepted with a specific probability.
This prevents the algorithm from getting stuck in local optima. Furthermore, it is
checked if the model violates the allowed signal deviation. If the model is not accepted,
then a new model is created by modifying the fixed-point type of randomly chosen
blocks. If the model is accepted, the current model is replaced. After that, depending on
the number of iterations, the temperature is reduced. If no new model was accepted for
a defined number of iterations, the algorithm is stopped. Otherwise, a new model is
created and the loop starts again.



Figure 4: Simulated Annealing flowchart
The exploration at SL in the Simulink environment has the advantage that the impact of
the digital part's change of functionality on the overall system is directly visible. As with
Timing Optimization, the outcome of this optimization strongly depends on the SL
testbench stimuli.

Transitions in the analog domain
In general, the design of analog circuits takes place in analog design environments
(ADEs). In top-down analog design methodologies as proposed in [5], it is suggested to
create behavioral models of analog components in HDL languages prior to circuit-level
implementation. These behavioral models serve as reference for the latter device-level
implementation. Yet, analog circuits are often still developed directly on device-level
without using an HDL description as a starting point. A reason for this is often that the
description in these text-based languages is very different compared to the common
graphical description in analog design on device level.
An automated transition between Simulink SL models describing analog components
and HDL descriptions can offer an easy way to create HDL behavioral models and
would close the gap between the Simulink design environment and ADEs. As both
Simulink and also the HDL-AMS languages VHDL-AMS and Verilog-AMS support
several models of computation (discrete-time and continuous-time signal flow as well as
electrical), there are several possibilities for transitions from Simulink to ADEs (see
Figure 5): One possibility is the mapping transition from Simulink and Simscape models
maintaining the MoC. Such transitions are depicted by the arrows 1, 2 and 4 in Figure 5.
Therefore, a translation between similar constructs between source and target language
should be possible. Yet, the transition from Simulink models to IL models is not trivial,
as Simulink uses its own proprietary descriptions languages. Another possibility is the
transition from continuous signal-flow SL models to electrical IL models (see Figure 5,
arrow 3). Finally, arrow 5 in Figure 5 shows the manual refinement of the reference HDL
model to a device-level description.



Figure 5: Possible top-down flows from Simulink in the analog domain
Automated top-down transition using HDL coder
We developed a flow realizing the transition depicted by arrow 1 in Figure 5. Thereby,
discrete-time, continuous-value Simulink models of analog components are transformed
into discrete-time, continuous-value IL models described both in Verilog-AMS and
VHDL. The advantage of discrete-time models is that they are several magnitudes
faster during simulation compared to continuous-time signal-flow models described in
VHDL-AMS or Verilog-AMS. This is because no analog solver is needed for the
simulation of such models. Therefore, these models are widely used in the simulation of
very complex mixed-signal designs where the behavior of analog components is crucial
for the whole systems behavior. Such systems often contain a feedback loop between
digital and analog components. The use of continuous-value HDL models allows
models in the implementation design environment that are simulated with the same
accuracy as the corresponding Simulink models.
Similar to the digital domain, we are also using HDL Coder for the transition from
Simulink in the analog domain. However, in the analog domain, we take advantage of
HDL Coders ability to translate Simulink models that contain continuous-value signals
into HDL descriptions containing real signals. Figure 6 and Figure 7 show a discrete-
time integrator described both in Simulink and in VHDL generated by HDL Coder.

Figure 6: Discrete-time integrator in Simulink


Figure 7: Discrete-time integrator described in VHDL generated by HDL Coder
(shortened)
The models generated by HDL Coder use a fixed sample rate. The sample rate thereby
is realized by a clock, which has to be connected to the analog model. The frequency of
the clock connected to our HDL description has to therefore correspond to the sample
rate used in the Simulink model. The sample rate used is crucial for the accuracy of the
model: A sufficient sample rate must be twice as high as the highest input frequency of
the model obeying the Nyquist criterion [6].

Integration into mixed-signal design environments
After the generation of the VHDL or Verilog code, the code can be integrated into an
ADE and be simulated there. We realized the integration of both generated VHDL and
Verilog code into Cadence Virtuoso ADE. Therein, components with electrical signals
can be connected to components with signal-flow ports. For this, the signal-flow
component has to possess external wreal ports. In Virtuoso ADE connect modules are
then automatically inserted between electrical and signal-flow ports.
For integrating generated Verilog models, we perform a post-processing of the Verilog
code: While the resulting Verilog modules are internally working with real signals, HDL
Coder converts these signals to 64-bit std_logic vectors at the in- and output ports of
Verilog modules because there are no real ports defined in the Verilog standard. We
automatically replace the std_logic vector ports by wreal ports, which are part of the
Verilog-AMS standard. These Verilog modules containing wreal ports can then be easily
linked to analog schematics in Cadence Virtuoso ADE.
In the case of generated VHDL models we create a wrapper which maps the VHDL real
ports to Verilog-AMS wreal ports. Using these wrappers the models can then also be
easily integrated in the Cadence Virtuoso ADE.

Implementation
All developed approaches were implemented as MATLAB functions and then integrated
into the Model Advisor by using the Simulink Verification and Validation (see Figure 8).
Hereby we provide the user with an easy way to apply our solution using a graphical
user interface.


Figure 8: Developed solutions integrated into Simulink Model Advisor
We implemented the presented optimizations for digital Simulink models and the
transition to a gate-level description. These optimizations analyze and modify the
selected digital Simulink subsystem. For the transition to a gate-level description HDL
Coder is called first for generating HDL code, and after that we call Synopsys Design
Compiler. Based on the synthesis results Model Advisor finally shows the user an
estimated area and power consumption of the gate-level description.
We also implemented the necessary steps for generating HDL behavioral models of
analog Simulink subsystems: First, an HDL behavioral model is generated using HDL
Coder. After that, our post-processing script is applied to the Verilog code in order to
adapt the module interfaces. Then, the model is compiled and integrated into the
Cadence Virtuoso ADE by automatically creating a schematic symbol.
By integrating both the solutions of the digital and the analog domain into one unified
GUI, we allow the user to easily transfer digital and analog subsystems of mixed-signal
Simulink systems to the mixed-signal design environment.

Experiments
In this section, we describe the application of the presented solutions to an actual
automotive SiP design. The experiments were based on a Simulink model representing
the executable specification of a complete SiP containing a pressure and temperature
sensor and a connected ASIC. In its analog part the ASIC contains two delta-sigma
modulators, one for the pressure and one for the temperature signal.
In the digital non-programmable part the ASIC contains two decimation filters (again
one for each sensor signal). In the digital programmable part the ASIC contains a digital
signal processor running software for further signal processing the temperature and
pressure values (Figure 9 shows a simplified Simulink model of the SiP). The model's
stimuli were composed by collaborating ECU and ASIC SL architects in order to cover
all relevant signal ranges both in time and frequency domain.

Figure 9: Simplified Simulink model of SiP used for experiments
Experiments based on the digital partition
First target during the experiments was the transfer of the digital non-programmable
part into an optimized VHDL description. For comparison a manually written, highly
optimized VHDL description exists, which consists of 934 lines of code. Both decimation
filters of the digital part decimate and filter the output bitstreams of the delta-sigma
modulators.
The decimation filter of the pressure datapath has an input sample rate of about 1 MHz
and decimates the signal by a factor of 64. The input sample rate of the decimation filter
of the temperature datapath is also about 1MHz, but it has two outputs where the signal
is decimated both by a factor of 64 and by a factor of 1024. The Simulink model of the
digital part was developed as a cycle-accurate executable specification. We applied the
presented optimizations to it and evaluated the quality of the VHDL description resulting
from HDL Coder. We compared the resulting VHDL description to the hand-coded
design by synthesizing the designs to gate-level descriptions. During all comparisons,
the used clock rate for the designs was fixed.
We applied Word-Length Optimization and Timing Optimization to the design. Hereby
the functionality of the design was maintained to be cycle-accurate and bit-true with
respect to the used testbench scenarios. The impact of the applied optimizations can be
seen in Table 1: The hand-coded VHDL design takes more than one week to be
manually implemented depending on the experience of the hardware designer. It serves
as reference for the comparison.
When the original Simulink model of the decimation filter was automatically transformed
into a VHDL description by HDL Coder, the VHDL code resulted in an implementation
consuming 77.62 times more area and 111.12 times more power than the hand-coded
design. After applying Word-Length Optimization to the Simulink model, the design
consumed 32.17 times more area and 47.57 times more power than the hand-coded
design. The application of Timing Optimization reduced the additional area consumption
to 59 % and the additional power consumption to 22 %. By combining both
optimizations, the area consumption was 17 % lower and the power consumption 29 %
lower than the values of the hand-coded design.


Table 1: Impact of optimizations
This large reduction of resource consumption is caused by the fact that the Simulink
model was not designed with respect to requirements of an ASIC implementation. The
model had inefficient characteristics like single sample rate and word-lengths, whose
value ranges were not exploited. By applying Timing Optimization, the sample rate of
several subsystems could be reduced. This also resulted in a reduced number of
registers in the implementation.
The improvement of resource consumption compared to the hand-coded design is
achieved because Word-Length Optimization optimizes the component while it is
embedded in the system. Thereby word-lengths of blocks which have little influence on
the overall system were reduced. The application of Word-Length Optimization took 15
hours and the application of Timing Optimization took 40 seconds with MATLAB
R2011b on a Linux system with an AMD Dual-Core 3 GHz Opteron CPU and 8 GB of
RAM. The reason for the long duration of Word-Length Optimization is that for every
optimization step, one complete simulation of the system is needed for the evaluation of
a solution.

Experiments based on the analog partition
The second target of our experiments was the generation of a HDL behavioral model
from the Simulink models of the two delta-sigma modulators contained in the analog
part of the ASIC design. Thereby, one modulator is a third-order MASH 2-1 modulator
and the other a second-order single-loop modulator. For both modulators, abstract
discrete-time continuous-value models existed as executable specifications in Simulink.
Figure 10 shows the Simulink model of the MASH 2-1 modulator.


Figure 10: Simulink model of the MASH 2-1 modulator
We applied our approach and generated HDL behavioral models from these Simulink
models. After post-processing the generated code and creating schematic symbols for
the models, we were able to integrate the models into our device-level representation of
the ASIC in the Cadence Virtuoso ADE. There, the models were successfully simulated
in the context of the whole system (see Figure 11).

Figure 11: Waveform in Cadence Virtuoso ADE
Evaluation of experiments
The experiments show that with our example design, the characteristics of the hand-
coded digital design could be surpassed in terms of area and power by using an
automatic transition and our optimizations. These results were achieved by
automatically adapting the design to the characteristics of the surrounding system, while
the hand-coded design was developed isolated from the overall system. This
improvement in terms of resource consumption leads to lower cost per piece (CPP) of
the final SiP, while these results are dependent on the considered design.
On the other hand, using our proposed flow, the time needed to receive an efficient
VHDL description based on a Simulink model is significantly shorter than the time
needed for the manual implementation, which results in a shorter time-to-market (TTM)
span. For designs that result in a higher resource consumption using our flow, the
shorter TTM span has to be balanced against the possible higher CPP.
We also showed that discrete-time continuous-value HDL behavioral models can be
directly generated from Simulink models that represent analog hardware. The
generated models can then serve as a reference for the analog designer for device-
level implementation. These resulting models facilitate the design of the analog
implementation because the reference model is available in the analog design
environment, where the behavior of model and implementation can easily be compared.
Furthermore, during the verification of the whole design, the generated models can also
be used for the acceleration of a comprehensive simulation in the analog design
environment. This acceleration can be achieved by replacing step by step device-level
components with behavioral models.

Conclusion
In this work, an approach for automated transitions from analog and digital parts of
Simulink models representing mixed-signal ASICs to mixed-signal design environments
was presented. Optimizations were developed, which are applied to Simulink models
representing non-programmable digital circuits. The optimizations modify Simulink
models in order to receive resource-efficient HDL descriptions.
By using HDL Coder we perform the transition from both digital and analog Simulink
models to mixed-signal design environments. From Simulink blocks representing digital
hardware we generate resource efficient HDL implementations that can be directly
synthesized into gate-level descriptions. From Simulink blocks that represent analog
circuits, time-discrete continuous-value HDL behavioral models are generated. These
models can be used as a reference in the mixed-signal design environment for the
further development of the analog component. For an easy application our developed
solutions were integrated into Simulink Model Advisor.
Our approach was applied to an automotive mixed-signal design. We could show that
from analog Simulink models behavioral models can be automatically created simulated
in the mixed-signal design environment. Further, we showed that using our
optimizations and the suggested transition from digital Simulink models, our flow can
lead to an HDL description in shorter time and with less resource consumption
compared to a manual flow.

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