Second DSD Project draft

Center for Advanced Studies in Engineering,

Islamabad
Department of Electrical Engineering
Project Name
Calculator (Algorithm based)
Submitted by
! Amber "ounas E#$%##&
' Saba Ahmed A(an E#$%#)*
+ ,%-ia%.l%/assan E#$%#$+
0ate of Submission '!st A1ril,'#!#
Center for Advanced Studies in Engineering
Second DSD Project draft
0esign and 2unctionality (com1lete detail)
We are making a 6-bit calculator wic will do addition! subtraction!
multiplication and division based on te algoritms described below"
!%) A00I3I4N 5CA66" 7448 A/EA0 A00E6
#ur implementation of a final stage adder for two 6-bit operands is a Carr$ %ook
Aead Adder! wic re&uires 6 full adders '(As)" (igure sows a carr$ look aead
adder for n-bit operands! producing n-bit sum outputs and a carr$ out" *e
functionalit$ of te adder is based on te fact tat a carr$ signal will be generated
in two cases+
,) wen bot bits Ai and -i are ,"
.) wen one of te two bits is , and te carr$in 'carr$ of te previous stage) is ,"
*us
C4.3 9 Ci:! 9 Ai ; <i : (Ai = <i);Ci; (!)
*e 5 = 5 stands for e>clusive 46 or ?46" #ne can write tis e/pression also! as
Ci:! 9 @i : Pi ; Ci (')
in wic!
@i 9 Ai ; <i (+)
Pi 9 (Ai = <i) (A)
are called te @enerate and Pro1agate term! respectivel$"
(rom '.) 0 '1) it is clear tat bot te Propagate and 2enerate terms onl$ depend
on te input bits and tus will be valid after one gate dela$" 3f we use te above
e/pression to calculate te carr$ signals! we do not need to wait for te carr$ to
ripple" So
C! 9 @# : P#;C#(*)
C' 9 @! : P!;C! 9 @! : P!;@# : P!;P#;C# (B)
C+ 9 @' : P';@! : P';P!;@# : P';P!;P#;C# ($)
CA 9 @+ : P+;@' : P+;P';@! : P+P';P!;@# : P+P';P!;P#;C# ())
C*9
CB9
4ow it is clear tat te carr$out
bit! Ci5,! of te last stage will be available after tree dela$s 'one dela$ to
calculate te Propagate signal and two dela$s as a result of te A4D
Center for Advanced Studies in Engineering
Second DSD Project draft
and #6 gate)" *e Sum signal can be calculated as follows!
Si 9 Ai = <i = Ci 9 Pi = Ci (&)
*e carr$lookaead adder can be broken up in two modules+
A) te Partial (ull Adder! P(A! wic generates Si! Pi and 2i as defined b$
e&uations 7! 1 and 8 above"
-) teCarr$ %ookaead%ogic! wic generates te carr$outbits according to
e&uations 9 to :"
*e 6bitadder can ten be built b$ using 6 P(As and te Carr$ %ookaead
logic block
as sown in te figure below
*e group Propagate P2 of a 1bit adder will ave te following e/pressions!
P2 ; P7"P."P,"P<= ',<)
22 ; 27 5 P72. 5 P7"P."2," 5 P7"P."P,"2< ',,)
Center for Advanced Studies in Engineering
Second DSD Project draft
'%) S.<36AC3I4N
Ce taDe t(os com1liment of substahend and add to minuend and ,onitor
sign bit for overflo(;
i;e; a % b 9 a : (%b)
+%) ,.73IP7ICA3I4N 5<443/ES A7@46I3/,F
>ere we will define te functionalit$ of our multiplier block b$ tis flowcart"
Center for Advanced Studies in Engineering
Second DSD Project draft
A%)0IGISI4N
2lo(chart for .nsigned <inary 0ivision
Center for Advanced Studies in Engineering