Electronic Design Automation

Prof. I. Sengupta
Department of Computer Science Engineering
IIT Kharagpur
Lecture - 2
Verilog : Part I

so in this lecture we would be talking about the uh verilog hardware description language
(01:12.610)
now before I go into the syntax and the semantics [coughing] because there are some
features of the language uh which require the require clear understanding of the
semantics (01:27.060)
what it really means from the point of view of uh the hardware design and
implementation (01:32.690)
so I would like to mention one thing (01:36.253)
verilog may be used by a designer in two different context (01:44.269)
number one you specify a design in this language (01:550.220)
you simulate and see that whether your specification is correct (01:54.520)
so here you are not thinking about synthesis (02:00.600)
just you are specifying something in a hardware description language (02:03.840)
you are simulating (02:04.740)
you are looking at the timing diagram (02:06.328)
you are happy that the cycle is working properly but you will have to understand or
remember one thing that when you are using this language in this particular mode that
your objective is to simulate and verify whether simulation is correct (02:22.470)
there you are using some features of the verilog language which is perhaps not possible to
synthesize (02:33.020)
so what I mean to say is that the verilog language or the instruction set or the features
there are two different parts to it (02:43.550)
their one portion of it is said to be synthesizable (02:47.430)
other portion is said to be non synthesizable (02:50.710)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 1 of 25
so you should clearly know that which are the features which can be synthesized and
which are the features which cannot be synthesized (02:58.540)
so if your target is to synthesize a design then you must restrict yourself to the
synthesizable sub set (03:05.860)
okay (03:06.395)
but otherwise you can use others other features (03:09.310)
why is the other parts existing (03:10.168)
other part existing because in many cases you you you uh may not want to go down the
synthesis (03:16.280)
say for example in some course work you want to just learn the language verilog
(03:21.480)
just you want to write some coding verilog and simulate and see that if it is correct
(03:26.718)
see the CAD tool for synthesis is very expensive but the CAD tool for simulation is very
cheap and available even even uh there are there are there are a number of versions
available on the net for free (03:41.630)
so so that in many institutions uh what in order to impart training in verilog what people
do they teach the language verilog and ask the students to simulate and see that whether
whether whatever they have written is correct or not (03:58.100)
just I am giving you giving you some examples (04:00.725)
((not synthesizable portions04:00.780))
the portion that cannot be synthesized can be simulated like I can give you some
examples (04:08.620)
there are some instructions to read some data from a file (04:11.750)
to print something (04:13.390)
to specify delays that after this statement give a particular delay then do this (04:18.840)
something like an infinite loop (04:21.050)
something like incompletive statement (04:23.291)
so there are ((cer04:24.495)) certain things which which in terms of semantic is fine
but when you think of the hardware implementation it becomes very difficult for the
synthesizer (04:32.714)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 2 of 25
that is why the synthesizer does not consider those features at all (04:36.465)
okay (04:37.760)
so we will see these things (04:40.062)
fine (04:43.547)
so now we would be (04:44.657)
((given a behavior description automatically it will decide 04:45.070))
given a behavior description a synthesizer will automatically synthesize it down to the
gate level netlist yes (04:56.030)
((04:58.290))
does not worry about synthesis (05:02.538)
there are a number of uh you can say flags uh which uh the user can specify
whether you want to optimize or not (05:11.160)
there are a number of feature whether you want to incorporate testability or not
(05:13.893)
there are certain options which the user must specify but but otherwise up to the logic
level it is fairly automatic (05:20.534)
there is no user interference (05:23.066)
it is fully optimized but uh the problem is that once you look at the optimized layout you
will not understand or you means you will not recognize your design (05:32.880)
suppose your design had four modules and after optimizing all four modules are mixed
together (05:38.895)
so you cannot really identify those four modules (05:41.490)
so a good practice is to do a partitioning at the high level itself and to synthesize the four
modules separately (05:49.096)
around the floor on the silicon you place them manually (05:53.267)
that is a good trade off (05:55.970)
((05.58.700))
internal design is optimized but even at the level of layout you would like to see that the
basic blocks remain unidentifiable (06:08.150)
this is your CPU (06:09.665)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 3 of 25
this is your controlling unit but if the CPU and controlling unit are mixed together you
may be little worried (06:14.110)
if there is a ((06:14.610)) what to do (06:15.120)
fine (06:23.385)
so as I mentioned uh in the last lecture there are two popular hardware description
languages which people very widely use nowadays (06:31.916)
one is of course verilog other is VHDL (06:34.166)
well we ((mention06:36.335)) also mentioned that in this course we would be
considering mainly verilog (06:41.351)
there is some reasons of course but first let us try to understand some of the differences
between VHDL and verilog (06:50.803)
see the language VHDL is evolved initially to support higher level specifications
(06:59.200)
to support system level design and specifications (07:02.520)
it did not support low level design like for example a gate level netlist (07:07.864)
VHDL does not support users to specify a gate level netlist (07:13.000)
for example here you can support system level design where the blocks are specified
to specify the blocks their behavior and how they are interconnected (07:24.461)
but verilog was designed from the other way round (07:30.310)
this was designed by the designers who were developing FPGAs and ASICs who are
more familiar with the low level description languages like logic equations like circuit
diagrams at the RTL level gate level (07:48.022)
so they design verilog from that point of view (07:52.080)
so you will see that in verilog it is very easy to specify designs from that level
(07:57.260)
we have already seen some examples (07:58.730)
so the language features are different as i mentioned (08:03.150)
so lets try to see some of the differences (08:06.690)
VHDL provides some high level constructs because i had mentioned this was primarily
designed for system level designs and and the high level you can have so many different
kinds of requirements to specify (08:25.822)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 4 of 25
so there are something called user defined types user defined configurations that are
possible in VHDL but in verilog these are not there (08:36.790)
VHDL there are no predefined types (08:41.930)
all types have to be defined by the user like integer boolean etcetera (08:48.330)
these types are not that free existing but in verilog since the primary emphasis was for
low level designs all the basic data types and constructs and the basic gates they are
available as primitives (09:04.270)
so you can straightaway start using verilog to design your circuits even from a low level
(09:10.880)
now in VHDL if you want to do this you cannot do it straightaway (09:16.630)
you will have to import or include something called packages (09:21.740)
packages are something which someone has already written and designed for you
(09:27.610)
packages are basically a set of modules where the behavior of all the low level
functionalities have been specified to the ((09.38.117)) (09:38.830)
so unless you do this you cannot use VHDL but in verilog as i told these things are
available as language primitive (09:47.950)
they are part of the language but in VHDL the data type the basic gates the modules we
use they are not part of the language (09:56.140)
they have to be imported or included as packages okay (10:00.980)
so if you have the packages of course you can use VHDL then but without packages uh
the language VHDL is moduled but if you have packages you can use of course
(10:12.780)
but again I am telling you verilog is more natural for persons for logic designers who are
more familiar with specifying in the terms of logic in terms of interconnection of gates
etcetera (10:25.230)
verilog is a more natural way of expressive as compared to VHDL (10:30.022)
that is why in this course uh we have chosen to select verilog (10:34.685)
of course you can also use VHDL (10:36.263)
there is nothing wrong with it (10:38.370)
so not let us try to look at some of the language features of verilog (10:43.770)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 5 of 25
fine in verilog the basic building block using which we design everything is called a
module (10:54.740)
so a module is the basic unit of hardware in terms of which we can specify the behavior
or the structure whatever (11:09.220)
so the whatever we specify in verilog that is in the form of a module (11:14.840)
now in a design there can be several modules (11:19.040)
there are some restrictions (11:25.000)
within a module definition you cannot include another module definition (11:30.380)
so a module definition within another module definition is not allowed but what is
allowed is like the example that we had seen in the last class uh we had seen we can
instantiate (11:43.250)
we can define a module externally (11:45.890)
we can include it as part of a high level module (11:49.170)
that is what is possible and since this is possible we can have a nice hierarchy of designs
(12:00.462)
you can design it using a bottom up fashion (12:02.587)
to define the low level modules use them to design slightly high level modules
(12:09.400)
use them to design high level modules (12:11.160)
so using this we can have a hierarchy of design (12:13.805)
you can either proceed top down or bottom up as you wish (12:15.930)
the language verilog supports this (12:18.680)
okay (12:20.330)
now we have already seen how a typical module looks like uh but in terms of the syntax
(12:28.510)
the basic constituents of a module are these (12:34.112)
so a so a module definition we start with the keyword module and end with a keyword
endmodule (12:43.667)
this is the module name (12:46.855)
you have to give a name to each module and here you will have to list all parameters
(12:54.270)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 6 of 25
see if you treat a module as a black box there will be some inputs to this module
(13:02.095)
there will be some outputs from this module (13:04.293)
these are sometimes called ports (13:07.590)
so you will have to list all the input and output ports out here (13:11.556)
next you will have to specify that which of these ports are input which of these ports are
output (13:19.735)
well you can also specify something called bi directional in input and output port
(13:24.000)
so there are some input output declaration lines out here (13:28.750)
so you will have to specify which of these are input parameters which of these are output
parameters and what are their data types (13:34.145)
they are single bit or vector or what and as I mentioned also in the last class there can be
some interconnection which is internal (13:43.375)
say inside a module you can have a gate here you can have a gate here (13:46.910)
there can be an interconnecting line in between but this line is neither present in the input
port list or the output port list but when you specify this circuit in a structural form you
will have to give some name here (14:01.430)
that will come here (14:03.740)
local net declarations (14:05.830)
nets means interconnecting wires (14:09.290)
so this interconnecting wires which are internal to these module this will come after this
(14:14.622)
then the actual specification of your block (14:19.640)
well here I will say that these are parallel statement because here you can specify a
number of statements and you understand in verilog we are trying to specify hardware
and each of these statements will be getting mapped into some hardware blocks
(14:36.780)
now now if you have several hardware blocks computation will ((auto..14.42.618)) will
will obviously go on in parallel (14:44.970)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 7 of 25
well unless they are interconnected in cascade or there is some clock or something which
is driving them (14:51.070)
so if there is no such thing all these computation will go on in parallel (14:57.570)
if there is an AND gate if there is an OR gate they will evaluate together (15:00.880)
okay (15:02.560)
if they are in cascade for example if there is an AND gate if there is an OR gate they will
evaluate in parallel but the output of the OR gate will get the valid value after one unit of
time (15:18.540)
suppose these inputs change state (15:22.330)
these are the inputs A B and C (15:24.070)
these inputs are changing (15:26.210)
so the output of the AND gate will change first and after a delay the output of the OR
gate will change (15:31.900)
so the gate delays will take care of that (15:34.630)
verilog take care of the delay (15:40.832)
you can explicitly specify delays or when you are picking up some modules from the
library or predefined or otherwise there are some pre assigned delays to the gates
(15:51.920)
if you are having a behavioral description ((15.52.810))
well if you are having a behavioral description of the gate you can explicitly specify the
delay in terms of a number (16:02.940)
you can specify this block as a delay of ten (16:06.265)
this block as delay of five (16:07.453)
there are ways of doing that (16:08.590)
we will see it later (16:09.862)
A B C you are saying suppose A B C the values were say zero one and one (16:23.860)
now they change to say uh one zero and uh no one one and zero (16:36.845)
now what i am saying that this values are changing together (16:41.830)
now just assume each gate has a delay of delta (16:46.090)
so after a time delta the output of the AND gate will change to one (16:50.475)
((16.51.720)) AND gate was zero earlier (16:52.830)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 8 of 25
now if you change to one (16:54.390)
now this value was one already so this output of OR gate is still one (17:00.720)
uh sorry this is not a good example of taking (17:05.910)
zero one zero right (17:11.270)
making it one zero (17:12.750)
fine (17:14.070)
so if one zero then both will be one because this this will be zero okay but earlier this was
one (17:25.087)
so this OR gate was evaluated at this time with the older value so the output will be one
(17:31.130)
so only after time twice delta this new value will be used to simulate (17:38.252)
now it will take zero zero the output will become zero (17:40.990)
what I am saying is that (17:46.580)
((17.47.060))
delay can be different because when the simulation is actually carried out its an event
driven simulation depend on the delays of the gates there will be an event queue which is
maintained (18:01.240)
the gate which is changing state earliest will be at the head of the key (18:04.710)
that will be a priority key (18:05.587)
that can be list (( 18.07.290))
we will be talking about this later (18:10.003)
simulation is an important part (18:12.920)
yes (18:14.690)
well at the logic level at the pre layout simulation phase interconnect delays are assumed
to be zero (18:24.152)
they are all ideally connected (18:25.685)
only at the level of post layout simulation you can take care of that (18:31.100)
that we will ignore (18:34.388)
fine (18:37.535)
so now let us uh again start by looking at very simple examples (18:43.300)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 9 of 25
start with a simple AND gate [coughing] which we are specifying in terms of the
behavior (18:49.600)
so just to correlate with the previous example module (18:54.812)
in module (18:55.603)
this is the name of the module (18:58.800)
these are the parameters (19:00.220)
two of these i am specifying as input (19:03.300)
one i am specifying as output and assign is a keyword (19:06.696)
this assign says that we evaluate the right hand side and assign it to the variable f
(19:14.470)
so this will typically be synthesized by an AND gate x y the output will be driving f
okay simple (19:25.060)
(())
now assign we will have to write something otherwise it will give an error syntax error
(19:30.870)
there are different ways of doing it (19:34.494)
I will ((19:34.732)) (19:34.880)
this assign is one way of making assignment (19:40.072)
there are other ways also (19:40.950)
we will see it later and as i mentioned that if we have some intermediate wires for
example as this example shows you can get a two level circuit (19:53.919)
here this ampersand means AND (19:56.135)
bar means OR (19:57.854)
tilder means NOT and hack means exclusive OR (20:01.713)
so actually what we are getting is we are having a AND gate with a b as the input
(20:09.550)
output is t one (20:10.940)
this is a NOR gate okay (20:13.680)
OR and NOR (20:14.625)
c and d the output is t two (20:23.883)
then we have an exclusive OR of t one and t two (20:27.118)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 10 of 25
this is f (20:32.102)
so depending on the the intermediate wires we use here we are specifying a two level
logic (20:44.940)
right (20:48.700)
well there is some problems here that can occur during some simulation (20:54.248)
that we will see later (20:55.063)
we will compute a little later (20:57.700)
so that if you are not very careful about it then our simulation results and the actual
synthesis ((21:48.840)) may differ (21:05.670)
even in case of simple case like this (21:11.320)
yes (21:12.800)
((21:13.691))
that is the problem that can occur (21:26.275)
i will come to the example and i will uh just come back to your answer a little later that
means what if this your write before t one and t two (21:32.032)
yes (21:32.530)
there is a problem that may arise there (21:35.200)
i will uh come to that shortly and uh this kind of example we have already seen earlier
(21:45.073)
i am just showing this there (21:46.820)
you can specify a hierarchical design by instantiating modules (21:50.117)
well here again we have the ports (21:53.760)
you specify some of them as inputs some of them as outputs (21:57.650)
these are the local interconnecting nets and these are the modules we are putting
(22:02.930)
so here why i have put this is that you can either specify a design in terms of its behavior
or you can specify in terms of its structure (22:12.740)
this is a structural design (22:14.680)
basically i have picked up three modules i have put them together and i have
interconnected them okay (22:20.450)
fine (22:21.740)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 11 of 25
now as you see from this example that the way we specify the interconnection is by
explicit naming (22:30.910)
this cy out zero and cy out zero means that the output of this module B zero will go into
the input of this module B one (22:38.437)
now there are two ways of specifying such connectivity (22:44.030)
one is called positional which was illustrated in the previous example (22:49.660)
here the relative positions of the different parameters are maintained (22:55.190)
i will assume that the first parameter is the output carry out (22:59.015)
second parameter is the sum out (23:04.390)
next two parameters are the two inputs (23:06.975)
the last parameter is the carry in (23:08.723)
this is the assumption we will use and we will maintain (23:13.035)
this is called positional association (23:15.923)
the connections are listed in the same order (23:18.300)
so when we instantiate a module we list the names of the nets in the same order
(23:24.292)
the first one is carry (23:25.887)
second one is sum (23:26.548)
two inputs and then carry in (23:28.188)
but you can also choose to jumble up this order (23:32.547)
this is called explicit association (23:34.750)
there we can list them in any order but obviously if you do that we will have to explicitly
say which one is worth (23:41.874)
so you will have to specify it in a way something like this (23:46.890)
you instantiate the module and this in one into c in and sum c out these are the names
which were defined in the parent module description and a b c in sum and c out are the
variables in the present module (24:06.850)
so you say that a is actually in one b is actually in two c is actually c in and this you can
specify in any order (24:14.406)
so we can use either of them (24:18.390)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 12 of 25
some people say that explicit association is better because your code becomes self
documenting (24:23.930)
otherwise in a just complex layout you may have to go back and forth consider which one
is you may lose track of the parameters if there are many (24:33.348)
okay (24:36.418)
now let us come to the variables (24:40.550)
now as the example showed that we have used some variables in our description
(24:51.050)
well apart from the input and output we had used only one other kind of a variable that
was called wire (24:58.270)
now let us look at it a little more formally (25:03.010)
the variable data types can broadly fall under two categories (25:09.570)
one is called net and as the implies [coughing] a net is primarily used to interconnect two
things and register (25:20.030)
register again as the name implies it is used to store something (25:24.042)
some kind of storage to register (25:27.292)
net and register the main difference is net must be continuously driven (25:37.520)
continuously driven means suppose i have an AND gate (25:41.990)
the output of that AND gate this can be a net (25:45.627)
say f (25:47.845)
f is a net (25:48.840)
continuously driven means if you have an AND gate you always have some value at the
output (25:55.540)
there is no time for you to dont have a value (25:57.795)
continuously driven means net will assume its value instantaneously as soon as the gate
changes state (26:06.050)
it will not have to wait till the next clock right (26:11.810)
that thats how we say it is continuously driven (26:15.830)
it is not synchronized with any other event (26:17.738)
as soon as the gate output changes the net will assume its new value and this as i
mentioned this is typically used to model interconnection between models (26:28.691)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 13 of 25
continuous assignments and instantiations (26:32.970)
we have used these things (26:34.170)
so the example i have shown we have used these things (26:37.555)
um register as the name implies it is supposed to retain the last value assigned to it
(26:47.650)
but you will see later it is not necessary that always it will have to retain because the
synthesizer at the time of optimizing it may see that well a register variable is means a
register is really not required (27:02.860)
we can use it as a net variable also (27:05.460)
these kind of optimizations can be done (27:08.020)
we will see it later (27:08.680)
but by definition a register variable is one which is supposed to retain the last value
assigned to it (27:15.285)
that means there has to be some storage facility (27:17.820)
so this is used to represent storage elements typically (27:21.390)
so first let us look at the net data types in some depth (27:27.105)
what are the different kinds of net data types available (27:29.484)
see there are a few other data types we are not going into that we are only considerating
our attention to those which are synthesizable (27:44.210)
there are net data types called wire (27:49.625)
wire we have already used in our examples (27:51.438)
there is wired or wired and tri state supply zero supply one (27:58.238)
this wire and tri state they are the same (28:03.422)
there is no difference between these two descriptions (28:05.390)
this wired or and wired and they are slightly different (28:12.720)
first let us see wire and tri (28:15.734)
wire and tri they are equivalent (28:16.990)
the idea is like this (28:18.540)
if you are using wire or tri state say it is something like this (28:24.560)
suppose you use a wire description lets call it f one and f two (28:28.710)
now suppose you have well i am just showing the diagram (28:35.861)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 14 of 25
i have not shown the verilog code (28:37.060)
we have a gate which is driving f one (28:40.655)
you have another gate which is driving f two (28:45.660)
this kind of an example we have already seen but you can have another scenario where
this gate is driving f one (28:54.378)
the other gate is also driving f one (28:58.420)
so the synthesizer will not given an error (29:01.510)
what it will do (29:02.790)
it will short these two outputs and will give the output as f one (29:09.445)
it will not give an error (29:10.412)
so the synthesizer will assume that you have taken care that the designer has taken care
that these two gates will be having tri state control but if not then it is the design error
you will be detecting during simulation (29:23.607)
so the output logic value will be showing as indeterminant (29:28.620)
but if you are using wired or or wired and (29:33.790)
suppose i had description as wired and f one and if i had something like this (29:47.310)
this is an AND gate which is driving f one and an OR gate which is driving f one
(29:55.496)
suppose i had a situation like this (29:58.310)
then what the synthesizer will do (30:00.500)
synthesizer will explicitly add an other AND gate (30:04.547)
we will connect these two to this and will call the output as f one (30:09.870)
similarly if it is wired or it will add a OR gate okay (30:17.000)
((30.17.350))
if it is only one then the AND will not be there (30:23.668)
if it is more than one then the AND will be there (30:25.220)
(())
OR also same thing (30:26.740)
[coughing]
so this wired or and wired and are similar (30:32.740)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 15 of 25
they insert an AND and OR gate and this supply zero and supply one are used because in
some cases you may need to supply a constant zero logic or one logic (30:41.350)
so you can use this keyword supply zero and supply one to specify that (30:46.770)
so lets look at some more examples very quickly (30:53.470)
so this is just like the example that i had mentioned (31:00.4470)
there is one one AND gate driving f (31:03.450)
there is another OR gate driving f (31:06.250)
since it is a wire type they will be shorted together (31:09.470)
right (31:13.130)
so the way you specify it this is a wrong specification (31:18.782 )
it will give it will give a simulation error at the output (31:22.160)
this example again (31:27.460)
this example i have taken if we use a wired AND this AND gate and this OR gate we will
have an explicit AND gate added to it (31:37.950)
seems to be similar and this example shows that how we can use the supply zero and
supply one (31:50.860)
well supply zero is a data type (31:54.260)
supply zero this is the variable gnd supply one vdd (31:58.735)
these are the variable names and the way i have specified here uh i think we have missed
something here (32:06.650)
there should be another line here (32:07.940)
wire t one t two (32:10.040)
so this will be there will be an AND gate (32:16.740)
there are three inputs vdd A and B (32:22.945)
its a three input AND gate one A and B (32:28.039)
the output is t one (32:29.540)
there will be an XOR gate (32:32.010)
this will be a two input C and ground (32:36.680)
this is C and this is ground zero (32:39.520)
output is t two (32:41.050)
these will be ANDed (32:43.900)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 16 of 25
output is f (32:47.550)
so here you can specify zero and one constant values also like this (32:52.110)
okay (32:54.220)
so these are regarding the net data types (32:59.990)
wire wired OR wired AND supply zero supply one (33:03.436)
these are the five values we typically use (33:07.230)
now let us look at the register data type (33:10.740)
the register data as i have mentioned it is something which is supposed to be synthesized
into a storage element (33:20.340)
a register data type can be of two types reg and integer (33:27.970)
[coughing]
the main difference is that when you define it as reg you must explicitly specify the size
of the storage (33:37.530)
like if you simply specify reg x comma y this will mean that x and y are single bit
variables single bit storage or you can specify in terms of vector like this (33:51.222)
reg fifteen colon zero (33:53.050)
this will be a sixteen bit register and the convention is that fifteen will be the MSB
(34:03.105)
zero will be the LSB and for integer normally the synthesizer or the simulator will be
taking the default size which is thirty two bits but if you are trying to optimize then it can
do a data flow analysis and it can try to deduce that what should be the minimum possible
value of that integer and it can just use that minimum value (34:31.320)
i will give an example (34:34.588)
i will give an example that i will show you and just other than this this is one main
difference (34:43.282)
in register you have to explicitly specify the size [coughing] and integer you dont specify
the size (34:48.500)
this is the default value is taken normally and other difference is that you can use the
register variables in any arithmetic expression and if you are using an integer it is taken
as a twos complement signed integer (35:04.570)
but a register value register value is taken as an as an unsigned quantity (35:10.060)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 17 of 25
there is no concept of a negative value there (35:12.532)
okay (35:13.829)
this is another difference and just to give you a broad guideline you will be using a reg
data type for all cases where you are actually trying to synthesize a register or a storage
element (35:30.810)
but sometimes when you are specifying in the behavioral level you may have to use a for
loop kind of a thing (35:37.540)
there the loop index variable for example (35:40.500)
that you can use as a integer (35:43.100)
that is just a rule of the thumb (35:47.740)
the ones where you know exactly what is happening you know the size you specify the
((35:52.893)) register (35:53.510)
the others you can leave it (35:56.582)
you can also specify some register no problem (35:58.140)
but you can also specify them as integer (36:00.040)
((36.01.680))
input output connections uh they are neither reg nor there (36:08.677)
they are just some signals coming in (36:10.771)
they will their type will be depending on the driver module the module which is driving
those signals (36:18.230)
so whether they are driving from a reg type or a (36:22.190)
((36.24.010))
no no (36:26.882)
i will show that example (36:29.987)
there actually we will be specifying the size (36:33.730)
i am showing with example (36:37.280)
(())
the type this by default it is taken to be register but default it is taken this is taken to be
register (36:45.590)
okay (36:51.550)
((36:51.965))
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 18 of 25
where you can also use a vector because in that example of that adder we had used a
vector here where we want a zero (37:00.910)
(())
they are synthesizable if the number of loops that is a constant (37:12.620)
there is some kind of infinite loop or a variable loop (37:17.420)
then the some of the synthesizer allow it some synthesizer dont allow it (37:21.750)
now let us uh look at examples (37:28.172)
well there is some some features they have not yet mentioned but you will understand
what this means (37:32.940)
this is the verilog description of a simple binary counter with synchronous research
(37:41.110)
this counter if you choose it as a black box (37:47.530)
this will be having one clock input (37:49.990)
this will be having one reset input and of course the count value (37:56.670)
clock and reset are inputs (38:03.380)
output is the count and here you can explicitly specify count to be a register (38:10.758)
this is another way of doing it (38:13.910)
you can ((38:16.860)) either specify it here itself [coughing]or after declaring you can
explicitly say count that whatever is coming this is a reg (38:23.736)
((38:28.120))
yeah if we want you can specify it (38:30.920)
((38:31.810))
no yeah no no no yeah if you just specify only count will take it to be just one bit
(38:40.140)
if you specify by vector you are specifying the exact size (38:43.030)
((38:42.990))
output thirty one to zero count you can also specify like that (38:49.850)
um now in terms of normally in the body this always is a very important step you can
understand what this means (38:59.107)
this we will uh just see later more ((39:03.640)) options (39:04.540)
it says begin end this is a block (39:08.060)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 19 of 25
it says that you you you execute this block every time there is a positive edge on the
clock (39:14.820)
always at posedge clock (39:18.080)
similarly you can specify negedge (39:21.060)
that means there is something like a clock (39:24.460)
every time there is a leading edge on the clock you execute this (39:27.370)
this says that if reset is also one then count this is one way of specifying a thirty two bit
zero quantity (39:58.500)
thirty two is the size (39:40.170)
[coughing]
apostrophe b means its in binary zero (39:45.540)
so thirty two times zero (39:47.880)
its a thirty two bit number (39:50.165)
this this count is initialized to zero or else count is incremented by one (39:56.240)
so this is just a counter (39:58.540)
with every clock it will either increase or it will be reset to zero if the reset is also high at
that time (40:03.260)
so this is an example where you have specified reg and of course in synthesis the counter
will be synthesized as a register with storage element (40:14.250)
((40:18.300))
one bit (40:22.210)
one bit you are overriding the definition in the next line (40:28.246)
this definition you can override (40:32.440)
just in the input output parameters you can simply specify (40:36.882)
this is input this is output (40:38.590)
the sizes you can override in the next statements (40:41.307)
that option you have (40:42.410)
((43.840))
yeah output you will register you can also specify here output thirty one colon zero
that also you can specify (40:54.580)
that is one way (40:56.327)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 20 of 25
thirty one not ((40:57.930)) (40:58.170)
i am just uh written this now to show you that it is possible write like this (41:02.030)
okay now now earlier i mentioned that that instead of register if we use integer then the
exact size of the variables is not known but the synthesizer tries to deduce the size of the
value (41:19.750)
so i have an example to show you that (41:22.700)
yes (41:22.850)
(())
twos complement in arithmetic (41:36.440)
whenever you are doing arithmetic it will be twos component arithmetic (41:38.690)
well now here [coughing] it will not matter (41:40.140)
it will be the same because the whenever when (41:44.720)
((41:45.190))
yes (41:50.170)
((41:50.450))
you see see (41:51.920)
if the count was initialized as integer (42:00.300)
well just an example lets take that it is an eight bit okay (42:04.010)
thirty two bit two bit (42:05.370)
suppose the count value was this (42:08.595)
maximum possible possible number in one (42:11.760)
now after that whenever you you add one your count will be this but if you treat it as a
twos component number this will mean minus one twenty eight (42:22.910)
but if it is a simple counter you dont care what it means in two complement (42:28.060)
more important to you is that the count value is this which to you this is equal to plus one
twenty eight (42:33. 845)
so ones complement two complement is a two complements is a way of looking at it
(42:41.510)
((42:42.170))
no no you can override this specification (42:49.690)
you can override everything here but by default they have taken as registers (42:54.230)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 21 of 25
okay (42:59.910)
lets share a small example to illustrate that when you are [coughing] using integers the
synthesis system can deduce the exact size of that value (43:20.820)
for example if we have a description like this (43:24.760)
this is a verilog port segment where one colon ten (43:29.900)
you can also specify like this (43:31.360)
this means ten will be your LSB one will be your MSB (43:34.653)
numbering you can specify in whatever way we want (43:37.520)
integer C and in the computation part you write C equal to A plus B (43:43.700)
now by using a data flow analysis this synthesizer can deduce that A is a ten bit quantity
(43:51.170)
B is a ten bit quantity and we are adding them up (43:56.280)
so the sum can be ten plus one eleven (43:59.757)
so there will be ten bits for this sum and one carry (44:05.430)
so C will be synthesized as a eleven bit (44:08.972)
ten bit raised to one (44:14.280)
so often the synthesizer tries to do this kind of data flow analysis and try to deduce the
value of (44:21.670)
see instead of instead of by default taking two by thirty two raised always it can try to
find out what can be the maximum value possible and take it (44:30.140)
((44:31.490))
no as of now i have not written just as an example i have just written these three
statements (44:36.530)
this assign will also be there (44:38.360)
assign will be there assign will be there (44:39.720)
so this is the ((44:47.740)) i have shown (44:48.530)
uh this example i have already shown this example in one of the example (44:54.210)
if for the counter when you initialize it to zero (44:57.020)
so how do we specify constant value (44:59.290)
well a constant value you can specify like this also by simply specifying the value
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 22 of 25
twenty five for example or you can specify the size in terms of the number of bits
(45:12.181)
then apostrophe base (45:16.135)
base can be binary hexadecimal and the actual number (45:23.150)
there are different ways of doing that (45:27.494)
see eight base b this (45:31.830)
means this is a eight bit binary number and this is the value (45:36.534)
so when i specify binary i have to give this value binary (45:40.240)
twelve bit hex this is the hex value (45:46.360)
twelve bit hex this is the hex value (45:49.820)
one bit binary this is the binary value (45:52.810)
one bit binary binary value (45:54.700)
now in the early example we have written something like this (45:57.770)
thirty bit binary zero (46:01.400)
this means this is a thirty bit binary number with a value zero (46:7.080)
[coughing]
to the value zero means thirty two zeros (46:11.030)
so all thirty two zeros will be assigned (46:13.530)
sir how do you ((46:18.190))
unsigned form it is up to your ((inter)) whether it is signed or unsigned it is up to your
interpretation because these are constant values are assigned (46:32.030)
no unsized (46:32.960)
unsized (46:34.305)
well unsized if you dont specify anything simply twenty five (46:37.650)
default is thirty two bits (46:40.000)
like this just simply specify (46:43.090)
[coughing]
whether can you take it in decimals (46:47.830)
you can take it in decimals (46:49.960)
you can take in decimal by default (46:52.200)
((..46:52.190))
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 23 of 25
you assign it to a wire (46:54.740)
you cannot you cannot assign it to wire (46:56.510)
you can assign it to a resistor because a constant cannot drive a wire (47:01.650)
only another module can drive a wire (47:03.040)
so in the next class we will be continuing from this point onwards (47:12.200)
we would be looking at some other features of the verilog language (47:15.710)
how to specify uh constants in terms of something called parameters (47:23.693)
in this all these blocks we will be looking in some more detail and ((47:27.617))
in fact here for the time being we have looked at only only at uh ways of specifying
combination logic and only one counter we have seen (47:37.220)
that is we will see that depending on the design style it will depend exactly what
hardware will be synthesized (47:43.880)
okay (47:45.890)
so if we have something on the back of the mind for example we want to synthesize a
decoder we can write our code in that way so that a decoder will be synthesized
(47:53.500)
so that we can force the synthesizer into synthesizing it in a particular way (47:58.517)
that is possible (47:59.560)
that we will slowly do in the next week classes (48:04.355)
((wire has to be continuously driven))
wire wire has to be continuously driven (48:09.675)
(())
output of an AND gate is a high impedance state (48:18.250)
it is continuously driving the wire that means the wire is having a value x z (48:25.718)
z is high impedance (48:26.880)
so z is also a valid value (48:29.420)
zero one undefined dont care (48:31.790)
so actually when you are saying it is continuously driven it means that it will have a value
at all times but when it is clocked only when clock comes the value will change
(48:42.000)
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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 24 of 25
but if the output of the AND gate changes from one to a high impedance state the wire
will also change to a high impedance state (48:48.150)
okay (48:29.270)
it is not clocked (48:51.520)
so let us stop for today (48:55.630)
we will be continuing with our next lecture (48:57.100)
thank you (48:59.140)






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Electronic Design Automation Lecture 2
Prof. I. Sengupta Page 25 of 25