Professional Documents
Culture Documents
V100R007
Hardware Description
Issue 02
Date 2007-09-10
Part Number 31401357
Website: http://www.huawei.com
Email: support@huawei.com
and other Huawei trademarks are the property of Huawei Technologies Co., Ltd.
All other trademarks and trade names mentioned in this document are the property of their respective holders.
Notice
The information in this document is subject to change without notice. Every effort has been made in the
preparation of this document to ensure accuracy of the contents, but the statements, information, and
recommendations in this document do not constitute a warranty of any kind, express or implied.
Contents
3 Subrack.........................................................................................................................................3-1
3.1 Structure..........................................................................................................................................................3-2
3.2 Capacity...........................................................................................................................................................3-3
3.3 Slot Allocation.................................................................................................................................................3-4
3.4 Technical Specifications...............................................................................................................................3-17
6.9 DX1...............................................................................................................................................................6-64
6.9.1 Version Description..............................................................................................................................6-65
6.9.2 Function and Feature............................................................................................................................6-65
6.9.3 Working Principle and Signal Flow.....................................................................................................6-66
6.9.4 Front Panel...........................................................................................................................................6-67
6.9.5 Valid Slots............................................................................................................................................6-68
6.9.6 Board Feature Code..............................................................................................................................6-68
6.9.7 TPS Protection for the Board...............................................................................................................6-69
6.9.8 Board Configuration Reference...........................................................................................................6-70
6.9.9 Technical Specifications......................................................................................................................6-70
6.10 DXA............................................................................................................................................................6-71
6.10.1 Version Description............................................................................................................................6-71
6.10.2 Function and Feature..........................................................................................................................6-72
6.10.3 Working Principle and Signal Flow...................................................................................................6-72
6.10.4 Front Panel.........................................................................................................................................6-73
6.10.5 Valid Slots..........................................................................................................................................6-74
6.10.6 Board Configuration Reference.........................................................................................................6-75
6.10.7 Technical Specifications....................................................................................................................6-75
6.11 SPQ4............................................................................................................................................................6-75
6.11.1 Version Description............................................................................................................................6-76
6.11.2 Function and Feature..........................................................................................................................6-76
6.11.3 Working Principle and Signal Flow...................................................................................................6-77
6.11.4 Front Panel.........................................................................................................................................6-80
6.11.5 Valid Slots..........................................................................................................................................6-81
6.11.6 TPS Protection for the Board.............................................................................................................6-82
6.11.7 Board Configuration Reference.........................................................................................................6-83
6.11.8 Technical Specifications....................................................................................................................6-83
10 Auxiliary Boards.....................................................................................................................10-1
10.1 EOW............................................................................................................................................................10-2
10.1.1 Version Description............................................................................................................................10-2
10.1.2 Function and Feature..........................................................................................................................10-2
10.1.3 Working Principle and Signal Flow...................................................................................................10-2
10.1.4 Front Panel.........................................................................................................................................10-3
10.1.5 Valid Slots..........................................................................................................................................10-5
10.1.6 Technical Specifications....................................................................................................................10-5
10.2 AUX............................................................................................................................................................10-6
10.2.1 Version Description............................................................................................................................10-6
10.2.2 Function and Feature..........................................................................................................................10-6
10.2.3 Working Principle and Signal Flow...................................................................................................10-7
10.2.4 Jumper..............................................................................................................................................10-11
10.2.5 Front Panel.......................................................................................................................................10-11
10.2.6 Valid Slots........................................................................................................................................10-14
10.2.7 Technical Specifications..................................................................................................................10-15
10.3 AMU..........................................................................................................................................................10-15
10.3.1 Version Description..........................................................................................................................10-15
10.3.2 Function and Feature........................................................................................................................10-15
10.3.3 Working Principle and Signal Flow.................................................................................................10-16
10.3.4 Front Panel.......................................................................................................................................10-17
10.3.5 Valid Slots........................................................................................................................................10-20
10.3.6 Technical Specifications..................................................................................................................10-20
10.4 FAN...........................................................................................................................................................10-21
10.4.1 Version Description..........................................................................................................................10-21
10.4.2 Function and Feature........................................................................................................................10-21
10.4.3 Working Principle and Signal Flow.................................................................................................10-22
10.4.4 Front Panel.......................................................................................................................................10-22
10.4.5 Valid Slots........................................................................................................................................10-23
10.4.6 Technical Specifications..................................................................................................................10-23
14 Cables.......................................................................................................................................14-1
14.1 Fiber Jumper................................................................................................................................................14-2
14.1.1 Types of Fiber Jumpers......................................................................................................................14-2
14.1.2 Connector...........................................................................................................................................14-3
14.2 Power Cables and Grounding Cables..........................................................................................................14-5
14.2.1 Cabinet –48 V/BGND/PGND Power Cable.......................................................................................14-5
14.2.2 Equipment –48 V/–60 V Power Cable/PGND Grounding Cable......................................................14-7
14.2.3 UPM Power Cable..............................................................................................................................14-9
14.3 Alarm Cable..............................................................................................................................................14-10
14.3.1 Alarm Input/Output Cable................................................................................................................14-10
14.4 Management Cable....................................................................................................................................14-12
14.4.1 OAM Serial Port Cable....................................................................................................................14-12
14.4.2 Serial 1–4/F1/F&f Serial Port Cable................................................................................................14-14
14.4.3 RS232/RS-422 Serial Port Cable.....................................................................................................14-15
14.4.4 Ordinary Telephone Wire.................................................................................................................14-17
14.4.5 COA Concatenating Cable...............................................................................................................14-18
14.4.6 Straight Through Cable....................................................................................................................14-19
14.4.7 Crossover Cable...............................................................................................................................14-20
14.5 Signal Cable..............................................................................................................................................14-21
14.5.1 75-ohm 8 x E1 Cable........................................................................................................................14-22
14.5.2 75-ohm 16 x E1 Cable......................................................................................................................14-23
14.5.3 120-ohm 8 x E1 Cable......................................................................................................................14-26
14.5.4 120-ohm 16 x E1 Cable....................................................................................................................14-28
14.5.5 E3/T3/STM-1 Cable.........................................................................................................................14-30
14.5.6 Framed E1 Cable..............................................................................................................................14-31
14.5.7 N x 64 kbit/s Cables.........................................................................................................................14-31
14.6 Clock Cable...............................................................................................................................................14-48
14.6.1 Clock Cable......................................................................................................................................14-48
14.6.2 One-Channel and Two-Channel Clock Transfer Cables..................................................................14-50
B Labels..........................................................................................................................................B-1
B.1 Safety Label...................................................................................................................................................B-2
B.1.1 Label Description..................................................................................................................................B-2
B.1.2 Label Position.......................................................................................................................................B-3
G Glossary.....................................................................................................................................G-1
H Acronyms and Abbreviations...............................................................................................H-1
Index.................................................................................................................................................i-1
Figures
Figure 14-5 Cabinet –48 V power cable and BGND power grounding cable....................................................14-6
Figure 14-6 Cabinet PGND protection grounding cable (JG2)..........................................................................14-6
Figure 14-7 Cabinet PGND protection grounding cable (OT)...........................................................................14-6
Figure 14-8 Structure of the equipment –48 V/–60 V Power Cable..................................................................14-8
Figure 14-9 PGND power cable.........................................................................................................................14-8
Figure 14-10 Structure of the UPM power cable...............................................................................................14-9
Figure 14-11 Structure of the alarm input/output cable...................................................................................14-11
Figure 14-12 Structure of the OAM serial port cable.......................................................................................14-13
Figure 14-13 Structure of the Serial 1–4/F1/F&f serial port cable..................................................................14-14
Figure 14-14 Structure of the RS232/RS-422 serial port cable........................................................................14-16
Figure 14-15 Structure of the ordinary telephone wire....................................................................................14-17
Figure 14-16 Structure of the COA concatenating cable.................................................................................14-18
Figure 14-17 Structure of the straight through cable........................................................................................14-19
Figure 14-18 Structure of the crossover cable..................................................................................................14-20
Figure 14-19 Structure of the 75-ohm 8 x E1 cable.........................................................................................14-22
Figure 14-20 Structure of the 75-ohm 16 x E1 cable.......................................................................................14-24
Figure 14-21 Structure of the 120-ohm 8 x E1 cable.......................................................................................14-26
Figure 14-22 Structure of the 120-ohm 16 x E1 cable.....................................................................................14-28
Figure 14-23 Structure of the E3/T3/STM-1 cable..........................................................................................14-30
Figure 14-24 Structure of the V.35 DCE cable................................................................................................14-33
Figure 14-25 Structure of the V.35 DTE cable................................................................................................14-35
Figure 14-26 Structure of the V.24 DCE cable................................................................................................14-36
Figure 14-27 Structure of the V.24 DTE cable................................................................................................14-38
Figure 14-28 Structure of the X.21 DCE cable................................................................................................14-39
Figure 14-29 Structure of the X.21 DTE cable................................................................................................14-40
Figure 14-30 Structure of the RS449 DCE cable.............................................................................................14-42
Figure 14-31 Structure of the RS449 DTE cable.............................................................................................14-43
Figure 14-32 Structure of the RS530 DCE cable.............................................................................................14-45
Figure 14-33 Structure of the RS530 DTE cable.............................................................................................14-47
Figure 14-34 Structure of the 75-ohm clock cable...........................................................................................14-49
Figure 14-35 Structure of the 120-ohm 8 x E1 cable.......................................................................................14-49
Figure 14-36 Structure of the one-channel clock transfer cable (75 ohms to 120 ohms)................................14-50
Figure 14-37 Structure of the two-channel clock transfer cable (75 ohms to 120 ohms)................................14-50
Figure B-1 Labels on the OptiX OSN 1500B subrack........................................................................................B-4
Figure B-2 Labels on the OptiX OSN 1500A subrack........................................................................................B-4
Figure B-3 Labels on a board..............................................................................................................................B-5
Figure B-4 Optical module labels........................................................................................................................B-5
Tables
Table 7-26 Relation between the board feature code and the optical interface type..........................................7-53
Table 7-27 Specifications of the optical interfaces of the EGS2........................................................................7-54
Table 7-28 Functions and features of the EMS4................................................................................................7-55
Table 7-29 Optical interfaces of the EMS4........................................................................................................7-62
Table 7-30 Valid slots for the EMS4 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500A
subrack................................................................................................................................................................7-62
Table 7-31 Valid slots for the EMS4 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500B
subrack................................................................................................................................................................7-62
Table 7-32 Relation between the board feature code and the optical interface type..........................................7-63
Table 7-33 Specifications of the optical interfaces of the EMS4.......................................................................7-66
Table 7-34 Functions and features of the EGS4.................................................................................................7-68
Table 7-35 Optical interfaces of the EGS4.........................................................................................................7-74
Table 7-36 Relation between the board feature code and the optical interface type..........................................7-74
Table 7-37 Specifications of the optical interfaces of the EGS4........................................................................7-78
Table 7-38 Functions and features of the EGR2................................................................................................7-79
Table 7-39 Optical interfaces of the EGR2 .......................................................................................................7-86
Table 7-40 Relation between the board feature code and the optical interface type..........................................7-86
Table 7-41 Specifications of the interfaces of the EGR2...................................................................................7-87
Table 7-42 Version description of the EMR0....................................................................................................7-88
Table 7-43 Comparison of features of the N1EMR0 and N2EMR0..................................................................7-88
Table 7-44 Functions and features of the EMR0................................................................................................7-89
Table 7-45 Optical interfaces of the EMR0 .......................................................................................................7-97
Table 7-46 Valid slots for the EMR0 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500A
subrack................................................................................................................................................................7-97
Table 7-47 Valid slots for the EMR0 and corresponding slots for the ETF8 and EFF8 in the OptiX OSN 1500B
subrack................................................................................................................................................................7-97
Table 7-48 Relation between the board feature code and the optical interface type..........................................7-98
Table 7-49 Specifications of the optical interfaces of the EMR0.......................................................................7-98
Table 7-50 Functions and features of the ADL4..............................................................................................7-100
Table 7-51 Optical interface of the ADL4 .......................................................................................................7-104
Table 7-52 Relation between the board feature code and the optical interface type........................................7-104
Table 7-53 Specifications of the optical interfaces of the ADL4.....................................................................7-105
Table 7-54 Functions and features of the ADQ1..............................................................................................7-107
Table 7-55 Optical interfaces of the ADQ1 .....................................................................................................7-111
Table 7-56 Relation between the board feature code and the optical interface type........................................7-111
Table 7-57 Specifications of the optical interfaces of the ADQ1.....................................................................7-112
Table 7-58 Functions and features of the IDL4................................................................................................7-114
Table 7-59 Optical interface of the IDL4 ........................................................................................................7-118
Table 7-60 Relation between the board feature code and the optical interface type........................................7-118
Table 7-61 Specifications of the optical interfaces of the IDL4.......................................................................7-119
Table 7-62 Functions and features of the IDQ1...............................................................................................7-121
Table 7-63 Optical interfaces of the IDQ1 ......................................................................................................7-126
Table 7-64 Relation between the board feature code and the optical interface type........................................7-126
Table 8-33 Valid slots for the TSB8 and corresponding slots for the PD3 and D34S.......................................8-45
Table 8-34 Valid slots for the TSB8 and corresponding slots for the SEP and EU04.......................................8-45
Table 8-35 Valid slots for the TSB8 and corresponding slots for the SEP and EU08.......................................8-45
Table 8-36 Valid slots for the TSB8 and corresponding slots for the EFS0 and ETS8.....................................8-46
Table 8-37 Valid slots for the TSB8 and corresponding slots for the PL3 and C34S........................................8-46
Table 8-38 Interfaces of the EFF8......................................................................................................................8-49
Table 8-39 Valid slots for the EFT8 and corresponding slots for the EFF8......................................................8-49
Table 8-40 Valid slots for the EFS0 and corresponding slots for the EFF8.......................................................8-49
Table 8-41 Valid slots for the EMS4 and corresponding slots for the EFF8.....................................................8-49
Table 8-42 Valid slots for the EMR0 and corresponding slots for the EFF8.....................................................8-50
Table 8-43 Specifications of the optical interfaces of the EFF8........................................................................8-50
Table 8-44 Interfaces of the ETF8......................................................................................................................8-53
Table 8-45 Pins of the RJ-45 connector of the ETF8.........................................................................................8-54
Table 8-46 Valid slots for the EFT8 and corresponding slots for the ETF8......................................................8-54
Table 8-47 Valid slots for the EFS0 and corresponding slots for the ETF8......................................................8-55
Table 8-48 Valid slots for the EMS4 and corresponding slots for the ETF8.....................................................8-55
Table 8-49 Valid slots for the EMR0 and corresponding slots for the ETF8.....................................................8-55
Table 8-50 Specifications of the electrical interfaces of the ETF8....................................................................8-55
Table 8-51 Interfaces of the ETS8......................................................................................................................8-58
Table 8-52 Pins of the RJ-45 connector of the ETS8.........................................................................................8-59
Table 8-53 Valid slots for the EFS0 and corresponding slots for the ETS8......................................................8-59
Table 8-54 Specifications of the electrical interfaces of the ETS8....................................................................8-59
Table 8-55 Interfaces on the front panel of the DM12.......................................................................................8-62
Table 8-56 Pins of the DB44 interfaces of the DM12........................................................................................8-63
Table 8-57 Pins of the DB28 interfaces of the DM12........................................................................................8-64
Table 8-58 Valid slots for the DX1 and corresponding slots for the DM12......................................................8-64
Table 9-1 Function and feature of the SDH processing unit of the CXL1...........................................................9-3
Table 9-2 Function and feature of the SCC unit of the CXL1.............................................................................9-3
Table 9-3 Function and feature of the cross-connect unit of the CXL1...............................................................9-4
Table 9-4 Function and feature of the clock unit of the CXL1............................................................................9-5
Table 9-5 Optical interface and switches on the CXL1......................................................................................9-11
Table 9-6 Relation between the board feature code and the optical interface type............................................9-11
Table 9-7 Logical slots displayed on the T2000 for the CXL1..........................................................................9-12
Table 9-8 Specifications of the optical interfaces of the CXL1.........................................................................9-12
Table 9-9 Function and feature of the SDH processing unit of the CXL4.........................................................9-14
Table 9-10 Function and feature of the SCC unit of the CXL4.........................................................................9-15
Table 9-11 Function and feature of the cross-connect unit of the CXL4...........................................................9-16
Table 9-12 Function and feature of the clock unit of the CXL4........................................................................9-16
Table 9-13 Optical interface and switches on the CXL4....................................................................................9-22
Table 9-14 Relation between the board feature code and the optical interface type..........................................9-22
Table 9-15 Logical slots displayed on the T2000 for the CXL4........................................................................9-23
Table 9-16 Specifications of the optical interfaces of the CXL4.......................................................................9-23
Table 9-17 Function and feature of the SDH processing unit of the CXL16.....................................................9-25
Table 9-18 Function and feature of the SCC unit of the CXL16.......................................................................9-26
Table 9-19 Function and feature of the cross-connect unit of the CXL16.........................................................9-27
Table 9-20 Function and feature of the clock unit of the CXL16......................................................................9-27
Table 9-21 Optical interface and switches on the CXL16..................................................................................9-33
Table 9-22 Relation between the board feature code and the optical interface type..........................................9-33
Table 9-23 Logical slots displayed on the T2000 for the CXL16......................................................................9-34
Table 9-24 Specifications of the optical interfaces of the CXL16.....................................................................9-34
Table 10-1 Functions and features of the EOW.................................................................................................10-2
Table 10-2 Interfaces on the front panel of the EOW........................................................................................10-4
Table 10-3 Pins of the PHONE interface of the EOW.......................................................................................10-5
Table 10-4 Pins of the S1, S2, S3 and S4 interfaces of the EOW......................................................................10-5
Table 10-5 Functions and features of the AUX..................................................................................................10-7
Table 10-6 Interfaces on the front panel of the AUX.......................................................................................10-12
Table 10-7 Pins of the CLK interface of the AUX...........................................................................................10-13
Table 10-8 Pins of the ETH and COM interfaces of the AUX.........................................................................10-13
Table 10-9 Pins of the ALM interface of the AUX..........................................................................................10-13
Table 10-10 Pins of the OAM interface of the AUX.......................................................................................10-14
Table 10-11 Pins of the F&f interface of the AUX..........................................................................................10-14
Table 10-12 Functions and features of the AMU.............................................................................................10-16
Table 10-13 Interfaces on the front panel of the AMU....................................................................................10-18
Table 10-14 Pins of the PHONE interface of the AMU...................................................................................10-19
Table 10-15 Pins of the S1 and S2 interfaces of the AMU..............................................................................10-19
Table 10-16 Pins of the LAMP1 and LAMP2 interfaces of the AMU.............................................................10-19
Table 10-17 Functions and features of the FAN..............................................................................................10-21
Table 11-1 Functions and features of the CMR2...............................................................................................11-3
Table 11-2 Optical interfaces of the CMR2.......................................................................................................11-7
Table 11-3 Feature code of the CMR2...............................................................................................................11-7
Table 11-4 Specifications of the optical interfaces of the CMR2......................................................................11-8
Table 11-5 Functions and features of the CMR4.............................................................................................11-10
Table 11-6 Optical interfaces of the CMR4.....................................................................................................11-13
Table 11-7 Feature code of the CMR4.............................................................................................................11-13
Table 11-8 Specifications of the optical interfaces of the CMR4....................................................................11-14
Table 11-9 Functions and features of the MR2................................................................................................11-16
Table 11-10 Optical interfaces of the MR2......................................................................................................11-19
Table 11-11 Feature code of the MR2..............................................................................................................11-19
Table 11-12 Specifications of the optical interfaces of the MR2.....................................................................11-20
Table 11-13 Functions and features of the MR2A...........................................................................................11-22
Table 11-14 Optical interfaces of the MR2A...................................................................................................11-25
Table 11-15 Specifications of the optical interfaces of the MR2A..................................................................11-25
Table 11-16 Functions and features of the MR2B...........................................................................................11-27
Table 11-17 Optical interfaces of the MR2B...................................................................................................11-30
Overview
This document describes the equipment structure, subrack structure and board classification.
This document also describes each board of different classes in details.
This document helps you get the detailed information on the equipment hardware.
Product Versions
The following table lists the product versions related to this document.
Intended Audience
The intended audience of this document are:
Organization
This document describes the cabinet, subrack, boards and each unit of the boards in terms of the
function and working principle.
Chapter Description
4 Board List and This chapter describes the classification of boards and
Classification appearance of the boards.
5 SDH Processing Boards This chapter describes the SDH processing boards in terms
of the function, principle, front panel, interface and
technical specifications.
6 PDH Processing Boards This chapter describes the PDH processing boards in terms
of the function, principle, front panel, interface and
technical specifications.
7 Data Processing Boards This chapter describes the data processing boards in terms
of the function, principle, front panel, interface and
technical specifications.
8 Interface Boards and This chapter describes the interface boards and switching
Switching Boards boards in terms of the function, principle, front panel,
interface and technical specifications.
9 Cross-Connect and System This chapter describes the cross-connect and system control
Control Boards boards in terms of the function, principle, front panel,
interface and technical specifications.
10 Auxiliary Boards This chapter describes the auxiliary boards in terms of the
function, principle, front panel, interface and technical
specifications.
11 WDM Processing Boards This chapter describes the WDM processing boards in
terms of the function, principle, front panel, interface and
technical specifications.
12 Optical Amplifier Boards This chapter describes the optical amplifier boards and
and Dispersion dispersion compensation boards in terms of the function,
Compensation Boards principle, front panel, interface and technical
specifications.
13 Power Interface Boards This chapter describes the power interface boards in terms
of the function, principle, front panel, interface and
technical specifications.
A Equipment and Board This appendix describes the indication of the equipment and
Alarm Indicators board alarm indicators.
Chapter Description
C Power Consumption and This appendix describes the power consumption and weight
Weight of each board.
H Acronyms and This appendix lists the acronyms and abbreviations used in
Abbreviations this document.
Conventions
Symbol Conventions
The following symbols may be found in this document. They are defined as follows.
Symbol Description
General Conventions
Convention Description
Convention Description
Boldface Names of files, directories, folders, and users are in boldface. For
example, log in as user root.
Command Conventions
Convention Description
{ x | y | ... } Alternative items are grouped in braces and separated by vertical bars.
One is selected.
{ x | y | ... } * Alternative items are grouped in braces and separated by vertical bars.
A minimum of one or a maximum of all can be selected.
GUI Conventions
Convention Description
Boldface Buttons, menus, parameters, tabs, window, and dialog titles are in
boldface. For example, click OK.
> Multi-level menus are in boldface and separated by the “>” signs. For
example, choose File > Create > Folder.
Keyboard Operation
Format Description
Key Press the key. For example, press Enter and press Tab.
Key 1+Key 2 Press the keys concurrently. For example, pressing Ctrl+Alt+A means
the three keys should be pressed concurrently.
Key 1, Key 2 Press the keys in turn. For example, pressing Alt, A means the two keys
should be pressed in turn.
Mouse Operation
Action Description
Click Select and release the primary mouse button without moving the pointer.
Double-click Press the primary mouse button twice continuously and quickly without
moving the pointer.
Drag Press and hold the primary mouse button and move the pointer to a certain
position.
Update History
Updates between document versions are cumulative. Therefore, the latest document version
contains all updates made to previous versions.
This release of the document fixes several bugs, adds product labels, and checks the parameters
of the dimensions and weight. It also details function block diagram and relative description for
each board.
This release of the document fixes several bugs, adds product labels. It also checks the parameters
of the slots and optical interfaces. In addition, it adds the description on the N1SL64 board.
This release of the document fixes several bugs in the document of previous version. The T2000
is upgraded from V200R003C02 to V200R004C01.
1 Equipment Structure
The OptiX OSN 1500A and the OptiX OSN 1500B are both case-shaped equipment. The OptiX
OSN 1500A/B subrack can be installed in a 300-mm or 600-mm ETSI cabinet, or a 19-inch
cabinet. The OptiX OSN 1500A/B can also be installed against the wall. The OptiX OSN 1500A
can be installed on the desk.
2 Cabinet
PowerCritical MajorMinor
W D
Table 2-1 lists the information about the indicators on the ETSI cabinet.
CAUTION
The cabinet indicators are driven by the subrack. The cabinet indicators can be lit only after the
cables are correctly connected and the subrack is powered on.
2.2.2 DC PDU
The DC PDU is on the top of the cabinet and used to supply power for the equipment.
1 2 3
OUTPUT
4
A B 1 2 3
OUTPUT
4
ON ON
OFF OFF
INPUT
32A 32A 20A 20A 32A 32A 20A 20A
For the OptiX OSN 1500A, the power terminals at side A and side B supply power to the PIU
boards at side A and side B of the subrack respectively. Table 2-2 shows the connections of the
power terminals at side A and side B.
For the OptiX OSN 1500B, the power terminals at sides A and B supply power to the PIU boards
at the upper and lower subrack respectively.
The UPM numbered GIE4805S can directly supply power to the OptiX OSN 1500. The UPM
directly converts the 220 V mains supply to the –48 V DC power supply required by the
communication equipment. If operators cannot provide the –48 V DC power supply for the
equipment or require that the battery be used, the UPM can be applied.
l COA
l Fiber management spool, which is used to spool the redundant fibers inside the cabinet.
600 (W) x 300 (D) x 2000 (H) 55 The number of allowed OptiX
OSN 1500A/1500B subracks
600 (W) x 600 (D) x 2000 (H) 79 varies with the cabinet capacity
600 (W) x 300 (D) x 2200 (H) 60 and the number of the power
supplies.
600 (W) x 600 (D) x 2200 (H) 84
3 Subrack
This chapter describes the cabinet in terms of the structure, capacity, slot allocation and technical
specifications.
3.1 Structure
The OptiX OSN 1500A subrack is of a one-layer structure. The subrack consists of the slot area
for boards, power supply area, fan area and fiber routing area. The OptiX OSN 1500B subrack
is of a two-layer structure. The subrack consists of the slot area for processing boards, slot area
for interface boards, slot area for the auxiliary interface board, power supply area and fan area.
3.2 Capacity
Both the OptiX OSN 1500A and the OptiX OSN 1500B have slots that can be divided into half-
width slots. These slots have different service access capacities before and after the slot division.
3.3 Slot Allocation
The OptiX OSN 1500A subrack has only one tier, where 12 slots are present before the division
of slots. The OptiX OSN 1500B subrack has two tiers. The upper tier of the subrack, where four
slots are present, is the slot area for interface boards. The lower tier of the subrack, where ten
slots are present before the division of slots (including slots 4 and 5), is the slot area for processing
boards.
3.4 Technical Specifications
The specifications of the subrack cover dimensions, weight and maximum power consumption.
3.1 Structure
The OptiX OSN 1500A subrack is of a one-layer structure. The subrack consists of the slot area
for boards, power supply area, fan area and fiber routing area. The OptiX OSN 1500B subrack
is of a two-layer structure. The subrack consists of the slot area for processing boards, slot area
for interface boards, slot area for the auxiliary interface board, power supply area and fan area.
Figure 3-1 shows the structure of the OptiX OSN 1500A subrack.
2
3 H
4 W
D
6
Figure 3-2 shows the structure of the OptiX OSN 1500B subrack.
2
3
4
4
H
W
5 D
7
1. Slot area for interface boards 2. Power supply area 3. Fan area
4. Slot area for processing boards 5. Slot area for the auxiliary interface board 6. Fiber routing area
7. Mounting ear
l Slot area for interface boards: This area is used to house the tributary interface boards and
Ethernet interface boards for the OptiX OSN 1500B.
l Slot area for processing boards: This area is used to house the line, tributary and Ethernet
processing boards for the OptiX OSN 1500B.
l Fan area: This area is used to house one fan module, which dissipates heat generated by
the equipment.
l Slot area for the auxiliary interface board: This area is used to house the auxiliary interface
board, which provides alarm interfaces, orderwire phone interface, management and
maintenance interface, and clock interface.
l Power supply area: This area is used to house two PIU boards, which are used to supply
power for the equipment.
l Fiber routing area: This area is used to route fibers and cables in the subrack.
3.2 Capacity
Both the OptiX OSN 1500A and the OptiX OSN 1500B have slots that can be divided into half-
width slots. These slots have different service access capacities before and after the slot division.
In the OptiX OSN 1500A subrack, slots 12 and 13 can be divided into half-width slots. In the
OptiX OSN 1500B subrack, slots 11–13 can be divided into half-width slots. Figure 3-3 shows
the slot access capacity of the OptiX OSN 1500A. Figure 3-4 shows the slot access capacity of
the OptiX OSN 1500B.
In the OptiX OSN 1500A subrack, slots 12 and 13 can be divided into half-width slots.
l When slot 12 is divided, the two half-width slots are numbered slot 2 and slot 12.
l When slot 13 is divided, the two half-width slots are numbered slot 3 and slot 13.
l When slots 12 and 13 are not divided, the access capacity of each slot is 2.5 Gbit/s.
l When slots 12 and 13 are divided, the access capacity of each half-width slot is 1.25 Gbit/
s.
In the OptiX OSN 1500B subrack, slots 11–13 can be divided into half-width slots.
l When slot 11 is divided, the two half-width slots are numbered slot 1 and slot 11.
l When slot 12 is divided, the two half-width slots are numbered slot 2 and slot 12.
l When slot 13 is divided, the two half-width slots are numbered slot 3 and slot 13.
l When slots 11–13 are not divided, the access capacity of each slot is 2.5 Gbit/s.
l When slots 11–13 are divided, the access capacity of each half-width slot is 1.25 Gbit/s.
Slot 14
Slot 18 PIU
Slot 15
Slot 16
Slot 19 PIU
Slot 17
slots are present, is the slot area for interface boards. The lower tier of the subrack, where ten
slots are present before the division of slots (including slots 4 and 5), is the slot area for processing
boards.
Figure 3-5 shows the slot layout of the OptiX OSN 1500A subrack.
Slots 12 and 13 in the OptiX OSN 1500A subrack can be divided into two half-width slots
respectively. See Figure 3-6.
Figure 3-6 Slot layout of the OptiX OSN 1500A subrack after the division of slots
Slot 1 Slot 11 Slot 6
Figure 3-7 shows the slot access capacity of the OptiX OSN 1500A.
Slot
XCS A 1 XCS B
Slot 11 Slot 6 1.25Gbit/s
When slots 12 and 13 are not divided, the access capacity of each slot is 2.5 Gbit/s. When slots
12 and 13 are divided, the access capacity of each slot is 1.25 Gbit/s.
The slots in the OptiX OSN 1500A subrack are allocated as follows:
l Slots for integrated boards of the line, SCC, cross-connect and timing units: slots 4–5
l Slots for processing boards before the division of slots: slots 6–9 and 12–13
l Slots for processing boards after the division of slots: slots 6–9, 12–13, and 2–3
l Slot for the orderwire board: slot 9 (also for the processing board)
l Slot for the auxiliary interface board: slot 10
Figure 3-8 shows the slot layout of the OptiX OSN 1500B subrack. Figure 3-9 shows the slot
access capacity of the OptiX OSN 1500B.
Slot 14
Slot 18 PIU
Slot 15
Slot 16
Slot 19 PIU
Slot 17
Slot 11 2.5Gbit/s Slot 6 622Mbit/s
NOTE
Slots 11–13 in the OptiX OSN 1500B subrack can be divided. As shown in Figure 3-10, the divided slots
are in the dashed area. The slots in the left portion of the original slots are slots 1–3, and the slots in the
right portion of the original slots are slots 11–13. After the division of slots, the maximum access capacity
of each slot is 1.25 Gbit/s. See Figure 3-11.
Figure 3-10 Slot layout of the OptiX OSN 1500B subrack (after the division of slots)
Slot 14 Interface board
Slot 18 PIU
Slot 15 Interface board
Slot 16 Interface board
Slot 19 PIU
Slot 17 Interface board
Slot 1 Slot 11 Processing Slot 6 Processing
board board
Slot 20 Slot 2 Slot 12 Processing Slot 7 Processing
board board
Slot 3 Slot 13 Processing Slot 8 Processing
board board
FAN Slot 4 CXL16/4/1 Slot 9 EOW
Slot 5 CXL16/4/1 Slot 10 AUX
Figure 3-11 Access capacity of the OptiX OSN 1500B subrack (after the division of slots)
Slot 14
Slot 18 PIU
Slot 15
Slot 16
Slot 19 PIU
Slot 17
Slot 1 1.25 Gbit/s Slot 11 1.25 Gbit/s Slot 6 622 Mbit/s
Slot 20 Slot 2 1.25 Gbit/s Slot 12 1.25 Gbit/s Slot 7 622 Mbit/s
Slot 3 1.25 Gbit/s Slot 13 1.25 Gbit/s Slot 8 622 Mbit/s
FAN Slot 4 2.5 Gbit/s Slot 9 622 Mbit/s
Slot 5 2.5 Gbit/s Slot 10 AUX
The slots in the OptiX OSN 1500B subrack are allocated as follows:
l Slots for integrated boards of the line, SCC, cross-connect and timing units: slots 4–5
l Slots for processing boards before the division of slots: slots 6–9 and 11–13
l Slots for processing boards after the division of slots: slots 1–9 and 11–13
l Slots for the interface boards: slots 14–17
l Slot for the orderwire board: slot 9 (also for the processing board)
l Slot for the auxiliary interface board: slot 10
l Slots for PIU boards: slots 18 and 19
l Slot for the fan board: slot 20
Mapping Relation Between Slots for Interface Boards and Slots for Processing
Boards
Table 3-1 lists the mapping relation between slots for interface boards and slots for processing
boards of the OptiX OSN 1500A.
Table 3-1 Mapping relation between slots for interface boards and slots for processing boards
of the OptiX OSN 1500A.
Table 3-2 lists the mapping relation between slots for interface boards and slots for processing
boards of the OptiX OSN 1500B.
Table 3-2 Mapping relation between slots for interface boards and slots for processing boards
of the OptiX OSN 1500B.
Slots for Slots for Interface Slots for Slots for Interface
Processing Boards Processing Boards
Boards Boards
Slots for Slots for Interface Slots for Slots for Interface
Processing Boards Processing Boards
Boards Boards
The corresponding interface boards for the PD3, PL3, SEP, and SPQ4 can be housed only in
slots of even numbers.
The boards housed in slots 12 and 7 share the same interface board housed in slot 15, and the
boards housed in slots 13 and 8 share the same interface board housed in slot 17. Therefore,
when you configure the boards:
l If slot 12 houses the N1EMS4 (used with an interface board) or R1PD1, slot 7 cannot house
any board used with an interface board.
l If slot 13 houses the N1EMS4 (used with an interface board) or R1PD1, slot 8 cannot house
any board used with an interface board.
Table 3-3 Boards and their valid slots for the OptiX OSN 1500A
R1SLD4 2 x STM-4 optical interface board Slots 2–3, 6–9, and 12–13
(half-width)
R1SL4 1 x STM-4 optical interface board Slots 2–3, 6–9, and 12–13
(half-width)
R1SLQ1 4 x STM-1 optical interface board Slots 2–3, 6–9, and 12–13
(half-width)
R1SL1 1 x STM-1 optical interface board Slots 2–3, 6–9, and 12–13
(half-width)
Table 3-4 lists the boards and their valid slots for the OptiX OSN 1500B.
Table 3-4 Boards and their valid slots for the OptiX OSN 1500B
Board Full Name Valid Slots
R1SLD4 2 x STM-4 optical interface board Slots 1–3 and 11–13 (for the
(half-width) board housed in any of slots 1–3
and 11–13, two optical interfaces
can be configured), slots 6–9 (for
the board housed in any of slots
6–9, one optical interface can be
configured)
R1SL4 1 x STM-4 optical interface board Slots 1–3, 6–9 and 11–13
(half-width)
R1SLQ1 4 x STM-1 optical interface board Slots 1–3, 6–9 and 11–13
(half-width)
R1SL1 1 x STM-1 optical interface board Slots 1–3, 6–9 and 11–13
(half-width)
N1EMS4 (not used 4 x GE Ethernet processing board Slots 11–13 (2.5 Gbit/s)
with the interface
board)
N1EFS0 (used with 10M/100M Ethernet processing Slots 12–13 (622 Mbit/s)
the interface board) board
N2EFS0 (used with 10M/100M Ethernet processing Slots 12–13 (1.25 Gbit/s)
the interface board) board
444 (W) x 262 (D) x 131 (H) 8 (the backplane, fans and two PIU
boards included)
Table 3-6 lists power consumption of the OptiX OSN 1500A subrack.
Table 3-6 Maximum power consumption of the OptiX OSN 1500A subrack
Subrack Type Maximum Power Fuse Capacity
Consumption
Table 3-7 lists the technical specifications of the OptiX OSN 1500B subrack.
444 (W) x 263 (D) x 221 (H) 9 (the backplane, fans and two PIU
boards included)
Table 3-8 lists power consumption of the OptiX OSN 1500B subrack.
Table 3-8 Maximum power consumption of the OptiX OSN 1500B subrack
Subrack Type Maximum Power Fuse Capacity
Consumption
This chapter describes the appearance, barcode and classification of boards used for the OptiX
OSN systems.
Table 4-1 lists the appearance figures and dimensions of boards for the OptiX OSN 1500.
Table 4-1 Appearance and dimensions of boards for the OptiX OSN 1500
Board
appearance
Note: The figure in the right cell illustrates the three dimensions. The H
height and width are measured for the front panel and the depth is
measured for the printed circuit board (PCB). D W
CAUTION
Wear the anti-static wrist strap when holding the board with hands. Make sure that the anti-static
wrist strap is well grounded. Otherwise, the static discharge may cause damage to the board.
DANGER
Avoid direct eye exposure to laser beams launched from the optical interface board or optical
interfaces. Otherwise, damage may be caused to the eyes.
CAUTION
l Do not directly insert the attenuators into the level optical modules. If the attenuators are
required, use the attenautors at the ODF side.
l If a board requires an attenuator, insert the attenuator in the IN interface instead of the OUT
interface.
l When performing the loopback, use attenuators to prevent damage to the optical modules.
The barcode is stuck on the front panel of a board. Figure 4-1 shows a barcode with 16-character
manufacturing code.
Bar code
0364401055000015 -SSN3SL16A01
① ② ③ ④ 5
NOTE
For details on the board feature code, see the section that describes the board feature code for each board.
Table 4-2 SDH processing boards for the OptiX OSN 1500A
Board Full Name
Table 4-3 lists the SDH processing boards supported by the OptiX OSN 1500B.
Table 4-3 SDH processing boards for the OptiX OSN 1500B
Board Full Name
Table 4-4 PDH processing boards for the OptiX OSN 1500A
Board Full Name Board Full Name
Table 4-5 lists the PDH processing boards supported by the OptiX OSN 1500B.
Table 4-5 PDH processing boards for the OptiX OSN 1500B
Board Full Name Board Full Name
Table 4-6 Data processing boards for the OptiX OSN 1500A
Board Full Name Board Full Name
Table 4-7 lists the data processing boards supported by the OptiX OSN 1500B.
Table 4-7 Data processing boards for the OptiX OSN 1500B
Board Full Name Board Full Name
Table 4-8 lists the interface boards and switching boards supported by the OptiX OSN 1500A.
Table 4-8 Interface boards and switching boards supported by the OptiX OSN 1500A
Table 4-9 lists the interface boards and switching boards supported by the OptiX OSN 1500B.
Table 4-9 Interface boards and switching boards supported by the OptiX OSN 1500B
Table 4-10 Cross-connect boards and SCC boards supported by the OptiX OSN 1500A and the
OptiX OSN 1500B
Board Full Name
Q2CXL1 Integrated board of the SCC, cross-connect and line units at the
STM-1 level
Q2CXL4 Integrated board of the SCC, cross-connect and line units at the
STM-4 level
Q2CXL16 Integrated board of the SCC, cross-connect and line units at the
STM-16 level
Table 4-11 Auxiliary boards supported by the OptiX OSN 1500A and the OptiX OSN 1500B
Board Full Name Board Full Name
Table 4-12 lists the optical add/drop multiplexing boards supported by the OptiX OSN 1500A.
Table 4-12 Optical add/drop multiplexing boards supported by the OptiX OSN 1500A
Table 4-13 lists the optical add/drop multiplexing boards supported by the OptiX OSN 1500B.
Table 4-13 Optical add/drop multiplexing boards supported by the OptiX OSN 1500B
Table 4-14 lists the optical amplifier boards and dispersion compensation boards supported by
the OptiX OSN 1500A and the OptiX OSN 1500B.
Table 4-14 Optical amplifier boards and dispersion compensation boards supported by the OptiX
OSN 1500A/B
Board Full Name
This chapter describes the SDH processing boards at the STM-1, STM-4, and STM-16 levels.
5.1 SL1
This section describes the SL1, a 1 x STM-1 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
5.2 SLQ1
This section describes the SLQ1, a 4 x STM-1 optical interface board, in terms of the version,
function, working principle, front panel and parameters.
5.3 SLO1
This section describes the SLO1, an 8 x STM-1 optical interface board, in terms of the version,
function, working principle, front panel and parameters.
5.4 SLT1
This section describes the SLT1, a 12 x STM-1 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
5.5 SEP1
This section describes the SEP1 board, in terms of the version, function, working principle, front
panel, and specifications.
5.6 SL4
This section describes the SL4, a 1 x STM-4 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
5.7 SLD4
This section describes the SLD4, a 2 x STM-4 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
5.8 SLQ4
This section describes the SLQ4, a 4 x STM-4 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
5.9 SL16
This section describes the SL16, a 1 x STM-16 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
5.10 SL16A
This section describes the SL16A, a 1 x STM-16 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
5.11 SF16
This section describes the SF16, a 1 x STM-16 optical interface board with the out-band FEC
function, in terms of the version, function, working principle, front panel and specifications.
5.1 SL1
This section describes the SL1, a 1 x STM-1 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
Table 5-1 lists the details on the versions of the SL1 board.
Item Description
Difference The N2SL1 supports the TCM function. The N1SL1 and R1SL1 do not
support the TCM function. The R1SL1 is housed in a divided slot.
Item Description
Specification of Supports standard optical interfaces of the I-1, S-1.1, L-1.1, L-1.2 and
the optical Ve-1.2 types. The optical interfaces of the I-1, S-1.1, L-1.1 and L-1.2 types
interface comply with ITU-T G.957 in features. The optical interface of the Ve-1.2
type complies with the standards defined by Huawei.
Specification of Supports detection and query of the information on the optical module.
the optical Supports the usage and detection of the pluggable optical module SFP for
module easy maintenance.
The optical interface supports the function of setting the on/off state of the
laser and the ALS function.
Service Supports the processing of the VC-12, VC-3 and VC-4 services.
processing
Overhead Supports the processing of the SOH bytes of the STM-1 signals.
processing Supports the transparent transmission and termination of the POH bytes.
Supports the setting and query of the J0/J1/C2 bytes.
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Protection Supports the two-fiber bidirectional MSP protection ring, linear MPS,
scheme SNCP, SNCTP and SNCMP.
Figure 5-1 shows the block diagram for the working principle of the SL1.
Figure 5-1 Block diagram for the working principle of the SL1
155 MHz Reference clock
155 MHz Cross-connect unit
PLL
....
Cross-connect unit A
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section MST: multiplex section termination MSA: multiplex section adaptation
termination
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery
CDR Module
l It recovers the data signal and the clock signal.
RST
l In the receive direction, RST performs frame alignment detection (A1, A2), regenerator
section trace recovery (J0) and mismatch detection, BIP-8 errored block count.
l In the transmit direction, RST performs frame alignment insertion, regenerator section path
trace insertion, BIP-8 calculation and insertion.
MST
l In the receive direction, MST performs BIP-24 errored block count, multiplex section-
remote error indication (MS_REI) recovery, multiplex section-remote defect indication
(MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection.
l In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI
MS_RDI and MS_AIS insertion.
l MST provides extraction or insertion of K1 byte and K2 byte.
MSA
l In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS
detection, pointer justification.
l In the transmit direction, MST it performs administration unit group (AUG) assembly,
AU-4 pointer generation, AU_AIS generation.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring)
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
DC/DC Converter
It provides the board with required DC voltages. It converts the –48/–60 V power supply to the
following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
SL1
STAT
ACT
PROG
SRV
CLASS1
LASER
PRODUCT
OUT
IN
SL1
Figure 5-3 shows the appearance of the front panel of the R1SL1.
SL1
STAT
ACT
PROG
SRV
OUT IN
SL1
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There is one pair of optical interfaces on the front panel of the SL1. Table 5-3 lists the type and
usage of the optical interfaces.
l The N1SL1 can be housed in any of slots 12–13 in the OptiX OSN 1500A subrack.
l The N2SL1 can be housed in any of slots 12–13 in the OptiX OSN 1500A subrack.
l The R1SL1 can be housed in any of slots 1–3, 6–9 and 11–13 in the OptiX OSN 1500B
subrack.
l The N1SL1 can be housed in any of slots 11–13 in the OptiX OSN 1500B subrack.
l The N2SL1 can be housed in any of slots 11–13 in the OptiX OSN 1500B subrack.
Table 5-4 lists the relation between the board feature code and optical interface type for the SL1.
Table 5-4 Relation between the board feature code and the optical interface type
You can use the T2000 to set the following parameters for the SL1:
l J0
l J1
l C2
Item Specification
Note: MLM indicates the multi-longitudinal mode and SLM indicates the single-longitudinal
mode.
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the N1SL1/N2SL1 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the N1SL1/N2SL1 is
14 W.
In the normal temperature (25℃), the maximum power consumption of the R1SL1 is 10.3 W.
5.2 SLQ1
This section describes the SLQ1, a 4 x STM-1 optical interface board, in terms of the version,
function, working principle, front panel and parameters.
Table 5-6 lists the details on the versions of the SLQ1 board.
Difference The N2SLQ1 supports the TCM function. The N1SLQ1 and R1SLQ1
do not support the TCM function. The R1SLQ1 is housed in a divided
slot.
Specification of Supports standard optical interfaces of the I-1, S-1.1, L-1.1, L-1.2 and
the optical Ve-1.2 types. The optical interfaces of the I-1, S-1.1, L-1.1 and L-1.2 types
interface comply with ITU-T G.957 in features. The optical interface of the Ve-1.2
type complies with the standards defined by Huawei.
Specification of Supports detection and query of the information on the optical module.
the optical The optical interface supports the function of setting the on/off state of
module the laser and the ALS function.
Supports the usage and detection of the pluggable optical module SFP for
easy maintenance.
Service Supports the processing of the VC-12, VC-3 and VC-4 services.
processing
Overhead Supports the processing of the SOH bytes of the STM-1 signals.
processing Supports the transparent transmission and termination of the POH bytes.
Supports the setting and query of the J0/J1/C2 bytes.
Supports one to four channels of ECC communication.
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Protection Supports the two-fiber unidirectional MSP protection ring, linear MSP,
scheme SNCP, SNCTP and SNCMP.
Figure 5-4 Block diagram for the working principle of the SLQ1
155 MHz Reference clock
155 MHz Cross-connect unit
PLL
....
Cross-connect unit A
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section MST: multiplex section termination MSA: multiplex section adaptation
termination
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery
CDR Module
l It recovers the data signal and the clock signal.
RST
l In the receive direction, RST performs frame alignment detection (A1, A2), regenerator
section trace recovery (J0) and mismatch detection, BIP-8 errored block count.
l In the transmit direction, RST performs frame alignment insertion, regenerator section path
trace insertion, BIP-8 calculation and insertion.
MST
l In the receive direction, MST performs BIP-24 errored block count, multiplex section-
remote error indication (MS_REI) recovery, multiplex section-remote defect indication
(MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection.
l In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI
MS_RDI and MS_AIS insertion.
l MST provides extraction or insertion of K1 byte and K2 byte.
MSA
l In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS
detection, pointer justification.
l In the transmit direction, MST it performs administration unit group (AUG) assembly,
AU-4 pointer generation, AU_AIS generation.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring)
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
DC/DC Converter
It provides the board with required DC voltages. It converts the –48/–60 V power supply to the
following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
SLQ1
STAT
ACT
PROG
SRV
CLASS1
LASER
PRODUCT
OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
SLQ1
Figure 5-6 shows the appearance of the front panel of the R1SLQ1.
SLQ1
STAT
ACT
PROG
SRV
SLQ1
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four pairs of optical interfaces on the front panel of the SLQ1. Table 5-8 lists the type
and usage of the optical interfaces.
l The R1SLQ1 can be housed in any of slots 2–3, 6–9 and 12–13 in the OptiX OSN 1500A
subrack.
l The N1SLQ1 can be housed in any of slots 12–13 in the OptiX OSN 1500A subrack.
l The N2SLQ1 can be housed in any of slots 12–13 in the OptiX OSN 1500A subrack.
l The R1SLQ1 can be housed in any of slots 1–3, 6–9 and 11–13 in the OptiX OSN 1500B
subrack.
l The N1SLQ1 can be housed in any of slots 11–13 in the OptiX OSN 1500B subrack.
l The N2SLQ1 can be housed in any of slots 11–13 in the OptiX OSN 1500B subrack.
Table 5-9 lists the relation between the board feature code and optical interface type for the
SLQ1.
Table 5-9 Relation between the board feature code and the optical interface type
SSN2SLQ110, 10 S-1.1
SSN1SLQ110
SSN2SLQ111, 11 L-1.1
SSN1SLQ111
SSN2SLQ112, 12 L-1.2
SSN1SLQ112
SSN2SLQ113, 13 Ve-1.2
SSN1SLQ113
SSN2SLQ114, 14 I-1
SSN1SLQ114
You can use the T2000 to set the following parameters for the SLQ1:
l J0
l J1
l C2
Item Specification
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the N1SLQ1/N2SLQ1 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the N1SLQ1/
N2SLQ1 is 15 W.
In the normal temperature (25℃), the maximum power consumption of the R1SLQ1 is 12 W.
5.3 SLO1
This section describes the SLO1, an 8 x STM-1 optical interface board, in terms of the version,
function, working principle, front panel and parameters.
Specification of the Supports standard optical interfaces of the I-1.1, S-1.1, L-1.1, L-1.2
optical interface and Ve-1.2 types. The optical interfaces of the I-1, S-1.1, L-1.1 and
L-1.2 types comply with ITU-T G.957 in features. The optical interface
of the Ve-1.2 type complies with the standards defined by Huawei.
Specification of the The optical module is pluggable. When optical modules of other types
optical module are inserted, an alarm indicating the mismatch of the optical module is
reported.
Supports detection and query of the information on the optical module.
Supports the default off state of the laser. The laser is turned off before
the software finishes the initialization when the board is powered on.
Supports the usage and detection of the pluggable optical module SFP.
Supports the setting and query of the on/off state of the laser. An alarm
is generated when the laser is turned off. Performance events are
reported to indicate the performance of the optical module.
Service processing Supports the processing of the VC-12, VC-3 and VC-4 services.
Overhead Supports the processing of the SOH bytes of the STM-1 signals.
processing Supports the transparent transmission and termination of the POH
bytes.
If the two SCC boards are not in service, the SLO1 does not transmit
overhead bytes (long 0s) to the two SCC boards.
Supports one to eight channels of ECC communication.
Alarm and Provides rich alarms and performance events for easy management and
performance event maintenance of the equipment.
Protection scheme Supports the two-fiber unidirectional MSP protection ring, linear MSP,
SNCP, SNCTP and SNCMP.
Figure 5-7 shows the block diagram for the working principle of the SLO1.
Figure 5-7 Block diagram for the working principle of the SLO1
155 MHz Reference clock
155 MHz Cross-connect unit
PLL
....
Cross-connect unit A
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section MST: multiplex section termination MSA: multiplex section adaptation
termination
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery
CDR Module
l It recovers the data signal and the clock signal.
RST
l In the receive direction, RST performs frame alignment detection (A1, A2), regenerator
section trace recovery (J0) and mismatch detection, BIP-8 errored block count.
l In the transmit direction, RST performs frame alignment insertion, regenerator section path
trace insertion, BIP-8 calculation and insertion.
MST
l In the receive direction, MST performs BIP-24 errored block count, multiplex section-
remote error indication (MS_REI) recovery, multiplex section-remote defect indication
(MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection.
l In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI
MS_RDI and MS_AIS insertion.
l MST provides extraction or insertion of K1 byte and K2 byte.
MSA
l In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS
detection, pointer justification.
l In the transmit direction, MST it performs administration unit group (AUG) assembly,
AU-4 pointer generation, AU_AIS generation.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring)
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
DC/DC Converter
It provides the board with required DC voltages. It converts the –48/–60 V power supply to the
following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
SLO1
STAT
ACT
PROG
SRV
OUT1 IN1
OUT2
IN2
OUT3 IN3 OUT4
IN4
OUT5 IN5
OUT6
IN6
OUT7 IN7
OUT8 IN8
CLASS1
LASER
PRODUCT
SLO1
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are eight pairs of optical interfaces on the front panel of the SLO1. Table 5-12 lists the
type and usage of the optical interfaces.
NOTE
The optical interfaces of the SLO1 are level optical interfaces and indented by 20 mm. The SLO1 board
can use the pluggable optical modules for easy maintenance.
WARNING
The optical interfaces of the SLO1 board are level optical interfaces. Thus, use the optical
attenuator only at the ODF side.
Table 5-13 lists the relation between the board feature code and optical interface type for the
SLO1.
Table 5-13 Relation between the board feature code and the optical interface type
SSN2SLO110 10 S-1.1
SSN2SLO111 11 L-1.1
SSN2SLO112 12 L-1.2
SSN2SLO113 13 Ve-1.2
SSN2SLO114 14 I-1
You can use the T2000 to set the following parameters for the SLO1:
l J0
l J1
l C2
Item Specification
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SLO1 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the SLO1 is 26W.
5.4 SLT1
This section describes the SLT1, a 12 x STM-1 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
Specification of Supports S-1.1 standard optical interfaces compliant with ITU-T G.957
the optical in features.
interface
Specification of Supports detection and query of the information on the optical module.
the optical The optical interface supports the function of setting the on/off state of
module the laser and the ALS function.
Supports the usage and detection of the pluggable optical module SFP for
easy maintenance.
Service Supports the processing of the VC-12, VC-3 and VC-4 services.
processing
Overhead Supports the processing of the SOH bytes of the STM-1 signals.
processing Supports the transparent transmission and termination of the POH bytes.
Supports the setting and query of the J0/J1/C2 bytes.
Supports one to eight channels of ECC communication.
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Protection Supports the two-fiber unidirectional MSP protection ring, linear MSP
scheme protection ring, SNCP, SNCTP, and SNCMP.
Figure 5-9 Block diagram for the working principle of the SLT1
155 MHz Reference clock
155 MHz Cross-connect unit
PLL
....
Cross-connect unit A
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section MST: multiplex section termination MSA: multiplex section adaptation
termination
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery
CDR Module
l It recovers the data signal and the clock signal.
RST
l In the receive direction, RST performs frame alignment detection (A1, A2), regenerator
section trace recovery (J0) and mismatch detection, BIP-8 errored block count.
l In the transmit direction, RST performs frame alignment insertion, regenerator section path
trace insertion, BIP-8 calculation and insertion.
MST
l In the receive direction, MST performs BIP-24 errored block count, multiplex section-
remote error indication (MS_REI) recovery, multiplex section-remote defect indication
(MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection.
l In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI
MS_RDI and MS_AIS insertion.
l MST provides extraction or insertion of K1 byte and K2 byte.
MSA
l In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS
detection, pointer justification.
l In the transmit direction, MST it performs administration unit group (AUG) assembly,
AU-4 pointer generation, AU_AIS generation.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring)
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
DC/DC Converter
It provides the board with required DC voltages. It converts the –48/–60 V power supply to the
following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
SLT1
STAT
ACT
PROG
SRV
CLASS1
LASER
PRODUCT
OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6
OUT7 IN7
OUT8 IN8
OUT9 IN9 OUT10 IN10 OUT11 IN11 OUT12 IN12
SLT1
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are 12 pairs of optical interfaces on the front panel of the SLT1. Table 5-16 lists the type
and usage of the optical interfaces.
WARNING
The optical interfaces of the SLT1 board are level optical interfaces. Thus, use the optical
attenuator only at the ODF side.
You can use the T2000 to set the following parameters for the SLT1:
l J0
l J1
l C2
Item Specification
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SLT1 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the SLT1 is 15 W.
5.5 SEP1
This section describes the SEP1 board, in terms of the version, function, working principle, front
panel, and specifications.
Basic function Processes 2 x STM-1 signals when interfaces are available on the front
panel.
Processes 8 x STM-1 signals when used with the interface board.
Specification of Supports detection and query of the information on the optical module.
the optical The optical interface supports the function of setting the on/off state of the
module laser and the ALS function.
Supports the usage and monitoring of the pluggable optical module SFP.
Service Supports the processing of the VC-12, VC-3 and VC-4 services.
processing
Overhead Supports the processing of the SOH bytes of the STM-1 signals.
processing Supports the transparent transmission and termination of the POH bytes.
Supports the setting and query of the J0/J1/C2 bytes.
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Protection Supports the TPS protection when used with the interface board and the
scheme switching board.
Supports the two-fiber unidirectional MSP protection ring, linear MSP
protection, and SNCP.
When the SEP1 is used with different interface boards and electrical interface switching boards,
the access capabilities for the STM-1 signals are different. See Table 5-19.
None Accesses and processes 2 x STM-1 electrical signals, and does not
support the TPS protection.
EU08+TSB8 Accesses and processes 8 x STM-1 electrical signals, and supports the
TPS protection for the SEP1 board.
CAUTION
When the SEP1 is used with the interface board, the two interfaces on the front panel are invalid.
The hybrid usage of the EU08 and OU08 is not supported.
Figure 5-11 Block diagram for the working principle of the SEP1
Reference clock
155 MHz PLL Cross-connect unit
K1 and K2 K1 and K2
insertion/extration Cross-connect unit
high speed
bus
Cross-connect
SPI
155 Mbit/s CMI NRZ 155 Mbit/s RST MST MSA HPT unit A
Transfo Encode/ CDR high speed
Port 1 155 Mbit/s Decode 155 Mbit/s
rmer bus
Cross-connect
unit B
155 Mbit/s CMI NRZ 155 Mbit/s
Encode/ CDR
Port 2 155 Mbit/s Transfor
mer Decode 155 Mbit/s
DCC
SCC unit
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.8 V converter -48 V/ -60 V
DC/DC
converter Fuse
+3.3 V backup
power
Figure 5-12 shows the block diagram for the working principle of the SEP used with the EU08.
Figure 5-12 Block diagram for the working principle of the SEP used with the EU08
Reference clock
155 MHz PLL Cross-connect
unit
EU08
SPI
155 Mbit/s CMI 155 Mbit/s
Encode CDR SDH overhead processing
Transfo module
155 Mbit/s /
Port 1 rmer 155 Mbit/s
Decode K1 and K2 K1 and K2
insertion/extration Cross-connect
unit
155 Mbit/s 155 Mbit/s
Port 8 CMI Encode CDR
155 Mbit/s Transfo / 155 Mbit/s high speed
rmer Decode bus
Cross-connect unit
A
155 Mbit/s CMI 155 Mbit/s RST MST MSA HPT high speed
NRZ
Transfo Encode/ CDR bus
Cross-connect unit
Port 1 155 Mbit/s rmer Decode 155 Mbit/s
B
Frame header
LOS Cross-connect unit
Communication and
control module Communication
SCC unit
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.8 V
converter -48 V/ -60 V
DC/DC
converter Fuse
+3.3 V backup
power
Figure 5-13 shows the block diagram for the working principle of the SEP used with the OU08.
Figure 5-13 Block diagram for the working principle of the SEP used with the OU08
Reference clock
155 MHz PLL Cross-connect unit
OU08
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.8 V converter -48 V/ -60 V
DC/DC
converter Fuse
+3.3 V backup
power
RST
l In the receive direction, RST performs frame alignment detection (A1, A2), regenerator
section trace recovery (J0) and mismatch detection, BIP-8 errored block count.
l In the transmit direction, RST performs frame alignment insertion, regenerator section path
trace insertion, BIP-8 calculation and insertion.
MST
l In the receive direction, MST performs BIP-24 errored block count, MS_REI recovery,
MS_RDI and MS_AIS detection.
l In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI
MS_RDI and MS_AIS insertion.
MSA
l In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS
detection, pointer justification.
l In the transmit direction, MSA performs AUG assembly, AU-4 pointer generation,
AU_AIS generation.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring)
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
SEP1
STAT
ACT
PROG
SRV
OUT1 IN1 OUT2 IN2
SEP1
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are two pairs of optical interfaces on the front panel of the SEP1. Table 5-20 lists the type
and usage of the optical interfaces.
Note: The SEP1 board can also be used with interface boards EU08 and OU08. In this case,
the SEP1 is defined as the SEP. When the SEP1 is used with the interface board, the two
interfaces on the front panel are invalid.
Protection Principle
Figure 5-15 shows the principle of the TPS protection for the SEP1 board.
TSB8 EU08
2 1 1 2
Cross-
connect
and timing
board
SLOT 9/10
Protection Working
SEP SEP
Fail
SLOT12 SLOT13
l Normal state: When the working boards are running normally, the control switch of the
EU08 is in position 1 and the EU08 directly accesses the service signals to the SEP1 board.
l Switching state: When a failure is detected on the working board, the working board housed
in each slot can be protected in the following ways.
– When the working board housed in slot 13 fails, the control switch of the corresponding
EU08 shifts from position 1 to position 2. At the same time, the control switch of the
TSB8 shifts from position 1 to position 2, and thus the working board housed in slot 13
is protected by the protection board housed in slot 12.
Hardware Configuration
Figure 5-16 shows the slot configuration for the 1:1 TPS protection for the SEP1.
Figure 5-16 Slot configuration for the 1:1 TPS protection for the SEP1
Slot 14 TSB8
Slot 18 PIU
Slot 15
Slot 16 EU08
Slot 19 PIU
Slot 17
Slot 11 Slot 6
Slot 20 Slot 12 Protection Slot 7
As shown in Figure 5-16, the protection board housed in slot 12 protects the board housed in
slot 13.
Table 5-21 lists the slots for the SEP1, EU08 and TSB8.
TSB8 Slot 14
EU08 Slot 16
You can use the T2000 to set the following parameters for the SEP1:
l J0
l J1
l C2
Connector SMB
Mechanical Specifications
The mechanical specifications of the SEP1 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.0
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the SEP1 is 17 W.
5.6 SL4
This section describes the SL4, a 1 x STM-4 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
The slots valid for the SL4 vary with the version of the board.
5.6.6 Board Feature Code
The code behind the board name in the barcode is the board feature code. The board feature code
of the SL4 indicates the optical interface type.
5.6.7 Board Configuration Reference
You can use the T2000 to set parameters for the SL4.
5.6.8 Technical Specifications
The technical specifications of the SL4 cover the optical interface specifications, board
dimensions, weight and power consumption.
Table 5-23 lists the details on the versions of the SL4 board.
Item Description
Difference The N2SL4 supports the TCM function. The N1 and R1SL4 do not
support the TCM function. The R1SL4 is housed in a divided slot.
The SL4 is used to transmit and receive STM-4 optical signals, to perform O/E conversion for
STM-4 signals, to extract or insert overhead bytes, and to generate alarm signals on the line.
Basic function Receives and transmits 1 x STM-4 optical signals, and processes 1 x
STM-4 standard or concatenation services.
Specification of Supports standard optical interfaces of the I-4, S-4.1, L-4.1, L-4.2 and
the optical Ve-4.2 types. The optical interfaces of the I-4, S-4.1, L-4.1 and L-4.2
interface types comply with ITU-T G.957 in features. The optical interface of the
Ve-4.2 type complies with the standards defined by Huawei.
Specification of Supports detection and query of the information on the optical module.
the optical module The optical interface supports the function of setting the on/off state of
the laser and the ALS function.
Supports the usage and monitoring of the pluggable optical module SFP.
Service Supports VC-12, VC-3, and VC-4 services and VC-4-4c concatenation
processing services.
Overhead Supports the processing of the SOH bytes of the STM-4 signals.
processing Supports the transparent transmission and termination of the POH bytes.
Supports the setting and query of the J0/J1/C2 bytes.
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Protection scheme Supports the two-fiber MSP protection ring, four-fiber MSP protection
ring, linear MSP, SNCP, SNCTP, and SNCMP.
Supports the optical-path-shared MSP and SNCP protection.
Figure 5-17 Block diagram for the working principle of the SL4
155 MHz Reference clock
155 MHz Cross-connect unit
PLL
....
Cross-connect unit A
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section MST: multiplex section termination MSA: multiplex section adaptation
termination
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery
CDR Module
l It recovers the data signal and the clock signal.
RST
l In the receive direction, RST performs frame alignment detection (A1, A2), regenerator
section trace recovery (J0) and mismatch detection, BIP-8 errored block count.
l In the transmit direction, RST performs frame alignment insertion, regenerator section path
trace insertion, BIP-8 calculation and insertion.
MST
l In the receive direction, MST performs BIP-24 errored block count, multiplex section-
remote error indication (MS_REI) recovery, multiplex section-remote defect indication
(MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection.
l In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI
MS_RDI and MS_AIS insertion.
l MST provides extraction or insertion of K1 byte and K2 byte.
MSA
l In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS
detection, pointer justification.
l In the transmit direction, MST it performs administration unit group (AUG) assembly,
AU-4 pointer generation, AU_AIS generation.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring)
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
DC/DC Converter
It provides the board with required DC voltages. It converts the –48/–60 V power supply to the
following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
SL4
STAT
ACT
PROG
SRV
CLASS1
LASER
PRODUCT
OUT
IN
SL4
Figure 5-19 shows the appearance of the front panel of the R1SL4.
SL4
STAT
ACT
PROG
SRV
OUT IN
SL4
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There is one pair of optical interfaces on the front panel of the SL4. Table 5-25 lists the type
and usage of the optical interfaces.
The SL4 board can use the pluggable optical modules for easy maintenance.
l The R1SL4 can be housed in any of slots 2–3, 6–9 and 12–13 in the OptiX OSN 1500A
subrack.
l The N1SL4 can be housed in any of slots 12–13 in the OptiX OSN 1500A subrack.
l The N2SL4 can be housed in any of slots 12–13 in the OptiX OSN 1500A subrack.
l The R1SL4 can be housed in any of slots 1–3, 6–9 and 11–13 in the OptiX OSN 1500B
subrack.
l The N1SL4 can be housed in any of slots 11–13 in the OptiX OSN 1500B subrack.
l The N2SL4 can be housed in any of slots 11–13 in the OptiX OSN 1500B subrack.
Table 5-26 lists the relation between the board feature code and optical interface type for the
SL4.
Table 5-26 Relation between the board feature code and the optical interface type of the SL4
You can use the T2000 to set the following parameters for the SL4:
l J0
l J1
l C2
Item Specification
Item Specification
Mechanical Specifications
The mechanical specifications of the N1SL4/N2SL4 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.0
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the N1SL4/N2SL4 is
15 W.
In the normal temperature (25℃), the maximum power consumption of the R1SL4 is 10 W.
5.7 SLD4
This section describes the SLD4, a 2 x STM-4 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
Table 5-28 lists the details on the versions of the SLD4 board.
Item Description
Difference The N2SLD4 supports the TCM function. The N1SLD4 and R1SLD4
do not support the TCM function. The SLD4 board of the R1SLD4 is
housed in a divided slot.
Basic function Receives and transmits 2 x STM-4 optical signals, and processes 2 x
STM-4 standard or concatenation services.
Specification of Supports standard optical interfaces of the I-4, S-4.1, L-4.1, L-4.2 and
the optical Ve-4.2 types. The optical interfaces of the I-4, S-4.1, L-4.1 and L-4.2
interface types comply with ITU-T G.957 in features. The optical interface of the
Ve-4.2 type complies with the standards defined by Huawei.
Specifications of Supports detection and query of the information on the optical module.
the optical module The optical interface supports the function of setting the on/off state of
the laser and the ALS function.
Supports the usage and monitoring of the pluggable optical module SFP.
Service Supports VC-12, VC-3, and VC-4 services and VC-4-4c concatenation
processing services.
Overhead Supports the processing of the SOH bytes of the STM-4 signals.
processing Supports the transparent transmission or termination of the POH bytes.
Supports the setting and query of the J0/J1/C2 bytes.
Supports one to two channels of ECC communication.
Alarm and Provides rich alarms and performance events for easy management and
performance event maintenance of the equipment.
Protection scheme Supports the two-fiber MSP protection ring, four-fiber MSP protection
ring, linear MSP, SNCP, SNCTP, and SNCMP.
Supports the optical-path-shared MSP and SNCP protection.
Figure 5-20 Block diagram for the working principle of the SLD4
155 MHz Reference clock
155 MHz Cross-connect unit
PLL
....
Cross-connect unit A
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section MST: multiplex section termination MSA: multiplex section adaptation
termination
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery
CDR Module
l It recovers the data signal and the clock signal.
RST
l In the receive direction, RST performs frame alignment detection (A1, A2), regenerator
section trace recovery (J0) and mismatch detection, BIP-8 errored block count.
l In the transmit direction, RST performs frame alignment insertion, regenerator section path
trace insertion, BIP-8 calculation and insertion.
MST
l In the receive direction, MST performs BIP-24 errored block count, multiplex section-
remote error indication (MS_REI) recovery, multiplex section-remote defect indication
(MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection.
l In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI
MS_RDI and MS_AIS insertion.
l MST provides extraction or insertion of K1 byte and K2 byte.
MSA
l In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS
detection, pointer justification.
l In the transmit direction, MST it performs administration unit group (AUG) assembly,
AU-4 pointer generation, AU_AIS generation.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring)
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
DC/DC Converter
It provides the board with required DC voltages. It converts the –48/–60 V power supply to the
following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
SLD4
STAT
ACT
PROG
SRV
CLASS1
LASER
PRODUCT
OUT1 IN1
OUT2 IN2
SLD4
Figure 5-22 shows the appearance of the front panel of the R1SLD4.
SLD4
STAT
ACT
PROG
SRV
OUT IN
OUT IN
SLD4
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are two pairs of optical interfaces on the front panel of the SLD4. Table 5-30 lists the
type and usage of the optical interfaces.
The SLD4 board can use the pluggable optical modules for easy maintenance.
Table 5-31 Relation between the board feature code and the optical interface type of the SLD4
SSN1SLD410, 10 S-4.1
SSN2SLD410
SSN1SLD411, 11 L-4.1
SSN2SLD411
SSN1SLD412, 12 L-4.2
SSN2SLD412
SSN1SLD413, 13 Ve-4.2
SSN2SLD413
SSN1SLD414, 14 I-4
SSN2SLD414
You can use the T2000 to set the following parameters for the SLD4:
l J0
l J1
l C2
Item Specification
Item Specification
Overload –8 –8 –8 –8 –13
optical power
(dBm)
Mechanical Specifications
The mechanical specifications of the N1SLD4/N2SLD4 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.0
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the N1SLD4/N2SLD4
is 15 W.
In the normal temperature (25℃), the maximum power consumption of the R1SLD4 is 11 W.
5.8 SLQ4
This section describes the SLQ4, a 4 x STM-4 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
Difference The N2SLQ4 supports the TCM function. The N1SLQ4 does not support
the TCM function.
Specification of Supports standard optical interfaces of the I-4, S-4.1, L-4.1, L-4.2 and
the optical Ve-4.2 types. The optical interfaces of the I-4, S-4.1, L-4.1 and L-4.2 types
interface comply with ITU-T G.957 in features. The optical interface of the Ve-4.2
type complies with the standards defined by Huawei.
Specification of Supports detection and query of the information on the optical module.
the optical The optical interface supports the function of setting the on/off state of
module the laser and the ALS function.
Supports the usage and monitoring of the pluggable optical module SFP .
Service Supports VC-12, VC-3, and VC-4 services and VC-4-4c concatenation
processing services.
Overhead Supports the processing of the SOH bytes of the STM-4 signals.
processing Supports the transparent transmission or termination of the POH bytes.
Supports the setting and query of the J0/J1/C2 bytes.
Supports one to four channels of ECC communication.
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Protection Supports the two-fiber MSP protection ring, four-fiber MSP protection
scheme ring, linear MSP, SNCP, SNCTP and SNCMP.
Supports the optical-path-shared MSP and SNCP protection.
Figure 5-23 Block diagram for the working principle of the SLQ4
155 MHz Reference clock
155 MHz Cross-connect unit
PLL
....
Cross-connect unit A
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section MST: multiplex section termination MSA: multiplex section adaptation
termination
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery
CDR Module
l It recovers the data signal and the clock signal.
RST
l In the receive direction, RST performs frame alignment detection (A1, A2), regenerator
section trace recovery (J0) and mismatch detection, BIP-8 errored block count.
l In the transmit direction, RST performs frame alignment insertion, regenerator section path
trace insertion, BIP-8 calculation and insertion.
MST
l In the receive direction, MST performs BIP-24 errored block count, multiplex section-
remote error indication (MS_REI) recovery, multiplex section-remote defect indication
(MS_RDI) and multiplex section-alarm indication signal (MS_AIS) detection.
l In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI
MS_RDI and MS_AIS insertion.
l MST provides extraction or insertion of K1 byte and K2 byte.
MSA
l In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS
detection, pointer justification.
l In the transmit direction, MST it performs administration unit group (AUG) assembly,
AU-4 pointer generation, AU_AIS generation.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring)
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
DC/DC Converter
It provides the board with required DC voltages. It converts the –48/–60 V power supply to the
following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3 V power supply.
SLQ4
STAT
ACT
PROG
SRV
CLASS1
LASER
PRODUCT
OUT1
IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
SLQ4
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four pairs of optical interfaces on the front panel of the SLQ4. Table 5-35 lists the
type and usage of the optical interfaces.
The SLQ4 board can use the pluggable optical modules for easy maintenance.
Table 5-36 lists the relation between the board feature code and optical interface type for the
SLQ4.
Table 5-36 Relation between the board feature code and the optical interface type of the SLQ4
SSN1SLQ410, 10 S-4.1
SSN2SLQ410
SSN1SLQ411, 11 L-4.1
SSN2SLQ411
SSN1SLQ412, 12 L-4.2
SSN2SLQ412
SSN1SLQ413, 13 Ve-4.2
SSN2SLQ413
SSN1SLQ414, 14 I-4
SSN2SLQ414
You can use the T2000 to set the following parameters for the SLQ4:
l J0
l J1
l C2
Mechanical Specifications
The mechanical specifications of the SLQ4 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.0
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the SLQ4 is 16 W.
5.9 SL16
This section describes the SL16, a 1 x STM-16 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
The SL16 board has three versions, N1, N2 and N3. The difference among the three versions
lies in the support for the TCM function and AU-3 services.
5.9.2 Function and Feature
The SL16 board is used to receive and transmit 1 x STM-16 optical signals and to process the
overhead.
5.9.3 Working Principle and Signal Flow
The SL16 board consists of the O/E conversion module, MUX/DEMUX module, SDH overhead
processing module, RST and so on.
5.9.4 Front Panel
On the front panel of the SL16, there are indicators, interfaces, barcode, laser safety class label,
and APD alarm label.
5.9.5 Valid Slots
The SL16 board can be housed in any of slots 12–13 in the OptiX OSN 1500A subrack, and any
of slots 11–13 in the OptiX OSN 1500B subrack.
5.9.6 Board Feature Code
The code behind the board name in the barcode is the board feature code. The board feature code
of the SL16 indicates the optical interface type.
5.9.7 Board Configuration Reference
You can use the T2000 to set parameters for the SL16.
5.9.8 Technical Specifications
The technical specifications of the SL16 cover the optical interface specifications, board
dimensions, weight and power consumption.
Difference The N1SL16 does not support the TCM function and AU-3 services.
The N2SL16 supports the TCM function, and it can be configured with
AU-3 services.
The TCM function and AU-3 services cannot be configured on the
N3SL16 at the same time.
The N3SL16 supports the board version replacement function.
Item Description
Specification Supports optical interfaces of the L-16.2, L-16.2Je, V-16.2Je (with BA),
of the optical U-16.2Je (with BA and PA) types. The optical interface of the L-16.2 type
interface complies with ITU-T G.957 and ITU-T G.692 in features. The optical
interfaces of the L-16.2Je, V-16.2Je (with BA), and U-16.2Je (with BA and
PA) comply with the standards defined by Huawei.
Supports the output of standard wavelengths that comply with ITU-T G.692.
The U-16.2Je optical interface can be directly connected to the DWDM
equipment.
Specification Supports detection and query of the information on the optical module.
of the optical The optical interface supports the function of setting the on/off state of the
module laser and the ALS function.
Service Supports VC-12, VC-3, and VC-4 services and VC-4-4c, VC-4-8c, and
processing VC-4-16c concatenation services.
Supports AU-3 services.
Processing of Processes two sets of K bytes. One SL16 board supports a maximum of two
the K byte MSP protection rings.
Function SL16
and Feature
Specifications Supports the setting and query of the REG working mode.
of the REG
Protection Supports the two-fiber MSP protection ring, four-fiber MSP protection ring,
scheme linear MSP protection, SNCP, SNCTP and SNCMP.
Supports the optical-path-shared MSP and SNCP protection.
Figure 5-25 shows the block diagram for the working principle of the SL16.
Figure 5-25 Block diagram for the working principle of the SL16
155 MHz 155 MHz Reference clock Cross-connect
PLL unit
K1 and K2
2.488 2.488 16 x 155 K1 and K2 insertion/extration Cross-connect
Gbit/s Gbit/s Mbit/s unit
O/E DEMUX
high speed bus Cross-connect
S unit A
P 2.488 16 x 155
2.488 I
Gbit/s Mbit/s
RST MST MSA HPT
Gbit/s high speed bus Cross-connect
O/E MUX unit B
DCC
SCC unit
SDH overhead processing module
l In the transmit direction, it converts the electrical signals into SDH optical signals, and then
send optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function to shut down the laser.
MUX/DEMUX Module
l In the receive direction, the DEMUX part demultiplexes the high rate electrical signals into
multiple parallel electrical signals, and recovery the clock signal at the same time.
l In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high rate electrical signals.
RST
l In the receiving direction, RST performs frame alignment detection (A1, A2), regenerator
section trace recovery (J0) and mismatch detection, and BIP-8 errored block count.
l In the transmitting direction, RST performs frame alignment insertion, regenerator section
path trace insertion, BIP-8 calculation and insertion.
MST
l In the receiving direction, MST performs BIP-24 errored block count, MS_REI recovery,
MS_RDI and MS_AIS detection.
l In the transmitting direction, MST performs calculation and insertion of BIP-24, insertion
of MS_REI MS_RDI and MS_AIS.
l Provides extraction or insertion of K1 byte and K2 byte.
MSA
l In the receiving direction, MSA performs AU4 pointer interpretation, LOP and AIS
detection, pointer justification.
l In the transmitting direction, MSA performs AUG assembly, AU-4 pointer generation, and
AU_AIS generation.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring)
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
l Tracing the clock signal from the active and the standby cross-connect units.
l Implements laser controlling function.
l Realizes the pass-through of orderwire and ECC bytes between the paired slots constituting
the ADM when the CXL is not online.
l Selects the clock and frame header from the active or the standby cross-connect units.
l Controls the indicator on the board.
SL16
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
! APD
Receiver
MAX:-9dBm
OUT
IN
SL16
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There is one pair of optical interfaces on the front panel of the SL16. Table 5-40 lists the type
and usage of the optical interfaces.
Table 5-41 lists the relation between the board feature code and optical interface type for the
SL16.
Table 5-41 Relation between the board feature code and the optical interface type for the SL16
SSN1SL1602, 02 L-16.2Je
SSN2SL1602, SSN3SL1602
SSN1SL1603, 03 V-16.2Je
SSN2SL1603, SSN3SL1603
SSN1SL1604, 04 U-16.2
SSN2SL1604, SSN3SL1604
You can use the T2000 to set the following parameters for the SL16:
l J0
l J1
l C2
Item Specification
Launched –2 to +3 5 to 7 –2 to +3 13 to 15 –2 to +3 15 to 18
optical (without (with BA) (without (with BA)
power BA) BA and
(dBm) PA)
Item Specification
Note: The optical interface of the Le-16.2 type is the same as the optical interface of the
L-16.2Je type.
The launched optical power of the optical interface of the V-16.2Je type is measured when
the booster amplifer (BA) is added. The launched optical power of the optical interfaces of
the V-16.2Je and U-16.2Je types ranges from –2 dBm to –3 dBm when no BA is added.
Table 5-43 Specifications of the ITU-T G.692-compliant optical interfaces that output standard
wavelengths
Item Specification
Mechanical Specifications
The mechanical specifications of the SL16 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.1
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the N1SL16 is 20 W.
In the normal temperature (25℃), the maximum power consumption of the N2SL16 is 20 W.
In the normal temperature (25℃), the maximum power consumption of the N3SL16 is 22 W.
5.10 SL16A
This section describes the SL16A, a 1 x STM-16 optical interface board, in terms of the version,
function, working principle, front panel and specifications.
Functional The SL16A has three versions, N1, N2, and N3.
version
Item Description
Difference The N1SL16A does not support the TCM function and AU-3 services.
The N2SL16A supports the TCM function, and it can be configured with
AU-3 services.
The TCM function and AU-3 services cannot be configured on the
N3SL16A at the same time.
The N3SL16A supports the board version replacement function and can
replace the N3SL16A and N1SL16A. After the N3SL16A and N1SL16A
are replaced, the N3SL16A and N1SL16A are consistent with the
N1SL16A in configuration and service status.
Specification of the Supports optical interfaces of the I-16, S-16.1, L-16.1, and L-16.2 types.
optical interface The optical interfaces comply with ITU-T G.957 and ITU-T G.692 in
features.
Supports the output of standard wavelengths that comply with ITU-T
G.692 and can be directly connected to the DWDM equipment.
Specification of the Supports detection and query of the information on the optical module.
optical module The optical interface supports the function of setting the on/off state of
the laser and the ALS function.
Supports the usage and monitoring of the SFP pluggable optical
module.
Service processing Supports VC-12, VC-3, and VC-4 services and VC-4-4c, VC-4-8c, and
VC-4-16c concatenation services.
Overhead Supports the processing of the SOH bytes of the STM-16 signals.
processing Supports the transparent transmission and termination of the POH
bytes. Supports the setting and query of the J0 bytes.
Specifications of Supports the setting and query of the REG working mode.
the REG
Protection scheme Supports the two-fiber MSP protection ring, four-fiber MSP protection
ring, linear MSP protection, SNCP, SNCTP and SNCMP.
Supports the optical-path-shared MSP and SNCP protection.
Figure 5-27 shows the block diagram for the working principle of the N1SL16A and N2SL16A.
Figure 5-27 Block diagram for the working principle of the N1SL16A and N2SL16A
155 MHz 155 MHz Reference clock Cross-connect
PLL unit
K1 and K2
2.488 2.488 16 x 155 K1 and K2 insertion/extration Cross-connect
Gbit/s Gbit/s Mbit/s unit
O/E DEMUX
high speed bus Cross-connect
S unit A
P 2.488 16 x 155
2.488 I
Gbit/s Mbit/s
RST MST MSA HPT
Gbit/s high speed bus Cross-connect
O/E MUX unit B
DCC
SCC unit
SDH overhead processing module
Figure 5-28 shows the block diagram for the working principle of the N3SL16A.
Figure 5-28 Block diagram for the working principle of the N3SL16A
155 MHz 155 MHz Reference clock Cross-connect
PLL unit
K1 and K2
2.488 2.488 16 x 155 Cross-connect
Gbit/s Gbit/s Mbit/s K1 and K2 insertion/extration unit
O/E DEMUX
high speed bus Cross-connect
S unit A
P 2.488 16 x 155
2.488 I
Gbit/s Mbit/s
RST MST MSA HPT
Gbit/s high speed bus Cross-connect
O/E MUX unit B
DCC
SCC unit
SDH overhead processing module
MUX/DEMUX Module
l In the receive direction, the DEMUX part demultiplexes the high rate electrical signals into
multiple parallel electrical signals, and recovery the clock signal at the same time.
l In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high rate electrical signals.
RST
l In the receiving direction, RST performs frame alignment detection (A1, A2), regenerator
section trace recovery (J0) and mismatch detection, and BIP-8 errored block count.
l In the transmitting direction, RST performs frame alignment insertion, regenerator section
path trace insertion, BIP-8 calculation and insertion.
MST
l In the receiving direction, MST performs BIP-24 errored block count, MS_REI recovery,
MS_RDI and MS_AIS detection.
l In the transmitting direction, MST performs calculation and insertion of BIP-24, insertion
of MS_REI MS_RDI and MS_AIS.
l Provides extraction or insertion of K1 byte and K2 byte.
MSA
l In the receiving direction, MSA performs AU4 pointer interpretation, LOP and AIS
detection, pointer justification.
l In the transmitting direction, MSA performs AUG assembly, AU-4 pointer generation, and
AU_AIS generation.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring)
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
SL16A
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
! APD
Receiver
MAX:-9dBm
OUT
IN
SL16A
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There is one pair of optical interfaces on the front panel of the SL16A. Table 5-46 lists the type
and usage of the optical interfaces.
Table 5-47 Relation between the board feature code and the optical interface type
Board Feature Code Optical Interface Type
SSN1SL16A01, 01 I-16
SSN2SL16A01,
SSN3SL16A01
SSN1SL16A02, 02 S-16.1
SSN2SL16A02,
SSN3SL16A02
SSN1SL16A03, 03 L-16.1
SSN2SL16A03,
SSN3SL16A03
SSN1SL16A04, 04 L-16.2
SSN2SL16A04,
SSN3SL16A04
Item Specification
Launched –10 to –3 –5 to 0 –2 to +3 –2 to +3
optical
power
(dBm)
Overload –3 0 –9 –9
optical
power
(dBm)
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SL16A are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the N1SL16A and
N2SL16A are 20 W.
In the normal temperature (25℃), the maximum power consumption of the N3SL16A is 17 W.
5.11 SF16
This section describes the SF16, a 1 x STM-16 optical interface board with the out-band FEC
function, in terms of the version, function, working principle, front panel and specifications.
Basic function Receives and transmits 1 x OTU1 (2.666 Gbit/s, FEC) optical signals.
Supports the enabling or disabling of the FEC function.
Specification Supports optical interfaces of the Ve-16.2c, Ve-16.2d, and Ve-16.2f types.
of the optical The optical interfaces of the Ve-16.2c, Ve-16.2d, and Ve-16.2f types
interface comply with the standards defined by Huawei.
The optical interface supports the output of standard wavelengths that
comply with ITU-T G.692 and can be directly connected to the DWDM
equipment.
Specification Supports detection and query of the information on the optical module.
of the optical The optical interface supports the function of setting the on/off state of the
module laser and the ALS function.
Service Supports VC-12, VC-3, and VC-4 services and VC-4-4c, VC-4-8c, and
processing VC-4-16c concatenation services.
Supports AU-3 services.
The SF16 board encapsulates and encodes signals with the FEC function,
and processes overhead bytes, which comply with ITU-T G.709.
Overhead Supports the processing of the OTU, ODU, and OPU overhead bytes,
processing performance monitoring, and alarm detection, which comply with ITU-T
G.709.
Supports the processing of the SOH of the STM-16 signals.
Supports the transparent transmission and termination of the POH bytes.
Supports the setting and query of the J0/J1/C2 bytes.
Processing of Processes two sets of K bytes. One SF16 board supports a maximum of two
the K byte MSP protection rings.
Specification Supports the setting and query of the REG working mode.
of the REG
Protection Supports the two-fiber MSP protection ring, four-fiber MSP protection
scheme ring, linear MSP protection, SNCP, SNCTP and SNCMP.
Supports the optical-path-shared MSP and SNCP protection.
Figure 5-30 shows the block diagram for the working principle of the SF16.
Figure 5-30 Block diagram for the working principle of the SF16
155 MHz Reference clock
155 MHz PLL 155 MHz PLL Cross-connect unit
MUX/DEMUX Module
l In the receive direction, the DEMUX part demultiplexes the high rate electrical signals into
multiple parallel electrical signals, and recovers the clock signal at the same time.
l In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the FEC module into high rate electrical signals.
FEC Module
l In the downstream direction, the FEC encoding and decoding module receives 2.488 Gbit/
s SDH signals, which are sent by the SDH overhead processing chip. After frame search,
FEC encoding, data packets encapsulation and scrambling, the 2.488 Gbit/s SDH signals
are converted to 2.666 Gbit/s signals and then transmitted to the MUX module.
l In the upstream direction, signals take the reverse process. The FEC encoding and decoding
module receives the 2.666 Gbit/s signals from the DEMUX module. After frame search,
FEC encoding, data packets encapsulation and scrambling in the FEC module, the 2.488
Gbit/s signals are recovered and then transmitted to SDH overhead processing chip. The
frame format of the 2.666 Gbit/s signals complies with ITU G.709.
l The FEC processing module connects to the communication and control unit through a
CPU bus. The CPU controls working modes of the FEC module by configuring the internal
register. The working mode can be regenerator mode, that is, REG mode. The CPU can
monitor the performance through the internal register.
RST
l In the receive direction, RST performs frame alignment detection (A1, A2), regenerator
section trace recovery (J0), mismatch detection, BIP-8 errored block count.
l In the transmit direction, RST performs frame alignment insertion, regenerator section path
trace insertion, BIP-8 calculation and insertion.
MST
l In the receive direction, MST performs BIP-24 errored block count, MS_REI recovery,
MS_RDI and MS_AIS detection.
l In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI
MS_RDI and MS_AIS insertion.
l Provides extraction or insertion of K1 byte and K2 byte.
MSA
l In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS
detection, pointer justification.
l In the transmit direction, MSA performs AUG assembly, AU-4 pointer generation, and
AU_AIS generation.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring)
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
DC/DC Converter
It provides the board with required DC voltages. It converts the –48 V/–60 V power supply to
the following voltages: + 3.3 V, + 1.8 V, + 5 V. It also provides protection for +3.3V power
supply.
SF 16
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT
IN
SF16
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There is one pair of optical interfaces on the front panel of the SF16. Table 5-50 lists the type
and usage of the optical interfaces.
NOTE
Launched optical –5 to –1 –5 to –1 –5 to –1
power (dBm)b
a: The numbers in the brackets indicate the specifications. For example, BA (14) indicates
that the optical power amplified by the BA is 14 dBm. "FEC+BA+PA+RA" indicates that the
optical interface is used with the FEC, PA, Raman amplifier and BA.
b: The specifications are for the optical module itself rather than for the amplifier.
c: The specifications are for the BA.
d: The specifications are for the PA.
Table 5-52 Specifications of the ITU-T G.692-compliant optical interfaces that output standard
wavelengths
Item Specification
Item Specification
Mechanical Specifications
The mechanical specifications of the SF16 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.1
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the SF16 is 26 W.
This chapter describes the PDH processing boards for the E1/T1, E3/T3, E4/STM-1, and DDN
signals.
6.1 PL1
This section describes the PL1, a 16 x E1 processing board, in terms of the version, function,
working principle, front panel and specifications.
6.2 PD1
This section describes the PD1, a 32 x E1 processing board, in terms of the version, function,
working principle, front panel and specifications.
6.3 PQ1
This section describes the PQ1, a 63 x E1 processing board, in terms of the version, function,
principle, front panel, configuration and specifications.
6.4 PQM
This section describes the PQM, a 63 x E1/T1 processing board, in terms of the version, function,
principle, front panel, configuration and specifications.
6.5 PL3
This section describes the PL3, a 3 x E3/T3 processing board, in terms of the version, function,
principle, front panel, configuration and specifications.
6.6 PL3A
This section describes the PL3A, a 3 x E3/T3 processing board, in terms of the version, function,
principle, front panel, configuration and specifications.
6.7 PD3
This section describes the PD3, a 6 x E3/T3 processing board, in terms of the version, function,
principle, front panel, configuration and specifications.
6.8 PQ3
This section describes the PQ3, a 12 x E3/T3 processing board, in terms of the version, function,
principle, front panel, configuration and specifications.
6.9 DX1
This section describes the DX1, a DDN interface convergence board, in terms of the version,
function, principle, front panel, configuration and specifications.
6.10 DXA
This section describes the DXA, a DDN convergence board, in terms of the version, function,
principle, front panel, configuration and specifications.
6.11 SPQ4
This section describes the SPQ4, a 4 x E1/STM-1 processing board, in terms of the version,
function, working principle, front panel and specifications.
6.1 PL1
This section describes the PL1, a 16 x E1 processing board, in terms of the version, function,
working principle, front panel and specifications.
6.1.1 Version Description
The functional version of the PL1 is R1.
6.1.2 Function and Feature
The PL1 is used to directly access and process E1 electrical signals, to process the overhead, to
report alarms and performance events and to provide the maintenance features.
6.1.3 Working Principle and Signal Flow
The PL1 consists of the PPI, E1 mapping/demapping, interface conversion module,
communication and control module and so on.
6.1.4 Front Panel
On the front panel of the PL1, there are indicators and interfaces.
6.1.5 Valid Slots
The PL1 can be housed in any of slots 6–9 of the OptiX OSN 1500A subrack or the OptiX OSN
1500B subrack.
6.1.6 Board Feature Code
The code behind the board name in the barcode is the board feature code. The board feature code
of the PL1 indicates the interface impedance type.
6.1.7 Board Configuration Reference
You can use the T2000 to set parameters for the PL1.
6.1.8 Technical Specifications
The technical specifications of the PL1 cover the optical interface specifications, board
dimensions, weight and power consumption.
Overhead processing Supports the transparent transmission and termination of POH bytes
at the VC-12 level, such as the J2 byte.
Alarm and Provides rich alarms and performance events for easy management
performance event and maintenance of the equipment.
+3.3 V
DC/DC Fuse -48 V/ -60 V
+2.5 V converter -48 V/ -60 V
DC/DC
+1.8 V converter Fuse
+3.3 V backup
power
E1
STM-1
LPA LPT HPA HPT
LPOH(V5/J2/N2/
K4)
insertion
PDH AIS TU-AIS/TU-LOP
Detector Detector
LPOH(V5/J2/N2/
K4)
Extraction
E1 STM-1
LPA LPT HPA HPT
PPI
The PPI module mainly consists of line interface units (LIUs). It provides inloop and outloop
function. This module:
E1 mapping/demapping
l LPA
l The 2 Mbit/s plesiochronous stream is inserted in a VC-12 container to be adapted so as to
be transported into the synchronous network for check of the PDH AIS.
l LPT
l The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are
distributed within a 125 us interval (for example, one STM–1 period), and consists of the
VC-12 container and POH. The latter contains nine octets equally distributed within the
frame bytes for VC-12: V5, J2, N2, and K4.
l HPA
l HPA generates and processes channel level TU-PTR. In the receive direction, the signals
are split into VC-12s, which are located and isolated in TU-12. TU-PTR is processed. TU-
AIS and TU-LOP alarms are monitored. In the transmit direction, VC-12s are located
precisely and added with TU-PTR. 63 TUG-3s are multiplexed into a VC-4 by bytes
interleaving. The sequence is: TUG2->TUG3->VC-4.
l HPT
l The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM–1 period), and consists of the
C4 container and POH.
l MST and RST
l These two functions are necessary to create a proprietary STM–1 signal in order to interface
the “E1 mapping/demapping” block with the multiplex unit.
DC/DC converter
It provides the board with required DC voltages. It converts the –48 V/–60 V power supply to
the following voltages: + 2.5 V, + 3.3 V, + 1.8 V. In addition, protection for +3.3 V power are
provided to the board.
PL1
STAT
ACT
PROG
SRV
1-16
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are 16 2mmHM interfaces on the front panel of the PL1. Table 6-2 lists the type and usage
of the interfaces.
Table 6-3 Relation between the board feature code and the optical interface type of the PL1
Board Feature Code Interface Impedance Type
l V5 byte
l Tributary loopback
l Service loading indication
Mechanical Specifications
The mechanical specifications of the PL1 are as follows:
l Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W)
l Weight (kg): 0.5
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the PL1 is 7 W.
6.2 PD1
This section describes the PD1, a 32 x E1 processing board, in terms of the version, function,
working principle, front panel and specifications.
Table 6-5 lists the details on the versions of the PD1 board.
Item Description
Difference The R2PD1 supports the E13 function and the board version replacement
function.
Function PD1
and
Feature R1PD1 R2PD1
Function PD1
and
Feature R1PD1 R2PD1
Overhead Supports the transparent transmission and termination of the POH bytes at the
processing VC-12 level, such as the J2 byte.
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Protection Supports the TPS protection when used with the electrical interface switching
scheme board.
+3.3 V
DC/DC Fuse -48 V/ -60 V
+2.5 V converter -48 V/ -60 V
DC/DC
+1.8 V converter Fuse
+3.3 V backup
power
E1
STM-1
LPA LPT HPA HPT
LPOH(V5/J2/N2/
K4)
insertion
PDH AIS TU-AIS/TU-LOP
Detector Detector
LPOH(V5/J2/N2/
K4)
Extraction
E1 STM-1
LPA LPT HPA HPT
PPI
The PPI module mainly consists of line interface units (LIUs). It provides inloop and outloop
function. This module:
E1 mapping/demapping
l LPA
l The 2 Mbit/s plesiochronous stream is inserted in a VC-12 container to be adapted so as to
be transported into the synchronous network for check of the PDH AIS.
l LPT
l The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are
distributed within a 125 us interval (for example, one STM–1 period), and consists of the
VC-12 container and POH. The latter contains nine octets equally distributed within the
frame bytes for VC-12: V5, J2, N2, and K4.
l HPA
l HPA generates and processes channel level TU-PTR. In the receive direction, the signals
are split into VC-12s, which are located and isolated in TU-12. TU-PTR is processed. TU-
AIS and TU-LOP alarms are monitored. In the transmit direction, VC-12s are located
precisely and added with TU-PTR. 63 TUG-3s are multiplexed into a VC-4 by bytes
interleaving. The sequence is: TUG2->TUG3->VC-4.
l HPT
l The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM–1 period), and consists of the
C4 container and POH.
l MST and RST
l These two functions are necessary to create a proprietary STM–1 signal in order to interface
the “E1 mapping/demapping” block with the multiplex unit.
DC/DC converter
It provides the board with required DC voltages. It converts the –48 V/–60 V power supply to
the following voltages: + 2.5 V, + 3.3 V, + 1.8 V. In addition, protection for +3.3 V power are
provided to the board.
PD1
STAT
ACT
PROG
SRV
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the PD1.
In the OptiX OSN 1500A subrack, the PD1 is used with the L75S or L12S, which provides 75-
ohm or 120-ohm E1 interfaces. For details, see the sections that describe the L75S and L12S.
In the OptiX OSN 1500B subrack, the PD1 is used with the D75S or D12S, which provides 75-
ohm or 120-ohm E1 interfaces. For details, see the sections that describe the D75S and D12S.
In the OptiX OSN 1500A subrack, the PD1 can be housed in any of half-width slots 2 and 12.
Table 6-7 lists the valid slots for the PD1 and corresponding slots for the L75S and L12S.
Table 6-7 Valid slots for the PD1 and corresponding slots for the L75S and L12S in the OptiX
OSN 1500A subrack
Valid Slot for the PD1 Corresponding Slot for the L75S and L12S
NOTE
Slot 2 can house a protection board of the TPS protection. The board housed in slot 2 protects the board
housed in slot 12.
In the OptiX OSN 1500B subrack, the PD1 can be housed in any of slots 1–3, 6–8 and 11–13.
Table 6-8 lists the valid slots for the PD1 and the corresponding slots for the D75S and D12S.
Table 6-8 Valid slots for the PD1 and corresponding slots for the D75S and D12S in the OptiX
OSN 1500B subrack
Valid Slot for the PD1 Corresponding Slot for the D75S and
D12S
Slot 2 Slot 14
Slot 3 Slot 16
NOTE
l Boards housed in slots 7 and 12 share the interface board housed in slot 15. The boards housed in slots
7 and 12 cannot be used with the interface board housed in slot 15 to add or drop services at the same
time.
l Boards housed in slots 8 and 13 share the interface board housed in slot 17. The boards housed in slots
8 and 13 cannot be used with the interface board housed in slot 17 to add or drop services at the same
time.
l Slot 1 can house a protection board of the TPS protection. The board housed in slot 1 protects the boards
housed in slots 2 and 3.
l Slot 11 can house a protection board of the TPS protection. The board housed in slot 11 protects the
boards housed in slots 12 and 13.
l Slot 6 can house a protection board of the TPS protection. The board housed in slot 6 protects the boards
housed in slots 7 and 8.
Table 6-9 Relation between the board feature code and the interface impedance type
Board Feature Code Interface Impedance
Type
Protection Principle
In the OptiX OSN 1500A subrack, used with the L75S or L12S, two PD1 boards can get 1:1
TPS protection. Figure 6-7 shows the principle for the TPS protection of the PD1.
Figure 6-7 Principle of the TPS protection for the PD1 in the OptiX OSN 1500A subrack
S S
L L
O O
E1protection bus
T T
6 7
L75S
L75S
E1
service
S S bus
L L
O O
T T
2 12
Fail
Protection
Working
PD1 PD1
Detect
TPS
board fault
switching
Cross-connect and timing control bus
board
In the OptiX OSN 1500B subrack, used with the D75S or D12S, the PD1 boards can get 1:N
(1≤2) TPS protection. Figure 6-8 shows the principle of the TPS protection for the PD1.
Figure 6-8 Principle of the TPS protection for the PD1 in the OptiX OSN 1500B subrack
E1 protection bus
D75S
D75S
E1
service bus
Fail
Detect
board fault TPS switching
control bus
Cross-connect and
timing board
When detecting a failure in the working PD1 board, the cross-connect board issues a command
to switch the services from the faulty PD1 to the protection PD1. In this way, services are
protected.
Hardware Configuration
In the OptiX OSN 1500A subrack, PD1 boards can be housed in the half-width slots to realize
the 1:1 TPS protection. Figure 6-9 shows the slot configuration for the 1:1 TPS protection for
the PD1.
Figure 6-9 Slot configuration for the 1:1 TPS protection for the PD1 in the OptiX OSN 1500A
subrack
Slot 1 Slot 11 Slot 6 L75S(17~32)
Table 6-10 shows the slot configuration for the 1:2 TPS protection for the PD1 in the OptiX
OSN 1500B subrack.
Table 6-10 Slot configuration for the 1:2 TPS protection for the PD1 in the OptiX OSN 1500B
subrack
The two protection groups that contain slots 6 and 11 share the protection bus and thus cannot
coexist. Before the slots are divided, the OptiX OSN 1500B supports one group of TPS protection
for E1 services. After the slots are divided, the OptiX OSN 1500B supports a maximum of two
TPS protection groups for E1 services.
You can use the T2000 to set the following parameters for the PD1:
l J2 byte
l V5 byte
l Tributary loopback
l Service loading indication
Mechanical Specifications
The mechanical specifications of the PD1 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the R1PD1 is 15 W.
In the normal temperature (25℃), the maximum power consumption of the R2PD1 is 10.4 W.
6.3 PQ1
This section describes the PQ1, a 63 x E1 processing board, in terms of the version, function,
principle, front panel, configuration and specifications.
Table 6-11 lists the details on the versions of the PQ1 board.
Item Description
Item Description
Difference The N2PQ1 supports the E13 function and the board version replacement
function.
The N2PQ1 does not perform the tributary timing function.
Replaceability When the tributary timing function is not required, the N1PQ1A can be
replaced by the N2PQ1A.
When the tributary timing function is not required, the N1PQ1B can be
replaced by the N2PQ1B.
NOTE: When the impedance of interfaces is ignored, the PQ1A (75 ohms) and PQ1B (100
ohms/120 ohms) are called PQ1 hereinafter.
Overhead Supports the transparent transmission and termination of the POH bytes at the
processing VC-12, such as the J2 byte.
Alarm and Provides rich alarms and performance events for easy management and
performanc maintenance of the equipment.
e event
Function PQ1
and
Feature N1PQ1 N2PQ1
Protection Supports the TPS protection when used with the interface board.
scheme When the working board is the PQ1, the protection board can be the PQM. In
this way, the hybrid protection is provided.
6 x 1.5 Mbit/s/
E1/T1 6 x 2 Mbit/s 155 Mbit/s High speed bus Cross-connect unit
LIU
E1/T1 Interface
A
P
P mapping/ coversion
I 6 x 1.5 Mbit/s/ demapping module
E1/T1 155 Mbit/s High speed bus Cross-connect unit
LIU 6 x 2 Mbit/s
B
+3.3 V
DC/DC Fuse -48 V/ -60 V
+2.5 V converter -48 V/ -60 V
DC/DC
+1.8 V converter Fuse
+3.3 V backup
power
Figure 6-11 shows the block diagram of the E1/T1 mapping/ demapping.
E1/T1
STM-1
LPA LPT HPA HPT
LPOH(V5/J2/N2/
K4)
insertion
PDH AIS TU-AIS/TU-LOP
Detector Detector
LPOH(V5/J2/N2/
K4)
Extraction
E1/T1 STM-1
LPA LPT HPA HPT
PPI
The PPI module mainly consists of line interface units (LIUs). It provides inloop and outloop
function. This module:
E1/T1 mapping/demapping
l LPA
l The 2 Mbit/s (1.5 Mbit/s) plesiochronous stream is inserted in a VC-12 container to be
adapted so as to be transported into the synchronous network for check of the PDH AIS.
l LPT
l The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are
distributed within a 125 us interval (for example, one STM–1 period), and consists of the
VC-12 container and POH. The latter contains nine octets equally distributed within the
frame bytes for VC-12: V5, J2, N2, and K4.
l HPA
l HPA generates and processes channel level TU-PTR. In the receive direction, the signals
are split into VC-12s, which are located and isolated in TU-12. TU-PTR is processed. TU-
AIS and TU-LOP alarms are monitored. In the transmit direction, VC-12s are located
precisely and added with TU-PTR. 63 TUG-3s are multiplexed into a VC-4 by bytes
interleaving. The sequence is: TUG2->TUG3->VC-4.
l HPT
l The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM–1 period), and consists of the
C4 container and POH.
l MST and RST
l These two functions are necessary to create a proprietary STM–1 signal in order to interface
the “E1/T1 mapping/demapping” block with the multiplex unit.
DC/DC converter
It provides the board with required DC voltages. It converts the –48 V/–60 V power supply to
the following voltages: + 2.5 V, + 3.3 V, + 1.8 V. In addition, protection for +3.3 V power are
provided to the board.
PQ1
STAT
ACT
PROG
SRV
PQ1
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the PQ1.
The D75S, D12S or D12B provides 75-ohm or 120-ohm E1/T1 interfaces for the PQ1. For
details, see the sections that describe the D75S, D12S and D12B.
The OptiX OSN 1500A does not support the PQ1 board.
In the OptiX OSN 1500B subrack, the PQ1 can be housed in any of slots 11–13, and must be
used with the D75S, D12S or D12B.
Table 6-13 lists the valid slots for the PQ1 and corresponding slots for the D75S, D12S or D12B.
Table 6-13 Valid slots for the PQ1 and corresponding slots for the D75S, D12S or D12B in the
OptiX OSN 1500B subrack
Valid Slot for the PQ1 Corresponding Slot for the D75S, D12S
and D12B
NOTE
l Slot 11 can house a protection board of the TPS protection. The board housed in slot 11 protects the
boards housed in slots 12 and 13.
l If the interface board for the boards housed in slot 12 and 13 is the D12B, the boards housed in slot 12
and 13 cannot get the TPS protection.
Table 6-14 lists the relation between the board feature code and interface impedance type for
the PQ1.
Table 6-14 Relation between the board feature code and the interface impedance type
Protection Principle
In the OptiX OSN 1500B subrack, used with the D75S or D12S, the PQ1 can get the 1:N (≤2)
TPS protection. Figure 6-13 shows the principle of the TPS protection for the PQ1.
Figure 6-13 Principle of the TPS protection for the PQ1 in the OptiX OSN 1500B subrack
S S S S
E1 L L L L
protection bus O O O O
T T T T
14 15 16 17
D75S
D75S
D75S
D75S
E1
service
bus
Fail
Protection
Working
Working
Detect
board fault
TPS switching
Cross-connect and control bus
timing board
When detecting a failure in the working PD1 board, the cross-connect board issues a command
to switch the services from the faulty PQ1 to the protection PQ1. In this way, services are
protected.
Hardware Configuration
Table 6-15 lists the slot configuration for the 1:2 TPS protection for the PQ1 in the OptiX OSN
1500B subrack.
Table 6-15 Slot configuration for the 1:2 TPS protection for the PQ1 in the OptiX OSN 1500B
subrack
Working Board Protection Board Slot
PQ1A (75 ohms) PQ1A (75 ohms) Slot 11 can house the protection board.
The board in slot 11 protects the boards
PQ1B (120 ohms) PQ1B (120 ohms) or in slots 12 and 13. Figure 6-14 shows the
PQM slot configuration for the 1:2 TPS
protection for the PQ1.
Figure 6-14 Slot configuration for 1:2 TPS protection of the PQ1
Slot 14 D75S
Slot 18 PIU
Slot 15 D75S
Slot 16 D75S
Slot 19 PIU
Slot 17 D75S
Slot 11 Protection Slot 6
Slot 20 Slot 12 Working Slot 7
Slot 13 Working Slot 8
FAN
Slot 4 CXL16/4/1 Slot 9 EOW
Slot 5 CXL16/4/1 Slot 10 AUX
You can use the T2000 to set the following parameters for the PQ1:
l J2 byte
l V5 byte
l Tributary loopback
l Service loading indication
Mechanical Specifications
The mechanical specifications of the PQ1 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the N1PQ1 is 19 W.
In the normal temperature (25℃), the maximum power consumption of the N2PQ1 is 13 W.
6.4 PQM
This section describes the PQM, a 63 x E1/T1 processing board, in terms of the version, function,
principle, front panel, configuration and specifications.
Function PQM
and Feature
Service The PQM accesses and processes 63 x E1/T1 electrical signals when used
processing with the interface board. Each channel can be configured as E1 or T1.
Function PQM
and Feature
Overhead Supports the transparent transmission and termination of the POH bytes at
processing the VC-12 level, such as the J2 byte.
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Protection When used with the interface board, the PQM supports the TPS protection.
scheme When the working board is the PQ1, the protection board can be the PQM.
In this way, the hybrid protection is provided.
6 x 1.5 Mbit/s/
E1/T1 6 x 2 Mbit/s 155 Mbit/s High speed bus Cross-connect unit
LIU
E1/T1 Interface
A
P
P mapping/ coversion
I 6 x 1.5 Mbit/s/ demapping module
E1/T1 155 Mbit/s High speed bus Cross-connect unit
LIU 6 x 2 Mbit/s
B
+3.3 V
DC/DC Fuse -48 V/ -60 V
+2.5 V converter -48 V/ -60 V
DC/DC
+1.8 V converter Fuse
+3.3 V backup
power
Figure 6-16 shows the block diagram of the E1/T1 mapping/ demapping.
E1/T1
STM-1
LPA LPT HPA HPT
LPOH(V5/J2/N2/
K4)
insertion
PDH AIS TU-AIS/TU-LOP
Detector Detector
LPOH(V5/J2/N2/
K4)
Extraction
E1/T1 STM-1
LPA LPT HPA HPT
PPI
The PPI module mainly consists of line interface units (LIUs). It provides inloop and outloop
function. This module:
E1/T1 mapping/demapping
l LPA
l The 2 Mbit/s (1.5 Mbit/s) plesiochronous stream is inserted in a VC-12 container to be
adapted so as to be transported into the synchronous network for check of the PDH AIS.
l LPT
l The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are
distributed within a 125 us interval (for example, one STM–1 period), and consists of the
VC-12 container and POH. The latter contains nine octets equally distributed within the
frame bytes for VC-12: V5, J2, N2, and K4.
l HPA
l HPA generates and processes channel level TU-PTR. In the receive direction, the signals
are split into VC-12s, which are located and isolated in TU-12. TU-PTR is processed. TU-
AIS and TU-LOP alarms are monitored. In the transmit direction, VC-12s are located
precisely and added with TU-PTR. 63 TUG-3s are multiplexed into a VC-4 by bytes
interleaving. The sequence is: TUG2->TUG3->VC-4.
l HPT
l The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM–1 period), and consists of the
C4 container and POH.
l MST and RST
l These two functions are necessary to create a proprietary STM–1 signal in order to interface
the “E1/T1 mapping/demapping” block with the multiplex unit.
DC/DC converter
It provides the board with required DC voltages. It converts the –48 V/–60 V power supply to
the following voltages: + 2.5 V, + 3.3 V, + 1.8 V. In addition, protection for +3.3 V power are
provided to the board.
PQM
STAT
ACT
PROG
SRV
PQM
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the PQM.
The D12S or D12B provides 100-ohm T1/E1 interfaces for the PQM. For details, see the sections
that describe the D12S and D12B.
Table 6-17 lists the valid slots for the PQM and corresponding slots for the D12S and D12B.
Table 6-17 Valid slots for the PQM and corresponding slots for the D12S and D12B in the OptiX
OSN 1500B subrack
Valid Slot for the PQM Corresponding Slot for the D12S and
D12B
NOTE
l Slot 11 can house a protection board of the TPS protection. The board housed in slot 11 protects the
boards housed in slots 12 and 13.
l If the interface board for the boards housed in slots 12 and 13 is the D12B, the boards housed in slots
12 and 13 cannot get the TPS protection.
Protection Principle
In the OptiX OSN 1500B, used with the D12S, the PQM can be configured into one 1:N (N≤
2) TPS protection group. Figure 6-18 shows the principle of the TPS protection for the PQM.
Figure 6-18 Principle of the TPS protection for the PQM in the OptiX OSN 1500B subrack
S S S S
E1/T1 L L L L
protection bus O O O O
T T T T
14 15 16 17
D12S
D12S
D12S
D12S
E1/T1
service
bus
Fail
Protection
Working
Working
Detect
board fault
TPS switching
Cross-connect and control bus
timing board
When detecting a fault in the working PQM board, the cross-connect board issues a command
to switch the services from the faulty PQM to the protection PQM. In this way, services are
protected.
Hardware Configuration
Table 6-18 lists the slot configuration for the 1:2 TPS protection for the PQM in the OptiX OSN
1500B subrack.
Table 6-18 Slot configuration for the 1:2 TPS protection for the PQM in the OptiX OSN 1500B
subrack
Working Protection Board Slot
Board
PQM (E1) PQM (E1) Slot 11 can house the protection board. The board
in slot 11 protects the boards in slots 12 and 13.
PQM (T1) PQM (T1) Figure 6-19 shows the slot configuration for the
1:2 TPS protection for the PQM.
Figure 6-19 Slot configuration for the 1:2 TPS protection for the PQM in the OptiX OSN 1500B
subrack
Slot 14 D12S
Slot 18 PIU
Slot 15 D12S
Slot 16 D12S
Slot 19 PIU
Slot 17 D12S
Slot 11 Protection Slot 6
Slot 20 Slot 12 Working Slot 7
Slot 13 Working Slot 8
FAN
Slot 4 CXL16/4/1 Slot 9 EOW
Slot 5 CXL16/4/1 Slot 10 AUX
You can use the T2000 to set the following parameters for the PQM:
l J2 byte
l V5 byte
l Tributary loopback
l Service loading indication
l Path service type
Mechanical Specifications
The mechanical specifications of the PQM are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the PQM is 22 W.
6.5 PL3
This section describes the PL3, a 3 x E3/T3 processing board, in terms of the version, function,
principle, front panel, configuration and specifications.
Table 6-19 lists the details on the versions of the PL3 board.
Item Description
Overhead Supports the setting and query of all path overhead bytes at the VC-3
processing level.
Alarm and Provides rich alarms and performance events for easy management and
performance event maintenance of the equipment.
Protection scheme Supports the TPS protection when used with the interface board and the
switching board.
6 x 34 Mbit/s/ High
E3/T3 6 x 45 Mbit/s 2 x 155 Mbit/s speed bus Cross-connect unit
LIU
E3/T3 Interface
A
P
P mapping/ coversion
I 6 x 34 Mbit/s/ demapping module High
E3/T3 2 x 155 Mbit/s speed bus Cross-connect unit
LIU 6 x 45 Mbit/s
B
+3.3 V
DC/DC Fuse -48 V/ -60 V
converter -48 V/ -60 V
+1.8 V DC/DC
converter Fuse
+3.3 V backup
power
E3/T3
STM-1
LPA LPT HPA HPT
LPOH(J1/C2/B3)
insertion
PDH AIS TU-AIS/TU-LOP
Detector Detector
LPOH(J1/C2/B3)
extraction
E3/T3 STM-1
LPA LPT HPA HPT
LPA: Low order Path Adaptation LPT: Low order Path Termination
HPA: High order Path Adaptation HPT: High order Path Termination
PPI
l The PPI module mainly consists of line interface units (LIUs). It provides inloop and
outloop function. This module:
l Encodes and decodes signals.
l Recovers data and clock.
l Processes the A_LOS alarm.
E3/T3 mapping/demapping
l LPA
l The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted
so as to be transported into the synchronous network.
l LPT
l The virtual container (VC-3) is formatted by lower order path termination (LPT).
l The VC-3 is structured so that its octets are distributed within a 125 us interval (for example,
one STM–1 period), and consists of the VC-3 container and POH. The latter contains nine
octets equally distributed within the frame bytes for VC-3: J1, B3, C2, G1, F2, H4, F3, K3,
and N1.
l HPA
l HPA generates and processes channel level TU-PTR. In the receive direction, the signals
are split into VC-3s, which are located and isolated in TU-3. TU-PTR is processed. In the
transmit direction, VC-3s are located precisely and added with TU-PTR. Three TUG-3s
are multiplexed into a VC-4 by bytes interleaving. The sequence is: TU-3->TUG3->VC-4.
l HPT
l The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM–1 period), and consists of the
C4 container and POH.
l MST and RST
l The functions are necessary to create a proprietary STM–1 signal in order to connect the
interface conversion module.
PL3
STAT
ACT
PROG
SRV
PL3
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the PL3.
The C34S, an electrical interface switching board, provides the E3/T3 interfaces for the PL3.
For details, see the section that describes the D34S.
Table 6-21 Valid slots for the PL3 and corresponding slots for the C34S in the OptiX OSN
1500B subrack
Valid Slot for the PL3 Corresponding Slot for the C34S
Slot 12 Slot 14
Slot 13 Slot 16
Protection Principle
In the OptiX OSN 1500B, used with the C34S and TSB8, the PL3 can be configured into one
1:1 TPS protection group. Figure 6-23 shows the principle of the TPS protection for the PL3.
Figure 6-23 Principle of the TPS protection for the PL3 in the OptiX OSN 1500B subrack
3 xE3/T3
Switch
control
TSB8 C34S signal
1 2
3 2 1
Cross-
connect
and timing
board
SLOT 4/5
Protection Working
PL3 PL3
Fail
SLOT12 SLOT13
l Normal state
When the working boards are running normally, the control switch of the C34S is in position
1 and services are directly accessed to the PL3 board.
l Switching state
When the working board detects a fault and requires a switching, the control switch of the
C34S is shifted to position 2 and the control switch of the TSB8 is shifted to a corresponding
position. In this way, the protection board protects the faulty working board.
Hardware Configuration
Table 6-22 lists the slot configuration for the 1:1 TPS protection for the PL3 in the OptiX OSN
1500B subrack.
Table 6-22 Slot configuration for the 1:1 TPS protection for the PL3 in the OptiX OSN 1500B
subrack
Working Protection Board Slot
Board
PL3 (E3) PL3 (E3)/PD3 (E3) If the working board is the PL3, the PD3
can be the protection board. Figure 6-24
PL3 (T3) PL3 (T3)/PD3 (T3) shows the slot configuration for the 1:1 TPS
protection for the PL3.
Figure 6-24 Slot configuration for the 1:1 TPS protection for the PL3 in the OptiX OSN 1500B
subrack
Slot 14 TSB8
Slot 18 PIU
Slot 15
Slot 16 C34S
Slot 19 PIU
Slot 17
Slot 11 Slot 6
Slot 20 Slot 12 Slot 7
Protection
FAN Slot 13 Working Slot 8
Slot 4 CXL16/4/1 Slot 9 EOW
Slot 5 CXL16/4/1 Slot 10 AUX
As shown in Figure 6-24, the protection board housed in slot 12 protects the board housed in
slot 13.
Table 6-23 lists the slots for the PL3, C34S and TSB8.
Table 6-23 Slots for the PL3, C34S and TSB8 in the OptiX OSN 1500B subrack
TSB8 Slot 14
C34S Slot 16
You can use the T2000 to set the following parameters for the PL3:
l J1 byte
l C2 byte
l Tributary loopback
l Service loading indication
l Path service type
Mechanical Specifications
The mechanical specifications of the PL3 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.0
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the N1PL3 is 15 W.
In the normal temperature (25℃), the maximum power consumption of the N2PL3 is 12 W.
6.6 PL3A
This section describes the PL3A, a 3 x E3/T3 processing board, in terms of the version, function,
principle, front panel, configuration and specifications.
Item Description
Overhead Supports the setting and query of all path overhead bytes at the VC-3 level.
processing
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Figure 6-25 shows the block diagram for the functions of the PL3A.
6 x 34 Mbit/s/ High
E3/T3 6 x 45 Mbit/s 2 x 155 Mbit/s speed bus Cross-connect unit
LIU
E3/T3 Interface
A
P
P mapping/ coversion
I 6 x 34 Mbit/s/ demapping module High
E3/T3 2 x 155 Mbit/s speed bus Cross-connect unit
LIU 6 x 45 Mbit/s
B
+3.3 V
DC/DC Fuse -48 V/ -60 V
converter -48 V/ -60 V
+1.8 V DC/DC
converter Fuse
+3.3 V backup
power
E3/T3
STM-1
LPA LPT HPA HPT
LPOH(J1/C2/B3)
insertion
PDH AIS TU-AIS/TU-LOP
Detector Detector
LPOH(J1/C2/B3)
extraction
E3/T3 STM-1
LPA LPT HPA HPT
LPA: Low order Path Adaptation LPT: Low order Path Termination
HPA: High order Path Adaptation HPT: High order Path Termination
PPI
l The PPI module mainly consists of line interface units (LIUs). It provides inloop and
outloop function. This module:
l Encodes and decodes signals.
l Recovers data and clock.
l Processes the A_LOS alarm.
E3/T3 mapping/demapping
l LPA
l The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted
so as to be transported into the synchronous network.
l LPT
l The virtual container (VC-3) is formatted by lower order path termination (LPT).
l The VC-3 is structured so that its octets are distributed within a 125 us interval (for example,
one STM–1 period), and consists of the VC-3 container and POH. The latter contains nine
octets equally distributed within the frame bytes for VC-3: J1, B3, C2, G1, F2, H4, F3, K3,
and N1.
l HPA
l HPA generates and processes channel level TU-PTR. In the receive direction, the signals
are split into VC-3s, which are located and isolated in TU-3. TU-PTR is processed. In the
transmit direction, VC-3s are located precisely and added with TU-PTR. Three TUG-3s
are multiplexed into a VC-4 by bytes interleaving. The sequence is: TU-3->TUG3->VC-4.
l HPT
l The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM–1 period), and consists of the
C4 container and POH.
l MST and RST
l The functions are necessary to create a proprietary STM–1 signal in order to connect the
interface conversion module.
l Selects the clock and frame header from the active or the standby cross-connect units.
l Controls the indicator on the board.
PL3A
STAT
ACT
PROG
SRV
OUT1
IN1
OUT2
IN2
OUT3
IN3
PL3A
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are three pairs of 75-ohm unbalanced interfaces, which are of the SMB type.
The PL3A can be housed in any of slots 12–13 in the OptiX OSN 1500A subrack.
The PL3A can be housed in any of slots 11–13 in the OptiX OSN 1500B subrack.
You can use the T2000 to set the following parameters for the PL3A:
l J1 byte
l C2 byte
l Tributary loopback
l Service loading indication
l Path service type
Mechanical Specifications
The mechanical specifications of the PL3A are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the N1PL3A is 15 W.
In the normal temperature (25℃), the maximum power consumption of the N2PL3A is 12 W.
6.7 PD3
This section describes the PD3, a 6 x E3/T3 processing board, in terms of the version, function,
principle, front panel, configuration and specifications.
Overhead Supports the setting and query of all path overhead bytes at the VC-3 level.
processing
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Function PD3
and Feature
Protection Supports the TPS protection when used with the interface and switching
scheme boards.
6 x 34 Mbit/s/ High
E3/T3 6 x 45 Mbit/s 2 x 155 Mbit/s speed bus Cross-connect unit
LIU
E3/T3 Interface
A
P
P mapping/ coversion
I 6 x 34 Mbit/s/ demapping module High
E3/T3 2 x 155 Mbit/s speed bus Cross-connect unit
LIU 6 x 45 Mbit/s
B
+3.3 V
DC/DC Fuse -48 V/ -60 V
converter -48 V/ -60 V
+1.8 V DC/DC
converter Fuse
+3.3 V backup
power
E3/T3
STM-1
LPA LPT HPA HPT
LPOH(J1/C2/B3)
insertion
PDH AIS TU-AIS/TU-LOP
Detector Detector
LPOH(J1/C2/B3)
extraction
E3/T3 STM-1
LPA LPT HPA HPT
LPA: Low order Path Adaptation LPT: Low order Path Termination
HPA: High order Path Adaptation HPT: High order Path Termination
PPI
l The PPI module mainly consists of line interface units (LIUs). It provides inloop and
outloop function. This module:
l Encodes and decodes signals.
l Recovers data and clock.
l Processes the A_LOS alarm.
E3/T3 mapping/demapping
l LPA
l The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted
so as to be transported into the synchronous network.
l LPT
l The virtual container (VC-3) is formatted by lower order path termination (LPT).
l The VC-3 is structured so that its octets are distributed within a 125 us interval (for example,
one STM–1 period), and consists of the VC-3 container and POH. The latter contains nine
octets equally distributed within the frame bytes for VC-3: J1, B3, C2, G1, F2, H4, F3, K3,
and N1.
l HPA
l HPA generates and processes channel level TU-PTR. In the receive direction, the signals
are split into VC-3s, which are located and isolated in TU-3. TU-PTR is processed. In the
transmit direction, VC-3s are located precisely and added with TU-PTR. Three TUG-3s
are multiplexed into a VC-4 by bytes interleaving. The sequence is: TU-3->TUG3->VC-4.
l HPT
l The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM–1 period), and consists of the
C4 container and POH.
PD3
STAT
ACT
PROG
SRV
PD3
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
No interfaces are present on the front panel of the PD3.
The D34S, an electrical interface switching board, provides the E3/T3 interfaces for the PD3.
For details, see the section that describes the D34S.
Table 6-29 Valid slots for the PD3 and corresponding slots for the D34S in the OptiX OSN
1500B subrack
Valid Slot for the PD3 Corresponding Slot for the D34S
Slot 12 Slot 14
Slot 13 Slot 16
Protection Principle
For the OptiX OSN 1500B, when used with the D34S and TSB8, the PD3 can be configured
into one 1:1 TPS protection group. Figure 6-31 shows the principle of the TPS protection for
the PD3.
Figure 6-31 Principle of the TPS protection for the PD3 in the OptiX OSN 1500B subrack
6 xE3/T3
Switch
control
TSB8 D34S signal
1 1 2
3 2
Cross-
connect
and
timing
board
SLOT 4/5
Protection Working
PD3 PD3
Fail
SLOT12 SLOT13
l Normal state
When the working boards are running normally, the control switch of the D34S is in position
1 and services are directly accessed to the PD3 board.
l Switching state
When the working board detects a fault and requires a switching, the control switch of the
D34S is shifted to position 2 and the control switch of the TSB8 is shifted to a corresponding
position. In this way, the protection board protects the faulty working board.
Hardware Configuration
Table 6-30 lists the slot configuration for the TPS protection for the PD3 in the OptiX OSN
1500B subrack.
Table 6-30 Slot configuration for the 1:1 TPS protection for the PD3 in the OptiX OSN 1500B
subrack
PD3 (E3) PD3 (E3) Figure 6-32 shows the slot configuration for
the 1:1TPS protection for the PD3
PD3 (T3) PD3 (T3)
Figure 6-32 Slot configuration for the 1:1 TPS protection for the PD3 in the OptiX OSN 1500B
subrack
Slot 14 TSB8
Slot 18 PIU
Slot 15
Slot 16 D34S
Slot 19 PIU
Slot 17
Slot 11 Slot 6
Slot 20 Slot 12 Protection Slot 7
As shown in Figure 6-32, the protection board housed in slot 12 protects the board housed in
slot 13.
Table 6-31 lists the slots for the PD3, D34S and TSB8.
Table 6-31 Slots for the PD3, D34S and TSB8 in the OptiX OSN 1500B subrack
TSB8 Slot 14
D34S Slot 16
You can use the T2000 to set the following parameters for the PD3:
l J1 byte
l C2 byte
l Tributary loopback
l Service loading indication
l Path service type
Mechanical Specifications
The mechanical specifications of the PD3 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the N1PD3 is 19 W.
In the normal temperature (25℃), the maximum power consumption of the N2PD3 is 12 W.
6.8 PQ3
This section describes the PQ3, a 12 x E3/T3 processing board, in terms of the version, function,
principle, front panel, configuration and specifications.
The technical specifications of the PQ3 cover the electrical interface specifications, board
dimensions, weight and power consumption.
Overhead Supports the setting and query of all path overhead bytes at the VC-3 level.
processing
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Protection Supports the TPS protection when used with the interface board and the
scheme switching board.
Figure 6-33 shows the block diagram for the functions of the PQ3.
6 x 34 Mbit/s/ High
E3/T3 6 x 45 Mbit/s 2 x 155 Mbit/s speed bus Cross-connect unit
LIU
E3/T3 Interface
A
P
P mapping/ coversion
I 6 x 34 Mbit/s/ demapping module High
E3/T3 2 x 155 Mbit/s speed bus Cross-connect unit
LIU 6 x 45 Mbit/s
B
+3.3 V
DC/DC Fuse -48 V/ -60 V
converter -48 V/ -60 V
+1.8 V DC/DC
converter Fuse
+3.3 V backup
power
E3/T3
STM-1
LPA LPT HPA HPT
LPOH(J1/C2/B3)
insertion
PDH AIS TU-AIS/TU-LOP
Detector Detector
LPOH(J1/C2/B3)
extraction
E3/T3 STM-1
LPA LPT HPA HPT
LPA: Low order Path Adaptation LPT: Low order Path Termination
HPA: High order Path Adaptation HPT: High order Path Termination
PPI
l The PPI module mainly consists of line interface units (LIUs). It provides inloop and
outloop function. This module:
l Encodes and decodes signals.
l Recovers data and clock.
l Processes the A_LOS alarm.
E3/T3 mapping/demapping
l LPA
l The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted
so as to be transported into the synchronous network.
l LPT
l The virtual container (VC-3) is formatted by lower order path termination (LPT).
l The VC-3 is structured so that its octets are distributed within a 125 us interval (for example,
one STM–1 period), and consists of the VC-3 container and POH. The latter contains nine
octets equally distributed within the frame bytes for VC-3: J1, B3, C2, G1, F2, H4, F3, K3,
and N1.
l HPA
l HPA generates and processes channel level TU-PTR. In the receive direction, the signals
are split into VC-3s, which are located and isolated in TU-3. TU-PTR is processed. In the
transmit direction, VC-3s are located precisely and added with TU-PTR. Three TUG-3s
are multiplexed into a VC-4 by bytes interleaving. The sequence is: TU-3->TUG3->VC-4.
l HPT
l The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM–1 period), and consists of the
C4 container and POH.
l MST and RST
l The functions are necessary to create a proprietary STM–1 signal in order to connect the
interface conversion module.
PQ3
STAT
ACT
PROG
SRV
PQ3
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the PQ3.
The D34S, an electrical interface switching board, provides the E3/T3 interfaces for the PQ3.
For details, see the section that describes the D34S.
Table 6-33 Valid slots for the PQ3 and corresponding slots for the D34S in the OptiX OSN
1500B subrack
Valid Slot for the PQ1 Corresponding Slot for the D34S
Protection Principle
In the OptiX OSN 1500B, used with the D34S and TSB8, the PQ3 can be configured into one
1:1 TPS protection group. Figure 6-36 shows the principle of the TPS protection for the PQ3.
Figure 6-36 Principle of the TPS protection for the PQ3 in the OptiX OSN 1500B subrack
6 xE3/T3 6 xE3/T3
Switch
TSB8 control
TSB8 D34S D34S signal
1 2 1 2 1 2 1 2
Cross-
connect
and timing
board
SLOT 4/5
Working
Protection PQ3
PQ3
Fail
SLOT12 SLOT13
l Normal state
When the working boards are running normally, the control switch of the D34S is in position
1 and services are directly accessed to the PQ3 board.
l Switching state
When the working board detects a fault and requires a switching, the control switch of the
D34S is shifted to position 2 and the control switch of the TSB8 is shifted to a corresponding
position. In this way, the protection board protects the faulty working board.
Hardware Configuration
NOTE
Two TSB8 boards are required to configure the TPS protection for the N2PQ3.
Table 6-34 lists the slot configuration for the TPS protection for the PQ3 in the OptiX OSN
1500B subrack.
Table 6-34 Slot configuration for the 1:1 TPS protection for the PQ3 in the OptiX OSN 1500B
subrack
PQ3 (E3) PQ3 (E3) Figure 6-37 shows the slot configuration for
the 1:3 TPS protection for the PQ3.
PQ3 (T3) PQ3 (T3)
Figure 6-37 Slot configuration for the 1:1 TPS protection for the PQ3 in the OptiX OSN 1500B
subrack
Slot 14 TSB8
Slot 18 PIU
Slot 15 TSB8
Slot 16 D34S
Slot 19 PIU
Slot 17 D34S
Slot 11 Slot 6
Slot 20 Slot 12 Protection Slot 7
As shown in Figure 6-37, the protection board housed in slot 12 protects the board housed in
slot 13.
Table 6-35 lists the slots for the PQ3, D34S and TSB8.
Table 6-35 Slots for the PQ3, D34S and TSB8 in the OptiX OSN 1500B subrack
Mechanical Specifications
The mechanical specifications of the PL1 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.1
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the PQ3 is 13 W.
6.9 DX1
This section describes the DX1, a DDN interface convergence board, in terms of the version,
function, principle, front panel, configuration and specifications.
6.9.1 Version Description
The functional version of the DX1 board is N1.
6.9.2 Function and Feature
The DX1, a DDN interface convergence board, cross-connects 48 x E1 signals at the 64k level
at the system side.
Function DX1
and
Feature
Used with Accesses eight channels of N x 64 kbit/s and 8 x framed E1 services and
the interface realizes the 1:N TPS protection when used with the DM12.
board One DX1 board should be used with two DM12 boards.
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Connector The connectors of the DB28 and DB44 are present on the front panel of the
DM12. The DB28 is for the N x 64 kbit/s signals, and the DB44 is for the
framed E1 signals.
Function DX1
and
Feature
DX1
DM12
Frame E1
8X Frame E1
interface encoding/decoding
Frame E1 and frame
module
processing 64kbit/s
Timeslot Framing/ mapping/ Cross-
module
N x 64 kbit/s cross- deframing demapping connect unit
8X interface connect module module
Nx64 kbit/s module Nx64k bit/s module
interface and
Power frame
processing
DM12 module
8X N x 64 kbit/s
Nx64 kbit/s interface
module
Communication SCC unit
Power
and control
Frame E1 module
interface
module +3.3 V
DC/DC Fuse
-48 V/-60 V
converter -48 V/-60 V
DC/DC
Fuse
converter +3.3 V
backup
power
The DX1 decodes the framed E1 signals and processes the frames. The DX1 also converts the
N x 64 kbit/s signals, processes the frames. The DX1 then transmits the signals to the 64 kbit/s
cross-connect module. The timeslot cross-connect module cross-connects and grooms the
signals in the 64 kbit/s granularities. The timeslot cross-connect module then transmits the
signals to the framing/deframing module. The framing/deframing module then maps the signals
into the VC-4 and transmits the signals into the SDH cross-connect board.
DX1
STAT
ACT
PROG
SRV
DX1
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the DX1.
When used with the DM12, the DX1 can input and output the framed E1 and N x 64 kbit/s
signals. For details, see the section that describes the DM12.
In the OptiX OSN 1500B subrack, the DX1 can be housed in any of slots 11–13, and must be
used with the DM12.
Table 6-37 lists the valid slots for the DX1 and corresponding slots for the DM12.
Table 6-37 Valid slots for the DX1 and corresponding slots for the DM12 in the OptiX OSN
1500B subrack
Valid Slot for the DX1 Corresponding Slot for the DM12
NOTE
l Slot 11 can house a protection board of the TPS protection. The board housed in slot 11 protects the
boards housed in slots 12 and 13.
l One DX1 should be used with two DM12 to access eight channels of N x 64 kbit/s signals. The DM12
board housed in the slot with a smaller slot number is used to access 8 x framed E1 and four channels
of N x 64 kbit/s signals. The DM12 board housed in the slot with a larger slot number is used to access
four channels of N x 64 kbit/s signals.
Table 6-38 lists the relation between the board feature code and interface impedance type for
the DX1.
Table 6-38 Relation between the board feature code and the interface impedance type
Board Barcode Feature Code Interface Impedance
Type
Protection Principle
In the OptiX OSN 1500B, used with the DM12, the DX1 can be configured into one 1:N (N≤
2) TPS protection group. Figure 6-40 shows the principle of the TPS protection for the DX1.
Figure 6-40 Principle of the TPS protection for the DX1 in the OptiX OSN 1500B subrack
S S S S
L L L L
protection bus O O O O
T T T T
14 15 16 17
DM12
DM12
DM12
DM12
service
bus
S S S
L L L
O O O
T T T
11 12 13
Fail
Protection
Working
Working
TPS
Detect switching
board fault control bus
Cross-connect and timing
board
When detecting a fault in the working DX1 board, the cross-connect board issues a command
to switch the services from the faulty DX1 to the protection DX1. In this way, services are
protected.
Hardware Configuration
Figure 6-41 shows the slot configuration for the 1:2 TPS protection for the DX1 in the OptiX
OSN 1500B subrack.
Figure 6-41 Slot configuration for the 1:2 TPS protection for the DX1 in the OptiX OSN 1500B
subrack
Slot 14 DM12
Slot 18 PIU
Slot 15 DM12
Slot 16 DM12
Slot 19 PIU
Slot 17 DM12
Slot 11 Protection Slot 6
Slot Slot 12 Slot 7
Working
20
Slot 13 Working Slot 8
FAN Slot 4 CXL16/4/1 Slot 9 EOW
As shown in Figure 6-41, the protection board housed in slot 11 protects the boards housed in
slots 12–13.
Table 6-39 lists the slots for the DX1 and DM12 in the OptiX OSN 1500B subrack.
Table 6-39 Slots for the DX1 and DM12 in the OptiX OSN 1500B subrack
You can use the T2000 to set the following parameters for the DX1:
l J2 byte
l Tributary loopback
l Service loading indication
l Protocol mode of serial ports
l DDN clock source management
Mechanical Specifications
The mechanical specifications of the DX1 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the DX1 is 15 W.
NOTE
After the TPS protection is performed, the power consumption of the DX1 is 31 W.
6.10 DXA
This section describes the DXA, a DDN convergence board, in terms of the version, function,
principle, front panel, configuration and specifications.
Alarm and Provides rich alarms and performance events for easy management and
performance event maintenance of the equipment.
64 kbit/s
Framing/ Mapping/
timeslot Cross-
deframing demapping
crossconnect connect
module module
module unit
signals and transmits the signals to the timeslot cross-connect module. The timeslot cross-
connect module cross-connects and grooms the signals in the 64 kbit/s granularities.
DXA
STAT
ACT
PROG
SRV
DXA
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the DXA.
The DXA can be housed in any of slots 12–13 in the OptiX OSN 1500A subrack.
The DXA can be housed in any of slots 11–13 in the OptiX OSN 1500B subrack.
Mechanical Specifications
The mechanical specifications of the DXA are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 0.8
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the DXA is 10 W.
6.11 SPQ4
This section describes the SPQ4, a 4 x E1/STM-1 processing board, in terms of the version,
function, working principle, front panel and specifications.
The OptiX OSN 1500A does not support the SPQ4 board.
6.11.6 TPS Protection for the Board
The SPQ4 supports the 1:N TPS protection.
6.11.7 Board Configuration Reference
You can use the T2000 to set parameters for the SPQ4.
6.11.8 Technical Specifications
The technical specifications of the SPQ4 cover the electrical interface specifications, board
dimensions, weight and power consumption.
Difference The equipment of the V100R001 and V100R002 versions support the
N1SPQ4. The equipment of the V100R003 and later versions support the
N2SPQ2.
Replaceability The N1SPQ4 can be replaced by the N2SPQ4. When the N1SPQ4 is
replaced, the NE should be upgraded.
Overhead Supports the processing of SOH bytes for the STM-1 signals, such as B1,
processing B2, K1, K2, M1, F1, and D1–D12.
Supports the transparent transmission and termination of POH bytes,
including J1, B3, C2, G1, and H4.
Supports the setting and query of the J0/J1/C2 bytes.
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Protection Supports the TPS protection when used with the interface board and the
scheme switching board.
Supports the two-fiber unidirectional MSP protection ring, linear MSP
protection, and SNCP.
DCC
SCC unit
K1 and K2
Cross-connect
unit
EN 140M/155M
Frame header Cross-connect
LOS Communication unit
and control Communication
Outloop/Inloop control module SCC unit
+3.3 V
DC/DC Fuse -48 V/ -60 V
5V
converter -48 V/ -60 V
+1.8V DC/DC
+2.5V converter Fuse
+3.3 V backup
power
139Mbit/s 155Mbit/s
LPA HPT PG MST RST
139Mbit/s 155Mbit/s
SIPO LPA HPT MST RST
Cross-
K1 and K2 insertion/extration connect unit
155 Mbit/s
155 Mbit/s
DCC
SCC unit
The principle of the E4/ STM-1 electrical interface units is described below.
PPI/SPI
l The PPI module mainly consists of line interface units (LIUs). It provides inloop and
outloop function. This module:
l Encodes and decodes signals.
l Recovers data and clock.
l Processes the PDH LOS signals.
l The SPI module mainly consists of line interface units (LIUs). It provides inloop and
outloop function. This module:
l Encodes and decodes signals.
l Recovers data and clock.
l Processes the R_LOS signals.
RST
l In the receive direction, RST performs frame alignment detection (A1, A2), regenerator
section trace recovery (J0) and mismatch detection, BIP-8 errored block count.
l In the transmit direction, RST performs frame alignment insertion, regenerator section path
trace insertion, BIP-8 calculation and insertion.
MST
l In the receive direction, MST performs BIP-24 errored block count, MS_REI recovery,
MS_RDI and MS_AIS detection.
l In the transmit direction, MST performs BIP-24 calculation and insertion, MS_REI
MS_RDI and MS_AIS insertion.
l Provides extraction or insertion of K1 byte and K2 byte.
MSA
l In the receive direction, MSA performs AU4's pointer interpretation, LOP and AIS
detection, pointer justification.
l In the transmit direction, MSA performs AUG assembly, AU-4 pointer generation,
AU_AIS generation.
HPT
l OH termination
l J1 path trace message recover
l REI information recovering
l HP_RDI detection (path status monitoring
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
LPA
The 140 Mbit/s plesiochronous stream is inserted in a C4 container to be adapted so as to be
transported into the synchronous network. PDH AIS is monitored and E4 AIS in inserted.
HPT
The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are distributed
within a 125 us interval (for example, one STM–1 period), and consists of the C4 container and
POH. The latter contains nine octets equally distributing within the frame. These overhead bytes
can be extracted: J1, B3. C2, G1, F2, H4, F3, K3 and N1.E4 AIS can be inserted in downstream
direction.
PG (Pointer generator)
A fixed pointer value is inserted in the SOH to structure the AU4 signal.
SPQ4
STAT
ACT
PROG
SRV
SPQ4
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the SPQ4. When used with the MU04, the SPQ4
can input or output the E4/STM-1 signals. For details, see the section that describes the MU04.
Table 6-43 lists the valid slots for the SPQ4 and corresponding slots for the MU04.
Table 6-43 Valid slots for the SPQ4 and corresponding slots for the MU04 in the OptiX OSN
1500B subrack
Valid Slot for the SPQ4 Corresponding Slot for the DMU04
Slot 12 Slot 14
Slot 13 Slot 16
Protection Principle
In the OptiX OSN 1500B, used with the MU04 and TSB8, the SPQ4 can be configured into one
1:1 TPS protection group. Figure 6-48 shows the principle of the TPS protection for the SPQ4.
Figure 6-48 Principle of the TPS protection for the SPQ4 in the OptiX OSN 1500B subrack
4×E4/STM-1
Switch
control
TSB8 signal
MU04
1 1 2
3 2
Cross-
connect
and
timing
board
SLOT 4/5
Protection Working
SPQ4 SPQ4
Fail
SLOT12 SLOT13
l Normal state
When the working boards are running normally, the control switch of the MU04 is in
position 1 and the MU04 directly accesses the service signals to the SLH1.
l Switching state
When the working board detects a fault and requires a switching, the control switch of the
MU04 is shifted to position 2 and the control switch of the TSB8 is shifted to a
corresponding position. In this way, the protection board protects the faulty working board.
Hardware Configuration
Figure 6-49 shows the slot configuration for the 1:2 TPS protection for the SPQ4 in the OptiX
OSN 1500B subrack.
Figure 6-49 Slot configuration for the 1:1 TPS protection for the SPQ4
Slot 14 TSB8
Slot 18 PIU
Slot 15
Slot 16 MU04
Slot 19 PIU
Slot 17
Slot 11 Slot 6
Slot 20 Slot 12 Slot 7
Protection
As shown in Figure 6-49, the protection board housed in slot 12 protects the board housed in
slot 13.
Table 6-44 lists the slots for the SPQ4, MU04 and TSB8.
Table 6-44 Slots for the SPQ4, MU04 and TSB8 in the OptiX OSN 1500B subrack
MU04 Slot 16
TSB8 Slot 14
You can use the T2000 to set the following parameters for the SPQ4:
l J1 byte
l C2 byte
Mechanical Specifications
The mechanical specifications of the SPQ4 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 0.9
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the SPQ4 is 24 W.
This chapter describes the data processing boards for the FE, GE, ATM, and SAN signals.
7.1 EFT4
This section describes the EFT4, a 4 x FE Ethernet transparent transmission board, in terms of
the version, function, principle, front panel, configuration and specifications.
7.2 EFT8
This section describes the EFT8, an 8/16 x FE Ethernet transparent transmission board, in terms
of the version, function, principle, front panel, configuration and specifications.
7.3 EFT8A
This section describes the EFT8A, an 8 x FE Ethernet transparent transmission board, in terms
of the version, function, principle, front panel, configuration and specifications.
7.4 EGT2
This section describes the EGT2, a 2 x GE Ethernet transparent transmission board, in terms of
the version, function, principle, front panel, configuration and specifications.
7.5 EFS0
This section describes the EFS0, an 8 x FE Ethernet processing board with Lanswitch, in terms
of the version, function, principle, front panel, configuration and specifications.
7.6 EFS4
This section describes the EFS4, a 4 x FE Ethernet processing board with Lanswitch, in terms
of the version, function, principle, front panel, configuration and specifications.
7.7 EGS2
This section describes the EGS2, a 2 x GE Ethernet processing board with Lanswitch, in terms
of the version, function, principle, front panel, configuration and specifications.
7.8 EMS4
This section describes the EMS4, a 4 x GE and 16 x FE Ethernet transparent transmission and
convergence board, in terms of the version, function, principle, front panel, configuration and
specifications.
7.9 EGS4
This section describes the EGS4, a 4 x GE Ethernet convergence board, in terms of the version,
function, principle, front panel, configuration and specifications.
7.10 EGR2
This section describes the EGR2, a 2 x GE Ethernet processing board, in terms of the version,
function, principle, front panel, configuration and specifications.
7.11 EMR0
This section describes the EMR0, a 12 x FE and 1 x GE Ethernet ring processing board, in terms
of the version, function, principle, front panel, configuration and specifications.
7.12 ADL4
This section describes the ADL4, a 1 x STM-4 ATM processing board, in terms of the version,
function, principle, front panel, configuration and specifications.
7.13 ADQ1
This section describes the ADQ1, a 4 x STM-1 ATM processing board, in terms of the version,
function, principle, front panel, configuration and specifications.
7.14 IDL4
This section describes the IDL4, a 1 x STM-4 ATM processing board, in terms of the version,
function, principle, front panel, configuration and specifications.
7.15 IDQ1
This section describes the IDQ1, a 4 x STM-1 ATM processing board, in terms of the version,
function, principle, front panel, configuration and specifications.
7.16 MST4
This section describes the MST4, a 4-channel multi-service transparent transmission board, in
terms of the version, function, principle, front panel, configuration and specifications.
7.1 EFT4
This section describes the EFT4, a 4 x FE Ethernet transparent transmission board, in terms of
the version, function, principle, front panel, configuration and specifications.
Format of service Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG.
frames Supports frames with a length ranging from 64 bytes to 9600 bytes.
Supports Jumbo frames with a length less than 9600 bytes.
Number of 4.
VCTRUNKs
Encapsulation HDLC.
format LAPS.
GFP-F.
Flow control Supports the IEEE 802.3x flow control based on FE port.
function
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Mapping module
Laser
LOS
shutdown
Communication Communication
and control SCC unit
Reference clock and frame header
module SCC unit
In the transmit direction, the parallel signals are converted to serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Mapping module
The mapping module consists of encapsulation and mapping.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is processed. Ethernet signals are then converted into SDH signals.
In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation
is compensated. After aligning, packets are decapsulated as per encapsulation format. The
decapsulated data are transmitted to the network processor module in packets.
The control module also contains basic logic units. This module enjoys the following functions:
l Writes and reads register
l Provides interface for CPU
l Checks, selects clock
l Performs phase discrimination and frequency division to the clock
l Checks the in-service state of the cross-connect, the SCC and the line boards
l Controls the shutting down of the optical module
l Processes communication
l Control indicators
Clock unit
This clock unit tracing the system reference clock and generates the required working clocks for
each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
EFT4
STAT
ACT
PROG
SRV
FE1
FE2
FE3
FE4
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
l Connection status indicator (LINK), which is green when lit.
l Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four FE interfaces on the front panel of the EFT4. Table 7-2 lists the type and usage
of the interfaces.
1 Transmitting positive
2 Transmitting negative
3 Receiving positive
4 Grounding
5 Grounding
6 Receiving negative
7 Grounding
8 Grounding
Mechanical Specifications
The mechanical specifications of the EFT4 are as follows:
l Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W)
l Weight (kg): 0.5
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EFT4 is 14 W.
7.2 EFT8
This section describes the EFT8, an 8/16 x FE Ethernet transparent transmission board, in terms
of the version, function, principle, front panel, configuration and specifications.
Specification of Supports the 10Base-T/100Base-TX signals when used with the ETF8.
the optical Supports the 100Base-FX/100Base-TX signals when used with the
interface EFF8. The optical interfaces comply with IEEE 802.3u.
Format of service Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG. Supports
frames frames with a length ranging from 64 bytes to 9600 bytes. Supports
Jumbo frames with a length less than 9600 bytes.
Number of 16.
VCTRUNKs
Flow control Supports the IEEE 802.3x flow control based on FE port.
function
Alarms and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
events
Mapping module
Laser
LOS
shutdown
Communication Communication
and control SCC unit
Reference clock and frame header
module SCC unit
In the transmit direction, the parallel signals are converted to serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Mapping Module
The mapping module consists of encapsulation and mapping.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is processed. Ethernet signals are then converted into SDH signals.
In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation
is compensated. After aligning, packets are decapsulated as per encapsulation format. The
decapsulated data are transmitted to the network processor module in packets.
The control module also contains basic logic units. This module enjoys the following functions:
l Writes and reads register
l Provides interface for CPU
l Checks, selects clock
l Performs phase discrimination and frequency division to the clock
l Checks the in-service state of the cross-connect, the SCC and the line boards
l Controls the shutting down of the optical module
l Processes communication
l Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for
each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
EFT8
STAT
ACT
PROG
SRV
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8
EFT8
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
l Connection status indicator (LINK), which is green when lit.
l Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are eight interfaces on the front panel of the EFT8. Table 7-5 lists the type and usage of
the interfaces.
Pin Description
1 Transmitting positive
2 Transmitting negative
3 Receiving positive
4 Grounding
5 Grounding
6 Receiving negative
7 Grounding
8 Grounding
Table 7-7 and Table 7-8 list the valid slots for the EFT8 and corresponding slots for the ETF8
and EFF8.
Table 7-7 Valid slots for the EFT8 and corresponding slots for the ETF8 and EFF8 in the OptiX
OSN 1500A
Valid Slot for the EFT8 Corresponding Slot for the ETF8 and EFF8
Table 7-8 Valid slots for the EFT8 and corresponding slots for the ETF8 and EFF8 in the OptiX
OSN 1500B
Valid Slot for the EFT8 Corresponding Slot for the ETF8 and EFF8
Slot 12 Slot 14
Slot 13 Slot 16
Mechanical Specifications
The mechanical specifications of the EFT8 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.0
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EFT8 is 26 W.
7.3 EFT8A
This section describes the EFT8A, an 8 x FE Ethernet transparent transmission board, in terms
of the version, function, principle, front panel, configuration and specifications.
Format of service Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG. Supports
frames frames with a length ranging from 64 bytes to 9600 bytes. Supports
Jumbo frames with a length less than 9600 bytes.
Number of 8.
VCTRUNKs
Mapping granularity Supports VC-12, VC-3, VC-12-Xv (X≤63), and VC-3-Xv (X≤3).
Flow control Supports the IEEE 802.3x flow control based on FE port.
function
Alarm and Provides rich alarms and performance events for easy management
performance event and maintenance of the equipment.
Mapping module
Laser
LOS
shutdown
Communication Communication
and control SCC unit
Reference clock and frame header
module SCC unit
In the transmit direction, the parallel signals are converted to serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Mapping Module
The mapping module consists of encapsulation and mapping.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is processed. Ethernet signals are then converted into SDH signals.
In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation
is compensated. After aligning, packets are decapsulated as per encapsulation format. The
decapsulated data are transmitted to the network processor module in packets.
The control module also contains basic logic units. This module enjoys the following functions:
l Writes and reads register
l Provides interface for CPU
l Checks, selects clock
l Performs phase discrimination and frequency division to the clock
l Checks the in-service state of the cross-connect, the SCC and the line boards
l Controls the shutting down of the optical module
l Processes communication
l Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for
each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
EFT8A
STAT
ACT
PROG
SRV
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8
EFT8A
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
l Connection status indicator (LINK), which is green when lit.
l Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are eight FE interfaces on the front panel of the EFT8A. Table 7-10 lists the type and
usage of the interfaces.
1 Transmitting positive
2 Transmitting negative
3 Receiving positive
4 Grounding
5 Grounding
6 Receiving negative
7 Grounding
8 Grounding
Mechanical Specifications
The mechanical specifications of the EFT8A are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.0
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EFT8A is 26 W.
7.4 EGT2
This section describes the EGT2, a 2 x GE Ethernet transparent transmission board, in terms of
the version, function, principle, front panel, configuration and specifications.
Format of service Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG. Supports
frames frames with a length ranging from 64 bytes to 9600 bytes. Supports
Jumbo frames with a length less than 9600 bytes.
Number of 2.
VCTRUNKs
Flow control Supports the IEEE 802.3x flow control based on GE port.
function
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Mapping module
Laser
LOS
shutdown
Communication Communication
and control SCC unit
Reference clock and frame header
module SCC unit
Mapping Module
The mapping module consists of encapsulation and mapping.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is processed. Ethernet signals are then converted into SDH signals.
In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation
is compensated. After aligning, packets are decapsulated as per encapsulation format. The
decapsulated data are transmitted to the network processor module in packets.
The control module also contains basic logic units. This module enjoys the following functions:
l Writes and reads register
l Provides interface for CPU
l Checks, selects clock
l Performs phase discrimination and frequency division to the clock
l Checks the in-service state of the cross-connect, the SCC and the line boards
l Controls the shutting down of the optical module
l Processes communication
l Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for
each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
EGT2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT
OUT1 IN1
OUT2 IN2
EGT2
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
l Connection status indicator (LINK), which is green when lit.
l Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are two GE interfaces on the front panel of the EGT2. Table 7-13 lists the type and usage
of the interfaces.
Table 7-14 lists the relation between the board feature code and optical interface type for the
EGT2.
Table 7-14 Relation between the board feature code and the optical interface type
Item Specification
Launched –4 to +2 –2 to +5 –9 to –3 –9.5 to 0
optical power
(dBm)
Overload –3 –3 –3 0
optical power
(dBm)
Extinction ratio 9 9 9 9
(dB)
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the EGT2 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EGT2 is 29 W.
7.5 EFS0
This section describes the EFS0, an 8 x FE Ethernet processing board with Lanswitch, in terms
of the version, function, principle, front panel, configuration and specifications.
The OptiX OSN 1500A does not support the EFS0. The OptiX OSN 1500B supports the EFS0.
Table 7-16 lists the details on the versions of the EFS0 board.
Functional The EFS0 has three versions, N1, N2, and N4.
version
Replaceability The N2EFS0 supports the board version replacement function and can
replace the N1EFS0.
The N4EFS0 supports the board version replacement function and can
replace the N1EFS0 and N2EFS0.
Used with the Accesses 8 x FE signals at the electrical interface when used with the
interface board ETF8.
Accesses 8 x FE signals at the optical interface when used with the EFF8.
Realizes the TPS protection for 8 x FE signals at the electrical interface
when used with the ETS8 and TSB8.
Specification of Supports the 10Base-T/100Base-TX signals when used with the ETF8.
the optical Supports the 100Base-FX signals when used with the EFF8. The optical
interface inerfaces comply with IEEE 802.3u.
Format of service Supports Ethernet II, IEEE 802.3, and IEEE 802.1 q/p. Supports frames
frames with a length ranging from 64 bytes to 9600 bytes. Supports Jumbo
frames with a length less than 9600 bytes.
Max. uplink The maximum uplink bandwidth of the N1EFS0 is 622 Mbit/s.
bandwidth The maximum uplink bandwidth of the N2EFS0 is 1.25 Gbit/s.
The maximum uplink bandwidth of the N4EFS0 is 1.25 Gbit/s.
Encapsulation GFP.
format
EPL Supports transparent transmission based on port and Ethernet private line
services based on port+VLAN.
EVPL Supports EVPL services that use the frame encapsulation formats of
MartinioE and stack VLAN.
EVPLAN Supports EVPLAN services. The N1EFS0 uses the frame encapsulation
formats of MPLS MartinioE, MPLS MartinioP and stack VLAN. The
N2EFS0 and N4EFS0 use the frame encapsulation formats of MPLS
MartinioE and stack VLAN.
MPLS Supported.
RSTP Supports broadcast packet suppression and RSTP, compliant with IEEE
802.1w.
CAR Supported.
The granularity is 64 kbit/s.
Service based The N1EFS0 supports the port service, port+VLAN ID service, and port
QoS flow +VLAN PRI service.
classification The N2EFS0 and N4EFS0 support the port flow, port+VLAN ID flow,
and port+VLAN PRI flow.
Flow control Supports the IEEE 802.3x flow control based on port.
function
Loopback Supports inloop at the Ethernet port (PHY layer or MAC layer). Supports
function inloop and outloop at the VC-3 level.
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
E Cross-connect unit
N
C
Control P
FE Ethernet V Interface
Network Switch C
access processor fabric coversion
module D P module
Data E Cross-connect unit
N
C
P
Network processor module Mapping module
Laser
LOS
shutdown
Communication
Communication SCC unit
and control module Reference clock and frame header
SCC unit
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.5 V
converter -48 V/ -60 V
Clock module +1.8 V DC/DC
+2.5 V converter Fuse
+3.3 V backup
power
50 77 125 155
MHz MHz MHz MHz
In the transmit direction, the parallel signals are converted to serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
After the striped Ethernet frame enters the core of network processor, the flow is classified as
per service type and configuration requirements. The frame is encapsulated or decapsulated.
These packets formats are supported:
In the receive direction, services are mapped and forwarded by adding Tunnel and VC double
labels as per service configuration. In the transmit direction, Tunnel or VC is extracted as per
the level (P or PE) of the equipment. Services are then routed or forwarded.
Mapping Module
The mapping module consists of encapsulation and mapping.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is processed. The LCAS function is supported. Ethernet signals are then
converted into SDH signals.
In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation
is compensated. After aligning, packets are decapsulated as per encapsulation format. The
decapsulated data are transmitted to the network processor module in packets.
The control module also contains basic logic units. This module enjoys the following functions:
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for
each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
EFS0
STAT
ACT
PROG
SRV
EFS0
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are no interfaces on the front panel of the EFS0. The interfaces are present on the ETF8
or EFF8.
Table 7-18 Valid slots for the EFS0 and corresponding slots for the ETF8 and EFF8 in the OptiX
OSN 1500B subrack
Valid Slot for the EFS0 Corresponding Slot for the ETF8 and EFF8
Slot 12 Slot 14
Slot 13 Slot 16
Figure 7-11 Slot configuration for the 1:1 TPS protection for the EFS0 in the OptiX OSN 1500B
subrack
Slot 14 TSB8
Slot 18 PIU
Slot 15
Slot 16 ETS8
Slot 19 PIU
Slot 17
Slot 11 Slot 6
Slot 20 Slot 12 EFS0 Protection Slot 7
As shown in Figure 7-11, the protection board housed in slot 12 protects the board housed in
slot 13. The ETS8, housed in slot 16, is used with the working ETS0. The TSB8, housed in slot
14, is used with the protection EFS0.
Mechanical Specifications
The mechanical specifications of the EFS0 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.0
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EFS0 is 35 W.
7.6 EFS4
This section describes the EFS4, a 4 x FE Ethernet processing board with Lanswitch, in terms
of the version, function, principle, front panel, configuration and specifications.
Replaceability The N2EFS4 supports the board version replacement function and can
replace the N1EFS4.
Format of service Supports Ethernet II, IEEE 802.3, and IEEE 802.1 q/p. Supports frames
frames with a length ranging from 64 bytes to 9600 bytes. Supports Jumbo frames
with a length less than 9600 bytes.
Max. uplink The maximum uplink bandwidth of the N1EFS4 is 622 Mbit/s.
bandwidth The maximum uplink bandwidth of the N2EFS4 is 1.25 Gbit/s.
Encapsulation GFP.
format
EPL Supports transparent transmission based on port and Ethernet private line
services based on port+VLAN.
EVPL Supports EVPL services that use the frame encapsulation formats of
MartinioE and stack VLAN.
EVPLAN Supports EVPLAN services. The N1EFS4 uses the frame encapsulation
formats of MPLS MartinioE, MPLS MartinioP and stack VLAN. The
N2EFS4 uses the frame encapsulation formats of MPLS MartinioE and
stack VLAN.
MPLS Supported.
RSTP Supports broadcast packet suppression and RSTP, compliant with IEEE
802.1w.
CAR Supported.
The granularity is 64 kbit/s.
Service based The N1EFS4 supports the port service, port+VLAN ID service, and port
+VLAN PRI service.
QoS flow The N2EFS4 supports the port flow, port+VLAN ID flow, and port
classification +VLAN PRI flow.
Flow control Supports the IEEE 802.3x flow control based on port.
function
Loopback Supports inloop at the Ethernet port (PHY layer or MAC layer). Supports
function inloop and outloop at the VC-3 level.
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Figure 7-12 shows the block diagram for the functions of the EFS4.
E Cross-connect unit
N
C
Control P
FE Ethernet V Interface
Network Switch C
access processor fabric coversion
module D P module
Data E Cross-connect unit
N
C
P
Network processor module Mapping module
Laser
LOS
shutdown
Communication
Communication SCC unit
and control module Reference clock and frame header
SCC unit
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.5 V
converter -48 V/ -60 V
Clock module +1.8 V DC/DC
+2.5 V converter Fuse
+3.3 V backup
power
50 77 125 155
MHz MHz MHz MHz
l Ethernet/ VLAN
In the receive direction, services are mapped and forwarded by adding Tunnel and VC double
labels as per service configuration. In the transmit direction, Tunnel or VC is extracted as per
the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module:
l Supports flow sense and flow classification
l Supports uni-cast, multi-cast and broadcast of the flow
l Provides data priority setting
l Provides weighted fair queuing (WFQ)
l Provides four classes of services (CoS)
Mapping Module
The mapping module consists of encapsulation and mapping.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is processed. The LCAS function is supported. Ethernet signals are then
converted into SDH signals.
In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation
is compensated. After aligning, packets are decapsulated as per encapsulation format. The
decapsulated data are transmitted to the network processor module in packets.
The control module also contains basic logic units. This module enjoys the following functions:
l Writes and reads register
l Provides interface for CPU
l Checks, selects clock
l Performs phase discrimination and frequency division to the clock
l Checks the in-service state of the cross-connect, the SCC and the line boards
l Controls the shutting down of the optical module
l Processes communication
l Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for
each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
EFS4
STAT
ACT
PROG
SRV
FE1
FE2
FE3
FE4
EFS4
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
l Connection status indicator (LINK), which is green when lit.
l Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four FE interfaces on the front panel of the EFS4. Table 7-21 lists the type and usage
of the interfaces.
Pin Description
1 Transmitting positive
2 Transmitting negative
3 Receiving positive
4 Grounding
5 Grounding
6 Receiving negative
7 Grounding
Pin Description
8 Grounding
Mechanical Specifications
The mechanical specifications of the EFS4 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.0
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EFS4 is 30 W.
7.7 EGS2
This section describes the EGS2, a 2 x GE Ethernet processing board with Lanswitch, in terms
of the version, function, principle, front panel, configuration and specifications.
Difference The maximum uplink bandwidth of the N1EGS2 is 1.25 Gbit/s. The
maximum uplink bandwidth of the N2EGS2 is 2.5 Gbit/s.
The number of the VCTRUNKs of the N1EGS2 is 24. The number of the
VCTRUNKs of the N2EGS2 is 48.
The encapsulation formats of the N1EGS2 are GFP, LAPS, and HDLC.
The encapsulation format of the N1EGS2 is GFP.
The N1EGS2 supports the MartinioP encapsulation of the MPLS. The
N2EGS2 does not support the MartinioP encapsulation.
The N2EGS2 supports the board version replacement function.
Replaceability On certain conditions, the N2EGS2 can replace the N1EGS2. When the
N2EGS2 replaces the N1EGS2, the N1EGS2 should not be configured
with MartinioP or CoS of the MPLS.
Format of service Supports Ethernet II, IEEE 802.3, and IEEE 802.1q/p. Supports frames
frames with a length ranging from 64 bytes to 9600 bytes. Supports Jumbo
frames with a length less than 9600 bytes.
Max. uplink The maximum uplink bandwidth of the N1EGS2 is 1.25 Gbit/s.
bandwidth The maximum uplink bandwidth of the N2EGS2 is 2.5 Gbit/s.
Encapsulation The encapsulation formats for the N1EGS2 are GFP, LAPS, and HDLC.
format The encapsulation format for the N2EGS2 is GFP.
CAR Supported.
The granularity is 64 kbit/s.
Service based The N1EGS2 supports the port service, port+VLAN ID service, and port
QoS flow +VLAN PRI service.
classification The N2EGS2 supports the port flow, port+VLAN ID flow, and port
+VLAN PRI flow.
Flow control Supports the IEEE 802.3x flow control based on port.
function
Loopback Supports inloop at the Ethernet port (PHY layer or MAC layer). Supports
function inloop and outloop at the VC-3 level.
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
event
Figure 7-14 shows the block diagram for the functions of the EGS2.
E Cross-connect unit
N
C
Control P
GE Ethernet V Interface
Network Switch C
access processor fabric coversion
module D P module
Data E Cross-connect unit
N
C
P
Network processor module Mapping module
Laser
LOS
shutdown
Communication
Communication SCC unit
and control module Reference clock and frame header
SCC unit
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.5 V
converter -48 V/ -60 V
Clock module +1.8 V DC/DC
+2.5 V converter Fuse
+3.3 V backup
power
50 77 125 155
MHz MHz MHz MHz
In the transmit direction, the parallel signals are converted to serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
After the striped Ethernet frame enters the core of network processor, the flow is classified as
per service type and configuration requirements. The frame is encapsulated or decapsulated.
These packets formats are supported:
l Multi-protocol label switching (MPLS)
l L2MPLS VPN
l Ethernet/ VLAN
In the receive direction, services are mapped and forwarded by adding Tunnel and VC double
labels as per service configuration. In the transmit direction, Tunnel or VC is extracted as per
the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module:
l Supports flow sense and flow classification
l Supports uni-cast, multi-cast and broadcast of the flow
l Provides data priority setting
l Provides weighted fair queuing (WFQ)
l Provides four classes of services (CoS)
Mapping Module
The mapping module consists of encapsulation and mapping.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is processed. The LCAS function is supported. Ethernet signals are then
converted into SDH signals.
In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation
is compensated. After aligning, packets are decapsulated as per encapsulation format. The
decapsulated data are transmitted to the network processor module in packets.
The control module also contains basic logic units. This module enjoys the following functions:
l Writes and reads register
l Provides interface for CPU
l Checks, selects clock
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for
each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
EGS2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT
OUT1 IN1
OUT2 IN2
EGS2
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
l Connection status indicator (LINK), which is green when lit.
l Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are two GE interfaces on the front panel of the EGS2. Table 7-25 lists the type and usage
of the interfaces.
Table 7-26 lists the relation between the board feature code and optical interface type for the
EGS2.
Table 7-26 Relation between the board feature code and the optical interface type
You can use the T2000 to set the following parameters for the EGS2:
l Working mode
l Enabling of the LCAS
l Maximum packet length
l Mapping protocol
Overload optical –3 –3 –3 0
power (dBm)
Extinction ratio 9 9 9 9
(dB)
Mechanical Specifications
The mechanical specifications of the EGS2 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.0
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EGS2 is 43 W.
7.8 EMS4
This section describes the EMS4, a 4 x GE and 16 x FE Ethernet transparent transmission and
convergence board, in terms of the version, function, principle, front panel, configuration and
specifications.
Used with the Accesses 16 x FE signals at the electrical interface when used with
interface board the ETF8.
Accesses 16 x FE signals at the optical interface when used with the
EFF8.
Accesses 8 x FE signals at the electrical interface and 8 x FE signals
at the optical interface when used with the ETF8 and EFF8.
Format of service Supports Ethernet II, IEEE 802.3, IEEE 802.1q TAG, and IEEE
frames 802.1p TAG.
Supports frames with a length ranging from 64 bytes to 9216 bytes.
Supports Jumbo frames with a length less than 9216 bytes.
EPLAN Supports the Layer 2 forwarding function and switching at the client
and SDH sides.
Supports 1k MAC switching or 4K VLAN MAC switching.
Supports the function of self-learning the source MAC address.
The length of the MAC address table is 128k. The aging time of the
MAC address can be set and queried.
The configuration of static MAC routes is supported.
Supports data isolation based on VB+VLAN.
Supports the creation, deletion and query of VB. The maximum
number of VBs is two.
VLAN Supports VLAN and QinQ, the addition, deletion and switching of
VLAN labels, compliant with IEEE 802.1q/p.
Multicast(IGMP- Supported.
Snooping)
ETH-OAM Supports CC for the multicast and LB test for the unicast.
Link convergence Supports manual link convergence and static link convergence.
Protection Supports the 1+1 hot backup for the board and the PPS protection.
CAR Supported.
The granularity is 64 kbit/s.
LPT Supported.
Flow control function Supports the IEEE 802.3x flow control based on port.
Loopback function Supports inloop at the Ethernet port (PHY layer) and outloop at the
SDH side.
Ethernet performance Supports Ethernet performance monitoring RMON at the port level
monitoring and VCTRUNK.
Alarm and Provides rich alarms and performance events for easy management
performance event and maintenance of the equipment.
E Cross-connect unit
N
C
Control P
GE/FE Ethernet V Interface
Network Switch C
access processor fabric coversion
module D P module
Data E Cross-connect unit
N
C
P
Network processor module Mapping module
Laser
LOS
shutdown
Communication
Communication SCC unit
and control module Reference clock and frame header
SCC unit
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.5 V
converter -48 V/ -60 V
Clock module +1.8 V DC/DC
+2.5 V converter
50 77 125 155
MHz MHz MHz MHz
If the switch is not required on the local, the data services are forwarded to other local ports
according to the configuration. If the data services are to be transmitted to the upstream SDH
line, the encapsulation module encapsulates the Ethernet frames in the GFP-F, LAPS or HDLC
formats. Finally, the encapsulation module transmits the frames to the mapping module, which
maps frames into VC-4/VC-3/VC-12, concatenated frames or a single VC-3 concatenated frame.
The interface module then transmits the frames to the cross-connect unit.
Mapping Module
The mapping module consists of encapsulation and mapping.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, GFP or HDLC
format. The concatenation is processed. The LCAS function is supported. Ethernet signals are
then converted into SDH signals.
In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation
is compensated. After aligning, packets are decapsulated as per encapsulation format. The
decapsulated data are transmitted to the network processor module in packets.
The control module also contains basic logic units. This module enjoys the following functions:
l Writes and reads register
l Provides interface for CPU
l Checks, selects clock
l Performs phase discrimination and frequency division to the clock
l Checks the in-service state of the cross-connect, the SCC and the line boards
l Controls the shutting down of the optical module
l Processes communication
l Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for
each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
EMS4
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
LINK ACT
EMS4
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
l Connection status indicator (LINK), which is green when lit.
l Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four pairs of optical interfaces on the front panel of the EMS4. Table 7-29 lists the
type and usage of the optical interfaces.
Table 7-30 Valid slots for the EMS4 and corresponding slots for the ETF8 and EFF8 in the
OptiX OSN 1500A subrack
Valid Slot for the EMS4 Corresponding Slot for the ETF8 and EFF8
Table 7-31 Valid slots for the EMS4 and corresponding slots for the ETF8 and EFF8 in the
OptiX OSN 1500B subrack
Valid Slot for the EMS4 Corresponding Slot for the ETF8 and EFF8
Table 7-32 Relation between the board feature code and the optical interface type
Board Barcode Feature Code Optical Interface Type
Protection Principle
When the BPS protection is performed to the EMS4, the GE and FE ports use the single-fed
dual-selective scheme to get protected. The EMS4 has four four GE ports and 16 FE ports, which
may be connected to many communication devices. Normally, the active board is working and
services are transmitted in the two directions of the active link. On the backup link, the EMS4
disables the transmission of all ports. In this case, the ports of opposite board are in the Linkdown
state. At the same time, the opposite board enables the transmission and does not transmit
services. In this way, the receive ports of the backup EMS4 are not in the Linkdown state. The
solid lines in Figure 7-18 show how the EMS4 normally works.
Active
communication
No.1 equipment
A
Active
Standby
EMS4 communication
No.2 equipment
No.3
Active
communication
equipment
XCS
B
Standby
No.1 communication
equipment
No.2
Standby Active
EMS4 No.3 communication
equipment
C
Standby
communication
equipment
l BPS Protection
For the BPS protection, when the active board detects the Linkdown fault of any link or any
board fault, the cross-connect board switches all services to the standby board. In this way,
services are protected. As the solid lines shown in Figure 7-19. The services numbered 1, 2 and
3 are all switched to the standby EMS4 and corresponding communication equipment.
Active
communication
No.1 equipment
A
Active
Standby
EMS4 communication
No.2 equipment
No.3
Active
communication
equipment
XCS
B
Standby
No.1 communication
equipment
No.2
Standby Active
EMS4 No.3 communication
equipment
C
Standby
communication
equipment
l PPS Protection
For the PPS protection, when the active board detects the Linkdown fault of any link or any
board fault, the cross-connect board switches all services to the standby board. In this way,
services are protected. The solid lines in Figure 7-20 show how the PPS protection is performed.
Only the service numbered 1 is switched to the standby EMS4 and the standby communication
equipment.
Active
communication
No.1 equipment
A
Active
Standby
EMS4 communication
No.2 equipment
No.3
Active
communication
equipment
XCS
B
Standby
No.1 communication
equipment
No.2
Standby Active
EMS4 No.3 communication
equipment
C
Standby
communication
equipment
The conditions that trigger the protection for the EMS4 are as follows:
l Fault at at the PHY layer of the MAC port, also Linkdown
l Fault in key board hardware units, such as the power supply module and the optical module
WARNING
When the board-level protection is performed, FE ports only support the 100M full duplex mode
and GE ports support the auto-negotiation and 1000M full duplex mode.
Board Configuration
Two EMS4 boards should be configured for the protection. One EMS4 is the active board and
the other is the standby board. For the protection, the access capacity of the slot for the standby
board must be larger than that of the slot for the active board.
l Working mode
l Enabling of the LCAS
l Maximum packet length
l Mapping protocol
Item Specification
Overload optical –3 –3 –3 0
power (dBm)
Extinction ratio 9 9 9 9
(dB)
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the EMS4 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EMS4 is 65 W if
the EMS4 is not used with an interface board.
In the normal temperature (25℃), the maximum power consumption of the EMS4 is 75 W if
the EMS4 is used with an interface board.
7.9 EGS4
This section describes the EGS4, a 4 x GE Ethernet convergence board, in terms of the version,
function, principle, front panel, configuration and specifications.
Format of service Supports Ethernet II, IEEE 802.3, IEEE 802.1q TAG, and IEEE
frames 802.1p TAG.
Supports frames with a length ranging from 64 bytes to 9216 bytes.
Supports Jumbo frames with a length less than 9216 bytes.
EPLAN Supports the Layer 2 forwarding function and switching at the client
and SDH sides.
Supports 1k MAC switching or 4k VLAN MAC switching.
Supports the function of self-learning the source MAC address. The
length of the MAC address table is 128k. The aging time of the MAC
address can be set and queried. The configuration of static MAC
routes is supported.
Supports data isolation based on VB+VLAN.
Supports the creation, deletion and query of VB. The maximum
number of VBs is two.
VLAN Supports VLAN and QinQ, the addition, deletion and switching of
VLAN labels, compliant with IEEE 802.1q/p.
Multicast(IGMP- Supported.
Snooping)
ETH-OAM Supports CC for the multicast and LB test for the unicast.
Link convergence Supports manual link convergence and static link convergence.
Protection Supports the 1+1 hot backup for the board and the PPS protection.
CAR Supported.
The granularity is 64 kbit/s.
LPT Supported.
Flow control Supports the IEEE 802.3x flow control based on port.
function
Alarm and Provides rich alarms and performance events for easy management
performance event and maintenance of the equipment.
E Cross-connect unit
N
C
Control P
GE Ethernet V Interface
Network Switch C
access processor fabric coversion
module D P module
Data E Cross-connect unit
N
C
P
Network processor module Mapping module
Laser
LOS
shutdown
Communication
Communication SCC unit
and control module Reference clock and frame header
SCC unit
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.5 V
converter -48 V/ -60 V
Clock module +1.8 V DC/DC
+2.5 V converter
50 77 125 155
MHz MHz MHz MHz
conversion is unnecessary. At PHY layer, the electrical signals are decoded and the ETH_LOS
alarms are tested. The electrical signals are converted from serial signals to parallel signals and
then sent to network processor.
In the transmit direction, the parallel signals are converted to serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
After the striped Ethernet frame enters the core of network processor, the flow is classified as
per service type and configuration requirements. The frame is encapsulated or decapsulated.
These packets formats are supported:
l Ethernet/ VLAN
Mapping Module
The mapping module consists of encapsulation and mapping.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, GFP or HDLC
format. The concatenation is processed. The LCAS function is supported. Ethernet signals are
then converted into SDH signals.
In the downstream direction, SDH signals are demapped. The time delay of virtual concatenation
is compensated. After aligning, packets are decapsulated as per encapsulation format. The
decapsulated data are transmitted to the network processor module in packets.
The control module also contains basic logic units. This module enjoys the following functions:
l Writes and reads register
l Provides interface for CPU
l Checks, selects clock
l Performs phase discrimination and frequency division to the clock
l Checks the in-service state of the cross-connect, the SCC and the line boards
l Controls the shutting down of the optical module
l Processes communication
l Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for
each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 155 MHz.
EGS4
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
LINK ACT
EGS4
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
l Connection status indicator (LINK), which is green when lit.
l Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four pairs of optical interfaces on the front panel of the EGS4. Table 7-35 lists the
type and usage of the optical interfaces.
Table 7-36 lists the relation between the board feature code and optical interface type for the
EGS4.
Table 7-36 Relation between the board feature code and the optical interface type
Protection Principle
When the BPS protection is performed to the EGS4, the GE and FE ports use the single-fed dual-
selective scheme to get protected. The EGS4 has four four GE ports and 16 FE ports, which may
be connected to many communication devices. Normally, the active board is working and
services are transmitted in the two directions of the active link. On the standby link, the EGS4
disables the transmission of all ports. In this case, the ports of the opposite board are in the
Linkdown state. At the same time, the opposite board enables the transmission and does not
transmit services. In this way, the receive ports of the standby EGS4 are not in the Linkdown
state. The solid lines in Figure 7-23 show how the EGS4 normally works.
Active
communication
No.1 equipment
A
Active Standby
EGS4 communication
No.2 equipment
No.3
Active
communication
equipment
XCS
B
Standby
No.1 communication
equipment
No.2
Standby Active
EGS4 No.3 communication
equipment
C
Standby
communication
equipment
l BPS Protection
For the BPS protection, when the active board detects the Linkdown fault of any link or any
board fault, the cross-connect board switches all services to the standby board. In this way,
services are protected. The lines in Figure 7-24 show how the BPS protection is performed. The
services numbered 1, 2 and 3 are all switched to the standby EGS4 and corresponding
communication equipment.
Active
communication
No.1 equipment
A
Active Standby
EGS4 communication
No.2 equipment
No.3
Active
communication
equipment
XCS
B
Standby
No.1 communication
equipment
No.2
Standby Active
EGS4 No.3 communication
equipment
C
Standby
communication
equipment
l PPS Protection
For the PPS protection, when the active board detects the Linkdown fault of any link or any
board fault, the cross-connect board switches all services to the standby board. In this way,
services are protected. The solid lines in Figure 7-25 show how the PPS protection is performed.
Only the service numbered 1 is switched to the standby EGS4 and the standby communication
equipment.
Active
communication
No.1 equipment
A
Active Standby
EGS4 communication
No.2 equipment
No.3
Active
communication
equipment
XCS
B
Standby
No.1 communication
equipment
No.2
Standby Active
EGS4 No.3 communication
equipment
C
Standby
communication
equipment
The conditions that trigger the protection for the EGS4 are as follows:
WARNING
When the protection is performed, the GE ports support auto-negotiation and 1000M full duplex
modes.
Board Configuration
Two EGS4 boards should be configured for the protection. One EGS4 is the active board and
the other is the standby board. For the protection, the access capacity of the slot for the standby
board must be larger than that of the slot for the active board.
You can use the T2000 to set the following parameters for the EGS4:
l Working mode
l Enabling of the LCAS
l Maximum packet length
l Mapping protocol
Item Specification
Overload optical –3 –3 –3 0
power (dBm)
Extinction ratio 9 9 9 9
(dB)
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the EGS4 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EGS4 is 70 W.
7.10 EGR2
This section describes the EGR2, a 2 x GE Ethernet processing board, in terms of the version,
function, principle, front panel, configuration and specifications.
Basic function Accesses and processes 2 x GE services. Supports the RPR feature.
Format of service Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG.
frames Supports frames with a length ranging from 64 bytes to 9600 bytes.
Supports Jumbo frames with a length less than 9600 bytes.
EVPL Supports EVPL services. The frame format can be Ethernet II, IEEE
802.3, IEEE 802.1q TAG, or MPLS Martini.
Supports the MPLS encapsulation and forwarding based on port and
port+VLAN.
Supports five types of LSP, including ingress LSP, egress LSP, transit
LSP, RPR ingress LSP, and RPR transit LSP. Supports 512 LSPs.
EVPLAN Supports EVPLAN services and uses the stack VLAN encapsulation.
Supports the function of self-learning the source MAC address. For the
N2EGR2, the capacity of the MAC address table is 64k. The aging time
of the MAC address can be set and queried.
Supports the configuration of static MAC routes (maximum: 4k).
Supports data isolation based on VB+VLAN.
Supports the creation, deletion and query of the VB. The maximum
number of the VBs is 16. The maximum number of logical ports for
each VB is 32.
VLAN Supports 4096 VLAN labels, the addition and deletion of VLAN labels,
and the switching function, compliant with IEEE 802.1q/p.
CAR Supported.
The granularity is 64 kbit/s.
Flow classification Supports the port flow, port+VLAN ID flow, and port+VLAN ID
+VLAN PRI flow.
Flow control Supports the IEEE 802.3x flow control based on port.
function
Echo test frame Supports the Echo function of the PRP OAM, which is used to test the
availability of the link.
Loopback function Supports inloop at the Ethernet port (PHY layer or MAC layer).
Alarm and Provides rich alarms and performance events for easy management and
performance event maintenance of the equipment.
Topology Supported.
automatic
discovery
E Cross-
Control N
singnal connect
C
P unit
GE/FE Ethernet RPR RPR V
Network Switch C Interface
access processor fabric MAC MAC P conversion
module east west D
module
Data N Cross-
C
P connect
unit
Network processor module RPR protocol
process module Mapping module
50 MHZ
77 MHZ
100 MHZ
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.5 V
converter -48 V/ -60 V
+2.5 V DC/DC
+1.8 V converter Fuse
+3.3 V backup
power
conversion is unnecessary. At PHY layer, the electrical signals are decoded and the ETH_LOS
alarms are tested. The electrical signals are converted from serial signals to parallel signals and
then sent to network processor.
In the transmit direction, the parallel signals are converted to serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
In the receive direction, services are mapped and forwarded by adding Tunnel and VC double
labels as per service configuration. In the transmit direction, Tunnel or VC is extracted as per
the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module:
l Supports flow sense and flow classification
l Supports uni-cast, multi-cast and broadcast of the flow
l Provides data priority setting
l Provides weighted fair queuing (WFQ)
l Provides four classes of services (CoS)
Mapping Module
The mapping module consists of encapsulation and mapping.
In the upstream direction, the virtual concatenation supports LCAS function. The encapsulation
formats are LAPS and GFP.
In the downstream direction, virtual concatenations are received. The time delay of virtual
concatenation is compensated. After aligning, packets are decapsulated as per encapsulation
format. The decapsulated data are transmitted to the RPR protocol processing module in packets.
The control module also contains basic logic units. This module enjoys the following functions:
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for
each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 100 MHz.
EGR2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT
OUT1 IN1
OUT2 IN2
EGR2
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
l Connection status indicator (LINK), which is green when lit.
l Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are two optical interfaces on the front panel of the EGR2. Table 7-39 lists the type and
usage of the optical interfaces.
Table 7-40 Relation between the board feature code and the optical interface type
Board Barcode Feature Code Optical Interface Type
Mechanical Specifications
The mechanical specifications of the EGR2 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.1
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EGR2 is 40 W.
7.11 EMR0
This section describes the EMR0, a 12 x FE and 1 x GE Ethernet ring processing board, in terms
of the version, function, principle, front panel, configuration and specifications.
Difference The N2EMR0 supports all functions of the N1EMR0. The N2EMR0 also
has some new functions and extends some functions of the N1EMR0. For
details, see Table 7-43.
EVPLAN services Supports EVPLAN services Supports EVPLAN services and uses
and uses the stack VLAN the stack VLAN encapsulation.
encapsulation.
MAC address table Supports the 16k MAC Supports the 64k MAC address table.
address table.
Flow classification Supports the port flow, port Supports the port flow, port+VLAN ID
+VLAN ID flow, and port flow, and port+VLAN ID+VLAN PRI
+VLAN PRI flow. flow.
Specification of the Supports the 10Base-T/100Base-TX signals when used with the ETF8.
optical interface The maximum transmission distance is 100 m.
Supports the 100Base-FX signals when used with the EFF8, compliant
with IEEE 802.3u.
Format of service Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG . Supports
frames frames with a length ranging from 64 bytes to 9600 bytes. Supports
Jumbo frames with a length less than 9600 bytes.
EVPL Supports EVPL services. The frame format can be Ethernet II, IEEE
802.3, IEEE 802.1q TAG, or MPLS Martini. EVPL services support
the MPLS encapsulation and forwarding based on port and port
+VLAN. Supports five types of LSP, including ingress LSP, egress
LSP, transit LSP, RPR ingress LSP, and RPR transit LSP. Supports 512
LSPs.
EVPLAN Supports EVPLAN services and uses the stack VLAN encapsulation.
Supports the function of self-learning the source MAC address. For the
N2EMR0, the capacity of the MAC address table is 16k. The aging time
of the MAC address can be set and queried.
Supports the configuration of static MAC routes (maximum: 4k).
Supports data isolation based on VB+VLAN.
Supports the creation, deletion and query of the VB. The N2EMR0
supports a maximum of 16 VBs. The maximum number of logical ports
for each VB is 32. The N1EMR0 supports a maximum of 32 VBs. The
maximum number of logical ports for each VB is 16.
VLAN Supports 4096 VLAN labels, the addition and deletion of VLAN labels,
and the switching function, compliant with IEEE 802.1q/p.
RSTP Supports broadcast packet suppression and RSTP, compliant with IEEE
802.1w.
CAR Supported.
The granularity is 64 kbit/s.
Flow classification The N1EMR0 supports the port flow, port+VLAN ID flow, and port
+VLAN PRI flow.
The N2EMR0 supports the port flow, port+VLAN ID flow, and port
+VLAN ID+VLAN PRI flow.
Flow control Supports the IEEE 802.3x flow control based on port.
function
Echo test frame Supports the Echo function of the PRP OAM, which is used to test the
availability of the link.
Loopback function Supports inloop at the Ethernet port (PHY layer or MAC layer).
Alarm and Provides rich alarms and performance events for easy management and
performance maintenance of the equipment.
events
Topology Supported.
automatic
discovery
E Cross-
Control N
singnal connect
C
P unit
GE/FE Ethernet RPR RPR V
Network Switch C Interface
access processor fabric MAC MAC P conversion
module east west D
module
Data N Cross-
C
P connect
unit
Network processor module RPR protocol
process module Mapping module
50 MHZ
77 MHZ
100 MHZ
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.5 V
converter -48 V/ -60 V
+2.5 V DC/DC
+1.8 V converter Fuse
+3.3 V backup
power
conversion is unnecessary. At PHY layer, the electrical signals are decoded and the ETH_LOS
alarms are tested. The electrical signals are converted from serial signals to parallel signals and
then sent to network processor.
In the transmit direction, the parallel signals are converted to serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
In the receive direction, services are mapped and forwarded by adding Tunnel and VC double
labels as per service configuration. In the transmit direction, Tunnel or VC is extracted as per
the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module:
l Supports flow sense and flow classification
l Supports uni-cast, multi-cast and broadcast of the flow
l Provides data priority setting
l Provides weighted fair queuing (WFQ)
l Provides four classes of services (CoS)
Mapping Module
The mapping module consists of encapsulation and mapping.
In the upstream direction, the virtual concatenation supports LCAS function. The encapsulation
formats are LAPS and GFP.
In the downstream direction, virtual concatenations are received. The time delay of virtual
concatenation is compensated. After aligning, packets are decapsulated as per encapsulation
format. The decapsulated data are transmitted to the RPR protocol processing module in packets.
The control module also contains basic logic units. This module enjoys the following functions:
l Writes and reads register
l Provides interface for CPU
l Checks, selects clock
l Performs phase discrimination and frequency division to the clock
l Checks the in-service state of the cross-connect, the SCC and the line boards
l Controls the shutting down of the optical module
l Processes communication
l Control indicators
Clock Unit
This clock unit tracing the system reference clock and generates the required working clocks for
each chip. The frequencies of these clocks are: 50 MHz, 77MHz, 125 MHz and 100 MHz.
EMR0
STAT
ACT
PROG
SRV
LINK
ACT
CLASS 1
LASER
PRODUCT
OUT1 IN1
FE1
FE2
FE3
FE4
EMR0
EMR0
STAT
ACT
PROG
SRV
LINK
ACT
CLASS 1
LASER
PRODUCT
OUT1
IN1
FE1
FE2
FE3
FE4
EMR0
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
l Connection status indicator (LINK), which is green when lit.
l Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are five interfaces on the front panel of the EMR0. Table 7-45 lists the type and usage of
the interfaces.
Table 7-46 and Table 7-47 list the valid slots for the EMR0 and corresponding slots for the
ETF8 and EFF8.
Table 7-46 Valid slots for the EMR0 and corresponding slots for the ETF8 and EFF8 in the
OptiX OSN 1500A subrack
Valid Slot for the EMR0 Corresponding Slot for the ETF8 and EFF8
Table 7-47 Valid slots for the EMR0 and corresponding slots for the ETF8 and EFF8 in the
OptiX OSN 1500B subrack
Valid Slot for the EMR0 Corresponding Slot for the ETF8 and EFF8
Slot 12 Slot 15
Slot 13 Slot 17
Table 7-48 lists the relation between the board feature code and optical interface type for the
EMR0.
Table 7-48 Relation between the board feature code and the optical interface type
You can use the T2000 to set the following parameters for the EMR0:
l Working mode
l Enabling of the LCAS
l Maximum packet length
l Mapping protocol
Item Specification
Item Specification
Overload optical –3 –3 –3 0
power (dBm)
Extinction ratio 9 9 9 9
(dB)
Mechanical Specifications
The mechanical specifications of the EMR0 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.2
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EMR0 is 50 W.
7.12 ADL4
This section describes the ADL4, a 1 x STM-4 ATM processing board, in terms of the version,
function, principle, front panel, configuration and specifications.
The code behind the board name in the barcode is the board feature code. The board feature code
of the ADL4 indicates the optical interface type.
7.12.7 Board Configuration Reference
You can use the T2000 to set parameters for the ADL4.
7.12.8 Technical Specifications
The technical specifications of the ADL4 cover the optical interface specifications, board
dimensions, weight and power consumption.
Optical interface type Supports the optical interfaces of the S-4.1, L-4.1, L-4.2 and Ve-4.2
types.
Flow type and QoS Supports IETF RFC2514, ATM forum TM4.0.
ATM protection (ITU- Supports unidirectional or bidirectional 1+1, 1:1, VP-Ring, VC-
T I.630) Ring protection schemes.
Maintenance feature Supports inloop and outloop at the ATM layer levels, supports
inloop at the optical interface, which are used for maintenance and
fault locating.
Alarm and performance Provides rich alarms and performance events. The loopback is used
event for maintenance and fault locating.
Figure 7-31 shows the block diagram for the functions of the ADL4.
50 MHz
77 MHz
Clock module
100 MHz
3.3 V DC/DC Fuse -48 V/ -60 V
converter -48 V/ -60 V
+1.2 V
Fuse
+1.5 V +3.3 V backup
power
DC/DC
+1.8 V converter
+2.5 V
ATM Module
The ATM module mainly performs ATM layer functions in the ATM protocol. These functions
include:
l Flow control
l Extraction and generation of cell headers
l ATM switching
E3 Module
The E3 module mainly processes the ATM services at E3 rate. This module:
l Mappings the ATM cells into E3 containers
l Demappings E3 containers to ATM cells
l Perform ATM physical layer function to the ATM service at E3 rate
Mapping Module
The mapping module:
l Mappings ATM cells into SDH frame payload
l Demappings SDH frame payload to ATM cells
l Supports ATM physical layer functions
l Supports VC-4-Xv (X≤4) virtual concatenation
Clock Module
This module mainly generates working clocks for each chip. The frequencies of the clocks are
50 MHz, 77 MHz and 100 MHz.
ADL4
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1 IN1
ADL4
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There is one optical interface on the front panel of the ADL4. Table 7-51 lists the type and usage
of the optical interface.
Table 7-52 Relation between the board feature code and the optical interface type
Board Feature Code Optical Interface Type
SSN1ADL410 10 S-4.1
SSN1ADL411 11 L-4.1
SSN1ADL412 12 L-4.2
SSN1ADL413 13 Ve-4.2
l Port type
l Flow type
l Service type
l Peak cell rate (PCR)
l Sustainable cell rate (SCR)
l Maximum cell burst size
l Cell delay variation tolerance (CDVT)
Item Specification
Overload optical –8 –8 –8 –8
power (dBm)
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the ADL4 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the ADL4 is 41 W.
7.13 ADQ1
This section describes the ADQ1, a 4 x STM-1 ATM processing board, in terms of the version,
function, principle, front panel, configuration and specifications.
Optical interface type Supports the optical interfaces of the Ie-1, S-1.1, L-1.1, L-1.2 and
Ve-1.2 types.
Statistical Supported.
multiplexing
Flow type and QoS Supports IETF RFC2514 and ATM forum TM4.0.
ATM protection (ITU- Supports unidirectional or bidirectional 1+1, 1:1, VP-Ring, VC-
T I.630) Ring protection schemes.
Maintenance feature Supports inloop and outloop at the ATM layer levels, supports
inloop at the optical interface, which are used for maintenance and
fault locating.
Alarm and Provides rich alarms and performance events, which are used for
performance event maintenance and fault locating.
50 MHz
77 MHz
Clock module
100 MHz
3.3 V DC/DC Fuse -48 V/ -60 V
converter -48 V/ -60 V
+1.2 V
Fuse
+1.5 V +3.3 V backup
power
DC/DC
+1.8 V converter
+2.5 V
ATM Module
The ATM module mainly performs ATM layer functions in the ATM protocol. These functions
include:
l Flow control
l Extraction and generation of cell headers
l ATM switching
E3 Module
The E3 module mainly processes the ATM services at E3 rate. This module:
Mapping Module
The mapping module:
Clock Module
This module mainly generates working clocks for each chip. The frequencies of the clocks are
50 MHz, 77 MHz and 100 MHz.
ADQ1
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
ADQ1
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four pairs of optical interfaces on the front panel of the ADQ1. Table 7-55 lists the
type and usage of the optical interfaces.
Table 7-56 Relation between the board feature code and the optical interface type
Board Feature Code Optical Interface Type
SSN1ADQ110 10 S-1.1
SSN1ADQ111 11 L-1.1
SSN1ADQ112 12 L-1.2
SSN1ADQ113 13 Ve-1.2
SSN1ADQ114 14 Ie-1
Item Specification
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the ADQ1 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the ADQ1 is 37 W.
7.14 IDL4
This section describes the IDL4, a 1 x STM-4 ATM processing board, in terms of the version,
function, principle, front panel, configuration and specifications.
Optical interface Supports the optical interfaces of the S-4.1, L-4.1, L-4.2 and Ve-4.2
type types.
IMA function Accesses and processes IMA services when used with E1 service
(ATM Forum IMA processing board N1PQ1/N1PQM.
1.1 standard) Supports a maximum of 63 IMA E1 services.
One ATM port supports a maximum of 16 IMA groups. Each IMA group
supports 1–32 E1 signals.
One ATM port supports a maximum of E1 links of 16 non-IMA groups.
The maximum IMA multichannel delay is 226 ms.
IMA feature Accesses and processes IMA services when used with E1 service
processing board.
Processes IMA services for a maximum of 63 x E1 signals.
Supports a maximum of 16 IMA groups. Each IMA group supports 1–
32 E1 signals.
The maximum IMA multichannel delay is 226 ms.
Statistical Supported.
multiplexing
Flow type and QoS Supports IETF RFC2514 and ATM forum TM4.0.
Maintenance Supports inloop and outloop at the ATM layer levels, supports inloop
feature at the optical interface, which are used for maintenance and fault
locating.
Alarm and Provides rich alarms and performance events, which are used for
performance event maintenance and fault locating.
Note: The IMA function can encapsulate ATM cells into E1 signals. The IMA group can
coexist with single E1. The IMA group can dynamically increase or decrease the bandwidth
to enhance the bandwidth utilization. The IMA group can also converge 2M services, and can
connect to other IMA equipment.
50 MHz
77 MHz Clock
module
100 MHz
+3.3 V Fuse -48 V/ -60 V
DC/DC
converter -48 V/ -60 V
+1.2 V
+1.5 V Fuse
+3.3 V backup
+1.8 V DC/DC power
+2.5 V converters
ATM Module
The ATM module mainly performs ATM layer functions in the ATM protocol. These functions
include:
l Flow control
l Extraction and generation of cell headers
l ATM switching
IMA Module
This module mainly performs IMA protocol functions. These functions are:
l Separation and re-creation of ATM cells
l Frame synchronization
l Insertion and extraction of IMA control protocol (ICP) cells
l Management of IMA groups
Mapping Module
The mapping module:
l Mappings ATM cells into SDH frame payload
l Demappings SDH frame payload to ATM cells
l Supports ATM physical layer functions
l Supports VC-4-Xv (X≤4) virtual concatenation
Clock Module
This module mainly generates working clocks for each chip. The frequencies of the clocks are
50 MHz, 77 MHz and 100 MHz.
IDL4
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1 IN1
IDL4
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are one optical interface on the front panel of the IDL4. Table 7-59 lists the type and
usage of the optical interface.
Table 7-60 Relation between the board feature code and the optical interface type
Board Feature Code Optical Interface Type
SSN1IDL410 10 S-4.1
SSN1IDL411 11 L-4.1
SSN1IDL412 12 L-4.2
SSN1IDL413 13 Ve-4.2
The paired slots for the IDL4 are slots 13 and 12.
Wavelength (nm) 1274 to 1356 1280 to 1335 1480 to 1580 1480 to 1580
Transmission 2 to 15 15 to 40 40 to 80 80 to 100
distance (km)
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the IDL4 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the IDL4 is 41 W.
7.15 IDQ1
This section describes the IDQ1, a 4 x STM-1 ATM processing board, in terms of the version,
function, principle, front panel, configuration and specifications.
Optical interface Supports the optical interfaces of the Ie-1, S-1.1, L-1.1, L-1.2 and Ve-1.2
type types.
IMA function Accesses and processes IMA services when used with E1 service
(ATM Forum IMA processing board N1PQ1/N1PQM.
1.1 standard) Supports a maximum of 63 IMA E1 services.
One ATM port supports a maximum of 16 IMA groups. Each IMA group
supports 1–32 E1 signals.
One ATM port supports a maximum of E1 links of 16 non-IMA groups.
The maximum IMA multichannel delay is 226 ms.
IMA feature Accesses and processes IMA services when used with E1 service
processing board.
Processes IMA services for a maximum of 63 x E1 signals.
Supports a maximum of 16 IMA groups. Each IMA group supports 1–
32 E1 signals.
The maximum IMA multichannel delay is 226 ms.
Statistical Supported.
multiplexing
Flow type and QoS Supports IETF RFC2514 and ATM forum TM4.0.
Maintenance Supports inloop and outloop at the ATM layer levels, supports inloop
feature at the optical interface, which are used for maintenance and fault
locating.
Alarm and Provides rich alarms and performance events, which are used for
performance event maintenance and fault locating.
Note: The IMA function can encapsulate ATM cells into E1 signals. The IMA group can
coexist with single E1. The IMA group can dynamically increase or decrease the bandwidth
to enhance the bandwidth utilization. The IMA group can also converge 2M services, and can
connect to other IMA equipment.
4 x 155 4 x 155
high speed bus
Mbit/s Mbit/s
E/O Cross-connet unit A
50 MHz
77 MHz Clock
module
100 MHz
+3.3 V Fuse -48 V/ -60 V
DC/DC
converter -48 V/ -60 V
+1.2 V
+1.5 V Fuse
+3.3 V backup
+1.8 V DC/DC power
+2.5 V converters
ATM Module
The ATM module mainly performs ATM layer functions in the ATM protocol. These functions
include:
l Flow control
l Extraction and generation of cell headers
l ATM switching
IMA Module
This module mainly performs IMA protocol functions. These functions are:
Mapping Module
The mapping module:
Clock Module
This module mainly generates working clocks for each chip. The frequencies of the clocks are
50 MHz, 77 MHz and 100 MHz.
IDQ1
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
IDQ1
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four optical interfaces on the front panel of the IDQ1. Table 7-63 lists the type and
usage of the optical interfaces.
Table 7-64 Relation between the board feature code and the optical interface type
Board Barcode Feature Code Optical Interface Type
SSN1IDQ110 10 S-1.1
SSN1IDQ111 11 L-1.1
SSN1IDQ112 12 L-1.2
SSN1IDQ113 13 Ve-1.2
SSN1IDQ114 14 Ie-1
Item Specification
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the IDQ1 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the IDQ1 is 41 W.
7.16 MST4
This section describes the MST4, a 4-channel multi-service transparent transmission board, in
terms of the version, function, principle, front panel, configuration and specifications.
Basic function Provides four independent ports to access multiple services, and supports
the transparent transmission of the SAN and Video services.
Distance The first and second ports support the distance extension function at the
extension SDH side. (FC100: 3000 km; FC200: 1500 km)
Max. uplink 2.5 Gbit/s (Four 622 Mbit/s buses are present on the backplane to directly
bandwidth connect to the cross-connect unit.)
ESCON Accesses four-channel ESCON services, and the total bandwidth is less
than 2.5 Gbit/s.
DVB-ASI Accesses four-channel DVB-ASI services, and the total bandwidth is less
than 2.5 Gbit/s.
Maintenance Supports the inloop and outloop at the port level of the client side. The
feature loopack is used for maintenance and fault locating.
Alarm and Provides rich alarms and performance events, which are used for
performance maintenance and fault locating.
event
Encaps Cross-connect
FC1_ FC2 FC1_
RCV SND ulation unit A/B
FC50 Client-
FC100 side Interface
FC200 access Mapping conversion
FICON module Cross-connect
module FC1_ FC1_ Decaps
DVB-ASI FC2 RCV ulation unit A/B
ESCON
SND
FC processing module
Encapsulation and
mapping module
Communication SCC unit
Communication and control
module Reference clock and frame header Cross-
connect unit
100 MHz
125 MHz
135 MHz Clock
212.5 MHz module
622 MHz
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.2 V converter -48 V/ -60 V
+1.5 V DC/DC
+1.8 V
+2.5 V converter Fuse
+3.3 V backup
power
According to signal flow direction, the function modules inside the chip can be classified into
modules in ingress direction and ones in egress direction. The ingress direction is for processing
from client side to line side. The egress direction is for line-side processing.
Ingress direction:
Through GFP-T encapsulation, 64B/65B conversion is performed to data bytes after decoding.
The data bytes are then mapped under GFP-T protocol.
Egress direction:
SDH data frames are received from the line-side interface module. After the overhead is
processed, GFP-T data frames are extracted from SDH concatenated channels and then are
transmitted to the decapsulating module for decapsulation.
MST4
STAT
ACT
PROG
SRV
OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
MST4
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four pairs of optical interfaces on the front panel of the MST4. Table 7-68 lists the
type and usage of the optical interfaces.
Table 7-69 lists the relation between the board feature code and service type.
Table 7-69 Relation between the board feature code and service type
SSN1MST410 10 2 x FC (SM) 2 km
SSN1MST411 11 2 x FC (SM) 15 km
ESCON/DVB-ASI (MM)
ESCON/DVB-ASI (SM)
SSN1MST417 17 1 x FC (SM) 2 km
2 x ESCON/DVB-ASI (SM) -
SSN1MST418 18 1 x FC (SM) 2 km
2 x ESCON/DVB-ASI (MM) -
You can use the T2000 to set the following parameters for the MST4:
l J1 byte
l C2 byte
Item Specification
Item Specification
Transmission 15 2 0.5 2 15
distance (km)
Mechanical Specifications
The mechanical specifications of the MST4 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 0.9
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the MST4 is 26 W.
This chapter describes the interface and switching boards. The interface boards are used to access
cables and fibers. The switching boards are used to provide the TPS protection.
8.1 L12S
This section describes the L12S, a 16 x E1/T1 electrical interface switching board, in terms of
the version, function, principle, front panel and specifications.
8.2 D12B
This section describes the D12B, a 32 x E1/T1 electrical interface board, in terms of the version,
function, principle, front panel and specifications.
8.3 D12S
This section describes the D12S, a 32 x E1/T1 electrical interface switching board, in terms of
the version, function, principle, front panel and specifications.
8.4 L75S
This section describes the L75S, a 16 x E1 electrical interface switching board, in terms of the
version, function, principle, front panel and specifications.
8.5 D75S
This section describes the D75S, a 32 x E1/T1 electrical interface switching board, in terms of
the version, function, principle, front panel and specifications.
8.6 D34S
This section describes the D34S, a 6 x E3/T3 electrical interface switching board, in terms of
the version, function, principle, front panel and specifications.
8.7 C34S
This section describes the C34S, a 3 x E3/T3 electrical interface switching board, in terms of
the version, function, principle, front panel and specifications.
8.8 EU04
This section describes the EU04, a 4 x STM-1 electrical interface board, in terms of the version,
function, working principle, front panel and specifications.
8.9 EU08
This section describes the EU08, an 8 x STM-1 electrical interface board, in terms of the version,
function, working principle, front panel and specifications.
8.10 OU08
This section describes the OU08, an 8 x STM-1 optical interface board, in terms of the version,
function, working principle, front panel and parameters.
8.11 MU04
This section describes the MU04, a 4 x E4/STM-1 electrical interface board, in terms of the
version, function, principle, front panel and specifications.
8.12 TSB8
This section describes the TSB8, an 8-channel optical interface switching board, in terms of the
version, function, principle, front panel and specifications.
8.13 EFF8
This section describes the EFF8, an 8 x 100M Ethernet optical interface board, in terms of the
version, function, principle, front panel and specifications.
8.14 ETF8
This section describes the ETF8, an 8 x 100M Ethernet twisted pair interface board, in terms of
the version, function, principle, front panel and specifications.
8.15 ETS8
This section describes the ETS8, an 8 x 10/100M Ethernet twisted pair interface switching board,
in terms of the version, function, principle, front panel and specifications.
8.16 DM12
This section describes the DM12, a DDN interface board, in terms of the version, function,
principle, front panel and specifications.
8.1 L12S
This section describes the L12S, a 16 x E1/T1 electrical interface switching board, in terms of
the version, function, principle, front panel and specifications.
8.1.1 Version Description
The functional version of the L12S is R1.
8.1.2 Function and Feature
The L12S is used to receive and transmit 16 x E1/T1 electrical signals, and the L12S must be
used with the PD1.
8.1.3 Working Principle and Signal Flow
The L12S consists of the interface module, switch matrix module, and power supply module.
8.1.4 Front Panel
On the front panel of the L12S, there are interfaces and barcode.
8.1.5 Valid Slots
As the interface board for the PD1, the L12S can be housed in any of slots 6 and 7 in the OptiX
OSN 1500A subrack.
8.1.6 Technical Specifications
The technical specifications of the L12S cover the board dimensions, weight and power
consumption.
E1/T1 PD1
Interface Module
The interface module receives and transmits the E1/T1 electrical signals.
In the transmit direction, the working direction of the switch matrix module is the reverse of the
receive direction.
L12S
1-16
Interfaces
On the front panel of the L12S, there are two 2mmHM connectors, which are used to access 16
x E1/T1 electrical signals.
Table 8-1 lists the valid slots for the PD1 and corresponding slots for the L12S. The L12S housed
in the slot with a smaller number accesses the first 16 (1–16) channels of E1/T1 electrical signals.
The L12S housed in the slot with a larger number accesses the last 16 (17–32) channels of E1/
T1 electrical signals.
Table 8-1 Valid slots for the PD1 and corresponding slots for the L12S in the OptiX OSN 1500A
subrack
Valid Slot for the PD1 Corresponding Slot for the L12S
Mechanical Specifications
The mechanical specifications of the L12S are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the L12S is 4.5 W.
8.2 D12B
This section describes the D12B, a 32 x E1/T1 electrical interface board, in terms of the version,
function, principle, front panel and specifications.
The D12B can be housed in any of slots 14–17 in the OptiX OSN 1500B subrack. The D12B
can be used as the interface board for the PQ1 or PQM.
8.2.6 Technical Specifications
The technical specifications of the D12B cover the board dimensions, weight and power
consumption.
E1/T1 PQ1/PQM
Interface
module
E1/T1 PQ1/PQM
Interface Module
The interface module receives and transmits the E1/T1 electrical signals.
D12B
1~8
9~16
17~24
25~32
D12B
Interfaces
There are four DB44 interfaces on the front panel of the D12B. Table 8-2 lists the type and
usage of the interfaces.
Table 8-4 Valid slots for the PQ1/PQM and corresponding slots for the D12B in the OptiX OSN
1500B subrack
Valid Slot for the PQ1/PQM Corresponding Slot for the D12B
Mechanical Specifications
The mechanical specifications of the D12B are as follows:
l Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W)
l Weight (kg): 0.3
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the D12B is 0 W.
8.3 D12S
This section describes the D12S, a 32 x E1/T1 electrical interface switching board, in terms of
the version, function, principle, front panel and specifications.
Figure 8-5 shows the block diagram for the functions of the D12S.
Interface Module
The interface module receives and transmits the E1/T1 electrical signals.
D12S
1~8
9~16
17~24
25~32
D12S
Interfaces
There are four DB44 interfaces on the front panel of the D12S. Table 8-5 lists the type and usage
of the optical interfaces.
Table 8-7 Valid slots for the PQ1/PQM and corresponding slots for the D12S in the OptiX OSN
1500B subrack
Valid Slot for the PQ1/PQM Corresponding Slot for the D12S
Mechanical Specifications
The mechanical specifications of the D12S are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the D12S in the switching
state is 9 W and that of the D12S in the normal state is 0 W.
8.4 L75S
This section describes the L75S, a 16 x E1 electrical interface switching board, in terms of the
version, function, principle, front panel and specifications.
Figure 8-7 shows the block diagram for the functions of the L75S.
E1 PD1
Interface Module
The interface module receives and transmits the E1 electrical signals.
In the transmit direction, the working direction of the switch matrix module is the reverse of the
receive direction.
L75S
1-16
Interfaces
On the front panel of the L75S, there are two 2mmHM connectors, which are used to access 16
x E1 electrical signals.
Table 8-8 lists the valid slots for the PD1 and corresponding slots for the L75S. The L75S housed
in the slot with a smaller number accesses the first 16 (1–16) channels of E1 electrical signals.
The L75S housed in the slot with a larger number accesses the last 16 (17–32) channels of E1
electrical signals.
Table 8-8 Valid slots for the PD1 and corresponding slots for the L75S
Valid Slot for the PD1 Corresponding Slot for the L75S
Mechanical Specifications
The mechanical specifications of the L75S are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the L75S is 2.7 W.
8.5 D75S
This section describes the D75S, a 32 x E1/T1 electrical interface switching board, in terms of
the version, function, principle, front panel and specifications.
Interface Module
The interface module receives and transmits the E1/T1 electrical signals.
D75S
1~8
9~16
17~24
25 ~32
D75S
Interfaces
There are four DB44 interfaces on the front panel of the D75S. Table 8-9 lists the type and usage
of the DB44 interfaces.
Table 8-11 Valid slots for the PQ1/PQM and corresponding slots for the D75S in the OptiX
OSN 1500B subrack
Valid Slot for the PQ1/PQM Corresponding Slot for the D75S
Mechanical Specifications
The mechanical specifications of the D75S are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the D75S in the switching
state is 6 W and that of the D75S in the normal state is 0 W.
8.6 D34S
This section describes the D34S, a 6 x E3/T3 electrical interface switching board, in terms of
the version, function, principle, front panel and specifications.
Figure 8-11 shows the block diagram for the functions of the D34S.
Interface Module
The interface module receives and transmits the E3/T3 electrical signals.
In the transmit direction, the working direction of the switch matrix module is the reverse of the
receive direction.
D34S
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
OUT5
IN5
OUT6
IN6
D34S
Interfaces
There are six pairs of electrical interfaces on the front panel of the D34S.
Table 8-12 lists the type and usage of interfaces on the D34S.
Table 8-13 Valid slots for the PD3 and corresponding slots for the D34S in the OptiX OSN
1500B subrack
Valid Slot for the PD3 Corresponding Slot for the D34S
Slot 12 Slot 14
Slot 13 Slot 16
Mechanical Specifications
The mechanical specifications of the D34S are as follows:
l Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W)
l Weight (kg): 0.4
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the D34S in the switching
state is 2 W and that of the D34S in the normal state is 0 W.
8.7 C34S
This section describes the C34S, a 3 x E3/T3 electrical interface switching board, in terms of
the version, function, principle, front panel and specifications.
Interface Module
The interface module receives and transmits the E3/T3 electrical signals.
C34S
OUT1
IN1
OUT2
IN2
OUT3
IN3
C34S
Interfaces
There are three pairs of electrical interfaces on the front panel of the C34S.
Table 8-15 lists the type and usage of interfaces on the C34S.
IN1–IN3 SMB Receive the first three channels (1–3) of E3/T3 electrical
signals.
OUT1–OUT3 SMB Transmit the first three channels (1–3) of E3/T3 electrical
signals.
Table 8-16 Valid slots for the PL3 and corresponding slots for the C34S in the OptiX OSN
1500B subrack
Valid Slot for the PL3 Corresponding Slot for the C34S
Slot 12 Slot 14
Slot 13 Slot 16
Item Specification
Mechanical Specifications
The mechanical specifications of the C34S are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the C34S in the switching
state is 2 W and that of the C34S in the normal state is 0 W.
8.8 EU04
This section describes the EU04, a 4 x STM-1 electrical interface board, in terms of the version,
function, working principle, front panel and specifications.
Figure 8-15 shows the block diagram for the functions of the EU04 when it processes 1 x STM-1
signals.
Interface Module
The interface module receives and transmits the STM-1 electrical signals.
EU04
OUT1 IN1
OUT2 IN2
OUT3 IN3 OUT4
IN4
EU04
Interfaces
There are four pairs of electrical interfaces on the front panel of the EU04.
Table 8-18 lists the type and usage of interfaces on the EU04.
Table 8-19 Valid slots for the SEP and corresponding slots for the EU04
Valid Slot for the SEP Corresponding Slot for the EU04
Slot 12 Slot 14
Slot 13 Slot 16
Item Specification
Code CMI
Mechanical Specifications
The mechanical specifications of the EU04 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EU04 is 6 W.
8.9 EU08
This section describes the EU08, an 8 x STM-1 electrical interface board, in terms of the version,
function, working principle, front panel and specifications.
The EU08 is used to receive and transmit 8 x STM-1 electrical signals, and the EU08 must be
used with the SEP.
8.9.3 Working Principle and Signal Flow
The EU08 consists of the interface module, switch matrix module, and power supply module.
8.9.4 Front Panel
On the front panel of the EU08, there are interfaces and barcode.
8.9.5 Valid Slots
As the interface board for the SEP, the EU08 can be housed in any of slots 14 and 16 in the
OptiX OSN 1500B subrack.
8.9.6 Technical Specifications
The technical specifications of the EU08 cover the electrical interface specifications, board
dimensions, weight and power consumption.
+3.3 V
+3.3 V Power Fuse backeup
supply power
module
Interface Module
The interface module receives and transmits the STM-1 electrical signals.
from the cross-connect board. When the TPS protection is not performed, the switch matrix
module transmits the signals to the SEP board. When the TPS protection is performed, the switch
matrix module transmits the signals to the TSB8 board for bridging.
In the transmit direction, the working direction of the switch matrix module is the reverse of the
receive direction.
EU08
OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6 OUT7 IN7 OUT8 IN8
EU08
Interfaces
There are eight pairs of electrical interfaces on the front panel of the EU08.
Table 8-21 lists the type and usage of interfaces on the EU08.
Table 8-22 lists the valid slots for the SEP and corresponding slots for the EU08 in the OptiX
OSN 1500B.
NOTE
The OptiX OSN 1500A does not support the EU08 board.
Table 8-22 Valid slots for the SEP and corresponding slots for the EU08
Valid Slot for the SEP Corresponding Slot for the EU08
Slot 12 Slot 14
Slot 13 Slot 16
Code CMI
Mechanical Specifications
The mechanical specifications of the EU08 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EU08 is 11 W.
8.10 OU08
This section describes the OU08, an 8 x STM-1 optical interface board, in terms of the version,
function, working principle, front panel and parameters.
Table 8-24 lists the details on the two versions of the OU08 board.
Item Specification
Item Specification
Difference The optical interface of the N1OU08 uses the LC connector. The optical
interface of the N2OU08 uses the SC connector. The N1OU08 uses the
pluggable optical module. The N2OU08 does not use the pluggable
optical module.
Replaceability None.
Figure 8-19 shows the block diagram for the functions of the OU08.
STM-1(o) SEP
Interface
module
STM-1(o)
SEP
Interface Module
In the receive direction, the interface module performs O/E convertion for the STM-1 signals,
and transmits the signals to the SEP board.
In the transmit direction, the interface module performs the E/O convertion for the STM-1
signals, and transmits the signals to the optical interface.
OU08
OUT1IN1OUT2 IN2 OUT3IN3 OUT4 IN4OUT5IN5 OUT6IN6 OUT7IN7OUT8 IN8
OU08
OU08
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
OUT5
IN5
OUT6
IN6
OUT7
OUT8
IN7
IN8
OU08
Interfaces
There are eight pairs of optical interfaces on each front panel of the N1OU08 and N2OU08.
Table 8-25 lists the interface type and usage for the N1OU08. Table 8-26 lists the interface type
and usage for the N2OU08.
Table 8-27 lists the valid slots for the SEP and corresponding slots for the OU08.
Table 8-27 Valid slots for the SEP and corresponding slots for the OU08
Valid Slot for the SEP Corresponding Slot for the OU08
Slot 12 Slot 14
Slot 13 Slot 16
Item Specification
Mechanical Specifications
The mechanical specifications of the OU08 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the OU08 is 6 W.
8.11 MU04
This section describes the MU04, a 4 x E4/STM-1 electrical interface board, in terms of the
version, function, principle, front panel and specifications.
Figure 8-22 shows the block diagram for the functions of the MU04.
+3.3 V
+3.3 V Power Fuse backeup
supply power
module
Interface Module
The interface module receives and transmits the E4/STM-1 electrical signals.
MU04
OUT1
IN1
OUT2
IN2
OUT3 IN3
OUT4
IN4
MU04
Interfaces
There are four pairs of electrical interfaces on the front panel of the MU04.
Table 8-29 lists the type and usage of interfaces on the MU04.
Table 8-30 Valid slots for the SPQ4 and corresponding slots for the MU04
Valid Slot for the SPQ4 Corresponding Slot for the MU04
Slot 12 Slot 14
Slot 13 Slot 16
Code CMI
Mechanical Specifications
The mechanical specifications of the MU04 are as follows:
l Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W)
l Weight (kg): 0.4
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the MU04 is 2 W.
8.12 TSB8
This section describes the TSB8, an 8-channel optical interface switching board, in terms of the
version, function, principle, front panel and specifications.
Figure 8-24 shows the block diagram for the functions of the TSB8 when it processes one-
channel signals.
+3.3
Power Fuse
V +3.3 V
module Power
In the transmit direction, the working direction of the switch matrix module is the reverse of the
receive direction.
TSB8
TSB8
Table 8-32 Valid slots for the TSB8 and corresponding slots for the SPQ4 and MU04
Valid Slot for the TSB8 Valid Slot for the SPQ4 Corresponding Slot for
the MU04
Table 8-33 lists the valid slots for the TSB8 and corresponding slots for the PD3 and D34S.
Table 8-33 Valid slots for the TSB8 and corresponding slots for the PD3 and D34S
Valid Slot for the TSB8 Valid Slot for the PD3 Corresponding Slot for
the D34S
Table 8-34 lists the valid slots for the TSB8 and corresponding slots for the SEP and EU04.
Table 8-34 Valid slots for the TSB8 and corresponding slots for the SEP and EU04
Valid Slot for the TSB8 Valid Slot for the SEP Corresponding Slot for
the EU04
Table 8-35 lists the valid slots for the TSB8 and corresponding slots for the SEP and EU08.
Table 8-35 Valid slots for the TSB8 and corresponding slots for the SEP and EU08
Valid Slot for the TSB8 Valid Slot for the SEP Corresponding Slot for
the EU08
NOTE
On the T2000, the SEP is displayed as the SEP or SEP1. When interfaces are available on the front panel
of the SEP, the SEP is displayed as the SEP1 on the T2000. When the SEP is used with the interface board
to realize the TPS protection, the SEP is displayed as the SEP on the T2000.
Table 8-36 lists the valid slots for the TSB8 and corresponding slots for the EFS0 and ETS8.
Table 8-36 Valid slots for the TSB8 and corresponding slots for the EFS0 and ETS8
Valid Slot for the TSB8 Valid Slot for the EFS0 Corresponding Slot for
the ETS8
Table 8-37 lists the valid slots for the TSB8 and corresponding slots for the PL3 and C34S.
Table 8-37 Valid slots for the TSB8 and corresponding slots for the PL3 and C34S
Valid Slot for the TSB8 Valid Slot for the PL3 Corresponding Slot for
the C34S
Mechanical Specifications
The mechanical specifications of the TSB8 are as follows:
l Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W)
l Weight (kg): 0.3
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the TSB8 in the
switching state is 5 W and that of the TSB8 in the normal state is 0 W.
8.13 EFF8
This section describes the EFF8, an 8 x 100M Ethernet optical interface board, in terms of the
version, function, principle, front panel and specifications.
When used with different Ethernet processing boards, the EFF8 can be housed in different slots.
8.13.6 Technical Specifications
The technical specifications of the EFF8 cover the optical interface specifications, board
dimensions, weight and power consumption.
Figure 8-26 shows the block diagram for the functions of the EFF8 when it processes 1 x 100M
Ethernet signals.
100M EFT8/EFS0/EMS4/EMR0
Interface Module
In the receive direction, the interface module performs the O/E convertion for the Ethernet
signals, and transmits the signals to the EFT8, EFS0, EMS4, or EMR0 board.
In the transmit direction, the interface module performs the E/O convertion for the Ethernet
signals, and transmits the signals to the optical interface.
EFF8
1
2
3
4
5
6
7
8
LINKACT
OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6 OUT7 IN7 OUT8 IN8
CLASS 1
LASER
PRODUCT
EFF8
Indicators
For indication of indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are eight pairs of optical interfaces on the front panel of the EFF8.
Table 8-38 lists the type and usage of interfaces on the EFF8.
l As the interface board for the EFT8, the EFF8 can be housed in any of slots 14–17 in the
OptiX OSN 1500B subrack.
l As the interface board for the EFS0, the EFF8 can be housed in any of slots 14–17 in the
OptiX OSN 1500B subrack.
l As the interface board for the EMS4, the EFF8 can be housed in any of slots 14–17 in the
OptiX OSN 1500B subrack.
l As the interface board for the EMR0, the EFF8 can be housed in any of slots 14–17 in the
OptiX OSN 1500B subrack.
Table 8-39 lists the valid slots for the EFT8 and corresponding slots for the EFF8.
Table 8-39 Valid slots for the EFT8 and corresponding slots for the EFF8
Valid Slot for the EFT8 Corresponding Slot for the EFF8
Table 8-40 lists the valid slots for the EFS0 and corresponding slots for the EFF8.
Table 8-40 Valid slots for the EFS0 and corresponding slots for the EFF8
Valid Slot for the EFS0 Corresponding Slot for the EFF8
Table 8-41 lists the valid slots for the EMS4 and corresponding slots for the EFF8.
Table 8-41 Valid slots for the EMS4 and corresponding slots for the EFF8
Valid Slot for the EMS4 Corresponding Slot for the EFF8
Valid Slot for the EMS4 Corresponding Slot for the EFF8
Table 8-42 lists the valid slots for the EMR0 and corresponding slots for the EFF8.
Table 8-42 Valid slots for the EMR0 and corresponding slots for the EFF8
Valid Slot for the EMR0 Corresponding Slot for the EFF8
Item Specification
Mechanical Specifications
The mechanical specifications of the EFF8 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EFF8 is 6 W.
8.14 ETF8
This section describes the ETF8, an 8 x 100M Ethernet twisted pair interface board, in terms of
the version, function, principle, front panel and specifications.
Figure 8-28 shows the block diagram for the functions of the ETF8 when it processes 1 x 100M
Ethernet signals.
100M EFT8/EFS0/EMS4/EMR0
+3.3 V Fuse
Power
+3.3 V Power
module
Interface Module
In the receive direction, the interface module performs the O/E convertion for the Ethernet
signals, and transmits the signals to the EFT8, EFS0, EMS4, or EMR0 board.
In the transmit direction, the interface module performs the E/O convertion for the Ethernet
signals, and transmits the signals to the optical interface.
ETF8
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8
ETF8
Interfaces
There are eight electrical interfaces on the front panel of the ETF8.
Table 8-44 lists the type and usage of interfaces on the ETF8.
Table 8-45 lists the pins of the RJ-45 connector of the ETF8.
1 Transmitting
positive
2 Transmitting
negative
3 Receiving positive
8 7 6 5 4 3 2 1
4 Grounding
5 Grounding
6 Receiving
negative
7 Grounding
8 Grounding
Table 8-46 Valid slots for the EFT8 and corresponding slots for the ETF8
Valid Slot for the EFT8 Corresponding Slot for the ETF8
Table 8-47 lists the valid slots for the EFS0 and corresponding slots for the ETF8.
Table 8-47 Valid slots for the EFS0 and corresponding slots for the ETF8
Valid Slot for the EFS0 Corresponding Slot for the ETF8
Table 8-48 lists the valid slots for the EMS4 and corresponding slots for the ETF8.
Table 8-48 Valid slots for the EMS4 and corresponding slots for the ETF8
Valid Slot for the EMS4 Corresponding Slot for the ETF8
Table 8-49 lists the valid slots for the EMR0 and corresponding slots for the ETF8.
Table 8-49 Valid slots for the EMR0 and corresponding slots for the ETF8
Valid Slot for the EMR0 Corresponding Slot for the ETF8
Mechanical Specifications
The mechanical specifications of the ETF8 are as follows:
l Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W)
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the ETF8 is 2 W.
8.15 ETS8
This section describes the ETS8, an 8 x 10/100M Ethernet twisted pair interface switching board,
in terms of the version, function, principle, front panel and specifications.
+3.3 V
+3.3 V Power Fuse backeup
supply power
module
Interface Module
The interface module receives and transmits the Ethernet optical signals.
ETS8
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8
ETS8
Interfaces
There are eight electrical interfaces on the front panel of the ETS8.
Table 8-51 lists the type and usage of interfaces on the ETS8.
Table 8-52 lists the pins of the RJ-45 connector of the ETS8.
1 Transmitting positive
2 Transmitting negative
3 Receiving positive
4 Grounding
5 Grounding
8 7 6 5 4 3 2 1 6 Receiving negative
7 Grounding
8 Grounding
Table 8-53 lists the valid slots for the EFS0 and corresponding slots for the ETS8.
Table 8-53 Valid slots for the EFS0 and corresponding slots for the ETS8
Valid Slot for the EFS0 Corresponding Slot for the ETS8
Slot 12 Slot 14
Slot 13 Slot 16
Item Specification
Mechanical Specifications
The mechanical specifications of the ETS8 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the ETS8 in the switching
state is 3 W and that of the ETS8 in the normal state is 0 W.
8.16 DM12
This section describes the DM12, a DDN interface board, in terms of the version, function,
principle, front panel and specifications.
Figure 8-32 shows the block diagram for the functions of the DM12 when it processes one
channel of N x 64 kbit/s or framed E1 electrical signals.
Interface Module
The interface module receives and transmits one channel of N x 64 kbit/s or framed E1 electrical
signals.
DM12
E1(1-8)
DDN1
DDN2
DDN3
DDN4
DM12
Interfaces
On the front panel of the DM12, there are DB44 and DB28 interfaces. Table 8-55 lists the
specifications of the interfaces.
37 R2 to receive the
second channel
22 of signals.
17 Receives the - -
clock signals.
18
Table 8-58 Valid slots for the DX1 and corresponding slots for the DM12
Valid Slot for the DX1 Corresponding Slot for the DM12
Mechanical Specifications
The mechanical specifications of the DM12 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the DM12 in the
switching state is 8 W and that of the DM12 in the normal state is 0 W.
The chapter describes the integrated boards of the cross-connect, SCC and line units at different
rates.
9.1 CXL1
This section describes the CXL1, an integrated board of the SCC, cross-connect and line units,
in terms of the version, principle, function, principle, front panel and specifications.
9.2 CXL4
This section describes the CXL4, an integrated board of the SCC, cross-connect and line units,
in terms of the version, principle, function, principle, front panel and specifications.
9.3 CXL16
This section describes the CXL16, an integrated board of the SCC, cross-connect and line units,
in terms of the version, principle, function, principle, front panel and specifications.
9.1 CXL1
This section describes the CXL1, an integrated board of the SCC, cross-connect and line units,
in terms of the version, principle, function, principle, front panel and specifications.
Table 9-1 Function and feature of the SDH processing unit of the CXL1
Function and CXL1
Feature
Specification of the Supports the optical interfaces of the I-1, S-1.1, L-1.1, L-1.2, and
optical interface Ve-1.2 types.
Specification of the l Supports detection and query of the information on the optical
optical module module.
l Supports the function of setting the on/off state of the laser and the
ALS function.
Service processing Supports the processing of the VC-12, VC-3 and VC-4 services.
Overhead processing l Supports the processing of the SOH bytes of the STM-1 signals.
l Supports the transparent transmission and termination of the POH
bytes. Supports the setting and query of the J0/J1/C2 bytes.
Alarm and Provides rich alarms and performance events for easy management
performance event and maintenance of the equipment.
Protection scheme Supports the two-fiber MSP protection ring, four-fiber MSP
protection ring, linear MSP protection, and SNCP.
SCC Unit
Table 9-2 lists the function and feature of the SCC unit of the CXL1.
Table 9-2 Function and feature of the SCC unit of the CXL1
Function and CXL1
Feature
Basic function Configures and monitors services, monitors the service performance,
and collects performance events and alarm information.
PIU management Provides the in-service check function for the PIU board, and the
failure check function for the lightning protection module of the PIU.
Protection scheme Supports 1+1 hot backup for the SCC unit.
Cross-Connect Unit
Table 9-3 lists the function and feature of the cross-connect unit of the CXL1.
Table 9-3 Function and feature of the cross-connect unit of the CXL1
Function and CXL1
Feature
Fast emergency Provides two 4M HDLC fast emergency channels, which are used for
channel the MSP and SNCP protection switching.
Protection scheme Supports the 1+1 hot backup (non-revertive) for the cross-connect
unit.
Clock Unit
Table 9-4 lists the function and feature of the clock unit of the CXL1.
Table 9-4 Function and feature of the clock unit of the CXL1
Function and CXL1
Feature
Other function Supports the extraction, insertion and management of the SSM and
clock ID.
Input and output l Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and
selects the external timing source.
l Outputs two-channel 2048 Hz or 2048 kbit/s timing signals.
Time & T1
synchronizaton Line units
(SETS)
38MHz T2
Tributary units
OSC
SETG T3
PIU
T0
Frame header
Service units
155 MHz
16x155
SDH overhead processing module high speed bus Another CXL
STM-1 unit
Mbit/s data
DEMUX
O/E Cross-connect
RST MST MSA HPT unit A
XC
high speed bus
STM-1
16x155
Mbit/s data
Cross Connect
O/E (HPC)
MUX
K1/K2 high speed bus
insertion/ Another
extration connect unit
SCC unit
XC
Performance report
Laser shut down
OAM interface
AUX
F&f interface
Phone interface
Power monitor
EOW
S1-S4 interface
Boot ROM FLASH RAM NVRAM
+1.6V
DC/DC
+1.8V converter
+1.2V
The synchronous timing unit can extract timing from three types of timing signal:
MUX/DEMUX Module
l In receive direction, the DEMUX part demultiplexes the high rate electrical signals into
multiple parallel electrical signals, and recovery the clock signal at the same time.
l In transmit direction, the MUX part multiplexes the parallel electrical signals received from
the SDH overhead processing module into high rate electrical signals.
RST
l In receiving direction, performs frame alignment detection (A1, A2), regenerator section
trace recovery (J0) and mismatch detection, BIP-8 errored block count.
l In transmitting direction, it performs frame alignment insertion, regenerator section path
trace insertion, BIP-8 calculation and insertion.
MST
l In receiving direction, performs BIP-24 errored block count, MS_REI recovery, MS_RDI
and MS_AIS detection.
l In transmitting direction, it performs BIP-24 calculation and insertion, MS_REI, MS_RDI
and MS_AIS insertion.
l Provides extraction or insertion of K1 byte and K2 byte.
MSA
l In receiving direction, performs AU4's pointer interpretation, LOP and AIS detection,
pointer justification.
l In transmitting direction, it performs AUG assembly, AU-4 pointer regeneration, AU_AIS
generation.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
Cross-connect Module
The cross-connect module consists of two parts:
l SNCP module, which tests relative alarms and reports the alarm to software to trigger SNCP
switching
l Higher and lower order cross-connect module, which performs the functions of higher and
lower order cross-connect units. This module consists of higher order cross-connect unit
and lower order cross-connect unit.
Figure 9-2 illustrates the block diagram of higher and lower order cross-connect modules.
Figure 9-2 Block diagram of higher and lower order cross-connect modules
Higher order
connection
XC_TOP VC_DATA_
TX_TOP RX_TOP
FIFO
Lower order
connection
The upper half part is the higher order cross-connect unit, which fully cross-connects 20 G higher
order services with VC-4 as the minimum service grooming granularity.
The lower half part is the lower order cross-connect unit, which cross-connects 20 G lower order
services.
Other Functions
l Responses to and processes k bytes
l Collects performance data of the optical module and shuts output of the optical module
l Collects and processes DCC of each board
l Inserts the DCC back into each line board after processing
l Monitors the power supply of the board
l Resets the unit
l Cuts alarms
CXL1
STAT
ACTX
ACTC
PROG
SRVX
SRVL
SYNC
ALMC
CLASS 1
LASER
PRODUCT
OUT IN
RESET
ALM CUT
CXL1
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Activating state indicator for the services at the cross-connect unit (ACTX), which is green
when lit.
l Active/standby state indicator for the SCC units (ACTC), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Alarm indicator (SRVX) for services at the cross-connect unit, which is red, green or yellow
when lit.
l Alarm indicator (SRVL) for services at the line units , which is red, green or yellow when
lit.
l Synchronization clock state indicator (SYNC), which is red or green when lit.
l Alarm cutting indicator (ALMC), which is yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the CXL1, there are one optical interface and two switches. Table 9-5 lists
the type and usage of the optical interface and switches on the CXL1.
RESET Warm reset Press the switch to reset the SCC unit.
switch
ALM CUT Alarm cut Press the switch to mute the alarm. Press the switch for three
switch seconds to mute the alarm permanently. Press the switch
again for three seconds to resume the alarm sound.
Table 9-6 lists the relation between the board feature code and optical interface type for the
CXL1.
Table 9-6 Relation between the board feature code and the optical interface type
Displayed Slot
The CXL1 is housed in one slot in the subrack.
The logical boards for the CXL1 are the Q1SL1, EXCL and GSCC.
Table 9-7 Logical slots displayed on the T2000 for the CXL1
Board Parameters
l J1 byte
l C2 byte
l Clock parameters
Item Specification
Item Specification
Cross-Connect Capacity
The cross-connect capacity of the CXL1 is as follows:
l Higher order cross-connect capacity: 20 Gbit/s
l Lower order cross-connect capacity: 20 Gbit/s
l Access capacity: 18.75 Gbit/s
Mechanical Specifications
The mechanical specifications of the CXL1 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.1
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the CXL1 is 40 W.
9.2 CXL4
This section describes the CXL4, an integrated board of the SCC, cross-connect and line units,
in terms of the version, principle, function, principle, front panel and specifications.
Table 9-9 Function and feature of the SDH processing unit of the CXL4
Specifications of Supports the optical interfaces of the I-4, S-4.1, L-4.1, L-4.2, and
optical interfaces Ve-4.2 types.
Specifications of the l Supports detection and query of the information on the optical
optical module module.
l Supports the function of setting the on/off state of the laser and the
ALS function.
Service processing Supports VC-12, VC-3, and VC-4 services and VC-4-4c
concatenation services.
Overhead processing l Supports the processing of the SOH bytes of the STM-4 signals.
l Supports the transparent transmission and termination of the POH
bytes. Supports the setting and query of the J0/J1/C2 bytes.
Alarms and Provides rich alarms and performance events for easy management
performance events and maintenance of the equipment.
Protection schemes Supports the two-fiber MSP protection ring, four-fiber MSP
protection ring, linear MSP protection, and SNCP.
SCC Unit
Table 9-10 lists the function and feature of the SCC unit of the CXL4
Table 9-10 Function and feature of the SCC unit of the CXL4
Basic function Configures and monitors services, monitors the service performance,
and collencts performance events and alarm information.
PIU management Provides the in-service check function for the PIU board, and the
failure check function for the lightning protection module of the PIU.
Protection scheme Supports 1+1 hot backup for the SCC unit.
Cross-Connect Unit
Table 9-11 lists the function and feature of the cross-connect unit of the CXL4.
Table 9-11 Function and feature of the cross-connect unit of the CXL4
Fast emergency Provides two 4M HDLC fast emergency channels, which are used for
channel the MSP and SNCP protection switching.
Protection scheme Supports the 1+1 hot backup (non-revertive) for the cross-connect
unit.
Clock Unit
Table 9-12 lists the function and feature of the clock unit of the CXL4.
Table 9-12 Function and feature of the clock unit of the CXL4
Other function Supports the extraction, insertion and management of the SSM and
clock ID.
Input and output l Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and
selects the external timing source.
l Outputs two-channel 2048 Hz or 2048 kbit/s timing signals.
T0
Frame header
Service units
155 MHz
16x155
SDH overhead processing module high speed bus Another CXL
STM-4 unit
Mbit/s data
DEMUX
O/E Cross-connect
RST MST MSA HPT unit A
XC
high speed bus
STM-4
16x155
Mbit/s data
Cross Connect
O/E (HPC)
MUX
K1/K2 high speed bus
insertion/ Another
extration connect unit
SCC unit
XC
Performance report
Laser shut down
OAM interface
AUX
F&f interface
Phone interface
Power monitor
EOW
S1-S4 interface
Boot ROM FLASH RAM NVRAM
+1.6V
DC/DC
+1.8V converter
+1.2V
source (T4) are generated. The boards apply 1 + 1 hot backup. Therefore, both the active and
the standby boards tracing the same reference source to ensure the identity between the system
clocks of the active and the standby boards.
The synchronous timing unit can extract timing from three types of timing signal:
l Timing signal (T1) from STM-N
l Timing signal (T2) from PDH
l Reference signal (T3) from external synchronous clock source (2MHz or 2Mbit/s)
MUX/DEMUX Module
l In receive direction, the DEMUX part demultiplexes the high rate electrical signals into
multiple parallel electrical signals, and recovery the clock signal at the same time.
l In transmit direction, the MUX part multiplexes the parallel electrical signals received from
the SDH overhead processing module into high rate electrical signals.
RST
l In receiving direction, performs frame alignment detection (A1, A2), regenerator section
trace recovery (J0) and mismatch detection, BIP-8 errored block count.
l In transmitting direction, it performs frame alignment insertion, regenerator section path
trace insertion, BIP-8 calculation and insertion.
MST
l In receiving direction, performs BIP-24 errored block count, MS_REI recovery, MS_RDI
and MS_AIS detection.
l In transmitting direction, it performs BIP-24 calculation and insertion, MS_REI, MS_RDI
and MS_AIS insertion.
l Provides extraction or insertion of K1 byte and K2 byte.
MSA
l In receiving direction, performs AU4's pointer interpretation, LOP and AIS detection,
pointer justification.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
Cross-connect Module
The cross-connect module consists of two parts:
l SNCP module, which tests relative alarms and reports the alarm to software to trigger SNCP
switching
l Higher and lower order cross-connect module, which performs the functions of higher and
lower order cross-connect units. This module consists of higher order cross-connect unit
and lower order cross-connect unit.
Figure 9-5 illustrates the block diagram of higher and lower order cross-connect modules.
Figure 9-5 Block diagram of higher and lower order cross-connect modules
Higher order
connection
XC_TOP VC_DATA_
TX_TOP RX_TOP
FIFO
Lower order
connection
The upper half part is the higher order cross-connect unit, which fully cross-connects 20 G higher
order services with VC-4 as the minimum service grooming granularity.
The lower half part is the lower order cross-connect unit, which cross-connects 20 G lower order
services.
Other Functions
l Responses to and processes k bytes
l Collects performance data of the optical module and shuts output of the optical module
l Collects and processes DCC of each board
l Inserts the DCC back into each line board after processing
l Monitors the power supply of the board
l Resets the unit
l Cuts alarms
CXL4
STAT
ACTX
ACTC
PROG
SRVX
SRVL
SYNC
ALMC
CLASS 1
LASER
PRODUCT
OUT IN
RESET
ALM CUT
CXL4
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Activating state indicator for the services at the cross-connect unit (ACTX), which is green
when lit.
l Active/standby state indicator for the SCC units (ACTC), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Alarm indicator (SRVX) for services at the cross-connect unit, which is red, green or yellow
when lit.
l Alarm indicator (SRVL) for services at the line units , which is red, green or yellow when
lit.
l Synchronization clock state indicator (SYNC), which is red or green when lit.
l Alarm cutting indicator (ALMC), which is yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the CXL4, there are one optical interface and two switches. Table 9-13
lists the type and usage of the optical interface and switches on the CXL4.
RESET Warm reset Press the switch to reset the SCC unit.
switch
ALM CUT Alarm cut Press the switch to mute the alarm. Press the switch for three
switch seconds to mute the alarm permanently. Press the switch
again for three seconds to resume the alarm sound.
Table 9-14 lists the relation between the board feature code and optical interface type for the
CXL4.
Table 9-14 Relation between the board feature code and the optical interface type
Displayed Slot
The CXL4 is housed in one slot in the subrack.
The logical boards for the CXL4 are the Q1SL4, EXCL and GSCC.
Table 9-15 Logical slots displayed on the T2000 for the CXL4
Board Parameters
l J1 byte
l C2 byte
l Clock parameters
Item Specification
Item Specification
Cross-Connect Capacity
The cross-connect capacity of the CXL4 is described as follows:
l Higher order cross-connect capacity: 20 Gbit/s
l Lower order cross-connect capacity: 20 Gbit/s
l Access capacity: 18.75 Gbit/s
Mechanical Specifications
The mechanical specifications of the CXL4 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.1
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the CXL4 is 40 W.
9.3 CXL16
This section describes the CXL16, an integrated board of the SCC, cross-connect and line units,
in terms of the version, principle, function, principle, front panel and specifications.
Table 9-17 Function and feature of the SDH processing unit of the CXL16
Specification of the Supports the optical interfaces of the I-16, S-16.1, L-16.1, and L-16.2
optical interface types.
Specification of the l Supports detection and query of the information on the optical
optical module module.
l Supports the function of setting the on/off state of the laser and the
ALS function.
Service processing Supports VC-12, VC-3, and VC-4 services and VC-4-4c, VC-4-8c,
and VC-4-16c concatenation services.
Overhead processing l Supports the processing of the SOH bytes of the STM-16 signals.
l Supports the transparent transmission and termination of the POH
bytes. Supports the setting and query of the J0/J1/C2 bytes.
Alarm and Provides rich alarms and performance events for easy management
performance event and maintenance of the equipment.
Protection scheme Supports the two-fiber MSP protection ring, four-fiber MSP
protection ring, linear MSP protection, and SNCP.
SCC Unit
Table 9-18 lists the function and feature of the SCC unit of the CXL16
Table 9-18 Function and feature of the SCC unit of the CXL16
Basic function Configures and monitors services, monitors the service performance,
and collects performance events and alarm information.
PIU management Provides the in-service check function for the PIU board, and the
failure check function for the lightning protection module of the PIU.
Protection scheme Supports 1+1 hot backup for the SCC unit.
Cross-Connect Unit
Table 9-19 lists the function and feature of the cross-connect unit of the CXL16.
Table 9-19 Function and feature of the cross-connect unit of the CXL16
Function and CXL16
Feature
Fast emergency Provides two 4M HDLC fast emergency channels, which are used for
channel the MSP and SNCP protection switching.
Protection scheme Supports the 1+1 hot backup (non-revertive) for the cross-connect
unit.
Clock Unit
Table 9-20 lists the function and feature of the clock unit of the CXL16.
Table 9-20 Function and feature of the clock unit of the CXL16
Function and CXL16
Feature
Other function Supports the extraction, insertion and management of the SSM and
clock ID.
Input and output l Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and
selects the external timing source.
l Outputs two-channel 2048 Hz or 2048 kbit/s timing signals.
T0
Frame header
Service units
155 MHz
16x155
SDH overhead processing module high speed bus Another CXL
unit
STM-16 Mbit/s data
DEMUX
O/E Cross-connect
RST MST MSA HPT unit A
XC
high speed bus
STM-16
16x155
Mbit/s data
Cross Connect
O/E (HPC)
MUX
K1/K2 high speed bus
insertion/ Another
extration connect unit
SCC unit
XC
Performance report
Laser shut down
OAM interface
AUX
F&f interface
Phone interface
Power monitor
EOW
S1-S4 interface
Boot ROM FLASH RAM NVRAM
+1.6V
DC/DC
+1.8V converter
+1.2V
The synchronous timing unit can extract timing from three types of timing signal:
MUX/DEMUX Module
l In receive direction, the DEMUX part demultiplexes the high rate electrical signals into
multiple parallel electrical signals, and recovery the clock signal at the same time.
l In transmit direction, the MUX part multiplexes the parallel electrical signals received from
the SDH overhead processing module into high rate electrical signals.
RST
l In receiving direction, performs frame alignment detection (A1, A2), regenerator section
trace recovery (J0) and mismatch detection, BIP-8 errored block count.
l In transmitting direction, it performs frame alignment insertion, regenerator section path
trace insertion, BIP-8 calculation and insertion.
MST
l In receiving direction, performs BIP-24 errored block count, MS_REI recovery, MS_RDI
and MS_AIS detection.
MSA
l In receiving direction, performs AU4's pointer interpretation, LOP and AIS detection,
pointer justification.
l In transmitting direction, it performs AUG assembly, AU-4 pointer regeneration, AU_AIS
generation.
HPT
l OH termination
l J1 path trace message recovery
l REI information recovering
l HP_RDI detection (path status monitoring
l UNEQ and AIS detection (signal label monitoring)
l VC-4 BIP-8 errored block count
Cross-connect Module
The cross-connect module consists of two parts:
l SNCP module, which tests relative alarms and reports the alarm to software to trigger SNCP
switching
l Higher and lower order cross-connect module, which performs the functions of higher and
lower order cross-connect units. This module consists of higher order cross-connect unit
and lower order cross-connect unit.
Figure 9-8 illustrates the block diagram of higher and lower order cross-connect modules.
Figure 9-8 Block diagram of higher and lower order cross-connect modules
Higher order
connection
XC_TOP VC_DATA_
TX_TOP RX_TOP
FIFO
Lower order
connection
The upper half part is the higher order cross-connect unit, which fully cross-connects 20 G higher
order services with VC-4 as the minimum service grooming granularity.
The lower half part is the lower order cross-connect unit, which cross-connects 20 G lower order
services.
Other Functions
l Responses to and processes k bytes
l Collects performance data of the optical module and shuts output of the optical module
l Collects and processes DCC of each board
l Inserts the DCC back into each line board after processing
l Monitors the power supply of the board
l Resets the unit
l Cuts alarms
DC Converter Module
This module provides the board with required DC voltages. It converts the –48/–60 V power
supply to the following voltages: +5V, +1.6V, +1.8V +1.2V and+3.3V.
CXL16
STAT
ACTX
ACTC
PROG
SRVX
SRVL
SYNC
ALMC
CLASS 1
LASER
PRODUCT
OUT IN
RESET
ALM CUT
CXL16
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Activating state indicator for the services at the cross-connect unit (ACTX), which is green
when lit.
l Active/standby state indicator for the SCC units (ACTC), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Alarm indicator (SRVX) for services at the cross-connect unit, which is red, green or yellow
when lit.
l Alarm indicator (SRVL) for services at the line units , which is red, green or yellow when
lit.
l Synchronization clock state indicator (SYNC), which is red or green when lit.
l Alarm cutting indicator (ALMC), which is yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the CXL16, there are one optical interface and two switches. Table 9-21
lists the type and usage of the optical interface and switches on the CXL16.
RESET Warm reset Press the switch to reset the SCC unit.
switch
ALM CUT Alarm cut Press the switch to mute the alarm. Press the switch for three
switch seconds to mute the alarm permanently. Press the switch
again for three seconds to resume the alarm sound.
Table 9-22 Relation between the board feature code and the optical interface type
Board Barcode Feature Code Optical Interface Type
SSQ2CXL1601 01 I-16
SSQ2CXL1602 02 S-16.1
SSQ2CXL1603 03 L-16.1
SSQ2CXL1604 04 L-16.2
Displayed Slot
The CXL16 is housed in one slot in the subrack.
The logical boards for the CXL16 are the Q1SL16, EXCL and GSCC.
Table 9-23 Logical slots displayed on the T2000 for the CXL16
Board Parameters
l J1 byte
l C2 byte
l Clock parameters
Item Specification
Item Specification
Min. overload –3 0 –9 –9
(dBm)
Cross-Connect Capacity
The cross-connect capacity of the CXL16 described as follows:
l Higher order cross-connect capacity: 20 Gbit/s
l Lower order cross-connect capacity: 20 Gbit/s
l Access capacity: 18.75 Gbit/s
Mechanical Specifications
The mechanical specifications of the CXL16 are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.1
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the CXL16 is 40 W.
10 Auxiliary Boards
This chapter describes the auxiliary boards, such as the EOW, AUX, AMU, and FANA.
10.1 EOW
This section describes the EOW, an orderwire processing board, in terms of the version, function,
principle, front panel and specifications.
10.2 AUX
This section describes the AUX, a system auxiliary interface board, in terms of the version,
function, working principle, front panel and specifications.
10.3 AMU
This section describes the AMU, an orderwire processing and alarm concatenation board, in
terms of the version, function, principle, front panel and specifications.
10.4 FAN
This section describes the FAN, a fan control board, in terms of the version, function, principle,
front panel, configuration and specifications.
10.1 EOW
This section describes the EOW, an orderwire processing board, in terms of the version, function,
principle, front panel and specifications.
Figure 10-1 shows the block diagram for the functions of the EOW.
S1~S4
interface S1~S4
Switch
Phone interface OHP module CXL unit A/B
E1/E2
module
SLIC
+3.3 V +3.3 V
DC/DC Fuse -48 V/ -60 V
+5 V converter -48 V/ -60 V
DC/DC
+1.8 V converter Fuse
+3.3 V backup
power from AUX
Clock Module
The clock module first divides frequencies of the system clock and header sent from the cross-
connect board. The system clock and header are then transmitted to other modules as OHP
Process module and the switch module.
Switch Module
The switch module performs non-blocking switching of 4096 x 4096 or 1024 x 1024 timeslots
under control of micro processor. The switch module can switch any timeslot of overhead signal
sent from the SCC to any timeslot of output overhead signals.
OHP Module
l Processes E1 and E2 bytes sent by the CXL board.
l Realizes interconnection between orderwire audio interface.
l Interconnects with orderwire phone port through SLIC unit.
l Processes serial1–serial4 sent from the CXL board.
l Provides S1–S4 as RS232/RS422 serial transparent data interfaces, the level of which can
be set by software.
DC/DC Converter
Through the DC/DC converter module, the power converting module generates required DC
voltages for each chip. The following DC voltages are provided: +1.8 V, +3.3 V, +5 V. In
addition, protection is provided to board +3.3 V power supply.
EOW
STAT
PROG
PHONE
S1
S2
S3
S4
EOW
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Connection status indicator (LINK), which is green when lit.
l Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are five interfaces on the front panel of the EOW. Table 10-2 lists the type and usage of
these interfaces.
4 Signal 1
5 Signal 2
8 7 6 5 4 3 2 1
Table 10-4 lists the pins of the S1, S2, S3 and S4 interfaces.
Table 10-4 Pins of the S1, S2, S3 and S4 interfaces of the EOW
Front View Pin Usage
7 Not defined
Mechanical Specifications
The mechanical specifications of the EOW are as follows:
l Board dmensions (mm): 111.8 (H) x 220 X (D) x 25.4 (W)
l Weight (kg): 0.4
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the EOW is 10 W.
10.2 AUX
This section describes the AUX, a system auxiliary interface board, in terms of the version,
function, working principle, front panel and specifications.
Management Provides the OAM/F&f interface, which supports the X.25 protocol.
interface Provides the ETH NMS interface.
Clock interface Provides two BITS clock input interfaces and two BITS clock output
interfaces (impedance: 120 ohms).
Alarm interface Provides three alarm input and one alarm output interfaces.
Backup and check of Monitors the two independent –48 power supplies in the subrack,
the power supply and performs the overvoltage (–72 V) check and undervoltage (–38.4
V) check.
Provides the central backup of the +3.3 V power supply for the
boards in the subrack, which is the 1:N protection for the secondary
power supply of each board. The power of the +3.3 V power supply
is 80 W.
Performs the overvoltage (3.8 V) check and undervoltage (3.1 V)
check on the output of the +3.3 V backup power supply.
Audible alarm Supports the audible alarm and the clearing of the audible alarm.
CLK
interface CXL
Control module
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.8 V converter
DC/DC -48 V/ -60 V
converter
+3.3 V backup
power
Figure 10-4 shows the block diagram for the functions of the R2AUX.
F&f/OAM
interface CXL
CLK
interface CXL
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.8 V converter
DC/DC -48 V/ -60 V
converter
+3.3 V backup
power
Communication Module
This module applies LAN Switch principle to construct inter-board communication for the OptiX
OSN 1500. This module provides:
l 13 x 10/100 Mbit/s FE interfaces (12 for other boards and 1 for the local board) to connect
the SCC, the cross-connect, the line and the tributary boards for inter-board communication
of the OptiX OSN 1500.
l 2 x 10/100 Mbit/s FE interfaces on the front panel. One interface is the commissioning
network interface for service slots, which forms a VLAN with the 13 inter-board
communication network interfaces. The other interface is the interface for network
management.
l 2 x 10/100 Mbit/s FE interfaces to connect network interfaces of the CXLA and the CXLB
boards. These two interfaces and one network interface on the front panel are of the same
VLAN.
Control Module
The control module mainly consists of CPUs and monitors the running state of the board.
Detection of –48 V and Backup +3.3 V Powers and Lightening Protection Module
This module detects:
Other Function
l F&f interface
l OAM serial interface for network management
l Two-in and two-out BITS clock interface (120 ohms)
l COM, ETH, F&f and OAM interfaces
Communication Module
This module applies LAN Switch principle to construct inter-board communication for the OptiX
OSN 1500. This module provides:
l 13 x 10/100 Mbit/s FE interfaces (12 for other boards and 1 for the local board) to connect
the SCC, the cross-connect, the line and the tributary boards for inter-board communication
of the OptiX OSN 1500.
l 2 x 10/100 Mbit/s FE interfaces on the front panel. One interface is the commissioning
network interface for service slots, which forms a VLAN with the 13 inter-board
communication network interfaces. The other interface is the interface for network
management.
l 2 x 10/100 Mbit/s FE interfaces to connect network interfaces of the CXLA and the CXLB
boards. These two interfaces and one network interface on the front panel are of the same
VLAN.
Control Module
The control module mainly consists of CPLDs and reports the local board state to the CXL board
through the control bus with the CXL board. This module also obtains the control information
of the local board.
Detection of –48 V and Backup +3.3 V Powers and Lightening Protection Module
This module detects:
Other Function
l F&f interface
l OAM serial interface for network management
l Two-in and two-out BITS clock interface (120 ohms)
l COM, ETH, F&f and OAM interfaces
10.2.4 Jumper
A jumper, J9, is present on the lower right of the AUX. The jumper is used to set the subrack as
the main subrack or extended subrack.
Figure 10-5 shows where the jumper J9 is located on the AUX board.
Power
Module
J9
AUX
ETH
COM
CLK
ALM
OAM/F&f
AUX
Interfaces
There are five interfaces on the front panel of the AUX. Table 10-6 lists the type and usage of
these interfaces.
Table 10-8 lists the pins of the ETH and COM interfaces.
Table 10-8 Pins of the ETH and COM interfaces of the AUX
1 Transmitting positive
2 Transmitting negative
3 Receiving positive
4 Not defined
8 7 6 5 4 3 2 1
5 Not defined
6 Receiving negative
Controlled by the software, a specific interface can be used as the OAM or F&f interface. Table
10-10 lists pins of the interface used as the OAM interface.
3 Transmits data.
4 Grounds.
8 7 6 5 4 3 2 1
5 Grounds.
6 Receives data.
Table 10-11 lists the pins of the interface used as the F&f interface.
5 Grounding end
Mechanical Specifications
The mechanical specifications of the AUX are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the AUX is 19 W.
10.3 AMU
This section describes the AMU, an orderwire processing and alarm concatenation board, in
terms of the version, function, principle, front panel and specifications.
Item AMU
Overhead processing Processes the E1, E2, and Serial 1–2 bytes.
Backup and check of Performs the overvoltage/undervoltage check on the output of the
the power supply power supply modules.
Figure 10-7 shows the block diagram for the functions of the AMU.
S1~S4
Overhead
E1/E2 process CXL unit
module
Power
supply -48 V
module
Clock Module
The clock module extracts and processes the reference clock signals from the CXL.
A1 A1 A1 A2 A2 A2 J0
B1 E1
D1 D2 D3 Serial 1 Serial 2
AU_PTR
B2 B2 B2 K1 K2
D4 D5 D6
D7 D8 D9
S1 M1 E2
AMU
STAT
PROG
PHONE
S1
S2
LAMP1
LAMP2
AMU
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Connection status indicator (LINK), which is green when lit.
l Data receiving and transmission indicator (ACT), which is orange when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are five interfaces on the front panel of the AMU. Table 10-13 lists the type and usage
of these interfaces.
4 Signal 1
5 Signal 2
8 7 6 5 4 3 2 1
5 Grounding
7 Not defined
Table 10-16 lists the pins of the LAMP1 and LAMP2 interfaces.
Table 10-16 Pins of the LAMP1 and LAMP2 interfaces of the AMU
LAMP1 LAMP2
Subrack 2
LAMP1 LAMP2
Subrack 1
Cabinet
Mechanical Specifications
The mechanical specifications of the AMU are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the AMU is 8 W.
10.4 FAN
This section describes the FAN, a fan control board, in terms of the version, function, principle,
front panel, configuration and specifications.
Hot swap function Provides the hot swap function for the fan frame.
Figure 10-11 shows the block diagram for the functions of the FAN.
48 V
Fan alarm
signals
Status
Voltage detection
drop unit unit
- 48 V GND
One OptiX OSN 1500 subrack uses one fan tray assembly.
Figure 10-12 shows the appearance of the front panel of the FAN.
FAN
RUN
ALM
Indicators
The following indicators are present on the front panel of the board:
l Board running state (RUN), which is green when lit.
l Fan alarm indicator (ALM), which is red when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Mechanical Specifications
The mechanical specifications of the FAN are as follows:
l Board dimensions (mm): 120 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.0
Power Consumption
In the normal temperature (25℃) and with –48 V input voltage, the maximum power
consumption of the FAN is 20 W.
Working Voltage
The working voltage for the FAN can be –48 V±20% DC.
This chapter describes the WDM processing boards, such as the CMR2, CMR4, MR2, MR2A,
MR2B, MR2C, MR4, LWX, OBU1, and FIB.
11.1 CMR2
This section describes the TN11CMR2, a dual-channel optical add/drop multiplexing board, in
terms of the version, function, principle, front panel, configuration and specifications.
11.2 CMR4
This section describes the TN11CMR4, a four-channel optical add/drop multiplexing board, in
terms of the version, function, principle, front panel, configuration and specifications.
11.3 MR2
This section describes the TN11MR2, a dual-channel optical add/drop multiplexing board, in
terms of the version, function, principle, front panel, configuration and specifications.
11.4 MR2A
This section describes the MR2A, a dual-channel optical add/drop multiplexing board, in terms
of the version, function, principle, front panel, configuration and specifications.
11.5 MR2B
This section describes the MR2B, a dual-channel optical add/drop multiplexing board, in terms
of the version, function, principle, front panel, configuration and specifications.
11.6 MR2C
This section describes the MR2C, a dual-channel optical add/drop multiplexing board, in terms
of the version, function, principle, front panel, configuration and specifications.
11.7 MR4
This section describes the TN11MR4, a four-channel optical add/drop multiplexing board, in
terms of the version, function, principle, front panel, configuration and specifications.
11.8 LWX
This section describes the LWX, an arbitrary rate wavelength converting board, in terms of the
version, function, principle, front panel, configuration and specifications.
11.9 OBU1
This section describes the TN11OBU1, an optical booster amplifier board, in terms of the
version, function, principle, front panel, configuration and specifications.
11.10 FIB
This section describes the FIB, a wavelength filter and isolation board, in terms of the version,
function, principle, front panel, configuration and specifications.
11.1 CMR2
This section describes the TN11CMR2, a dual-channel optical add/drop multiplexing board, in
terms of the version, function, principle, front panel, configuration and specifications.
Channel expansion Provides the intermediate port used for expansion. Under certain
conditions, the capacity of upstream and downstream channels can be
expanded when the intermediate port is connected to other optical
add/drop multiplexing boards.
OADM module
Delayed
startup
Fuse
SCC
Back plane
-48 V/-60 V -48 V/-60 V SCC
The CMR2 mainly includes the optical add/drop multiplexer (OADM) module adding/dropping
two channels of signals. The OADM adds/drops and multiplexes two channels of signals. It also
provides concatenation interfaces to connect other add/drop multiplexing boards for more
powerful add/drop capability. The CMR2 is a passive board that has no interface with the
backplane.
OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream
station. The Drop optical module drops through optical interfaces D01 and D02 two wavelengths
from the signal. These two dropped wavelengths are output from the MO optical interface.
The MI optical interface receives one multiplexed signal that travels over the main optical path.
The Add optical module adds two wavelengths through optical interfaces A01 and A02 and
multiplexes them with the signal in the main optical path into one signal. This multiplexed signal
is output through OUT.
CMR2
STAT
LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
OUT
IN
MO
MI
D1
A1
D2
A2
CMR2
Indicator
On the front panel of the CMR2, there is one board hardware state indicator (STAT), which is
red or green when lit.
For indication of the indicator, see A Equipment and Board Alarm Indicators.
Interfaces
There are eight optical interfaces on the front panel of the CMR2. Table 11-2 lists the type and
usage of the optical interfaces.
First four characters Wavelength for the optical The wavelength is for the
signals first channel of optical
signals processed by the
board.
Last four characters Wavelength for the optical The wavelength is for the
signals second channel of optical
signals processed by the
board.
The maximum launched optical power of the optical interfaces ranges from 10 dBm (10 mW)
to 22.15 dBm (164 mW).
Mechanical Specifications
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
Power Consumption
l In the normal temperature (25℃), the maximum power consumption of the CMR2 is 0.2
W.
l In the high temperature (55℃), the maximum power consumption of the CMR2 is 0.3 W.
11.2 CMR4
This section describes the TN11CMR4, a four-channel optical add/drop multiplexing board, in
terms of the version, function, principle, front panel, configuration and specifications.
Channel expansion Provides the intermediate port used for expansion. Under certain
conditions, the capacity of upstream and downstream channels can be
expanded when the intermediate port is connected to other optical
add/drop multiplexing boards.
Figure 11-3 shows the block diagram for the functions of the CMR4.
OADM module
Delayed
startup
Fuse
SCC
Back plane
-48 V/-60 V -48 V/-60 V SCC
OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream
station. The Drop optical module drops through optical interfaces D01–D04 four wavelengths
from the signal. These four dropped wavelengths are output from the MO optical interface.
The MI optical interface receives one multiplexed signal that travels over the main optical path.
The Add optical module adds four wavelengths through optical interfaces A01–A04 and
multiplexes them with the signal in the main optical path into one signal. This multiplexed signal
is output through OUT.
CMR4
STAT
LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
OUT
IN
MO
MI
D1
A1
D2
A2
D3
A3
D4
A4
CMR4
Indicator
One the front panel of the CMR4, there is one board hardware state indicator (STAT), which is
red or green when lit.
For indication of the indicator, see A Equipment and Board Alarm Indicators.
Interfaces
There are twelve optical interfaces on the front panel of the CMR4. Table 11-6 lists the type
and usage of these optical interfaces.
Characters 1–2 Wavelength for the optical The characters are two
signals middle characters of the four
that indicate the wavelength
for the first channel of optical
signals.
Characters 3–4 Wavelength for the optical The characters are two
signals middle characters of the four
that indicate the wavelength
for the second channel of
optical signals.
Characters 5–6 Wavelength for the optical The characters are two
signals middle characters of the four
that indicate the wavelength
for the third channel of
optical signals.
Characters 7–8 Wavelength for the optical The characters are two
signals middle characters of the four
that indicate the wavelength
for the fourth channel of
optical signals.
l "47" indicates that the wavelength for the first channel of optical signals is 1471 nm.
l "49" indicates that the wavelength for the second channel of optical signals is 1491 nm.
l "59" indicates that the wavelength for the third channel of optical signals is 1591 nm.
l "61" indicates that the wavelength for the fourth channel of optical signals is 1611 nm.
The maximum launched optical power of the optical interfaces ranges from 10 dBm (10 mW)
to 22.15 dBm (164 mW).
Mechanical Specifications
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 0.9
Power Consumption
l In the normal temperature (25℃), the maximum power consumption of the CMR4 is 0.2
W.
l In the high temperature (55℃), the maximum power consumption of the CMR4 is 0.3 W.
11.3 MR2
This section describes the TN11MR2, a dual-channel optical add/drop multiplexing board, in
terms of the version, function, principle, front panel, configuration and specifications.
Channel expansion Provides the intermediate port used for expansion. Under certain
conditions, the capacity of upstream and downstream channels can be
expanded when the intermediate port is connected to other optical
add/drop multiplexing boards.
OADM module
Delayed
startup
Fuse
SCC
Back plane
-48 V/-60 V -48 V/-60 V SCC
OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream
station. The Drop optical module drops through optical interfaces D01 and D02 two wavelengths
from the signal. These two dropped wavelengths are output from the MO optical interface.
The MI optical interface receives one multiplexed signal that travels over the main optical path.
The Add optical module adds two wavelengths through optical interfaces A01 and A02 and
multiplexes them with the signal in the main optical path into one signal. This multiplexed signal
is output through OUT.
MR2
STAT
LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
OUT
IN
MO
MI
D1
A1
D2
A2
MR2
Indicator
On the front panel of the MR2, there is one board hardware state indicator (STAT), which is red
or green when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are eight optical interfaces on the front panel of the MR2. Table 11-10 lists the type and
usage of the optical interfaces.
First four (1–4) characters Frequency of optical signals The four characters are the
last four characters of the
figure that marks the
frequency of the first channel
of optical signals.
Last four (5–8) characters Frequency of optical signals The four characters are the
last four characters of the
figure that marks the
frequency of the second
channel of optical signals.
l "9360" indicates that the frequency of the first channel of optical signals is 193.60 THz.
l "9370" indicates that the frequency of the second channel of optical signals is 193.70 THz.
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
Power Consumption
l In the normal temperature (25℃), the maximum power consumption of the MR2 is 0.2 W.
l In the high temperature (55℃), the maximum power consumption of the MR2 is 0.3 W.
11.4 MR2A
This section describes the MR2A, a dual-channel optical add/drop multiplexing board, in terms
of the version, function, principle, front panel, configuration and specifications.
Basic function Adds/Drops two arbitrary adjacent wavelengths, which are compliant
with ITU-T G.692 (DWDM). The signals are transparently
transmitted, and the working wavelength ranges from 1535.82 nm to
1560.61 nm.
OTM function The MR2A can be used as the two-channel wavelength adding/
dropping OTM station. Two MR2C boards can be concatenated and
upgraded to the four-channel wavelength adding/dropping OTM
station. See Figure 11-7.
IN MO IN MO IN MO
Drop Drop Drop
OUT OUT
MI MI OUT MI
Add Add Add
A1 A2 A1 A2 A1 A2
(1) (2)
Figure 11-8 MR2A and LWX used as the two-channel wavelength adding/dropping OADM
station
LWX
A2 D2
Out MO
In MR2A MI
D1 A1
LWX
OADM module
Delayed
startup
Fuse
SCC
Back plane
-48 V/-60 V -48 V/-60 V SCC
The MR2A mainly includes the optical add/drop multiplexer (OADM) module adding/dropping
two channels of signals. The OADM adds/drops and multiplexes two channels of signals. It also
provides concatenation interfaces to connect other add/drop multiplexing boards for more
powerful add/drop capability. The MR2A is a passive board that has no interface with the
backplane.
OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream
station. The Drop optical module drops through optical interfaces D01 and D02 two wavelengths
from the signal. These two dropped wavelengths are output from the MO optical interface.
The MI optical interface receives one multiplexed signal that travels over the main optical path.
The Add optical module adds two wavelengths through optical interfaces A01 and A02 and
multiplexes them with the signal in the main optical path into one signal. This multiplexed signal
is output through OUT.
MR2A
CLASS 1
LASER
PRODUCT
OUT AO1
AO2 M I
M O DO2
DO1 IN
MR2A
Interfaces
There are four pairs of LC optical interfaces on the front panel of the MR2A. Table 11-14 lists
the type and usage of the optical interfaces.
Item Description
Item Description
The maximum launched optical power of the optical interfaces ranges from 10 dBm (10 mW)
to 22.15 dBm (164 mW).
Mechanical Specifications
The mechanical specifications of the MR2A are as follows:
Power Consumption
In the normal temperature (25℃), the MR2A does not consume power.
11.5 MR2B
This section describes the MR2B, a dual-channel optical add/drop multiplexing board, in terms
of the version, function, principle, front panel, configuration and specifications.
OTM function The MR2B can be used as the two-channel wavelength adding/
dropping OTM station. Two MR2B boards can be concatenated and
upgraded to the four-channel wavelength adding/dropping OTM
station. See Figure 11-11.
IN MO IN MO IN MO
Drop Drop Drop
OUT OUT
MI MI OUT MI
Add Add Add
A1 A2 A1 A2 A1 A2
(1) (2)
Figure 11-12 MR2B and LWX used as the two-channel wavelength adding/dropping OADM
station
LWX
A2 D2
Out MO
In MR2B MI
D1 A1
LWX
Figure 11-13 shows the block diagram for the functions of the MR2B.
OADM module
Delayed
startup
Fuse
SCC
Back plane
-48 V/-60 V -48 V/-60 V SCC
The MR2B mainly includes the optical add/drop multiplexer (OADM) module adding/dropping
two channels of signals. The OADM adds/drops and multiplexes two channels of signals. It also
provides concatenation interfaces to connect other add/drop multiplexing boards for more
powerful add/drop capability. The MR2B is a passive board that has no interface with the
backplane.
OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream
station. The Drop optical module drops through optical interfaces D01 and D02 two wavelengths
from the signal. These two dropped wavelengths are output from the MO optical interface.
The MI optical interface receives one multiplexed signal that travels over the main optical path.
The Add optical module adds two wavelengths through optical interfaces A01 and A02 and
multiplexes them with the signal in the main optical path into one signal. This multiplexed signal
is output through OUT.
MR
MR2B
2B
CLASS 1
LASER
PRODUCT
OUT AO1 AO2 M I
MO DO2 DO1 IN
MR2B
Interfaces
There are four pairs of optical interfaces on the front panel of the MR2B. Table 11-17 lists the
type and usage of the optical interfaces.
Item Description
Item Description
The maximum launched optical power of the optical interfaces is lower than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the MR2B are as follows:
Power Consumption
In the normal temperature (25℃), the MR2B does not consume power.
11.6 MR2C
This section describes the MR2C, a dual-channel optical add/drop multiplexing board, in terms
of the version, function, principle, front panel, configuration and specifications.
OTM function The MR2C can be used as the two-channel wavelength adding/
dropping OTM station. Two MR2C boards can be concatenated and
upgraded to the four-channel wavelength adding/dropping OTM
station. See Figure 11-15.
IN MO IN MO IN MO
Drop Drop Drop
OUT OUT
MI MI OUT MI
Add Add Add
A1 A2 A1 A2 A1 A2
(1) (2)
Figure 11-16 Two-channel wavelength adding/dropping OADM station realized by the MR2C
and LWX
LWX
A2 D2
Out MO
In MR2C MI
D1 A1
LWX
Figure 11-17 shows the block diagram for the functions of the MR2C.
OADM module
Delayed
startup
Fuse
SCC
Back plane
-48 V/-60 V -48 V/-60 V SCC
The MR2C mainly includes the optical add/drop multiplexer (OADM) module adding/dropping
two channels of signals. The OADM adds/drops and multiplexes two channels of signals. It also
provides concatenation interfaces to connect other add/drop multiplexing boards for more
powerful add/drop capability. The MR2C is a passive board that has no interface with the
backplane.
OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream
station. The Drop optical module drops through optical interfaces D01 and D02 two wavelengths
from the signal. These two dropped wavelengths are output from the MO optical interface.
The MI optical interface receives one multiplexed signal that travels over the main optical path.
The Add optical module adds two wavelengths through optical interfaces A01 and A02 and
multiplexes them with the signal in the main optical path into one signal. This multiplexed signal
is output through OUT.
MR2C
CLASS 1
LASER
PRODUCT
OUT AO1
AO2 M I
M O DO2
DO1 IN
MR2C
Interfaces
There is four pairs of optical interfaces on the front panel of the MR2C. Table 11-20 lists the
type and usage of the optical interfaces.
Mechanical Specifications
The mechanical specifications of the MR2C are as follows:
l Board dimensions (mm): 262.05 (H) x 110 (D) x 22 (W)
l Weight (kg): 1.0
Power Consumption
In the normal temperature (25℃), the MR2C does not consume power.
11.7 MR4
This section describes the TN11MR4, a four-channel optical add/drop multiplexing board, in
terms of the version, function, principle, front panel, configuration and specifications.
Channel expansion Provides the intermediate port used for expansion. Under certain
conditions, the capacity of upstream and downstream channels can be
expanded when the intermediate port is connected to other optical
add/drop multiplexing boards.
Figure 11-19 shows the block diagram for the functions of the MR4.
OADM module
Delayed
startup
Fuse
SCC
Back plane
-48 V/-60 V -48 V/-60 V SCC
OADM module
The board receives through IN one multiplexed optical signal that travels from the upstream
station. The Drop optical module drops through optical interfaces D01–D04 four wavelengths
from the signal. These four dropped wavelengths are output from the MO optical interface.
The MI optical interface receives one multiplexed signal that travels over the main optical path.
The Add optical module adds four wavelengths through optical interfaces A01–A04 and
multiplexes them with the signal in the main optical path into one signal. This multiplexed signal
is output through OUT.
MR4
STAT
LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
OUT
IN
MO
MI
D1
A1
D2
A2
D3
A3
D4
A4
MR4
Indicator
On the front panel of the MR4, there is one board hardware state indicator (STAT), which is red
or green when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are twelve optical interfaces on the front panel of the MR4. Table 11-23 lists the type and
usage of the optical interfaces.
First four characters Frequency of optical signals The four characters are the
last four characters of the
figure that marks the
frequency of the first channel
of optical signals.
Last four characters Frequency of optical signals The four characters are the
last four characters of the
figure that marks the
frequency of the fourth
channel of optical signals.
l "9210" indicates that the frequency of the first channel of optical signals is 192.10 THz.
l "9240" indicates that the frequency of the fourth channel of optical signals is 192.40 THz.
The four channels of optical signals the MR4 processes are successive:
The maximum launched optical power of the optical interfaces ranges from 10 dBm (10 mW)
to 22.15 dBm (164 mW).
Mechanical Specifications
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 0.9
Power Consumption
l In the normal temperature (25℃), the maximum power consumption of the MR4 is 0.2 W.
l In the high temperature (55℃), the maximum power consumption of the MR4 is 0.3 W.
11.8 LWX
This section describes the LWX, an arbitrary rate wavelength converting board, in terms of the
version, function, principle, front panel, configuration and specifications.
Basic Realizes the convertion between the wavelength at an arbitrary rate at the
function client side and the wavelength compliant with ITU-T G.692 (DWDM).
Transparently transmits signals.
3R function Provides the 3R function for the signals at the client side ranging from 10
Mbit/s to 2.7 Gbit/s. Recovers the clock, and monitors the rate.
Protection Single fed and single Supports the inter-board protection and 1+1 inter-
scheme receiving board hot backup. The switching time is less than 50
ms.
ALS function Supports the ALS function. When no signals are received, the corresponding
optical transmit module is automatically turned off.
Loopback Provides the inloop and outloop at the optical interface level, which are used
function for locating faults.
Performance Provides rich alarms and performance events for easy maintenance.
and alarm
monitoring
10 Mbit/s~2.7 Gbit/s
O/
E 2×2 Cross- Multi-rate
WDM side
Optical module at
loopback connection
CDR
client side
10 Mbit/s~2.7 Gbit/s O/
E Data
LOS
Laser shut down
communication
and control
module
LOS
Loopback control
Reference
clock
10 Mbit/s~2.7 Gbit/s
O/
E
Optical module 1
at WDM side
Clock
10 Mbit/s~2.7 Gbit/s
O/
Optical E Data
splitter
LOS
communication
and control
Laser shut down
module Communication
SCC Unit
+3.3 V
DC/DC Fuse -48 V/ -60 V
+1.5 V converter
DC/DC module -48 V/ -60 V
+5V converter
+1.8 V module Fuse
+3.3 V backup
power
l In the transmit direction, the module converts the electrical signals into SDH optical signals,
and then send optical signals to fibers for transmission.
l Detect the R_LOS alarm and provide the function to shut down the laser.
Cross-connect Module
l Supports data selection from client side to WDM side and from WDM side to client side
l Supports WDM side optical module selection
l Supports loopback of client side signals
l Supports loopback of WDM side signals
CDR Module
l Supports recovering data and clock signals from 10 Mbit/s to 2.7 Gbit/s
l Supports reading rates of accessed services
LWX
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCTTX RX
OUT1 IN1
OUT2 IN2
LWX
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are six optical interfaces on the front panel of the LWX. Table 11-27 lists the type and
usage of the optical interfaces.
Table 11-28 Relation between the board feature code and the receive/transmit scheme
Item Specification
Item Specification
Transmission 15 40 80
distance (km)
Side mode 30 30 30
suppression ratio
(dB)
Eye pattern Compliant with the Compliant with the Compliant with the
template defined in template defined in template defined in
ITU-T G.957 ITU-T G.957 ITU-T G.957
Recommendations Recommendations Recommendations
Channel 100
spacing (GHz)
Item Specification
Max. mean –2 –2 +7 –2
launched optical
power (dBm)
Min. mean +3 +3 +5 +3
launched optical
power (dBm)
Eye pattern Compliant with Compliant with Compliant with Compliant with
the template the template the template the template
defined in ITU- defined in ITU- defined in ITU- defined in ITU-
T G.957 T G.957 T G.957 T G.957
Recommendati Recommendati Recommendati Recommendati
ons ons ons ons
Item Specification
Min. overload –9 0
(dBm)
Mechanical Specifications
The mechanical specifications of the LWX are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the LWX is 30 W.
11.9 OBU1
This section describes the TN11OBU1, an optical booster amplifier board, in terms of the
version, function, principle, front panel, configuration and specifications.
Typical gain The typical gain of the OBU101 is 20 dB. The typical gain of the
OBU102 is 23 dB.
Gain-locking The EDFA of the board has the gain-locking function. When one or
technology more channels are added or dropped, or optical signals of certain
channels fluctuate, the signal gains of other channels are not affected.
Transient control The EDFA of the board has the transient control function. When
technology channels are added or dropped, the system can be upgraded or expanded
without interrupting services if the optical power fluctuation is
suppressed.
NOTE
The OBU1 is of two types: OBU101 and OBU102. The OBU101 is used at the receive end. The OBU102
is used at the transmit end.
Figure 11-23 shows the block diagram for the functions of the OBU1.
Detecting for
Pumping PIN temperature and
current
pumping current
+5 V DC/DC
converter
Delayed
startup
Fuse
Backplane
-48 V/-60 V -48 V/-60 V SCC
Signal Flow
The OBU1 accesses the multiplexed optical signals, which are amplified by the EDFA optical
module. The OBU1 then outputs the amplified optical signals through the OUT port. The OBU1
also outputs few monitoring signals to the test instrument for performance analysis.
Optical Splitter
The splitter is used to split the optical signals received from the EDFA optical module into two
channels of signals with different power. One channel of signlas are output from OUT optical
interface and then transmitted in the main optical channel. The other channel of signals are output
to the MON port for sepctrum detection and monitoring. The power of signals at the MON is
one ninety-nineth of that at the OUT interface. In other words, the power of signals at MON is
20 dB lower than that at the OUT interface.
OBU1
STAT
ACT
PROG
SRV
LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
MON
OUT
IN
OBU1
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are three pairs of optical interfaces on the front panel of the OBU1. Table 11-32 lists the
type and usage of the optical interfaces.
Last two (5–6) characters Maximum nominal input Maximum nominal input
optical power optical power
For example, the feature code of the TN11OBU1 is G23I-3. The feature code indicates that the
gain is 23 dB and the maximum nominal input optical power is –3 dBm.
Item Specification
OBU1C01 OBU1C02
The maximum launched optical power of the optical interfaces ranges from 10 dBm (10 mW)
to 22.15 dBm (164 mW).
Mechanical Specifications
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.3
Power Consumption
l The power consumption of OBU101:
– In the normal temperature (25℃), the maximum power consumption of the OBU1 is
16 W.
– In the high temperature (55℃), the maximum power consumption of the OBU1 is 17.6
W.
l The power consumption of OBU102:
– In the normal temperature (25℃), the maximum power consumption of the OBU1 is
18 W.
– In the high temperature (55℃), the maximum power consumption of the OBU1 is 19.8
W.
11.10 FIB
This section describes the FIB, a wavelength filter and isolation board, in terms of the version,
function, principle, front panel, configuration and specifications.
11.10.1 Version Description
The functional version of the FIB board is N1.
11.10.2 Function and Feature
The FIB, a filter and isolation board, is used to filter and isolate 1 x STM-16 optical signals.
11.10.3 Working Principle and Signal Flow
The FIB consists of an isolator and a filter.
11.10.4 Front Panel
On the front panel of the FIB, there are two pairs of optical interfaces.
11.10.5 Valid Slots
The FIB can be housed in any of slots 12–13 in the subrack.
11.10.6 Technical Specifications
The technical specifications of the FIB cover the optical interface specifications, board
dimensions, weight and power consumption.
FIB
a(54dB) b(18dB)
Optical isolator The isolator lets optical signals pass in a unidirectional manner. The
working wavelength ranges from 1529 nm to 1561 nm.
Optical filter The filter filters all signals carried in wavelengths except those in the
1550.12 nm wavelength.
Figure 11-26 Block diagram for the working principle of the FIB
Isolator Filter
After travelling for a long distance in fibers, optical signals are heavily attenuated and then
degraded. The degraded signals cannot be normally received by optical receiver. In this case,
the ROP should be used to amplify the gain of the optical signals. The ROP has high optical
power. To prevent other factors from affecting the ROP, use the FIB to filter wavelengths.
The filter of the FIB lets optical signals pass in a unidirectional manner. The filter filters all
signals carried in other wavelengths except those in the 1550.12 nm wavelength. In this way,
the optical receiver can normally receive optical signals.
FIB
CLASS1
LASER
PRODUCT
OUT
IN
FIB
Interfaces
On the front panel of the FIB, there are a LC optical interface and a E2000 optical interface,
which are used to receive and transmit 1-channel 2.5 Gbit/s optical signals. The optical interfaces
use pluggable optical modules for easy maintenance.
Mechanical Specifications
The mechanical specifications of the FIB are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 0.4
Power Consumption
The FIB does not consume power.
This chapter describes the optical amplifier boards, such as the BA2, BPA, and COA, and the
dispersion compensation boards, such as the DCU.
12.1 BA2
This section describes the BA2, 2-channel optical booster amplifier board, in terms of the
version, function, working principle, front panel and specifications.
12.2 BPA
This section describes the BPA, one-channel amplifier and one-channel pre-amplifier board, in
terms of the version, function, principle, front panel and specifications.
12.3 COA
This section describes the COA, a case-shaped optical amplifier, in terms of the version, function,
principle, front panel, installation position and specifications.
12.1 BA2
This section describes the BA2, 2-channel optical booster amplifier board, in terms of the
version, function, working principle, front panel and specifications.
Figure 12-1 shows the location of the BA in the optical transmission system.
Transmit BA Receive
The BA2 amplifies the power of two-channel optical signals. Table 12-1 lists the functions and
features of the BA2.
Basic function Increases the launched optical power of the line board to 13–15 dBm
or 15–18 dBm. Thus, when the G.652 optical fiber with a loss of 0.275
dB/km is used, the transmission distance can be 120 km, 130 km, or
above.
EDFA Automatically controls the optical power and laser temperature of the
EDFA module.
Automatically monitors the input and output optical power of the EDFA
module and queries the optical power.
Protects the EDFA module. When no optical signals are input, the laser
is automatically turned off. When optical signals are input, the laser is
automatically turned on.
Performance and Reports the performance parameters of the laser. Provides rich alarms
alarm monitoring and performance events for easy management and maintenance of the
equipment.
Software upgrade Supports the software upgrade and expansion without interrupting
services.
NOTE
The BA2 provides the IPA function. When the IPA function is enabled, the pumping laser is turned off if
no input signals are detected on the receive end of the line board. Thus, this function is used to prevent the
high laser power from damaging eyes.
Input Output
power power
monitor Laser pump monitor
(Pin1) (Pin2)
Pump
Input Pump Output
current Temperature
power current power
detect
Laser Pump
shutdown temperature
Manual control
control LOS in
AD/DA
Control&Generation alarms
Control module
Communication
Communication SCC unit
module
+3.3 V DC/DC
Fuse -48 V/ -60 V
converter
5V DC/DC module -48 V/ -60 V
converter
module Fuse
+3.3 V backup
power
EDFA Module
The optical amplifier unit consists of two EDFA modules. One is BA and the other PA. When
the board is used as a pre-amplifier (PA), an optical filter with 1550.12 nm as the central
wavelength is added to the optical output end of the module. A booster amplifier (BA) does not
have the filter. A semi-conductor laser bump with 980 nm as the central wavelength is in the
erbium fiber inside the EDFA module. Bump light and input signal light are coupled into the
erbium fiber through an optical coupler. The input and output optical signals of the module are
led out by two fiber splitters as per a specific coupling ratio. The optical signals are then converted
to optical current by two PIN photoelectrical diodes. The input and output powers of the EDFA
module are determined as per the optical signals. The module also applies optical isolating
measures at the input and the output ends to improve the performance of the module.
Control Module
The control module:
l Detects and drives bump electricity
l Controls the pump temperature of laser
l Detects input and output power
l Reports alarms
The control module consists of A/D converting unit, D/A converting unit and CPU. The A/D
converting unit converts the temperature value of the cooling electricity and the input/output
optical power from analog values to digital values. The converted values are then sent to CPU,
which generates performance reporting event or alarm. The A/D converting unit also converts
bump electricity from analog values to digital values. The converted values are then sent to CPU.
After the CPU processes the converted values, the D/A converting unit controls precisely the
driving analog circuit of the bump laser of the EDFA optical module. The internal temperature
of the bump laser module is kept at 25℃. The temperature sensor inside the bump laser outputs
temperature change to drive cooler to keep the internal temperature of the bump laser module
at 25℃.
Communication Module
The communication module supports ethernet communication.
BA2
STAT
ACT
PROG
SRV
OUT1 IN1
OUT2 IN2
BA2
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the BA2, there are two pairs of LC optical interfaces, which use the
pluggable optical modules for easy maintenance. Table 12-2 lists the type and usage of these
optical interfaces.
Table 12-3 lists the relation between the board feature code and the output optical power.
Table 12-3 Relation between the board feature code and output optical power for the BA2
Item Specification
Mechanical Specifications
The mechanical specifications of the BA2 are as follows:
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the BA2 is 20 W.
12.2 BPA
This section describes the BPA, one-channel amplifier and one-channel pre-amplifier board, in
terms of the version, function, principle, front panel and specifications.
The code behind the board name in the barcode is the board feature code. The board feature code
of the BPA indicates the output optical power of the optical interfaces.
12.2.7 Technical Specifications
The technical specifications of the BPA cover the optical interface specifications, board
dimensions, weight and power consumption.
Figure 12-4 shows the location of the BA and PA in the optical transmission system.
Transmit BA Receive
Transmit PA Receive
Basic function Increases the launched optical power of the line board to 13–15 dBm
or 15–18 dBm. Thus, when the G.652 optical fiber with a loss of 0.275
dB/km is used, the transmission distance can be 120 km, 130 km, or
above.
Function of the PA Provides the PA module to preamplify the received optical signals.
Increases the power of the small volume of optical signals by 22–25
dB, and thus enhances the sensitivity of the receiver to –37 dBm.
Performance and Reports the performance parameters of the laser. Provides rich alarms
alarm monitoringa and performance events for easy management and maintenance of the
equipment.
Software upgrade Supports the software upgrade and expansion without interrupting
services.
a:The BPA does not support the alarm in the test state and the query of the power supply
voltage.
Figure 12-5 Block diagram for the working principle of the BPA
EDFA module
Doped
erbium
Optical input fiber Optical output
Fiber Input WDM Output Filter Optical
distributor isolate coupler isolate splitter
Input Output
power power
monitor Laser pump monitor
(Pin1) (Pin2)
Pump
Input Pump Output
current Temperature
power current power
detect
Laser Pump
shutdown temperature
Manual control
control LOS in
AD/DA
Control&Generation alarms
Control module
Communication
Communication SCC unit
module
+3.3 V DC/DC
Fuse -48 V/ -60 V
converter
5V DC/DC module -48 V/ -60 V
converter
module Fuse
+3.3 V backup
power
EDFA Module
The optical amplifier unit consists of two EDFA modules. One is BA and the other PA. When
the board is used as a pre-amplifier (PA), an optical filter with 1550.12 nm as the central
wavelength is added to the optical output end of the module. A booster amplifier (BA) does not
have the filter. A semi-conductor laser bump with 980 nm as the central wavelength is in the
erbium fiber inside the EDFA module. Bump light and input signal light are coupled into the
erbium fiber through an optical coupler. The input and output optical signals of the module are
led out by two fiber splitters as per a specific coupling ratio. The optical signals are then converted
to optical current by two PIN photoelectrical diodes. The input and output powers of the EDFA
module are determined as per the optical signals. The module also applies optical isolating
measures at the input and the output ends to improve the performance of the module.
Control Module
The control module:
l Detects and drives bump electricity
l Controls the pump temperature of laser
l Detects input and output power
l Reports alarms
The control module consists of A/D converting unit, D/A converting unit and CPU. The A/D
converting unit converts the temperature value of the cooling electricity and the input/output
optical power from analog values to digital values. The converted values are then sent to CPU,
which generates performance reporting event or alarm. The A/D converting unit also converts
bump electricity from analog values to digital values. The converted values are then sent to CPU.
After the CPU processes the converted values, the D/A converting unit controls precisely the
driving analog circuit of the bump laser of the EDFA optical module. The internal temperature
of the bump laser module is kept at 25℃. The temperature sensor inside the bump laser outputs
temperature change to drive cooler to keep the internal temperature of the bump laser module
at 25℃.
Communication Module
The communication module supports ethernet communication.
BPA
STAT
ACT
PROG
SRV
BOUT BIN
POUT
PIN
BPA
Indicators
The following indicators are present on the front panel of the board:
l Board hardware state indicator (STAT), which is green or red when lit.
l Service activating state indicator (ACT), which is green when lit.
l Board software state indicator (PROG), which is green or red when lit.
l Service alarm indicator (SRV), which is red, green or yellow when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the BPA, there are two pairs of LC optical interfaces, which use the
pluggable optical modules for easy maintenance. Table 12-6 lists the type and usage of these
optical interfaces.
Table 12-7 Relation between the board feature code and output optical power for the BPA
Board Barcode Feature Code Description
NOTE
When performing loopback to the PA module of the BPA, prevent the damage caused by high input optical
power to the optical module.
Mechanical Specifications
The mechanical specifications of the BPA are as follows:
l Board dimensions (mm): 262.05 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.0
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the BPA is 20 W.
12.3 COA
This section describes the COA, a case-shaped optical amplifier, in terms of the version, function,
principle, front panel, installation position and specifications.
Functional The COA has three versions, 61, 62, and N1.
version
Difference The 61COA is the EDFA optical amplifier in the 1550-nm fiber
communication window.
The N1COA is the EDFA optical amplifier in the 1530 nm to 1560 nm
fiber communication window.
The N1COA does not have the filter and is a multi-wavelength amplifier.
The 62COA uses the Raman optical amplifier module.
installed in the ETSI cabinetwithout occupying slots in the subrack and are independently
powered.
The application of the 61COA and N1COA in the optical transmission system is the same as
that of the BA2 and BPA. Table 12-10 lists the functions and features of the 61COA and N1COA.
Function of the BA The 61COA enhances the launched optical power to 13–15 dBm or
15–17 dBm, and thus the valid transmission distance of optical
signals can be extended.
Function of the PA The N1COA is a PA, with a receiver sensitivity of –38 dBm.
Function of the serial Communicates with the CXL through the RS232 serial port, reports
communication the alarms and performance events from the COA to the T2000, and
receives the configuration commands issued by the T2000.
62COA
The 62COA, a case-shaped Raman optical amplifier, is used at the receive end of the SDH
equipment.
The 62COA inputs counter-propagated pumping optical signals to fibers for distributed Raman
amplification. Different from that of the 61COA, the gain medium of Raman amplification is
the line fiber that can realize better noise performance. Thus, the 62COA can extend the
transmission distance, lower the signal-to-noise ratio and realize ultra long hop transmission for
a single span.
Figure 12-8 lists the appearance of the 62COA.
1
2
3
The 62COA, a case-shaped Raman optical amplifier, is used at the receive end of the transmission
system. During the transmission, the 62COA amplifies optical signals based on the stimulated
Raman scattering of the fiber. The 62COA provides optical transmission for more than 170 km,
when used with the EDFA. See Figure 12-9.
During the optical transmission, the Raman amplifier amplifies optical signals by inputing
counter-propagated pumping optical signals to fibers for distributed Raman amplification. Thus,
the phase of optical signals is significantly different from that of pumping signals. The power
fluctuation of the Raman pumping is offset in the counter-propagation, and thus the noise caused
by the pumping can be effectively suppressed.
Table 12-11 lists the functions and features of the 62COA.
Basic function Configured at the receive end of the SDH system, and provides extra
long-haul transmission (more than 170 km), when used with an
EDFA at the transmit end with an output power of 17 dBm.
Function of the PA The 62COA is a PA, with a receiver sensitivity of -39 dBm.
Function of the serial Communicates with the CXL through the RS232 serial port, reports
communication the alarms and performance events from the COA to the T2000, and
receives the configuration commands issued by the T2000.
Figure 12-10 Block diagram for the functions of the 61COA and N1COA
EDFA module
Doped
erbium
Optical input fiber Optical output
Fiber Input WDM Output Filter Optical
distributor isolate coupler isolate splitter
Input Output
power power
monitor Laser pump monitor
(Pin1) (Pin2)
Pump
Input Pump Output
current Temperature
power current power
detect
Laser Pump
shutdown temperature
Manual control
control LOS in
AD/DA
Control&Generation alarms
Control module
Communication
Communication SCC unit
module
+3.3 V DC/DC
Fuse -48 V/ -60 V
converter
5V DC/DC module -48 V/ -60 V
converter
module Fuse
+3.3 V backup
power
EDFA Module
The optical amplifier unit consists of two EDFA modules. One is BA and the other PA. When
the board is used as a pre-amplifier (PA), an optical filter with 1550.12 nm as the central
wavelength is added to the optical output end of the module. A booster amplifier (BA) does not
have the filter. A semi-conductor laser bump with 980 nm as the central wavelength is in the
erbium fiber inside the EDFA module. Bump light and input signal light are coupled into the
erbium fiber through an optical coupler. The input and output optical signals of the module are
led out by two fiber splitters as per a specific coupling ratio. The optical signals are then converted
to optical current by two PIN photoelectrical diodes. The input and output powers of the EDFA
module are determined as per the optical signals. The module also applies optical isolating
measures at the input and the output ends to improve the performance of the module.
Control Module
The control module:
The control module consists of A/D converting unit, D/A converting unit and CPU. The A/D
converting unit converts the temperature value of the cooling electricity and the input/output
optical power from analog values to digital values. The converted values are then sent to CPU,
which generates performance reporting event or alarm. The A/D converting unit also converts
bump electricity from analog values to digital values. The converted values are then sent to CPU.
After the CPU processes the converted values, the D/A converting unit controls precisely the
driving analog circuit of the bump laser of the EDFA optical module. The internal temperature
of the bump laser module is kept at 25℃. The temperature sensor inside the bump laser outputs
temperature change to drive cooler to keep the internal temperature of the bump laser module
at 25℃.
Communication Module
The communication module supports ethernet communication.
1 2 3 4 5 6 7 11
Figure 12-12 shows the appearance of the front panel of the 62COA.
Indicators
The following indicators are present on the front panel of the board:
l Board running state (RUN), which is green when lit.
l Fan alarm indicator (ALM), which is red when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the 61COA and N1COA, there are one pair of SC/PC optical interfaces,
which are used to input or output one channel of optical signals. The input optical interface of
the 62COA is connected to the E2000 flange and the output optical interface is connected to the
SC flange. Figure 12-13 shows the SC/PC optical interfaces of the 61COA and N1COA.
Figure 12-14 shows the flange and fiber connector used at the input optical interface of the
62COA.
NOTE
The dust cap is specially designed for the E2000 fiber jumper. Do not remove the cap during fiber
connection. For normal fiber connection, directly insert the fiber jumper into the E2000 flange.
The COA has two RS232 serial interfaces, which are connected to the SCC unit for reporting
of alarms and performance events.
Table 12-12 lists the pins of the RS232 interface.
3 3 Pin for
9
transmitting data
1
5 5 Pin for common
grounding
TIP
For the communication with the CXL, the RS232-1 interface of the COA is connected to the F&f interface
through the serial control cable.
The RS232-2 interface is used in the case of several COA on one NE.
Use the serial interface cable to connect the RS232-2 interface of the COA numbered 1 to the
RS232-1 interface of the COA numbered 2. Then connect the RS232-2 interface of the COA
numbered 2 to the RS232-1 of the COA numbered 1. Connect the RS232-1 and RS232-2
interfaces in this way. All the COA use the RS232-1 interface of the COA numbered 1 to
communicate with the SCC unit in the subrack.
The COA has two MONITOR interfaces. The MONITOR-1 and MONITOR-2 interfaces are
the alarm output interfaces when the 61COA is used separately. The two interfaces are the same.
Table 12-13 lists the pins of the MONITOR-1 and MONITOR-2 interfaces.
the threshold.
5 5 Digital ground.
The 62COA has one RJ-45 connector, through which the 62COA is connected to the computer
for software loading. Table 12-14 lists the pins of the RJ-45 connector of the 62COA.
1 Transmitting positive
2 Transmitting negative
3 Receiving positive
4 Not defined
8 7 6 5 4 3 2 1
5 Not defined
6 Receiving negative
Table 12-15 Relation between the board feature code and output optical power for the 61COA
SS61COA01 01 14 dBm
SS61COA02 02 17 dBm
Item Specification
Item Specification
Range of input optical BA: -6 to +3 -10 to -37 –39 to –20 (2.5 Gbit/s signals
power (dBm) PA: -10 to -37 without FEC)
Mechanical Specifications
The mechanical specifications of the 61COA and N1COA are as follows:
l Board dimensions (mm): 50 (H) x 190 (D) x 240 (W)
l Weight (kg): 3.5
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the 61COA and N1COA
is 10 W.
In the normal temperature (25℃), the maximum power consumption of the 62COA is 75 W.
This chapter describes the power interface boards, such as the UPM (CAU), PIU, and PIUA.
13.1 UPM
This section describes the UPM, an uninterruptable power module, in terms of the version,
function, principle, front panel and specifications.
13.2 PIU
This section describes the PIU, a power interface unit, in terms of the version, function, principle,
front panel, configuration and specifications.
13.3 PIUA
This section describes the PIUA, a power interface unit, in terms of the version, function,
principle, front panel, configuration and specifications.
13.1 UPM
This section describes the UPM, an uninterruptable power module, in terms of the version,
function, principle, front panel and specifications.
5S
80
E4
GI
NOTE
One the T2000, the UPM is displayed as a CAU board. Thus, add a CAU on the T2000 to manage and
maintain the UPM.
The storage battery of the UPM is used with the power supply case. If the external AC current
normally charges the storage battery, the storage battery can provide power for four hours when
the external 110 V or 220 V AC current is interrupted. When the UPM provides power supply
for the OptiX OSN equipment, only one power supply case should be connected to the storage
battery group.
The OptiX OSN equipment requires two power supply cases and one storage battery group
composed of four 12 V –40 Ah storage batteries. If the equipment does not require the storage
battery, only configure one power supply case. The standard full configuration for each power
supply case requires two rectifier modules and one monitoring module.
Item UPM
Two-channel hot The converting portion of the UPM has the hot backup function of
backup two-channel AC/DC rectifier modules. In addition, the two rectifier
modules with the function of load balance can work at the same. If
one rectifier module fails, the other one immediately takes over the
entire load. As a result, the working equipment is not affected, and
the system stability is enhanced.
Hot swap function In the UPM power supply system, the AC/DC rectifier modules have
the hot swap function. When the faulty rectifier module is removed,
the other rectifier module is not affected. Thus, the system
maintainability is enhanced.
Protection function The UPM can protect the storage battery. When the mains supply is
for the storage interrupted, the power supply system can automatically switch to the
battery storage battery. Thus, the normal running of equipment is not
affected. The capacity of the storage battery module is 40 Ah.
Function of The UPM integrates the monitoring module and T2000 monitoring
monitoring module. The monitoring module monitors and controls the
parameters and states of the rectifier module, AC/DC power
distribution, and storage battery group in real time, and then reports
the parameters and states to the T2000. The storage battery
automaticallly realizes the floating charging and current limiting
management.
Band loading The band loading capacity of each rectifier module is 270 W.
capacity
When the UPM works normally, the monitoring module controls the rectifier module, battery
loop circuit and loading loop circuit, which then work according to the preset parameters and
user settings. The monitoring module also monitors their status and data.
When the mains power supply goes faulty, the battery power supply system supplies power to
the equipment. Before the mains power supply goes faulty, the battery power supply system
must be present. When the mains power supply fails and the battery starts discharging, the
monitoring module reports the alarms indicating the fault of the mains power supply. As the
battery discharges, the battery voltage decreases. When the battery voltage decreases to 45 V,
the monitoring module reports the alarm indicating the undervoltage. When the battery voltage
decreases to 43 V, the battery cuts off the connection to the equipment and protects itself.
When the mains power supply recovers, the UPM works normally.
48V+
48V-
LOAD1 LOAD2
5 6
RS232
1 2 3
Indicators
The following indicators are for the rectifier module on the left of the UPM.
The following indicators are for the monitoring module on the top panel of the UPM.
l Power supply system fault indicator (ALM), which is red when lit.
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are four interfaces on the rear panel of the UPM. Table 13-2 lists the type and usage of
these interfaces.
AC100–240 Power interface Acts as a socket for the AC mains supply and
accesses 110 V or 220 V AC power supply.
Red switch button Button Locates on the right of the panel of the rectifier
module. Press the switch button to enable or
disable the functioning of the rectifier module.
Power output Power interface Three power output interfaces are on the most
interface right of the power box. The top interface is a
battery interface, which can be connected to the
socket on the battery by using battery cables.
The bottom two are loading interfaces, which
can be connected to the OptiX OSN equipment
and supply power to the equipment.
Item Specification
Rated output current 8 A (Two loading outputs, each of which has the loading
voltage not more than 5 A)
Item Specification
Mechanical Specifications
The mechanical specifications of the UPM are as follows:
l Dimensions of the UPM (mm): 438 (H) x 240 (D) x 44 (W)
l Dimensions of a battery (mm): 197 (H) x 165 (D) x 170 (W)
13.2 PIU
This section describes the PIU, a power interface unit, in terms of the version, function, principle,
front panel, configuration and specifications.
The OptiX OSN 1500B supports the PIU and the OptiX OSN 1500A does not.
13.2.1 Version Description
The functional version of the PIU is R1.
13.2.2 Function and Feature
The PIU is used to access the power supply, and to provide the lightning protection and filtering.
13.2.3 Working Principle and Signal Flow
The PIU consists of the protecting unit, filter unit, power detecting unit and clock protecting
unit.
13.2.4 Front Panel
On the front panel of the PIU, there are indicators and power interfaces.
Function of Provides the lightning protection, and reports the alarm indicating the
lightning protection failure of the lightning protection module.
Power supply Provides one 50 W power interface for external devices, such as the
interface COA.
Power supply of the Provides –48 V ± 20% voltage for the FAN.
FAN
Clock interface Provides 75-ohm clock input and output interfaces, and protects clock
signals.
Power supply Supports the 1+1 hot backup. Any one PIU can provide power for the
backup entire subrack by itself.
RTN(+) RTN(+)
Power
detecting
unit
Filter Unit
The filter unit uses the electromagnetic interference (EMI) filter to filter the electromagnetic
interference signals and thus to keep the equipment running in a stable manner.
Protecting Unit
This unit is used to prevent the equipment from overcurrent and lightning.
PIU
O
I
POWER
NEG(-)
PWR
PWS
RTN(+)
CLK OUT
CLK IN
PIU
Indicators
A power supply indicator (POWER) is present on the front panel of the board and is green when
lit..
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
There are three power interfaces on the front panel of the PIU. Table 13-6 lists the type and
usage of the interfaces.
Mechanical Specifications
The mechanical specifications of the PIU are as follows:
l Board dimensions (mm): 108 (H) x 110 (D) x 41.5 (W)
l Weight (kg): 1.3
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the PIU is 1.5 W.
Input Voltage
The input voltage of the PIU ranges from –38.4 V to –72 V.
Fuse Tube
The main loop fuse of the PIU is 250 V-10 A-0.006 ohm.
13.3 PIUA
This section describes the PIUA, a power interface unit, in terms of the version, function,
principle, front panel, configuration and specifications.
The OptiX OSN 1500A supports the PIUA and the OptiX OSN 1500B does not.
13.3.1 Version Description
The functional version of the PIUA is R1.
13.3.2 Function and Feature
The PIUA is used to access the power supply, and to provide the lightning protection and
filtering.
13.3.3 Working Principle and Signal Flow
The PIUA consists of the power interface unit, protecting unit, filter unit, power supply detecting
unit, fan power supply unit and external power supply interface unit.
13.3.4 Front Panel
On the front panel of the PIUA, there are indicators and power interfaces.
13.3.5 Valid Slots
The PIUA can be housed in any of slots 1–11 in the subrack.
13.3.6 Technical Specifications
The technical specifications of the PIUA cover the dimensions, weight, power consumption,
input voltage and fuse tube.
Function of Provides the lightning protection, and reports the alarm indicating the
lightning protection failure of the lightning protection module.
Power supply Provides one 50 W power interface for external devices, such as the
interface COA.
Power supply Supports the 1+1 hot backup. Any one PIU can provide power for the
backup entire subrack by itself.
LED
indication
Protection Unit
This unit is used to prevent the equipment from overcurrent and lightning.
Filter Unit
The filter unit uses the electromagnetic interference (EMI) filter to filter the electromagnetic
interference signals and thus to keep the equipment running in a stable manner.
PIUA
POWER
PWS
I
O
NEG(-)
RTN(+)
PIUA
Indicators
A power supply indicator (POWER) is present on the front panel of the board and is green when
lit..
For indication of these indicators, see A Equipment and Board Alarm Indicators.
Interfaces
On the front panel of the PIUA, there are two interfaces and one switch. Table 13-8 lists the
type and usage of the interfaces and switch.
Table 13-8 Interfaces and switch on the front panel of the PIUA
Interface Interface Type Usage
PWS Output interface Outputs the 50 W power supply for the COA or HUB.
for the 50 W
power supply
Mechanical Specifications
The mechanical specifications of the PIUA are as follows:
l Board dimensions (mm): 111.8 (H) x 220 (D) x 25.4 (W)
l Weight (kg): 1.5
Power Consumption
In the normal temperature (25℃), the maximum power consumption of the PIUA is 3 W.
Input Voltage
The input voltage of the PIUA ranges from –38.4 V to –72 V.
Fuse tube
The main loop fuse of the PIU is 250 V-10 A-0.006 ohm.
14 Cables
This chapter describes the cables used for the equipment. The cables include the fiber jumpers,
power cables, alarm cables, management cables, signal cables and clock cables.
Select the fiber connector and the fiber length according to the on-site survey.
CAUTION
When selecting the fiber connector, make sure that the single-longitudinal mode or multi-
longitudinal mode optical transmitting module is connected to the single-mode fiber.
14.1.2 Connector
The OptiX OSN equipment can use various types of connectors.
l Interfaces on the front panel of boards are mostly the LC/PC optical interfaces. See Figure
14-1.
l The N2OU08 and 61COA provide the SC/PC optical interfaces.
l The "IN" interface on the externally-installed case-shaped 62COA uses the E2000/APC
connector. See Figure 14-4.
l The ODF at the client side uses the FC/PC or SC/PC optical interface. Figure 14-3 and
Figure 14-2 show the corresponding FC/PC and SC/PC optical connectors.
The axial operation instead of rotation is required to insert or remove the LC/PC optical interface.
Align the head of the fiber jumper with the optical interface with proper strength to insert the
fiber jumper into the LC/PC connector. To remove the LC/PC fiber jumper, first press the clip,
and then push fiber connector inward slightly, and pull out the connector.
Structure
Figure 14-5 shows the structure of the –48 V cabinet power cable/BGND power grounding
cable. Figure 14-6 and Figure 14-7 show the structure of the PGND protection grounding cable.
Figure 14-5 Cabinet –48 V power cable and BGND power grounding cable
1 2
3
1. Cord end terminal 2. Bare connector-OT type 3. Cable tie
Pin Assignment
None
Technical Specifications
Item Description
Fireproof level CM
Length 10 m, 20 m, 30 m
Structure
Figure 14-8 shows the structure of the equipment –48 V/–60 V power cable. Figure 14-9 shows
the structure of the PGND grounding cable.
A3
A
A2
A1
Pin Assignment
For details on the pin assignment, refer to Table 14-3.
Technical Specifications
Item Equipment –48 V/–60 V PGND grounding cable
power cable
Number of 2 1
cores
Fireproof CM CM
level
Length 15 m, 30 m 15 m, 30 m
Structure
Figure 14-10 shows the power cable that is used to connect the UPM to the OptiX OSN 1500.
B
A1 A B 1
A2 2
A3
X1 X2
Cable connector X1 Cable connector-D type-3PIN-female (two female and one male)
Number of 2
cores
Fireproof CM
class
Length 2.5 m
Structure
Figure 14-11 shows the structure of the alarm input/output cable.
Pin Assignment
Table 14-6 lists the pin assignment of the alarm input/output cable.
X1.1 Blue Twisted pair Positive for critical and major SW_INPUT 1+
alarms
Technical Specifications
Item Description
Item Description
Number of 8
cores
Fireproof class CM
Length 10 m, 20 m, 30 m
Use the RJ-45 connector to connect one end of the cable to the OAM interface of the equipment.
Use the DB25 or DB9 connector to connect the other end to a laptop, T2000 computer or modem.
Structure
Figure 14-12 shows the structure of the OAM serial port cable (DB25 connector).
1. Network interface 2. Main tag 3. Cable connector- A-A. Sectional view in B-B. Sectional view in
connector–RJ-45 DB25 male direction A direction B
Pin Assignment
Table 14-7 lists the pin assignment of the alarm input/output cable.
X1.5
Technical Specifications
Item Description
Item Description
Number of 8
cores
Fireproof class CM
Length 5000 mm
Structure
Figure 14-13 shows the structure of the Serial 1–4/F1/F&f serial port cable.
1. Network interface 2. Main tag 3. Cable connector- A-A. Sectional view in B-B. Sectional view in
connector–RJ-45 DB25 male direction A direction B
Pin Assignment
Table 14-8 lists the pin assignment of the Serial 1–4/F1/F&f cable.
Table 14-8 Pin assignment of the Serial 1–4/F1/F&f serial port cable
Connector X1 Connector X2 Relation Description
Technical Specifications
Item Description
Number of 8
cores
Fireproof class CM
Structure
Figure 14-14 shows the structure of the RS232/RS-422 serial port cable.
Pin Assignment
Table 14-9 lists the pin assignment of the RS232/RS-422 serial port cable.
Technical Specifications
Item Description
Number of cores 8
Fireproof class CM
Length 15 m
Structure
Figure 14-15 shows the structure of the ordinary telephone wire.
Pin Assignment
Table 14-10 lists the pin assignment of the ordinary telephone wire.
Technical Specifications
Item Description
Number of cores 2
Fireproof class CM
Length 15 m
Use the DB9 connectors at both ends. Connect one end to the RS232-1 of one COA and connect
the other end to the RS232-2 of another COA.
Structure
Figure 14-16 shows the structure of the COA concatenating cable.
Pin Assignment
Table 14-11 lists the pin assignment of the COA concatenating cable.
3 2 One pair
2 3
5 5 Grounding
Technical Specifications
Item Description
Fireproof class CM
Structure
Figure 14-17 shows the structure of the straight through cable.
Pin Assignment
Table 14-12 lists the pin assignment of the straight through cable.
Technical Specifications
Item Description
Number of cores 8
Fireproof class CM
Length 5 m, 10 m, 20 m, 30 m
Structure
Figure 14-18 shows the structure of the crossover cable.
Pin Assignment
Table 14-13 lists the pin assignment of the crossover cable.
Technical Specifications
Item Description
Number of cores 8
Fireproof class CM
Length 5 m, 30 m
The N x 64 kbit/s cable is connected to the DB28 connector of the DM12 to access one channel
of N x 64 kbit/s services.
Structure
Figure 14-19 shows the structure of the 75-ohm 8 x E1 cable.
Pin Assignment
Table 14-14 lists the pin assignment of the 75-ohm 8 x E1 cable.
38 Ring 1 R1 34 Ring 1 R5
23 Tip 19 Tip
37 Ring 3 R2 33 Ring 3 R6
22 Tip 18 Tip
36 Ring 5 R3 32 Ring 5 R7
21 Tip 17 Tip
35 Ring 7 R4 31 Ring 7 R8
20 Tip 16 Tip
15 Ring 2 T1 11 Ring 2 T5
30 Tip 26 Tip
14 Ring 4 T2 10 Ring 4 T6
29 Tip 25 Tip
13 Ring 6 T3 9 Ring 6 T7
28 Tip 24 Tip
12 Ring 8 T4 8 Ring 8 T8
27 Tip 7 Tip
Shell External braid shield layer Shell External braid shield layer
Technical Specifications
Item Description
Fireproof class CM
Number of cores 8 x E1
Length 3 m, 10 m, 15 m, 20 m, 25 m, 30 m, 40 m
CAUTION
The pin assignment table for the E1 cable is placed in the same packing case with the cable. Do
not discard it before installation.
Use the 2mmHM connector at one end to connect the cable to the 75-ohm E1 electrical interface
board. Use a connector to connect the other end to the DDF. The connector should be made
according to the on-site requirements. Each cable can transmit 16 channels of E1 signals.
Structure
Figure 14-20 shows the structure of the 75-ohm 16 x E1 cable.
Pin Assignment
Table 14-15 lists the pin assignment of the 75-ohm 16 x E1 cable.
Technical Specifications
Item Description
Fireproof class CM
Number of cores 16 x E1
Item Description
Length 10 m, 15 m, 20 m, 25 m, 30 m
CAUTION
The pin assignment table for the E1 cable is placed in the same packing case with the cable. Do
not discard it before installation.
Structure
Figure 14-21 shows the structure of the 120-ohm 8 x E1 cable.
Pin Assignment
Table 14-16 lists the pin assignment of the 120-ohm 8 x E1 cable.
29 White 22 White
27 White 20 White
24 Red 17 Red
Shell External braid shield layer Shell External braid shield layer
Technical Specifications
Item Description
Number of cores 16
Fireproof class CM
Item Description
Length 10 m, 15 m, 20 m, 30 m, 40 m
Use the 2mmHM connector at one end to connect the cable to the 120-ohm E1 electrical interface
board, L12S or PL1B. Use a connector to connect the other end to the DDF. The connector
should be made according to the on-site requirements. Each cable can transmit 16 channels of
E1 signals.
Structure
Figure 14-22 shows the structure of the 120-ohm 16 x E1 cable.
W2
X
W1
2
Pin Assignment
Table 14-17 lists the pin assignment of the 120-ohm 16 x E1 cable.
Technical Specifications
Item Description
Number of 32
cores
Inner 0.5 mm
conductor
diameter
Fireproof class CM
Length 10 m, 15 m, 20 m, 25 m, 30 m
Structure
Figure 14-23 shows the structure of the E3/T3/STM-1 cable.
Pin Assignment
None
Technical Specifications
Item Description
Item Description
Length: 10 m, 15 m, 20 m, 30 m
Length: 15 m, 20 m, 25 m, 30 m, 40 m
Length: 15 m, 20 m, 25 m, 30 m, 130 m
Length: 30 cm
Fireproof CM
class
l See the section that describes the 75-ohm 8 x E1 cable for details on the structure, pin
assignment and technical specifications of the 75-ohm framed E1 cable.
l See the section that describes the 120-ohm 8 x E1 cable for details on the structure, pin
assignment and technical specifications of the 120-ohm framed E1 cable.
5 NC - -
According to the protocols for the N x 64 kbit/s signals, the N x 64 kbit/s cables are classified
into the following ten types.
Pos.28
A W B
Pos.1
A B
C D
E F
H J
X1 X2 M
K
P
N
L
R
S T
U V
W X
Y Z
AA BB
CC DD
EE FF
HH JJ
KK LL
MM NN
Table 14-19 lists the pin assignment of the V.35 DCE cable.
19 P Twisted pair
20 S
1 R Twisted pair
2 T
15 V Twisted pair
16 X
3 Y Twisted pair
4 AA
17 U Twisted pair
18 W
11 F -
22 J -
23 C -
13 D -
25 H -
27 E -
21 B -
Item Description
Cable type Twisted pair cable-100 ohms-0.38 mm-28AWG-5 pairs and 8 core-
PANTONE 296U-exclusively used by OEM
Length 3m
Pos.28
A W B
Pos.1
B A
X1 X2 F
D
J
E
L N K M
C
H
R T P S
V X U W
Z BB Y AA
DD FF CC EE
JJ LL HH KK
NN MM
Table 14-20 lists the pin assignment of the V.35 DTE cable.
1 P Twisted pair
2 S
19 R Twisted pair
20 T
17 V Twisted pair
18 X
3 Y Twisted pair
4 AA
15 U Twisted pair
16 W
11 F -
22 J -
13 C -
23 D -
27 H -
25 E -
21 B -
Item Description
Cable type Twisted pair cable-100 ohms-0.38 mm-28AWG-5 pairs and 8 core-
PANTONE 296U-exclusively used by OEM
Core 0.32 mm
diameter
Length 3m
A
W B
Pos.28
Pos.1 X1
X2
Table 14-21 lists the pin assignment of the V.24 DCE cable.
19 2 Twisted pair
1 3
23 4 Twisted pair
13 5
25 20 Twisted pair
27 6
11 8 Twisted pair
22 18
3 15 Twisted pair
17 24
15 17 -
21 1 Single
Cable type Twisted pair cable-100 ohms-0.38 mm-28AWG-5 pairs and 8 core-
PANTONE 296U-exclusively used by OEM
Length 3m
A
W B
Pos.28
Pos.25 X1
X2
Table 14-23 lists the pin assignment of the V.24 DTE cable.
1 2 Twisted pair
19 3
13 4 Twisted pair
23 5
27 20 Twisted pair
25 6
11 8 Twisted pair
22 18
3 15 Twisted pair
15 24
17 17 -
21 1 Single
Item Description
Item Description
Cable type Twisted pair cable-100 ohms-0.38 mm-28AWG-5 pairs and 8 core-
PANTONE 296U-exclusively used by OEM
Core 0.32 mm
diameter
Length 3m
1 2 3
Pos.15
Pos.1
W B
A
Pos.28
Pos.1
X2 X1
Table 14-25 lists the pin assignment of the X.21 DCE cable.
13 5 Twisted pair
14 12
23 3 Twisted pair
24 10
19 2 Twisted pair
20 9
1 4 Twisted pair
2 11
15 6 Twisted pair
16 13
21 1 –
Cable type Twisted pair cable-100 ohms-0.38 mm-28AWG-5 pairs and 8 core-
PANTONE 296U-exclusively used by OEM
Core 0.32 mm
diameter
Length 3m
W
B
A
Pos.28
Pos.15
X2 X1
Table 14-27 lists the pin assignment of the X.21 DTE cable.
13 3 Twisted pair
14 10
23 5 Twisted pair
24 12
19 4 Twisted pair
20 11
1 2 Pair
2 9
15 6 Twisted pair
16 13
17 6 Twisted pair
18 13
21 1 –
Cable type Twisted pair cable-100 ohms-0.38 mm-28AWG-5 pairs and 8 core-
PANTONE 296U-exclusively used by OEM
Length 3m
W
B
A
Pos.28
Pos.15
X2 X1
Table 14-29 lists the pin assignment of the RS449 DCE cable.
27 11 Twisted pair
28 29
25 12 Twisted pair
26 30
13 9 Twisted pair
14 27
23 7 Twisted pair
24 25
11 13 Twisted pair
12 31
19 4 Twisted pair
20 22
1 6 Twisted pair
2 24
15 8 Twisted pair
16 26
17 17 Twisted pair
18 35
3 5 Twisted pair
4 23
22 10 –
21 1 –
Number of cores 26
Length 3m
1 2 3
Pos.37
Pos.28
A
W B
Pos.1 X1
X2 Pos.1
Table 14-31 lists the pin assignment of the RS449 DTE cable.
27 12 Twisted pair
28 30
25 11 Twisted pair
26 29
13 7 Twisted pair
14 25
23 9 Twisted pair
24 27
11 13 Twisted pair
12 31
19 6 Twisted pair
20 24
1 4 Twisted pair
2 22
15 17 Twisted pair
16 35
17 8 Twisted pair
18 26
3 5 Twisted pair
4 23
22 10 -
21 1 -
Item Description
Number of 26
cores
Core 0.32 mm
diameter
1 2 3
Pos.25
Pos.1
A W B
X1 Pos.28
Pos.1 X2
Table 14-33 lists the pin assignment of the RS530 DCE cable.
28 22 Twisted pair
27 6
26 23 Twisted pair
25 20
24 19 Twisted pair
23 4
22 18 Single
21 1 Single
20 14 Twisted pair
19 2
18 11 Twisted pair
17 24
16 9 Twisted pair
15 17
14 13 Twisted pair
13 5
12 10 Twisted pair
11 8
4 12 Twisted pair
3 15
2 16 Twisted pair
1 3
Number of 26
cores
Core 0.32 mm
diameter
Length 3m
A W B
Pos.28
X1
Pos.25 X2
Table 14-35 lists the pin assignment of the RS530 DTE cable.
27 20 Twisted pair
28 23
25 6 Twisted pair
26 22
13 4 Twisted pair
14 19
23 5 Twisted pair
24 13
11 8 Twisted pair
12 10
19 3 Twisted pair
20 16
1 2 Twisted pair
2 14
15 24 Twisted pair
16 11
17 17 Twisted pair
18 9
3 15 Twisted pair
4 12
22 18 –
21 1 –
Number of 26
cores
Core 0.32 mm
diameter
Length 3m
Structure
Figure 14-34 and Figure 14-35 show the structure of the 75-ohm clock cable and the 120-ohm
clock cable respectively.
1. Tag 1 (R) and Tag2 (T) 2. Communication cable 3. Main tag 4. Network interface connector-RJ-45
Pin Assignment
Table 14-37 lists the pin assignment of the 120-ohm clock cable.
X1 W Remark
X1.1 Blue W1
X1.2 White
X1.4 Orange W2
X1.5 White
Technical Specifications
Item Description
Item Description
Length: 10 m, 15 m, 20 m, 30 m
Length: 5 m, 10 m, 20 m, 30 m, 40 m, 50 m, 70 m, 100 m
Structure
Figure 14-36 and Figure 14-37 show the structure of the one-channel clock transfer cable and
two-channel clock transfer cable respectively.
Figure 14-36 Structure of the one-channel clock transfer cable (75 ohms to 120 ohms)
Figure 14-37 Structure of the two-channel clock transfer cable (75 ohms to 120 ohms)
Pin Assignment
Table 14-38 lists the pin assignment of the two-channel clock transfer cable (75 ohms to 120
ohms).
Table 14-38 Pin assignment of the two-channel clock transfer cable (75 ohms to 120 ohms)
Connector 75-ohm Cable Color 120-ohm Cable
X1 Core Blue W3
X2 Core Blue W4
Technical Specifications
Item Description
Length: 30 m
Length: 30 m
This chapter describes the equipment and board alarm indicators for the OptiX OSN equipment.
Indicator Indication
Normal power supply indicator: Power When it is lit, it indicates that the power is supplied
(green) to the equipment.
Critical alarm indicator: Critical (red) When it is lit, it indicates that critical alarms are
generated in the equipment.
Major alarm indicator: Major (orange) When it is lit, it indicates that major alarms are
generated in the equipment.
Minor alarm indicator: Minor (yellow) When it is lit, it indicates that minor alarms are
generated in the equipment.
Lit (green) The service is in the activating state and the board is
working.
Circularly lit for 100 ms and unlit for The board software or FPGA is being loaded to the
100 ms (green) FLASH.
Circularly lit for 300 ms and unlit for The board software is being initialized and is in the
300 ms (green) BIOS boot state.
Lit (green) l The clock is working in the free-run mode and the
system clock priority list is not set. By default, the
system clock priority list contains only the internal
source.
l The clock is working in the tracing mode and
tracing the clock source rather than the internal
source in the priority list.
Lit (red) The system clock priority list is set. Except the
internal clock source, all clock sources are lost. The
clock is working in the hold-over or free-run mode.
Ethernet Indicator
Indicator Status Indication
Description
Green running Flash once every two The COA is running normally.
indicator (RUN) seconds (green)
Rectifier ALM Lit (red) The rectifier module fails. Normally, it is unlit.
module
Vout Lit (green) The output of the rectifier module is normal.
Monitorin RUN Flashes (green) The entire power supply system is normal.
g module
ALM Lit (red) The entire power supply system becomes
faulty. Normally, it is unlit.
B Labels
This chapter describes various labels for the OptiX OSN equipment, including the safety labels,
optical module labels, and cable labels.
LASER
Laser safety class The label suggests the class of
RADIATION the laser source.
DO NOT VIEW DIRECTLY
CLASS 1 WITH OPTICAL
INSTRUMENTS
LASER CLASS 1M
LASER
PRODUCT PRODUCT
certification.
received, including interference that may cause
undesired operation.
N14036
华为技术有限公司 中国制作
HUAWEI TECHNOLOGIES CO.,LTD. MADE IN CHINA
N14036
华为技术有限公司 中国制作
HUAWEI TECHNOLOGIES CO.,LTD. MADE IN CHINA
N14036
华为技术有限公司 中国制作
HUAWEI TECHNOLOGIES CO.,LTD. MADE IN CHINA
N14036
华为技术有限公司 中国制作
HUAWEI TECHNOLOGIES CO.,LTD. MADE IN CHINA
合格证/QUALIFICATION CARD
Qualification card label The equipment is qualified.
HUAWEI
华为技术有限公司 中国制作
HUAWEI TECHNOLOGIES CO.,LTD. MADE IN CHINA
合格证/QUALIFICATION CARD
HUAWEI
华为技术有限公司 中国制作
HUAWEI TECHNOLOGIES CO.,LTD. MADE IN CHINA
N14036
华为技术有限公司 中国制作
HUAWEI TECHNOLOGIES CO.,LTD. MADE IN CHINA
严禁在风扇高速旋转时接触叶片
ATTENTION 警告
CLEAN PERIODICALLY 定期清洗
合格证/QUALIFICATION CARD
HUAWEI
华为技术有限公司 中国制作
HUAWEI TECHNOLOGIES CO.,LTD. MADE IN CHINA
N14036
华为技术有限公司 中国制作
HUAWEI TECHNOLOGIES CO.,LTD. MADE IN CHINA
严禁在风扇高速旋转时接触叶片
ATTENTION 警告
CLEAN PERIODICALLY 定期清洗
SL16
CLASS 1
LASER
PRODUCT
! APD
Receiver
MAX:-9dBm
BA2
LASER
RADIATION
As shown in Table B-2, different types of optical module have different codes.
This chapter describes the power consumption and weight of each board for the OptiX OSN
1500.
Table C-1 Power consumption and weight of each board for the OptiX OSN 1500
Board Consumpti Weight (kg) Board Consumpt Weight (kg)
on (W) ion (W)
N1DXA 10 0.8 - - -
Table D-1 Board versions that are compatible with the OptiX OSN products
Product OptiX OptiX OptiX OptiX OptiX OptiX OptiX
OSN OSN OSN OSN OSN 2500 OSN OSN
7500 3500 3500T 2500 REG 1500A 1500B
N1SL64 Y Y Y N Y N N
N2SL64 N Y Y N Y N N
T2SL64 Y N N N N N N
T2SL64A Y N N N N N N
N1SF64 Y Y Y N Y N N
N1SLD64 Y Y Y N N N N
N1SL16 Y Y Y Y N Y Y
N2SL16 Y Y Y Y Y Y Y
N3SL16 Y Y Y Y Y Y Y
N1SL16A Y Y Y Y N Y Y
N2SL16A Y Y Y Y N Y Y
N3SL16A Y Y Y Y Y Y Y
N1SLD16 N Y Y N N N N
N2SLQ16 Y Y Y N N N N
N1SF16 Y Y Y Y Y Y Y
N1SL4 Y Y Y Y N Y Y
N2SL4 Y Y Y Y N Y Y
R1SL4 N N N Y N Y Y
N1SLQ4 Y Y Y Y N Y Y
N2SLQ4 Y Y Y Y N Y Y
N1SLD4 Y Y Y Y N Y Y
N2SLD4 Y Y Y Y N Y Y
R1SLD4 N N N Y N Y Y
N1SLT1 Y Y Y Y N Y Y
N1SLQ1 Y Y Y Y N Y Y
N2SLQ1 Y Y Y Y N Y Y
R1SLQ1 N N N Y N Y Y
N1SL1 Y Y Y Y N Y Y
N2SL1 Y Y Y Y N Y Y
R1SL1 N N N Y N Y Y
N1SLH1 Y Y Y N N N N
N1SEP1 Y Y Y Y N Y Y
N2SLO1 Y Y Y Y N Y Y
R1PL1 N N N N N Y Y
R1PD1 N N N Y N Y Y
R2PD1 N N N Y N Y Y
N1PQ1 Y Y Y Y N N Y
N2PQ1 Y Y Y Y N N Y
N1PQM Y Y Y Y N N Y
N1PL3 Y Y Y Y N N Y
N2PL3 Y Y Y Y N N Y
N1PL3A Y Y Y Y N Y Y
N2PL3A Y Y Y Y N Y Y
N1PD3 Y Y Y Y N N Y
N2PD3 Y Y Y Y N N Y
N2PQ3 Y Y Y Y N N Y
N1DX1 Y Y Y Y N N Y
N1DXA Y Y Y Y N Y Y
N1SPQ4 N Y Y Y N N Y
N2SPQ4 Y Y Y Y N N Y
R1EFT4 N N N Y N Y Y
N1EFT8 Y Y Y Y N Y Y
N1EFT8A Y Y Y Y N Y Y
N1EGT2 Y Y Y Y N Y Y
N1EFS0 N Y Y Y N N Y
N2EFS0 Y Y Y Y N N Y
N4EFS0 Y Y Y Y N N Y
N1EFS4 Y Y Y Y N Y Y
N2EFS4 Y Y Y Y N Y Y
N1EGS2 N Y Y Y N Y Y
N2EGS2 Y Y Y Y N Y Y
N1EMS4 Y Y Y Y N Y Y
N1EGS4 Y Y Y Y N Y Y
N2EGR2 Y Y Y Y N Y Y
N1EMR0 N Y Y Y N Y Y
N2EMR0 Y Y Y Y N Y Y
N1ADL4 Y Y Y Y N Y Y
N1ADQ1 Y Y Y Y N Y Y
N1IDL4 Y Y Y Y N Y Y
N1IDQ1 Y Y Y Y N Y Y
N1MST4 Y Y Y Y N Y Y
N1EU08 Y Y Y Y N N Y
N1OU08 Y Y Y Y N N Y
N2OU08 Y Y Y Y N N Y
N1D75S Y Y Y Y N N Y
N1MU04 Y Y Y Y N N Y
N1D34S Y Y Y Y N N Y
N1C34S Y Y Y Y N N Y
N1EU04 N Y Y Y N N Y
N1D12S Y Y Y Y N N Y
N1D12B Y Y Y Y N N Y
R1L12S N N N N N Y N
R1L75S N N N N N Y N
N1EFF8 Y Y Y Y N N Y
N1ETF8 Y Y Y Y N N Y
N1ETS8 Y Y Y Y N N Y
N1DM12 Y Y Y Y N N Y
N1TSB4 N Y Y Y N N Y
N1TSB8 Y Y Y Y N N Y
Q2CXL1 N N N Y N Y Y
Q2CXL4 N N N Y N Y Y
Q2CXL16 N N N Y N Y Y
T1GXCSA Y N N N N N N
N1GXCSA N Y Y N N N N
T1EXCSA Y N N N N N N
N1EXCSA N Y Y N N N N
T2UXCSA Y N N N N N N
N1UXCSA N Y Y N N N N
N1UXCSB N Y Y N N N N
T1SXCSA Y N N N N N N
T2SXCSA Y N N N N N N
N1SXCSA N Y Y N N N N
N1SXCSB N Y Y N N N N
T1IXCSA Y N N N N N N
N1IXCSA N Y Y N N N N
N1IXCSB N Y Y N N N N
N1XCE N Y Y N N N N
N1GSCC N Y N N N N N
N2GSCC Y N N N N N N
N3GSCC Y Y Y N N N N
CRG N N N N Y N N
T1EOW Y N N N N N N
R1EOW N N N N N Y Y
T1AUX Y N N N N N N
N1AUX N Y Y N N N N
R1AUX N N N N N Y Y
R2AUX N N N N N Y Y
R1AMU N N N N N Y Y
Q1SAP N N N Y Y N N
Q2SAP N N N Y Y N N
Q1SEI N N N Y Y N N
N1FAN N Y Y Y Y N N
R1FAN N N N N N Y Y
N1FANA Y Y Y N N N N
TN11CMR Y Y Y Y N Y Y
2
TN11CMR Y Y Y Y N Y Y
4
TN11MR2 Y Y Y Y N Y Y
TN11MR4 Y Y Y Y N Y Y
N1MR2A Y Y Y Y N Y Y
N1MR2B N N N Y N Y Y
N1MR2C Y Y Y Y N N Y
N1LWX Y Y Y Y N Y Y
TN11OBU Y Y Y Y Y Y Y
1
N1FIB Y Y Y Y Y Y Y
N1BA2 Y Y Y Y Y Y Y
N1BPA Y Y Y Y Y Y Y
61COA Y Y Y Y Y Y Y
62COA Y Y Y Y Y Y Y
N1COA Y Y Y Y Y Y Y
N1DCU Y Y Y N Y N N
N2DCU Y Y Y N Y N N
UPM N N N Y Y Y Y
T1PIU Y N N N N N N
N1PIU N Y Y N N N N
Q1PIU N N N Y Y N N
R1PIU N N N N N Y Y
R1PIUA N N N N N Y N
E Board Loopbacks
The SDH, PDH, data processing board for the OptiX OSN equipment support various types of
loopbacks.
In the case of the SDH boards for the OptiX OSN equipment, Table E-1 lists the capability of
supporting the loopbacks.
Table E-1 Loopbacks of the SDH boards for the OptiX OSN equipment
Board Port Inloop Port Outloop VC-4 Inloop VC-4 Outloop
In the case of the PDH boards for the OptiX OSN equipment, Table E-2 lists the capability of
supporting the loopbacks.
Table E-2 Loopbacks of the PDH boards for the OptiX OSN equipment
Board Port Inloop Port Outloop
In the case of the Ethernet boards for the OptiX OSN equipment, Table E-3 lists the capability
of supporting the loopbacks.
Table E-3 Loopbacks of the Ethernet boards for the OptiX OSN equipment
Board MAC MAC PHY PHY VC-4 VC-3
Layer Layer Layer Layer Inloop, Inloop,
Outloo Inloop Outloop Inloop VC-4 VC-3
p Outloop Outloop
In the case of the ATM/IMA boards for the OptiX OSN equipment, Table E-3 lists the capability
of supporting the loopbacks.
Table E-4 Loopbacks of the Ethernet boards for the OptiX OSN equipment
Board External Port External Port Internal Port Internal Port
Outloop Inloop Outloop Inloop
The T2000 can be used to configure various parameters for SDH boards, PDH boards, data
processing boards, and cross-connect and timing boards.
J0 Byte
J0 is the section trace byte, the J0 are transmitted in a successive manner. Hence, the receive
end learns that it is in the continuous connection with the specified transmit end. The value of
J1 is "0" by default.
J1 Byte
The J1 byte is the path tracing byte. The transmit end uses the J1 byte to transmit the higher
order access point identifiers in a successive manner. Hence, the receive end learns that it is in
the continuous connection with the specified transmit end in this channel. When the receive end
detects the J1 mismatch, the corresponding VC-4 channel generates an HP_TIM alarm.
Set the J1 byte as " HuaWei SBS " for the SL01 and as "0" for all other boards.
NOTE
By default, the J1 byte is " HuaWei SBS ". One space is present before "HuaWei SBS" and five behind.
C2 Byte
The C2 byte is the signal label byte, which is used to indicate the multiplexing structure of the
VC frames and the payload property. The received C2 should be the same as the transmitted C2.
If C2 mismatch occurs, the corresponding VC-4 channel generates the HP_SLM alarm.
Table F-1 lists the mapping relation between the service type and setting of the C2.
Table F-1 Mapping relation between the service type and setting of the C2
TUG structure 02
Unequipped 00
J1 Byte
The J1 byte is the path tracing byte. The transmit end transmits the higher order access point
identifiers in a successive manner. Hence, the receive end learns that it is in the continuous
connection with the specified transmit end. When the receive end detects the J1 mismatch, the
corresponding VC-4 channel generates an HP_TIM alarm.
NOTE
C2 Byte
The C2 byte is the signal label byte, which is used to indicate the multiplexing structure of the
VC frames and the payload property. The received C2 should be the same as the transmitted C2.
If C2 mismatch occurs, the corresponding VC-4 channel generates the HP_SLM alarm.
Table F-2 lists the mapping relation between the service type and setting of the C2.
Table F-2 Mapping relation between the service type and setting of the C2
TUG structure 02
Unequipped 00
J2 Byte
The J2 is a VC-12 channel tracing byte. The transmit end uses the J2 byte to transmit the lower
order access point identifiers in a successive manner. Hence, the receive end learns that it is in
the continuous connection to the specified transmit end in this channel.
V5 Byte
The V5 is a channel status and signal identification byte. This byte is used to detect bit error and
indicate remote faults or defect in lower order channel. The LP_REI and LP_RFI alarms are
generated accordingly. Table F-3 lists the mapping relation between the service type and setting
of the V5.
Table F-3 Mapping relation between the service type and setting of the V5
Asynchronization 02
Byte synchronization 04
HDLC/PPP mapping 0A
Unequipped or Supervisory-Unequipped 00
Equipping Indication
When a service channel just carries the service and does not process the service, select
Unequipped or Supervisory-Unequipped.
When a service channel carries the service and also processes the service, select Equipped-
Unspecific Payload.
Tributary Loopback
The tributary loopback function is used to locate faults in the service channels.
The tributary loopback is also a diagnosis function. When the tributary loopback is performed,
related services are interrupted.
J1 Byte
The J1 byte is the path tracing byte. The transmit end transmits the J1 byte in a successive manner.
Hence, the receive end learns that it is in the continuous connection to the specified transmit end
in this path.
When detecting the J1 mismatch, the receive end generates the LP_TIM_VC3 alarm in the VC-3
path and the HP_TIM_VC4 in the VC-4 path.
If the J1 byte is of the default value, "0", these alarms are not reported.
NOTE
l For the N1EFS4 and MST4, the J1 byte is " HuaWei SBS " by default. For other boards, the J1
byte is "0".
l For the EMS4 and EGS4, set the J1 byte as " HuaWei SBS ".
C2 Byte
The C2 byte is the signal label byte, which is used to indicate the multiplexing structure of the
VC frames and the payload property. The received C2 should be the same as the transmitted C2.
In case of the C2 mismatch, the LP_SLM_VC3 alarm is generated in the VC-3 path and the
HP_SLM_VC4 alarm is generated in the VC-4 path.
J2 Byte
The J2 is a VC-12 path tracing byte. The transmit end uses the J2 byte to transmit the lower
order access point identifiers in a successive manner. Hence, the receive end learns that it is in
the continuous connection to the specified transmit end in this path.
In case of the J2 mismatch, the LP_TIM_VC12 alarm is generated in the VC-12 path.
If the J1 byte is of the default value, "0", these alarms are not reported.
V5 Byte
The V5 is a path status and signal identification byte. This byte is used to detect bit error and
indicate remote faults or defect in lower order path. The LP_REI and LP_RFI alarms are
generated accordingly.
When detecting the V5 mismatch, the receive end generates the LP_SLM_VC12 in the VC-12
path.
Table F-4 lists the mapping relation between the service type and setting of the V5.
Table F-4 Mapping relation between the service type and setting of the V5
Asynchronization 02
Byte synchronization 04
HDLC/PPP mapping 0A
Unequipped or Supervisory-Unequipped 00
Working Mode
Generally, the interconnected equipment should work in the same fixed working mode. If the
working modes at both ends mismatch, packets may be lost or the rate becomes less. In case of
large volume of data, services may be even interrupted.
For EGT2, EGS2 and EGS4, set the working mode to auto-negotiation or 1000M full-duplex.
For the EFT8 and EFT8A, set the working mode to auto-negotiation or 10/100M full-duplex.
For the EFS4 and EFS0, set the working mode to auto-negotiation, 10M half-duplex, 10M full-
duplex, 100M half full-duplex or 100M full-duplex.
For the GE ports of the EMS4, EMR0 and EGR2, set the working mode to auto-negotiation or
1000M full-duplex. For the FE ports, set the working mode to auto-negotiation, 10M half-duplex,
10M full-duplex, 100M half full-duplex or 100M full-duplex.
LCAS State
Enable or disable the LCAS.
Mapping Protocol
The mapping protocols of the interconnected equipment should be the same.
For the EGT2, EFT8, EFT8A, EFF8 and ETF8, set the mapping protocol to HDLC, LAPS and
GFP-F. By default, the mapping protocol is GFP-F.
Choose the GFP-F mapping protocol for the EGS2, EFS4 and EFS0.
For the EMR0 and EGR2, set the mapping protocol to LAPS and GFP. By default, the mapping
protocol is GFP.
TAG Flag
The TAG flag is used to identify the type of packets. The TAG flag can be set to TAG Aware,
Access and Hybrid.
1. When the TAG flag is set as the TAG Aware for a port, the port transparently transmits the
packets with a TAG and discards the packets without a TAG.
2. When the TAG flag is set as Access for a port, the port adds a TAG to the received packets
that does not contain any TAG according to the VLAN ID of the port, and discards the
packets that contain a TAG.
3. When the TAG flag is set as Hybrid for a port, the port can process the packets with a TAG
or without any TAG. In this case, the port adds a TAG to the received packets that does
not contain any TAG according to the VLAN ID of the port.
VLAN ID
Set the default VLAN ID of the local port.
Port Type
For the boards that support the MPLS function, set the port type to P or PE. Provider edge (PE)
indicates the edge port of the service provider and provider (P) indicates the core network port
of the service provider. When configuring the EVPL and EVPLAN services, set this parameter.
Set the external port to PE and the internal port to P.
Port Attribute
For boards that support the QinQ function, set the port attribute to UNI, NNI, U-NNI, S-Aware
or C-Aware.
Port Type
The port types include NNI and UNI (default).
Flow Type
The flow type should meet the requirements of the port.
Service Type
There are four service types, CBR, rt-VBR, nrt-VBR, and UBR.
Set the following parameters when the external clock is configured and the SSM is enabled.
l Reference clock source
l Reference clock source level
l Building integrated timing supply (BITS) type
l S1 byte
l Threshold for selecting the clock in case of the switching protection
G Glossary
1:N protection A 1:N protection architecture has N normal traffic signals, N working
SNCs/trails and one protection SNC/trail. It may have one extra traffic
signal.
1+1 protection A 1+1 protection architecture has one normal traffic signal, one working
SNC/trail, one protection SNC/trail and a permanent bridge.
100Base-TX Physical Layer specification for a 100 Mbit/s CSMA/CD local area
network over two pairs of Category 5 unshielded twisted-pair (UTP) or
shielded twisted-pair (STP) wire.
19-inch cabinet A cabinet which is 19 inches in width and 600mm in depth, compliant
with the standards of the IEC297.
Administrator A user who has authority to access all the Management Domains of the
EML Core product. He has access to the whole network and to all the
management functionalities.
Back up A method to copy the important data into a backing storage in case that
the original is damaged or corrupted.
Backplane A PCB circuit board in the subrack, which is connected with all the
boards in position.
Board Version A function that enables a board supporting several board IDs. Generally,
Replacement a board of an old version is used to the NE also of an old version, which
Function does not support the board of a new version. When a board of a new
version is used to replace a board of an old version, the former should
work with the ID of the board of the old version. The board of a new
version works on the NE of a new version with the ID of the board of
new version. In this way, the board of the new version has several board
IDs.
Bridge The action of transmitting identical traffic (SPE contents) on both the
working and protection channels.
Broadcast The act of sending a frame addressed to all stations on the network
CBR Constant Bit Rate. The Constant Bit Rate service category is used by
connections that request a static amount of bandwidth that is
continuously available during the connection lifetime. This amount of
bandwidth is characterized by a peak cell Rate (PCR) value.
CDVT Cell Delay Variation Tolerance. Information sent in the forward and
backward direction to determine the upper bound of the tolerance
admitted for the time interval between cells pertaining to a given cell
flow. The backward CDVT values included in the IAM and MOD shall
be interpreted as maximum acceptable values for the cell flow in the
backward direction.
Coded Mark This is the STS-3 line code. This is a two level non-return to zero code.
Inversion A binary 1 is coded by either of the amplitude levels, +A or -A, for one
full unit time interval (T) in such a way that the level alternates for
successive binary ones. For a binary zero there is always a positive
transition (-A to +A) at the mid point of the binary unit interval (T/2).
Configuration data The data that configures the NE hardware for coordination between this
NE and other NEs in the entire network, and for operation of specified
services. Configuration data is the instruction file of NEs, and it is a key
element to ensure that the network runs efficiently. The typical
configuration data includes board configuration, clock configuration
and protection relationship.
Convergence The process of developing a model of the echo path which will be used
in the echo estimator to produce the estimate of the circuit echo.
Drop The port on a network element where the service to an end customer
may be connected, e.g., a tributary card on a SONET ADM. For
example, a drop for a DS1 customer service may be provided by a VT1.5
card terminating a VT1.5 trail.
Dual-Fed A description of a ring that has entry nodes that add traffic to the ring
via the bridging function.
EDFA Erbium-Doped Fiber Amplifier. The optical amplifier that its fiber
doped with the rare earth element erbium, which can amplify at 1530 to
1610 nm when the optical amplifier is pumped by an external light
source.
Ejector lever A component at the two ends of the front panel of a board, which is used
for inserting or removing the board.
ESCON Enterprise System Connection. A path protocol which connects the host
with various control units in an storage system. It is a serial bit stream
transmission protocol. The transmission rate is 200 Mbit/s.
ESD jack Electrostatic discharge jack. A hole in the cabinet or subrack, which
connect the subrack or cabinet to the insertion of ESD wrist strap.
Ethernet A data link level protocol comprising the OSI model's bottom two layers.
It is a broadcast networking technology that can use several different
physical media, including twisted pair cable and coaxial cable. Ethernet
usually uses CSMA/CD. TCP/IP is commonly used with Ethernet
networks.
EVPL Ethernet Virtual Private Line. An EVPL service is a service that is both
a line service and a virtual private service.
Fan tray assembly A module which contains fans used for heat dissipation.
Fiber connector A device mounted on the end of a fiber-optic cable, light source,
receiver, or housing that mates to a similar device to couple light into
and out of optical fibers. A connector joins two fiber ends, or one fiber
end and a light source or detector.
Fiber jumper The fiber which is used to connect the subrack with the ODF.
Frame A cyclic set of consecutive time slots in which the relative position of
each time slot can be identified.
Free-run mode An operating condition of a clock, the output signal of which is strongly
influenced by the oscillating element and not controlled by servo phase-
locking techniques. In this mode the clock has never had a network
reference input, or the clock has lost external reference and has no access
to stored data, that could be acquired from a previously connected
external reference. Free-run begins when the clock output no longer
reflects the influence of a connected external reference, or transition
from it. Free-run terminates when the clock output has achieved lock to
an external reference.
Full duplex Pertaining to both parties that can send and receive data at the same time
on the communication link.
Gain The ratio between the optical power from the input optical interface of
the optical amplifier and the optical power from the output optical
interface of the jumper fiber, which expressed in dB.
Guide rail A groove in the subrack, which ensures the correct connection of a board
to the backplane.
Half duplex Pertaining to, both parties that only one party can send data, while the
other party can only receive data on the communication link.
IMA frame The IMA frame is used as the unit of control in the IMA protocol. It is
a logical frame defined as M consecutive cells, numbered 0 to M-l,
transmitted on each of the N links in an IMA group.
Interface board The area for the interface boards on the subrack.
area
Laser The device that generates the directional light covering a narrow range
of wavelengths. Laser light is more coherent than ordinary light.
Semiconductor diode lasers are the used light source in fiber-optic
system.
Loopback The fault of each path on the optical fiber can be located by setting
loopback for each path of the line. There are three kinds of loopback
modes: No loopback, Outloop, Inloop.
Lower subrack The subrack close to the bottom of the cabinet when a cabinet contains
several subracks.
MAC Media Access Control. The data link sublayer that is responsible for
transferring data to and from the Physical Layer.
Mean launched The average power of a pseudo-random data sequence coupled into the
power fiber by the transmitter.
Mounting ear A component on the side of a subrack, which is used to install the subrack
in a cabinet.
MSP The MSP function provides capability for switching a signal between
and including two MST functions, from a working to a protection
channel.
Multiplex section A function provides capability for switching a signal between and
protection including two MST functions, from a working to a protection channel.
Multiplexing A procedure by which multiple lower order path layer signals are
adapted into a higher order path or the multiple higher order path layer
signals are adapted into a multiplex section.
NNI Network Node Interface. NNI identifies the interface between the ATM
network nodes. Compare SDH NNI.
Noise figure The specification to scale the random signal in the system presenting in
addition to any wanted signal.
NRZ Non Return to Zero. A digital code in which the signal level is low for
a 0 bit and high for a 1 bit and dose not return to 0 between successive
1 bits.
OADM Optical Add/Drop Multiplexer. A device that can be used to add the
optical signals of various wavelengths to one channel and drop the
optical signals of various wavelengths from one channel.
ODF Optical Distribution Frame. A frame which is used to transfer and spool
fibers.
Optical add/drop A process that add the optical signals of various wavelengths to one
multiplexing channel and drop the optical signals of various wavelengths from one
channel.
Optical interface A device to allow two or more corresponding optical transmitting units
to be connected.
Overhead Extra bits in a digital stream used to carry information besides traffic
signals. Orderwire, for example, would be considered overhead
information.
Packing case A case which is used for packing the board or subrack.
Paired Slots When SDH boards are used to configure the MSP ring, the two boards
forming a ring must be inserted in paired slots.
Path protection The working principle of path protection: When the system works in
path protection mode, the PDH path uses the dual-fed and signal
selection mode. Through the tributary unit and cross-connect unit, the
tributary signal is sent simultaneously to the east and west lines.
Meanwhile, the cross-connect matrix sends the signal dually sent from
the opposite end to the tributary board through the active and standby
buses, and the hardware of the tributary board automatically and
selectively receive the signal from the two groups of buses automatically
according to the AIS number of the lower order path.
Path A logical connection between the point at which a standard frame format
for the signal at the given rate is assembled, and the point at which the
standard frame format for the signal is disassembled.
PCR Peak Cell Rate. An upper limit on the rate at which cells can be submitted
on an ATM connection.
Plesiochronous A network with nodes timed by separate clock sources with almost the
same timing.
Pointer An indicator whose value defines the frame offset of a virtual container
with respect to the frame reference of the transport entity on which it is
supported.
Power unit A direct current power distribution unit at the upper part of a cabinet,
which supplies power for the subracks in the cabinet.
PRBS When there are cross-connections between a line board and a tributary/
data board, many alarms are raised on the tributary/data board if alarms
are raised on the line board. These alarms are all reported to the T2000.
Such a large number of alarms can disturb the troubleshooting and affect
the problem solution efficiency. Therefore, the inter-board alarm
suppression function is used to solve this problem.
Receiver overload Receiver overload is the maximum acceptable value of the received
average power at point R to achieve a 1 x 10-10 BER.
Reference clock A clock of very high stability and accuracy that may be completely
autonomous and whose frequency serves as a basis of comparison for
the frequency of other clocks.
Regeneration The process of receiving and reconstructing a digital signal so that the
amplitudes, waveforms and timing of its signal elements are constrained
within specified limits.
Revertive In revertive switching, there is a working and protection line, board and
switching so on. Services always revert back to the original working line or board
if the switch requests are terminated; that is, when the working line or
board has recovered from the fault or the external request is cleared.
Side mode The ratio of the largest peak of the total source spectrum to the second
suppression ratio largest peak.
Signal cable The cable which is used to transmit electrical signals, different from the
power cable or fiber.
Signal fail A signal indicating the associated data has failed in the sense that a near-
end defect condition (not being the degraded defect) is active.
SNCTP The SNCTP provides protection paths at the VC-4 level. When the
working path is faulty, all its services can be switched to the protection
path.
Span The set of SONET lines between two adjacent nodes on a ring.
TCM Tandem Connection Monitor. In the SDH transport hierarchy, the TCM
is located between the AU/TU management layer and HP/LP layer. It
uses the N1/N2 byte of POH overhead to monitor the quality of the
transport channels on a transmission section (TCM section).
Tray A discal component in the cabinet, which is used to place the chassis or
other equipment.
Tributary A fault location method. A fault can be located for each service path by
loopback performing loopback on each path of the tributary board. There are three
types of loopback modes: Non-loopback, Outloop and Inloop.
Upload To report all or part of the configuration data of the NE to the T2000
and overwrite the configuration data saved in the NE layer on the T2000.
Upper subrack The subrack close to the top of the cabinet when a cabinet contains
several subracks.
Virtual The payload whose transmission bandwidth is bigger than VC4. Virtual
concatenation concatenation combines multiple VC4 payloads (successive or non-
successive) to form a virtual large structure VC4-Xv in cascade mode
for transmission. The transmission of the broadband cascaded payload
is implemented via the virtual cascade, thus improving the SDH
transmission payload bandwidth capability from VC4 to VC4-4C.
VLAN Virtual local area network. A subset of the active topology of a Bridged
Local Area Network. Associated with each VLAN is a VLAN Identifier
(VID).
CC Continuity Check
DC Direct Current
FC Fiber Channel
FE Fast Ethernet
GE Gigabit Ethernet
LB LoopBack
NA Not available
PA Power Amplifier
RD Receive Data
SG Signaling Ground
TD Transmit Data
Index
T
TSB8
front panel, 8-44
function and feature, 8-43
principle and signal flow, 8-43
technical specification, 8-46
valid slot, 8-45
version, 8-43
U
UPM
function and feature, 13-2
principle and signal flow, 13-3
rear panel, 13-4
technical specifications, 13-6
valid slot, 13-6