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AND GATE

entity AND_Gate is --begin entity AND_GATE


Port ( a : in STD_LOGIC; --single bit input a
b : in STD_LOGIC; --single bit input b
c : out STD_LOGIC); --single bit output c
end AND_Gate; --end entity AND_GATE

architecture arch_and_gate of AND_Gate is

begin --begin the statement

c <= a and b; --statement

end arch_and_gate; --end of the architecture


2-1 MULTIPLEXER

entity mux is
Port ( a : in STD_LOGIC; --single bit input a
b : in STD_LOGIC; --single bit input a
c : out STD_LOGIC; --single bit output c
s : in STD_LOGIC); --single bit selection input s
end mux;

architecture Behavioral of mux is

begin --begin the statement

process (a,b,s) --the statement process
begin --begin the process
if s='0' then --if selection pin equal to 0
c <= a; --then output c get the input as value
elsif s='1' then --if selection pin equal to 1
c <= b; --then output c get the input bs value

end if; --end if statement
end process; --end the process

end Behavioral; --end the behavioral


4-1 MULTIPLXER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity multiplexer4_1 is
port (
i0 : in std_logic;
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
sel : in std_logic_vector(1 downto 0);
bitout : out std_logic
);
end multiplexer4_1;

architecture Behavioral of multiplexer4_1 is
begin

process(i0,i1,i2,i3,sel)
begin
case sel is
when "00" => bitout <= i0;
when "01" => bitout <= i1;
when "10" => bitout <= i2;
when others => bitout <= i3;
end case;
end process;

end Behavioral;


8- BIT AND GATE

entity and_gate_8bit is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0); --eight bit input a
b : in STD_LOGIC_VECTOR (7 downto 0); --eight bit input b
clock: in STD_LOGIC; --single bit clock
c : out STD_LOGIC_VECTOR (7 downto 0)); -- eight bit output c
end and_gate_8bit; --end entity 8 bit and

architecture arch_and_gate_8bit of and_gate_8bit is

begin --begin the statement

process (a,b,clock) --the statement process

begin --begin the process
if(clock ='1' and clock'event) then --if rising-edge set
c <= a and b; --then output c get a and b value
end if; --end if statement

end process; --end process
end arch_and_gate_8bit; --end of the architecture


8-BIT MULTIPLEXER

entity mux_8bit is
Port ( a_mux8bit : in STD_LOGIC_VECTOR (7 downto 0); --eight bit input a
b_mux8bit : in STD_LOGIC_VECTOR (7 downto 0); --eight bit input b
c_mux8bit : out STD_LOGIC_VECTOR (7 downto 0); --eight bit output c
s_mux8bit : in STD_LOGIC; --single bit selection
clock : in STD_LOGIC); --single bit clock
end mux_8bit;

architecture Behavioral of mux_8bit is

begin --begin the statement

process (a_mux8bit,b_mux8bit,s_mux8bit,clock) --the statement process

begin --begin the process
if(clock ='1' and clock'event) then --if rising-edge set
if s_mux8bit='0' then --if selection pin equal to 0
c_mux8bit <= a_mux8bit; --then output c get the input as value
elsif s_mux8bit='1' then --if selection pin equal to 1
c_mux8bit <= b_mux8bit; --then output c get the input bs value
end if; --end if statement
end if; --end if statement

end process; -- end process

end Behavioral; --end of behavioral


2-1 MULTIFLEXER (Using 8 bit AND Gate )

entity and_mux_8bit is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
c : out STD_LOGIC_VECTOR (7 downto 0);
d : out STD_LOGIC_VECTOR (7 downto 0));
end and_mux_8bit;

architecture Behavioral of and_mux_8bit is

component and_gate_8bit is --component instance of 8 bit Multiplexer
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
clock : in STD_LOGIC;
c : out STD_LOGIC_VECTOR (7 downto 0));
end component and_gate_8bit;

component mux_8bit is --component instance of 8 bit Multiplexer
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
b : in STD_LOGIC_VECTOR (7 downto 0);
c : out STD_LOGIC_VECTOR (7 downto 0);
s : in STD_LOGIC;
clock : in STD_LOGIC);
end component mux_8bit;

begin

end Behavioral;








8-BIT FULL ADDER












entity full_adder is --begin entity declaration
Port ( a_fulladder : in STD_LOGIC_VECTOR (7 downto 0); --eight bit input a
b_fulladder : in STD_LOGIC_VECTOR (7 downto 0); --eight bit input b
c_fulladder : in STD_LOGIC; -- single bit input c
cout_fulladder : out STD_LOGIC; -- single bit carry out
sum_fulladder : out STD_LOGIC_VECTOR (7 downto 0); --single bit output sum
clock : in STD_LOGIC); --single bit input clock

end full_adder; --end entity declaration

architecture Behavioral of full_adder is

begin --begin the statement
process (a_fulladder,b_fulladder,c_fulladder,clock) --begin the process statement
variable x,y: STD_LOGIC; --variables used inside the process construct
variable j: INTEGER; --variables can be defined only in this place
begin --begin the process
if (clock='1' and clock'event) then --if rising-edge set
x:=c_fulladder; --assign the value of var.c to var.x
for J in 0 to 7 loop --scan all elements of the array
sum_fulladder(j)<=a_fulladder(j)xor b_fulladder(j) xor x;
y:=((a_fulladder(j) xor b_fulladder(j)) and x) or (a_fulladder(j) and b_fulladder(j));
x:=y;
end loop;
cout_fulladder<=x;
end if; --end if statement
end process; --end process
end Behavioral; --end behavioral full adder


8-BIT INVERTER


entity inverter is --begin entity inverter
Port ( a_invert : in STD_LOGIC_VECTOR (7 downto 0); --8 bit input a
b_invert: out STD_LOGIC_VECTOR (7 downto 0); --8 bit output a
clock : in STD_LOGIC); --single bit input clock
end inverter;

architecture arch_inverter of inverter is
begin --begin the statement
process (a_invert, clock) --begin the process statement
begin --begin the process
if(clock='1' and clock'event) then --if rising- edge set
b_invert <= not a_invert; --get inverse of a to b
end if; --end if statement
end process; --end process
end arch_inverter; --end behavioral of inverter




ADD SUB PROGRAM















entity add_sub_unit is --begin entity
Port ( aa : in STD_LOGIC_VECTOR (7 downto 0); --8 bit input aa
bb : in STD_LOGIC_VECTOR (7 downto 0); --8 bit input bb
s : in STD_LOGIC; --single bit input s
clock : in STD_LOGIC; -- single bit input clock
sout : out STD_LOGIC_VECTOR (7 downto 0); --8 bit output sout
cout : out STD_LOGIC); --single bi output
end add_sub_unit; --end of entity add_sub

Architecture arch_add_sub_unit of add_sub_unit is

component inverter is --component instance of inverter
Port ( a_invert : in STD_LOGIC_VECTOR (7 downto 0);
b_invert: out STD_LOGIC_VECTOR (7 downto 0);
clock : in STD_LOGIC);
end component inverter;

component mux_8bit is --component instance of imultiplexer
Port ( a_mux8bit : in STD_LOGIC_VECTOR (7 downto 0);
b_mux8bit : in STD_LOGIC_VECTOR (7 downto 0);
c_mux8bit : out STD_LOGIC_VECTOR (7 downto 0);
s_mux8bit : in STD_LOGIC;
clock : in STD_LOGIC);
end component mux_8bit;

component full_adder is --component instance of full adder
Port ( a_fulladder : in STD_LOGIC_VECTOR (7 downto 0);
b_fulladder : in STD_LOGIC_VECTOR (7 downto 0);
c_fulladder : in STD_LOGIC;
cout_fulladder : out STD_LOGIC;
sum_fulladder : out STD_LOGIC_VECTOR (7 downto 0);
clock : in STD_LOGIC);
end component full_adder;

signal b1, b2: STD_LOGIC_VECTOR (7 downto 0); --declare internal signals used to connect component
--Signals can only be defined in this place before
--begin keyword
begin
invt : inverter --the inverter instantiation statement
Port map( a_invert => bb, --the input port a of inverter is connected to the signal bb
b_invert => b1, --the output port (b) of inverter is connected to the
Internal signal (b1) of add_sub_unit
clock => clock); --inverters clock is connected to the clock of add_sub_unit


mux : mux_8bit --the multiplexer instantiation statement
Port map( a_mux8bit => b1, --the input port a of multiplexer is connected to the
signal b1
b_mux8bit => bb, --the input port (b) of multiplexer is connected to the
Internal signal bb of add_sub_unit
c_mux8bit => b2, --the output port (c) of multiplexer is connected to the
Internal signal b2 of add_sub_unit
s_mux8bit => s, --the input selection pin (s) of multiplexer is connected to the selection pin
(s) of add_sub_unit
clock => clock); --the clock of the multiplexer is connected to the add_sub_unit clock

fulladder : full_adder --the adder instantiation statement
Port map( a_fulladder => aa, -- the input port a of adder is connected to the
signal aa
b_fulladder => b2, --the input port (b) of adder is connected to the
Internal signal b2 of add_sub_unit
c_fulladder => s, --the input port (c) of adder is connected to the
selection pin (s) of add_sub_unit
cout_fulladder => cout, --the cout of the adder is connected to the
cout of the add_sub_unit
sum_fulladder => sout, --the sum of the adder is connected to the
sout of the add_sub_unit
clock => clock); --the clock of the adder is connected to the clock of add_sub_unit

end arch_add_sub_unit; --end of the architecture












3 to 8 DECODER


entity dec3to8 is
port
(
-- inputs
signal sel: in std_logic_vector(2 downto 0); -- selector
signal en: in std_logic; -- enable

-- outputs
signal y: out std_logic_vector(7 downto 0) -- outputs are high true
);
end dec3to8;


architecture behavior of dec3to8 is
begin
process (sel,en)
begin

y <= "11111111";
if (en = '1') then
case sel is
when "000" => y(0) <= '1';
when "001" => y(1) <= '1';
when "010" => y(2) <= '1';
when "011" => y(3) <= '1';
when "100" => y(4) <= '1';
when "101" => y(5) <= '1';
when "110" => y(6) <= '1';
when "111" => y(7) <= '1';
when others => y(7) <= '1';
end case;
end if;
end process;
end behavior;


4 BIT COMPARATOR

entity comparator_4bit is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
equal : out STD_LOGIC;
greater : out STD_LOGIC;
lower : out STD_LOGIC
);
end comparator_4bit;

architecture comparator_4bit_arc of comparator_4bit is
begin

comparator : process (a,b) is
begin
if (a=b) then
equal <= '1';
greater <= '0';
lower <= '0';
elsif (a<b) then
equal <= '0';
greater <= '0';
lower <= '1';
else
equal <= '0';
greater <= '1';
lower <= '0';
end if;
end process comparator;

end comparator_4bit_arc;


8 BITS COMPARATOR

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- 8 Bit Unsigned Comparator
entity cmp8 is
port (
A,B : in std_logic_vector(7 downto 0);
aeqb, altb, agtb : out std_logic
);
end cmp8;

architecture a of cmp8 is

begin

aeqb <= '1' when (a = b) else '0';
altb <= '1' when (a < b) else '0';
agtb <= '1' when (a > b) else '0';

end;



HALF ADDER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------------------------------------
entity HalfAdder2 is
Port ( X : in std_logic;
Y : in std_logic;
SUM : out std_logic;
CARRY: out std_logic);
end HalfAdder2;
architecture HalfAdder2_arch of HalfAdder2 is
begin
process(X,Y)
begin
if(X/=Y) then
SUM<='1';
else
SUM<='0';
end if;
end process;
process(X,Y)
begin
if((X='1') and (Y='1')) then
CARRY<='1';
else
CARRY<='0';
end if;
end process;
end HalfAdder2_arch;