Sram

Anurag Engineering College
Department of ECE 1

1. INTRODUCTION
The semiconductor memory is generally classified according to the type of data
storage and data access. Read/Write memory must permit the modification of data bits
stored in the memory array, as well as their retrieval on demand. The read write
memory is commonly called Random Access Memory (RAM), mostly due to its
historical reasons. Unlike sequential access magnetic tapes, any cell can be accessed
with nearly equal access time. The stored data is volatile; i.e., the stored data is lost
when the power supply voltage is turned off. Based on the operation type of the
individual data storage cells, RAMs are classified into two main categories dynamic
rams and static rams. The dram cell consists of a capacitor to store binary information
1 or 0 and a transistor to access the capacitor. Cell information is degraded mostly due
to a junction leakage current at the storage node. Therefore, the cell data must be read
and rewritten periodically even when memory arrays are not accessed. On the other
hand the SRAM cell consists of a latch, therefore the cell data is kept as long as the
power is turned on and refresh operation is not required. Due to low cost and high
density, dram is widely used for main memory in personal and mainframe computers.
SRAM is mainly used for cache memory in microprocessors, main frames and
engineering workstations.
This project addresses the analysis and design of VLSI SRAM memories,
commonly known as semiconductor memories. Today, the memories are classified
into two main categories; Volatile memory such as SRAM etc., and Non-Volatile
memory such as PROM, EPROM, and EEPROM etc. In volatile memories the
memory content can be stored and can be retrieved as long as the power supply
voltage is ON and in Non-volatile memories (ROMs), only retrieval of previously
stored data is possible and it does not permit modification of the stored information
contents during normal operation, but the stored data is not lost even when the power
supply is OFF. Generally, the memory circuits come in different forms including
SRAM, DRAM, ROM, EPROM, E
2
PROM, Flash, and FRAM. While each form has a
different cell design, the basic structure, organization, and access mechanisms are
largely the same.
This project deals with design of low power static random-access memory
(RAM) cells and peripheral circuits for cache memory, focusing on stable operation
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and reduced read and write power .In this project, the focus is laid on the low power
design of the static RAM and reducing power consumption with addressing high-
speed issues under low voltages. As the technology shrinks (in Sub-micron
technologies), the power issue becomes very prominent due to high transistor density,
increased leakage currents and increase in interconnect parasitics. In spite of the
cropping up of power issues, the power consumption can be reduced by adopting
suitable techniques. The hierarchal bit line technique improves the speed of our
memory.
Static random-access memory (SRAM) continues to be a critical component
across a wide range of microelectronics applications from consumer wireless to high-
end workstation and microprocessor applications. For almost all fields of applications,
semiconductor memory has been a key enabling technology. It is forecasted that
embedded memory in SOC designs will cover up to 90% of the total chip area. A
representative example is the use of cache memory in microprocessors. The
operational speed could be significantly improved by the application of on-chip cache
memory that temporarily stored a fraction of the data and instruction content of the
main memory. Most of the microprocessors use large on-chip SRAM caches to bridge
the performance gap between the processor and the main memory. Due to their
growing embedded applications coupled with the technology scaling challenges,
considerable attention is given to the design of low-power and high-performance
SRAMs. However, there are many challenges in the design of both embedded and
stand-alone SRAMs, such as, the estimation and optimization of stand-by power, and
the design of high-speed peripheral circuits.
1.1 Types of Memory circuits
Within the category of read/write RAMs, many subdivisions have been
created to satisfy the performance and system architecture requirements of the various
applications. Basically there are two types of read/write RAMsdynamic and static
(DRAMs and SRAMs). The terms dynamic or static refer to the structure of the
actual storage circuit (the cell structure) used to hold each data bit within the memory
chip. In addition to static and dynamic RAMs, there is an attempt to combine both
technologies, thus merging the high storage density of dynamic memory cells with the
simplicity of use of static RAMs. Referred to as pseudo static or pseudo dynamic
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RAMs, these memories include circuits on the chip to automatically provide the
refresh signals needed by the dynamic cells in the memory array. Since the signals do
not have to be supplied by the external system, the memory appears to function like a
static RAM. There are many other forms of semiconductor memories in use-mask-
programmable read-only memories (ROMs), fuse-programmable read-only memories
(PROMs), ultraviolet-erasable programmable read-only memories (UV EPROMs),
electrically alterable read-only memories (EAROMs), electrically erasable
programmable read-only memories (EPROMs), flash EPROMs, non-volatile static
RAMs (NV SRAMs), and ferroelectric memories. Figure 1.1 shows the different
types of memories.

Figure 1.1 Types of Memory

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2. LITERATURE SURVEY
2.1 Static Random Access Memory (SRAM)
SRAM is a type of semiconductor memory consisting of CMOS transistors.
Unlike dynamic RAM (DRAM) which must be periodically refreshed, SRAM is
based on a bi-stable latch which will retain its value as long as the circuit is powered.
Each bit is made of 6 transistors, arranged as two cross-coupled inverters and two
access switches, as show in Figure 3 below. This bit has two stable states to represent
either a logic zero or a logic one. There are two additional transistors, labeled as
M5 and M6 in the figure below, which are known as access transistors since they
control the access to the storage cell during write and read operations.
Memories are said to be static if no periodic clock signals are required to
retain stored data indefinitely. Memory cells in these circuits have a direct path to
power supply or GND or both. Read-write memory cell arrays based on flip-flop
circuits are commonly referred to as Static RAM or SRAMs.
2.1.1 Merits of SRAM
Low power dissipation
Superior noise margin
High switching speeds suitable for high-density SRAM arrays.
The memory cells do not need to be refreshed.
SRAMs are faster than DRAMs because of the differential pair of bit-lines.
The operational modes of SRAMs are simpler because the row and column
address signals are simultaneously loaded.
2.1.2 Demerits of SRAM
Very expensive
Low density
On the other hand, static memories have the great disadvantage of a large
memory cell compared to dynamic memories. The main reason for this is that
resistive loads or load transistors must counteract the leakage currents flowing
through the cell. This increases the cell area. Therefore, their capacities are
normally smaller than those of dynamic RAMs.
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2.1.3 Challenges in SRAM
The following are the major challenges in the design of an efficient SRAM.
a) Power Consumption
In recently presented reduced-power processors, nearly half of the total
system power consumption is attributed to the memory circuits. Hence, reducing the
power dissipation in memories can significantly improve the system Power-
efficiency, performance, reliability and overall costs.
b) Read and Write Access Times
Memory applications require techniques for maximizing the access speeds of
static memories with minimal power consumption to optimize the overall system
performance. The performance of the address decoders, sense amplifiers and the
periphery I/O circuitry need to be simultaneously improved for achieving this goal.
c) Reliability
CMOS technology scaling trends, applications and operating conditions have
added both reliability and robustness as design metrics in addition to the traditional
metrics of power, speed, area and cost. Reliability is normally deals with the
immunity to hard failures such as electro migration, hot carrier effects, or dielectric
breakdowns.
2.1.4 Applications of SRAM
SRAM is used in personal computers, workstations, routers and peripheral
equipment, internal CPU caches and external burst mode SRAM caches, hard disks
buffers, router buffers, etc. LCD screens and printers also normally employ static
RAM to hold the image displayed or to be printed. Some SRAM buffers are
Also found in CDROM and CDRW drives; usually 256 KB or more are used
to buffer track data, which is transferred in blocks instead of as single values.
Many categories of industrial and scientific subsystems, automotive
electronics, and similar contains static RAM. Some amounts (kilobytes or less)
are also embedded in practically all modern appliances, toys, etc that
implements an electronic user interface. Several megabytes may be used in
complex products such as digital cameras, cell phones, synthesizers; etc.
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SRAM in its dual ported form is sometimes used for real-time digital signal
processing circuits.
The standalone SRAMs can be integrated as an external memory during board
design stage.
2.2 Architecture of SRAM
The preferred organization for Random Access Memory is shown in Fig 2.1.
This Organization is random-access architecture, which is an Asynchronous design.
The name is derived from the fact that memory locations (addresses) can be accessed
in random order at a fixed rate, independent of physical location, for reading or
writing. The storage array, or core, is made up of simple cell circuits arranged to share
connections in horizontal rows and vertical columns. The horizontal lines, which are
driven only from outside the storage array, are called word lines, while the vertical
lines, along which data flow into and out of cells, are called bit lines. A cell is
accessed for reading or writing by selecting its row and column.
Each Cell can store 0 or 1. Memories may simultaneously select 4, 8, 16, 32,
or 64 columns in one row depending on the application. The row and column (or
group of columns) to be selected is determined by decoding binary address
information. For example, consider a row decoder that has 2
n
out-put lines, a
different one of which is enabled for each different n-bit input codes. The column
decoder takes m inputs and produces 2
m
bit line access signals, of which any of them
can be enabled at one time. The bit selection is done using a multiplexer circuit to
direct the corresponding cell outputs to data registers. In total, 2
n
X 2
m
cells are
stored in the core array

Figure 2.1: Memory organizations
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2.2.1 Circuit design
A Schematic Editor is used for capturing (i .e. describing) the transistor-level
design of the gate. The Schematic Editors provide simple, intuitive means to draw, to
place and to connect individual components that make up the design. The resulting
schematic drawing must accurately describe the main electrical properties of all
components and their interconnections. Also included in the schematic are the supply
connections (V
dd
and Gnd), as well as all pins for the input and output signals of the
circuit. From the schematic, a net list is generated, which is used in later stages of the
design. The schematic design of single SRAM cell is shown below.

Figure 2.2: schematic of single SRAM
2.2.2 Working principle
The Data storage cell i.e., the 1-bit memory cell in static RAM arrays
invariably consists of simple latch circuit with two stable operating points (states).
Depending on the persevered state of the two-inverter latch circuit, the data being held
in the memory cell will be interpreted either as a logic 0 or as logic 1. To access
(read and write) the data contained in the memory cell via the bit line, we need at least
one switch, which is controlled by the corresponding word line, i.e., the row address
selection signal. Usually, two complementary bit lines (columns). This can be likened
to turning the car steering wheel with both left and right hands in complementary
directions.

Pass
transistor
Department of ECE 8

2.2.3 Operation of SRAM
SRAM memory cells are based on the latch Structure with two back-to-back
connected inverters & two pass transistors. Data can be written by driving WL high &
driving the lines BL & ~BL with data with complementary values. Because the bit
lines are driven with more force than the force with which the cell retains its
information (the transistors driving the lines BL & ~BL are more powerful, i.e. these
are larger than the NMOS of inverters), the cell will be forced to the state presented
on the lines BL & ~BL.

Figure 2.3: schematic of single SRAM cell when bit line bar is enabled

Figure 2.4: schematic of single SRAM cell when bit line is enabled

BL=0
BL_bar=1

BL=1
BL_bar=0

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2.3 Problem Definition
Static RAM plays a key role in modern devices as the technology advances
and the needs for high speed and performance of very deep sub-micron CMOS
designs are increasing. As the sizing of the SRAM is in nanometre scale the variations
in electrical parameters i.e., density of impurity concentration, oxide thickness and
diffusion depths have to maintain carefully. The conventional 6T memory cell
comprises of two CMOS inverters cross coupled with two pass transistors connected
to a complementary bit lines. The data retention of the SRAM cell in hold state and
the read state are important constraints in advanced CMOS processes.

2.3.1 Problem definition
Semiconductor memory arrays capable of storing large quantities of digital
information are essential to all digital systems. The amount of memory required in a
particular system depends on the type of application, but, in general, the number of
transistors for the information (data) storage function is much larger than the number
of transistors used for logic operations and other purposes. The ever-increasing
demand for larger data storage capacity has driven the fabrication technology and
memory development toward more compact design rule and, consequently, toward
higher data storage densities. Thus, the maximum realizable data storage capacity of
single-chip semiconductor memory arrays approximately doubles every two years.
On-chip memory has become widely used subsystems in many VLSI circuits, and
commercially available single-chip read/write memory capacity has reached one
gigabytes. This trend toward higher memory density and larger storage capacity will
continue to push the leading edge of digital system design.

In this project we are going to design SRAM has a nine transistor latch structure
to hold the state of each cell node. This SRAM design is going to be done in 45nm
technology where full custom layout design is done. The tool which we are going to
use is MICROWIND.

Department of ECE 10

3. EXISTING SYSTEM
In this chapter different types of SRAM cell operations are explained. They
are:
a) 6T SRAM Cell
b) 7T SRAM Cell
c) 8T SRAM Cell
d) 9T SRAM Cell
e) 11T SRAM Cell
3.1 Traditional 6T SRAM Cell

Figure 3.1: Schematic diagram of 6T SRAM cell
Single bit SRAM memory cell is shown in Figure 3.1. Static latches are used
in the SRAM cell. SRAM cell is made up of flip flop comprising of two cross coupled
inverters. Two access transistors are used to access the stored data in the cell. These
transistors are turned ON/OFF by the control line called word line(WL). Generally
this word line is connected to the output of row decoder circuits. When WL=V
DD
the
SRAM cell is connected to bit line(BL) and complement of bit line (BLbar) allowing
both read and write operations. Read-write operation is carried out by the help of
access transistors.
Read operation:
Consider node Y as reference node of the SRAM cell. Cell is said to be storing
1 if node Y is high at V
DD
and node Ybar is at 0V. For the reverse voltage conditions

cell is said to be storing zero. Let us assume that cell is storing 1.Before the read
operation starts BL and BLbar lines are precharged to V
DD
/2. When the WL is
activated the current flows through M5 and M6. Now current from V
DD
will flow
through M1 and M5 charging the bit line capacitance, say C
BL
. The existing
capacitance on the line BLbar, say C
BLbar
discharges through the transistors M6 and
M4. This process develops a voltage difference between node Y and node Ybar which
is sensed by the sense amplifier to detect it as 1. Similarly a 0 in the cell is also
detected by the sense amplifier.
Write operation:
Let us consider the write operation of zero to the cell which is storing a value
of 1. For this, sense amplifiers and precharge circuits are disabled. The cell is selected
by activating the corresponding WL signal. To write zero to the cell, BL line held low
and BLbar line is raised to V
DD
by the write circuit. Thus the node Ybar is pulled up
towards the V
DD
/2 while node Y is pulled down to V
DD
/2. When the voltage crosses
this level on two nodes, feedback action starts. Parasitic capacitances developed by
M3, M5 and M4, M6 are charged and discharged respectively. Ultimately node Y
stabilises at the value 1. Since these parasitic capacitances offered by transistors are
comparatively much lesser than the bit line capacitances, write operation is faster than
read operation.
3.1.1 Single Ended 6T SRAM cell:
The following circuit shows in the figure 3.2 is single ended 6T SRAM cell. In
this there are one bitline (BL) and one write word line (WWL) and two NMOS
transistors (M5 and M6) are known as pass transistors. These are used to transfer the
data from bitline to cell and from cell to bitline. Two invertors (INV1, INV2) are
connected in back to back configuration.


Figure 3.2: 6T Single ended SRAM
. The read and write operations are done as following steps .
If we operate single ended 6T SRAM cell, it uses 2 additional access transistors one
for write and another for read.
Write operation : <steps>
1. bit line is pre charged with the required value and
2. WWL is held high and
3. write access transistor(MWA) is off to weaken feedback
Reading operation : <steps>
1. RWL is held high
2. Read access transistor(MRA) is ON and
3. Reading is done through this access transistor and M6.
3.2 7T SRAM Cell
The circuit of 7T SRAM cell consists of two CMOS inverters that connected
to the cross coupled to each other with additional NMOS transistor which connected
to write line (W) and having two pass NMOS transistors connected to bit lines (BL)
and bitlines bar (BL_bar) respectively. Figure 3.2 shows circuit of 7T SRAM Cell,
where the access transistor N3 is connected to the word-line (WL) to perform the
access write and N4 is connected to the Read-line (R) to perform the read operations.
Bit-lines act as I/O nodes carrying the data from SRAM cells to a sense amplifier
during read operation, or from write in the memory cells during write operations.
The 7T SRAM cell depends on cutting off the feedback connection between the two

inverters, inv1 and inv2, before a write operation. The feedback connection and
disconnection is performed by an extra NMOS transistor N5 and the cell only depends
on BL _bar to perform a write operation.


Write Operation:
The write operation of 7T SRAM cell starts by turning N5 off this cut off the
feedback connection. BL bar carries complement of the input data, N3 is turned on,
while is N4 off as shown in Figure 3.2(a). These types of 7T SRAM cell looks like
two cascaded inverters connected in series, inv2 followed Fig. 5: 7T SRAM cell by
inv1, as shown in Figure 3.2(b). N3 transistor transfers the data from BL_ bar to
which drives inv2, P2 and N2, to develop Q, the cell data. Similarly, Q drives inv1, P1
and N1, to develop Q _bar which quals Q2 if data is 0 and lightly higher than Q2 if
data is 1. Then, Word Line is turned off and N5 is turned on to reconnect the
feedback connection between the two inverters to stably store the new data. Both bit
line (BL and BL_bar) are pre-charged high. By the use of proposed write scheme,
BL _bar is kept high to write 0 with negligible power consumption and careful
transistor sizing is essential to guarantee a stable write 0. To store 1 in the cell,
BL _bar is discharged to 0. To store a 0 in the cell, there is no need to discharge
bit line (BL _bar) and therefore, the activity factor of discharging bit line BL_bar is
less than 1 and depends on the percentage of writing 1.

Figure 3.3(a) 7T SRAM cell during write operation

Figure 3.3(b) Equivalent circuit of 7T SRAM cell during write operation
Read Operation:
In the read operation of 7T SRAM cell, both word line (WL) and read signal R are
turned on, while transistor N5 is kept on. When Q = 0, the read path consists of
transistor N2 and N4,

Figure 3.3(c): 7T SRAM cell during read operation


Figure 3.3(d): Equivalent circuit of 7T SRAM cell during read operation

As shown in Figure 3.2(c), and it behaves like a conventional 6T cell. When Q
= 1, the read path consists of transistor N1, N5 and N3, which represents a read
path as shown in Figure 3.2(d). In this, the three transistors are onnected in series,
which reduces the driving capability of the cell unless these transistors are carefully
sized.
3.2.1 Modified 7T SRAM cell
The following circuit shows in the figure 3.1 is 7T SRAM cell. In this there
are two bitlines (BL,BLB) and one word line(W) and two NMOS transistors (M1 and
M2) are known as pass transistors. These are used to transfer the data from bitline to
cell and from cell to bitline. Two invertors are connected in back to back
configuration. There is a separate bitline(BLR) to read the data, through the
transistor M7.During read and write operations we are considering two virtual
grounds to weak the feed back.

Figure 3.4: modified 7T SRAM cell

Write operation:
1. MW transistor is OFF
2. Pre charge BL and BLB
3. Make Word line ON.
Read operation:
MW and RWL is high and
1. Data is read through MR transistor.
2. It uses a separate Read BLR so it has better RSNM.

3.3 8T SRAM Cell
The following circuit shows in the figure 3.6 is 8T SRAM cell. In this there are three
bitlines (BL,BL,RBL) and one word line(WWL) and two NMOS transistors (M5 and
M6) are known as pass transistors. These are used to transfer the data from bitline to
cell and from cell to bitline. Two invertors(INV1,INV2) are connected in back to
back configuration.

Figure 3.5: 8T SRAM cell

Write operation:
Its write operation is same as 6T SRAM cell.


Read operation:
While reading data the following control signals have to be follows
RBL and RWL are useful in reading SRAM,
Keep RWL high and read RBL

3.4 9T SRAM Cell
The schematic of a 9T SRAM cell is shown in figure 3.4. A 9T SRAM cell
enhances data stability and reduces leakage power consumption. The upper sub-
circuit of the new memory cell is essentially a 6T SRAM cell with minimum sized
devices (composed of N1, N2, N3, N4, P1, and P2 with W=Wmin and L=Lmin). The
two write access transistors (N3 and N4) are controlled by a write signal (WR). The
data is stored within this upper memory sub-circuit. The lower sub-circuit of the new
cell is composed of the bit-line access transistors (N5 and N6) and the read access
transistor (N7). The operations of N5 and N6 are controlled by the data stored in the
cell. N7 is controlled by a separate read signal (RD).

Write operation:
During a write operation, WR signal transitions high while RD is maintained
low, as shown in figure 3. N7 is cutoff and the two write access transistors N3 and N4
are turned on. In order to write a 0 to Node1, BL and BLB are discharged and

charged, respectively. A 0 is forced into the SRAM cell through N3. Alternatively,
for writing a 0 to Node2, BL and BLB are charged and discharged, respectively. A
0 is forced onto Node2 through N4. During read operation, since N3 and N4 are
cutoff, the storage nodes Node1 and Node2 are completely isolated from the bit lines
as shown in figure 4. Unlike the 6T SRAM cell, the voltage of the node, which stores
0, is strictly maintained at the ground level during a read operation. The read
stability of the 9T SRAM cell is thereby enhanced as compared to a standard 6T
SRAM cell.

Figure 3.7: 9T SRAM Cell Write Operation
Read operation:
During a read operation, RD signal transitions high while WR is maintained
low, as illustrated in figure 3.6. The read access transistor N7 is activated. Provided
that Node1 stores 1, BL is discharged through N5 and N7. Alternatively, provided
that Node2 stores 1, the complementary bit line (BLB) is discharged through N6
and N7. Since N3 and N4 are cutoff, the storage nodes Node1 and Node2 are
completely isolated from the bit lines during a read operation.

Figure 3.8: 9T SRAM Cell Read Operation

3.4.1 Modified 9T SRAM CELL
The following circuit shows in the figure 3.7 is 9T SRAM cell. In this there are two
bitlines (WBL, WBLB) and one word line and two NMOS transistors (M1 and M2)
are known as pass transistors. These are used to transfer the data from bitline to cell
and from cell to bitline. Two invertors are connected in back to back configuration.
There is a separate bitline(BLR) to read the data, through the transistors M8,M7 and
M9.

Figure 3.9: modified 9T SRAM cell


The following are the read and write steps
Write operation:
Similar to 6T SRAM
Read operation:
By Controlling RWL throughM7,M8 and M9 we perform read operation

3.5 Proposed 9T SRAM Cell design

Figure 3.10: proposed 9T SRAM cell

Write operation:
The writing of data into cell is done as follows-
Step 1: M9 is switched off by making WR low (it weakens the feedback so we obtain
a faster write operation).
Step2: Bit lines BL and BLB are driven with the data.
Read operation:
The reading of data from the cell is done as follows-
Step1: WR is switched high (so that data at the nodes remains stable).

Step2: WL is kept low and RBL is pre charged high
Step3: Make RWL high to read Logic 0 on BL.

3.6 11T SRAM Cell
An 11T SRAM cell is shown in Figure 3.7. The implemented circuit consists
of 11 transistors instead of just 6 as in conventional SRAM cell. Due to lesser power
dissipation of the 11T SRAM cell, the area overhead of the cell can be tolerated. The
circuit consists of two cross coupled inverters along with an access transistor (N5)
which is controlled by the read word line (RWL) for read operation and two more
access transistors (N3 and N4) which are controlled by the write word line (WWL) for
write operation. The two other NMOS transistors, N6 and N8 are used during the read
operation to reduce power dissipation while NMOS transistors, N7 and N9 are used
during the write operation to reduce power dissipation of the cell. The two tail
transistors, N7 and N9 are controlled by the bit lines, BLB and BL, respectively while
the read operation uses a single bit line RBL.

Read Operation:
During the read operation there is no need to assert the WWL. For read
operation RWL is turned ON. Now, either read1 or read 0 operations can be
performed depending on the data stored at node B. The output of the read operation is

taken through the bit line RBL. In 11T SRAM cell, a lot of power is saved as no bit
line discharges during the read operation. The simplified model of the 11T SRAM cell
during the read operation is shown in Figure 3.7(a).

Figure 3.11(a). 11T SRAM cell read operation

Write Operation:
The write operation is performed using the write word line WWL and the read
word line RWL can be set to value zero. Depending on whether write 0 or write 1
operation is to be performed; appropriate value of bit lines BL and BLB is selected.
The simplified model of 11T SRAM cell during the write 0 and write 1
operations is shown below in Figure 3.7(b). In both the operations write 0 and write
1 neither BL and BLB is neither charging nor discharging, thats why a lot of
power is saved during write 1 and write 0 operations.

Figure 3.11(b). 11T SRAM Cell Write Operation

3.7 Power Dissipation & Reduction Techniqes
It is more convenient to talk about power dissipation of digital circuits at this
point. Although power depends greatly on the circuit style, it can be divided, in
general, into static and dynamic power. The static power is generated due to the DC
bias current, as is the case in transistor-transistor-logic (TTL), emitter-coupled logic
(ECL), and N-type MOS (NMOS) logic families, or due to leakage currents. In all of
the logic families except for the push-pull types such as CMOS, the static power tends
to dominate. That is the reason why CMOS is the most suitable circuit style for very
large scale integration (VLSI).
CMOS is the logic family preferred in many designs due to following reasons:-
(a) Impeccable noise margins.
(b) Perfect logic levels.
(c) Negligible static power dissipation.
(d) Gives good performance in most cases.
The power consumed when the CMOS circuit is in use can be decomposed into two
basic classes: static power and dynamic power.


3.7.1 Static Power
The static or steady state power dissipation of a circuit is expressed by the
following relation
P
stat
= I
stat
V
DD
..................................................................[Eq. 3.1]

Where, I
stat
is the current that flows through the circuit when there is no
switching activity. Ideally, CMOS circuits dissipate no static (DC) power since in the
steady state there is no direct path from V
DD
to ground as PMOS and NMOS
transistors are never on simultaneously. Of course, this scenario can never be realized
in practice since in reality the MOS transistor is not a perfect switch. Thus, there will
always be leakage currents and substrate injection currents, which will give to a static
component of CMOS power dissipation
Another form of static power dissipation occurs for the so-called Ratioed logic.
Pseudo-NMOS is an example of a Ratioed CMOS logic family. In this, the PMOS
pull-up is always on and acts as a load device for the NMOS pull-down network.
Therefore, when the gate output is in low-state, there is a direct path from V
DD
to
ground and the static currents flow. In this state, the exact value of the output voltage
depends on the ratio of the strength of PMOS and NMOS networks hence the name.
The static power consumed by these logic families can be considerable. For this
reason, logic families such as this, which experience static power consumption,
should be avoided for low-power design. With that in mind, the static component of
power consumption in low-power CMOS circuits should be negligible and the focus
shifts primarily to dynamic power consumption.

Figure 3.12: CMOS Inverter for Power Analysis

3.7.2 Dynamic Power
The dynamic component of power dissipation arises from the transient
switching behavior of the CMOS device. At some point during the switching
transient, both the NMOS and PMOS devices will be turned on. This occurs for gate
voltages between V
tn
and V
DD
- V
tp
. During this time, a short-circuit exists between
V
DD
and ground and the currents are allowed to flow. A detailed analysis of this
phenomenon by Veendrick reveals that with careful design of the transition edges,
this component can be kept below 10-15% of the total power ; this can be achieved by
keeping the rise and fall times of all the signals throughout the design within a fixed
range (preferably equal). Thus, although short circuit dissipation cannot always be
completely ignored, it is certainly not the dominant component of power dissipation
in well-designed CMOS circuits. Instead, dynamic dissipation due to capacitance
charging consumes most of the power. This component of dynamic power dissipation
is the result of charging and discharging of the parasitic capacitances in the circuit.
The situation is modeled in Figure 2.1, where the parasitic capacitances are lumped at
the output in the capacitor C. Consider the behavior of the circuit over one full cycle

of operation with the input voltage going from V
DD
to ground and back to V
DD
again.
As the input switches from high to low, the NMOS pull-down network is cut-off and
PMOS pull-up network is activated charging load capacitance C up to V
DD
. This
charging process draws energy equal to CV
DD
2
from the power supply. Half of this is
dissipated immediately in the PMOS transistors, while the other half is stored on the
load capacitance. Then, when the input returns to V
DD
, the process is reversed and the
capacitance is discharged, its energy being in the NMOS network. In summary, every
time a capacitive node switches from ground to V
DD
(and back to ground), energy of
CV
DD
2
is consumed.
This leads to the conclusion that CMOS power consumption depends on the
switching activity of the signals involved. We can define activity, as the expected
number of zero to one transition per data cycle. If this is coupled with the average
data rate, f, which may be the clock frequency in a synchronous system, then the
effective frequency of nodal charging is given the product of the activity and the data
rate: f. This leads to the following formulation for the average CMOS power
consumption:
.[Eq 3.2]
This classical result illustrates that the dynamic power is proportional to the switching
activity, capacitive loading and the square of the supply voltage. In CMOS circuits,
this component of power dissipation is by far the most important accounting for at
least 90% of the total power dissipation.
So, to reduce the power dissipation, the circuit designer can minimize the
switching event, decrease the node capacitance, reduce the voltage swing or apply a
combination of these methods. Yet, in all these cases, the energy drawn from the
power supply is used only once before being dissipated. To increase the energy
efficiency of the logic circuits, other measures can be introduced for recycling the
energy drawn from the power supply.
A novel class of logic circuits called ADIABATIC LOGIC offers the
possibility of further reducing the energy dissipated during the switching events and

the possibility of recycling or reusing some of the energy drawn from the power
supply. To accomplish this goal, the circuit topology and the operating principle have
to be modified, sometimes drastically. The amount of energy recycling achievable
using adiabatic techniques is also determined by the fabrication technology, switching
speed and the voltage swing.


4. PROPOSED SYSTEM
4.1 Energy dissipation reduction techniques
Power consumption is one of the basic parameters of any kind of integrated circuit
(IC). Power and performance are always traded off to meet the system requirements.
Power has a direct impact on the system cost. If an IC is consuming more power, then
a better cooling mechanism would be required to keep the circuit in normal
conditions. Otherwise, its performance is degraded and on continuous use it may be
permanently damaged. There are mainly two techniques in Power Dissipation
Reduction. They are
a) Sub Threshold Region
b) Adiabatic logic

4.1.2 Sub Threshold Region
To reduce the power dissipation the transistors can be operated in sub
threshold region. Generally transistors can operate above the cuttin (threshold)
voltage. But we can also operate the transistor just below the cuttin voltage by
adjusting the W/L ratios of the transistors. This scenario is known as Sub Threshold
Region.

4.1.2 Adiabatic logic
The word ADIABATIC comes from a Greek word that is used to describe
thermodynamic processes that exchange no energy with the environment and
therefore, no energy loss in the form of dissipated heat. In real-life computing, such
ideal process cannot be achieved because of the presence of dissipative elements like
resistances in a circuit. However, one can achieve very low energy dissipation by
slowing down the speed of operation and only switching transistors under certain
conditions. The signal energies stored in the circuit capacitances are recycled instead,
of being dissipated as heat. The adiabatic logic is also known as energy recovery
CMOS.

Adiabatic logic is a potential successor for static CMOS circuit design when it
comes to ultra-low-power energy consumption. Future development like the
evolutionary shrinking of the minimum feature size as well as revolutionary novel
transistor concepts will change the gate level savings gained by adiabatic logic. In
addition, the impact of worsening degradation effects has to be considered in the
design of adiabatic circuits. The impact of the technology trends on the figures of
merit of adiabatic logic, energy saving potential and optimum operating frequency,
are investigated, as well as degradation related issues. Adiabatic logic benefits from
future devices, is not susceptible to Hot Carrier Injection, and shows less impact of
Bias Temperature Instability than static CMOS circuits. Major interest also lies on the
efficient generation of the applied power-clock signal. This oscillating power supply
can be used to save energy in short idle times by disconnecting circuits. An efficient
way to generate the power-clock is by means of the synchronous 2N2P LC oscillator,
which is also robust with respect to pattern-induced capacitive variations. An easy to
implement but powerful power-clock gating supplement is proposed by gating the
synchronization signals. Diverse implementations to shut down the system are
presented and rated for their applicability and other aspects like energy reduction
capability and data retention.
Adiabatic computation has been widely studied as a low-power design
technique. In the recent years, several adiabatic or energy recovery logic architectures
have been proposed. They have achieved significant power savings compared to
conventional CMOS circuits. The outputs of these circuits are only valid during a
particular phase of the power clock cycle. Hence, multiple-phase clocking is required
to drive a chain of cascaded adiabatic logic circuits. The need for a multiple-phase
power clock not only increases the power dissipation of the clocking network, but also
it results in extra complexity of both the logic and the required power clock generator.
The 2N-2P and the 2N-ZN2P circuits, and the efficient charge recovery logic circuit
(EClZL) require four-phase clocking. The pass-transistor adiabatic logic (PAL)
requires two-phase clocking, which eliminates the path to ground and thereby
achieves higher power saving.
The methodology for designing adiabatic circuits in this paper has elements
that are different from the previous studies. First, the algebraic expressions and the
corresponding properties of power-clocked signals in adiabatic circuits are studies that

serve as the mathematical basis for designing adiabatic circuits. Then some adiabatic
gates with a physical restoration function are designed by converting the demand of
level-restoration in conventional CMOS gates into the demand of pulse-restoration
in adiabatic CMOS gates. All of the adiabatic gates proposed in this paper do not have
cross-coupled structure and the sequential characteristic, that is, the output and the
input signals will appear in the, same clock phase.
Considering that the basic circuits in adiabatic CMOS circuits are the gates,
the structure of the adiabatic gates and their working principles are investigated first.
Similar to the traditional CMOS gates, the adiabatic CMOS gates should also be of
physical-restoration. In traditional CMOS gates, the outputs are always clamped to
either the power supply by a conductive PMOS transistor for the high-level output or
the ground by a conductive nMOS transistor for the low-level output, whereby the
level-restoration is realized. Similarity, the outputs of the adiabatic CMOS gates
should also be 'clamped' to the power clock by a conductive MOS switch to obtain
'pulse-restored' outputs. Because of the alternating feature of the power clock, the
MOS switch used should be a complementary CMOS transmission gate.
Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier
Injection, and shows less impact of Bias Temperature Instability than static CMOS
circuits. Major interest also lies on the efficient generation of the applied power-clock
signal. This oscillating power supply can be used to save energy in short idle times by
disconnecting circuits. An efficient way to generate the power-clock is by means of
the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-
induced capacitive variations. An easy to implement but powerful power-clock gating
supplement is proposed by gating the synchronization signals. Diverse
implementations to shut down the system are presented and rated for their
applicability and other aspects like energy reduction capability and data retention.
Advantageous usage of adiabatic logic requires compact and efficient arithmetic
structures. A broad variety of adder structures and a Coordinate Rotation Digital
Computer are compared and rated according to energy consumption and area usage,
and the resulting energy saving potential against static CMOS proves the ultra-low-
power capability of adiabatic logic.


4.2 Adiabatic logic circuit level approach to low power VLSI design
The popularity of complementary MOS technology can be mainly attributed to
inherently lower power dissipation and high levels of integration. However, the
current trend towards ultra low-power has made researchers search for techniques to
recover/ recycle energy from the circuits. In the early days, researchers largely
focused on the possibility of having physical machines that consume almost zero
energy while computing and tried to find the lower bound of energy consumption. In
conventional level-restoring CMOS logic circuits with rail-to-rail output voltage
swing, each switching event causes an energy transfer from the power supply to the
output node or from the output node to the ground. During a 0-to-V
DD
transition of the
output, the total output charge Q = C
load
V
DD
is drawn from the power supply at a
constant voltage. Thus, an energy of E
supply
= C
load
V
DD
2
is drawn from the power
supply during this transition. Charging the output node capacitance to the voltage
level V
DD
means that at the end of the transition, the amount of stored energy in the
output node is E
stored
= C
load
V
DD
2
/ 2. Thus, half of the injected energy from the power
supply is dissipated in the PMOS network while only one half is delivered to the
output node. During a subsequent V
DD
-to- 0 transition of the output node, no charge is
drawn from the power supply and the energy stored in the load capacitance is
dissipated in the NMOS network.
To reduce the dissipation, the circuit designer can minimize the switching
events, decrease the node capacitance, reduce the voltage swing, or apply a
combination of these methods. Yet in all these cases, the energy drawn from the
power supply is used only once before being dissipated. To increase the energy
efficiency of the logic circuits, other measures can be introduced for recycling the
energy drawn from the power supply.
A novel class of logic circuits called adiabatic logic offers the possibility of
further reducing the energy dissipated during the switching events, and the possibility
of recycling, or reusing, some of the energy drawn from the power supply. To
accomplish this goal, the circuit topology and the operation principles have to be
modified, sometimes drastically. The amount of energy recycling achievable using

adiabatic techniques is also determined by the fabrication technology, switching
speed, and the voltage swing.

4.2.1 Principle of Adiabatic Switching
It should be noted that the fully adiabatic operation of the circuit is an ideal
condition which may only be approached asymptotically as the switching process is
slowed down. In most practical cases, the energy dissipation associated with a charge
transfer event is usually composed of an adiabatic component and a non-adiabatic
component. Therefore, reducing all the energy loss to zero may not possible,
regardless of the switching speed. With the adiabatic switching approach, the circuit
energies are conserved rather than dissipated as heat. Depending on the application
and the system requirements, this approach can sometimes be used to reduce the
power dissipation of the digital systems.

Figure 4.1 (a) Capacitor Charging


Figure 4.1(b). Circuit explaining Adiabatic Switching

Here, the load capacitance is charged by a constant-current source (instead of the
constant-voltage source as in the conventional CMOS circuits).
Here, R is the resistance of the PMOS network. A constant charging current
corresponds to a linear voltage ramp. Assume, the capacitor voltage V
C
is zero
initially.
The voltage across the switch = IR
P(t) in the switch = I
2
R
Energy during charge = (I
2
R) T
[Eq 4.1]
[Eq 4.2]
.[Eq 4.3]
where, the various terms of Equation [4.3] are described as follows:
E energy dissipated during charging,
Q charge being transferred to the load,
C value of the load capacitance,

R resistance of the MOS switch turned on,
V final value of the voltage at the load,
T time spent for charging
Now, a number of observations can be made based on Equation [4.3] as follows:
(i) The dissipated energy is smaller than for the conventional case, if the charging
time T is larger than 2RC. That is, the dissipated energy can be made
arbitrarily small by increasing the charging time,
(ii) Also, the dissipated energy is proportional to R, as opposed to the
conventional case, where the dissipation depends on the capacitance and
the voltage swing. Thus, reducing the on-resistance of the PMOS network
will reduce the energy dissipation.

4.2.2 A Simple Adiabatic Logic Gate
In the following, we will examine simple circuit configurations which can be
used for adiabatic switching. Figure 4.2(a) shows a general circuit topology for the
conventional CMOS gates and adiabatic counterparts. To convert a conventional
CMOS logic gate into an adiabatic gate, the pull-up and the pull-down networks must
be replaced with complementary transmission-gate (T-gate) networks.
The T-gate network implementing the pull-up function is used to drive the true
output of the adiabatic gate, while the T-gate network implementing the pull-down
function drives the complementary output node. Note that all the inputs should also be
available in complementary form. Both the networks in the adiabatic logic circuit are
used to charge-up as well as charge-down the output capacitance, which ensures that
the energy stored at the output node can be retrieved by the power supply, at the end
of each cycle. To allow adiabatic operation, the DC voltage source of the original
circuit must be replaced by a pulsed-power supply with the ramped voltage output.

Figure 4.2 (a): The general circuit topology of a conventional CMOS Logic Gate

Figure 4.2 (b): The topology of an Adiabatic Logic Gate implementing the same
function

4.2.3 Power Supplies for Adiabatic Circuits
The design of a power clock generator is an important part of the whole
adiabatic system design. Many studies on adiabatic logic design have been made and
various approaches have been proposed. All of them require extra circuitry for one or
more time- varying power sources to provide extended charging time. There are
methods such as those using either inductive power supplies, step-wise charging
through banks of capacitance tanks, or resonant drivers, etc.


4.2.4 Phases in an Adiabatic Power Supply
The constant-current source needed for the adiabatic operation is usually a
trapezoidal or, sinusoidal voltage source. In an adiabatic circuit, the power supply also
acts as a clock. Hence, it is given the term power clock. A single-phase sinusoidal
power-clock can easily be generated using resonant circuits.

Figure 4.3 Phases in an Adiabatic Power Supply
As shown in Figure 4.3 a trapezoidal voltage waveform acts as an adiabatic
power supply. The four phases of the clock are also shown initially, the adiabatic
supply is in the IDLE / WAIT phase and the supply voltage is LOW maintaining at
the same time the outputs in the LOW state. Then the inputs are set (one goes LOW
the other HIGH) and the supply voltage ramps-up. As the inputs are evaluated, the
outputs change complementary to each other and the one that goes HIGH follows the
power supply until it reaches V
DD
. At that moment the inputs are returned to the LOW
state and after a certain period of time in the HOLD 1 phase, the supply ramps
down with the outputs following until the LOW state is reached again. That is, to say,
during the IDLE/ WAIT phase, the circuit idles. In the EVALUATE phase, the load
capacitance either charges up or does not, depending upon the inputs to the functional
blocks. In the HOLD phase, the output is kept at steady, so that the subsequent stage
can evaluate. Finally, in the RECOVERY/ RESET phase, the charge held on the
capacitance is recovered.


5. DESIGN AND IMPLEMENTATION
5.1 Adiabatic charging
Considor a situation that using a time varying current I(t)

Figure 5.1: Adiabatic charging
The above ckt is used to model a cmos ckt with certain output resistance driving a
capacitive load. The capacitance is not havng any charge at time t=0. The voltage
across he capacitar as a function of time is given by:
V
C
(t) =
I(t) t .(5.1)
The avarage current from 0 to t is I(t) = t
.(5.2)
The energy dissipation in R from 0 to t (=T) is E
diss
= R
dt
= R
T
Write equation 2 in above equation
=

Abservations:
If T = 2RC then E
diss
=

It is equal to the energy dissipation in conventional cmos ckt.
If T >2RC then E
diss
<

Hence power dissipation decreases than the lower limit (
).
Here one question can rise that how we can make the T > 2RC. This can obtain by
applying time varying voltage as shown in figure.

Figure 5.2: Charging time comparisions
Here T
1
< T
2
< T
3

Since it is linear voltage, it is acts as a constant current source. Due to this constant
current source there is no effect on ckt. Thouse we can make T (>2RC) larger as our
requerement. By making T > 2RC we can reduse the energy loss for switching less
than the conventional cmos ckt energy loss.
There is another way to reduse the energy dissipation, that is decreases the recistance
value(R).
E
diss
=
......... (5.3)
Thuse by using adiabatic charging we can reduse the power by increasing T or by
decreasing R. the dissipation can be made arbitararily small by further extending the
charging time T.

5.2 Partially adiabatic circuit
The current adiabatic circuits can be classified as either partially adiabatic or
fully adiabatic. In the fully adiabatic circuit, all the charge on the load capacitance is
recovered by the power supply while in the partially adiabatic circuit, only some
charge is recovered. The examples of the fully adiabatic circuits are Pass Transistor
Adiabatic Logic (PAL) and Split Rail Charge Recovery Logic (SCRL). These types of
circuits however are difficult to implement due to complexity of synchronization
between cascading stages which limits its maximum operating speed. In contrast the
partial adiabatic circuits can be designed based on CMOS logic. The popular partially
adiabatic families include 2N- 2N2P, Efficient Charge Recovery Logic (ECRL),

Clock Adiabatic Logic (CAL), and True Single Phase Adiabatic Logic (TSEL). The
power supply for adiabatic operation is usually a trapezoidal or sinusoidal voltage
source. Although it is simple to implement and has a rather high operating frequency,
the voltage output low of 2N-2N2P is not equal to GND but a threshold of PMOS. We
proposed a partially adiabatic circuit based on 2N-2N2P structure which uses two
omplementary sinusoidal supply clocks. The circuit gives a full swing output while
still possesses the advantages of 2N-2N2P. As a result, energy saving are improved.

5.3 partially adiabatic circuits
The current adiabatic circuits can be classified as either partially adiabatic or
fully adiabatic. In the fully adiabatic circuit, all the charge on the load capacitance is
recovered by the power supply while in the partially adiabatic circuit, only some
charge is recovered. The examples of the fully adiabatic circuits are Pass Transistor
Adiabatic Logic (PAL) and Split Rail Charge Recovery Logic (SCRL). These types of
circuits however are difficult to implement due to complexity of synchronization
between cascading stages which limits its maximum operating speed. In contrast the
partial adiabatic circuits can be designed based on CMOS logic. The popular partially
adiabatic families include 2N- 2N2P, Efficient Charge Recovery Logic (ECRL),
Clock Adiabatic Logic (CAL), and True Single Phase Adiabatic Logic (TSEL). The
power supply for adiabatic operation is usually a trapezoidal or sinusoidal voltage
source. Although it is simple to implement and has a rather high operating frequency,
the voltage output low of 2N-2N2P is not equal to GND but a threshold of PMOS. We
proposed a partially adiabatic circuit based on 2N-2N2P structure which uses two
omplementary sinusoidal supply clocks. The circuit gives a full swing output while
still possesses the advantages of 2N-2N2P. As a result, energy saving are improved.

5.3.1 2N-2N2P adiabatic logic
The 2N-2N2P is a partially adiabatic circuit, as shown in figure.3. It uses a
pair of cross-coupled NMOS (MN1 and MN2) to obtain non-floating output. To
cascade 2N-2N2P circuits it needs four-phase ac-supply. Note that MP1, MP2 are
used for both charging the output node and return charge to the supply.

Figure 5.3: 2N-2N2P adiabatic logic
A variant of the ECRL logic family is 2N-2N2P family, the only difference is that 2N-
2N2P has a pair of cross-coupled NMOS transistors in addition to the cross-coupled
PMOS transistors common to both families as shown in figure 5.3 2N-2N2P thus has
cross-coupled full inverters and thus is very similar to a standard SRAM cell. The
timing and logical operation of 2N-2N2P is identical to that of 2N2P.

5.3.2 Positive Feedback Adiabatic Logic
The structure of PFAL logic is shown in gure 5.4. Two n-trees realize the logic
functions. This logic family also generates both positive and negativeoutputs. The two
major dierences with respect to ECRL are that the latch is made by two pMOSFETs
and two nMOSFETs, rather than by only two pMOSFETs as in ECRL, and that the
functional blocks are in parallel with the transmission pMOSFETs. Thus the
equivalent resistance is smaller when the capacitance needs to be charged.

Fgure 5.4: Positive Feedback Adiabatic Logic


5.3.3 ECRL-Efficient Charge Recovery Logic
Efficient Charge Recovery Logic (ECRL) proposed by Moon and Jeong,
shown in Figure 5.5, uses cross-coupled PMOS transistors. It has the structure similar
to Cascode Voltage Switch Logic (CVSL) with differential signaling. It consists of
two cross-coupled transistors M1 and M2 and two NMOS transistors. An AC power
supply pwr is used for ECRL gates, so as to recover and reuse the supplied energy.
Both out and /out are generated so that the power clock generator can always drive a
constant load capacitance independent of the input signal. A more detailed description
of ECRL can be found in. Full output swing is obtained because of the cross-coupled
PMOS transistors in both precharge and recovers phases.

Figure 5.5: The Basic Structure of the Adiabatic ECRL Logic


5.4 Proposed model
The proposed model of 9T SRAM Cell is designed by using Efficient Charge
Recovery Logic (ECRL) logic circuit. The proposed cell is shown below figure 5.6.
As shown in figure PMOS transistors are connected in back to back. Input and output
are two-railed signals. Inputs are given to NMOS transistor through the transmission
gate. It has two control inputs (RWL & WWL) for read and write.

Figure 5.6 prposed model of 9T SRAM design

Write 0:
The writing of the data zero (0) into cell is done as follows-
Give write word line (WWL) =1 and read word line (RWL) =0 then transistors
N3, N4 are goes to OFF and N5, N6 are goes to ON. The data zero is put on bit
line(BL) as low voltage(0), it is transfer to out node. Then this 0 is turns ON the
transistor P2 so, the node of comlement of true out will becomes high.

Write 1:
The writing of the data one (1) into cell is done as follows-
N3, N4 are going to OFF and N5, N6 are goes to ON. The data 1 is put on bit
line(BL) as high voltage(1), it is transfer to out node. Then this 1 is turns OFF the
transistor P2 then comlement node is disconnected power suplly. So the node
comlement of true out will become 0.

Read 0:
The reading of the data zero (0) from cell is done as follows-
N3, N4 are goes to ON and N5, N6 are goes to OFF. The data (0) stored on node out
will transfer on to the bitline (BL).

Read 1:
The reading of the data one (1) from cell is done as follows-
N3, N4 are goes to ON and N5, N6 are goes to OFF. The data (1) stored on node out
transfer to the bitline(BL).


6. RESULTS ANALYSIS
6.1 9T proposed layout and waveforms
The below figure shown the proposed 9T SRAM cell circuit diagram. It has
following input and control inputs WBL= word bitline, WBLB= word bitline bar,
WWL=write word line, RWL= read word line and RBL=read bit line.
Circuit diagram:

Figure 6.1: prposed 9T SRAM design

Layout:
The below figure shown the conventional 9T SRAM cell layout. The layout of
the proposed 9T SRAM is drawn in microwind tool i shown below figure. The design
of layout should follow some design rules. The design rools are given in appendix.
Input and control input values are have to give to get the proper simulation esults.


Figure 6.2: layout of proposed 9T SRAM cell circuit

Write operation from 1 to 0:
The writing value of zero(0) is shown below figure. By giving the proper inputs we
get the output 0 on node Q and 1 on node Q_bar.

Figure 6.3: Output of writng the value of 1 into cell


The output of write data, zero(1) is shown below figure. By giving the proper inputs
we get the output 1 on node Q and 0 on node Q_bar.


Read data 1:
The reading of the data value on the node Q is done by applying the propoer
controlling inputs we get the output Q=1 as shown in beloew figure.


Figure 6.5: Output of reading the value of 1 from cell

Read data 0:


Hold:
This is the second ohase of the pulsed power supply. In this state the output values of
the circuit remains as it is, whether it is zero or one. In this state the two output values
are in stable state. In the below figure the output on node Q is one is stable still the
next phase will come.

Figure 6.7: hold state of proposed 9T SRAM


6.2 9T base proposed with
/2
In this case we ar giving the power supply value of V
dd
/2 insted of V
dd
to reduce the
power dissipation. The writing value of zero(0) is shown below figure. The inputs and
control inputs are given as follows.





Read data 1:


Read data 0:


Hold:


Figure 6.12: hold state of proposed 9T SRAM with power supply as V
dd
/2

6.3 9T Proposed Method
Circuit Diagram:
This is the proposed model of 9T SRAM design. In this we are using thepartially
adiabatic logic and subthreshold power supply concepts. By using these two concepts
w canreduce the power dissipations and time delays while read and write operations.

Figure 6.13: proposed model of 9T SRAM design

Layout:
The layout of the 9T SRAM is drawn in microwind tool i shown below figure.
The design of layout should follow some design rules. The design rools are given in
appendix. Input and control input values are have to give to get the proper simulation
esults.

Figure 6.14: layout of proposed model of 9T SRAM cell circuit




The writing value of zero(0) is shown below figure. By giving the proper inputs we
get the output 0 on node Q and 1 on node Q_bar.


Read data 0:



Read data 1:


Hold:


Figure 6.19: hold state of proposed model of 9T SRAM

6.4 Delay and power Comparisons
While writing and reading of the data ino the memory cell, delay time and
power dissipation of various memory cells of proposed system have difeerent values.
These comparision of delay values is shown below table.
Delay comparisions:
Delay (nS) 6T 7T 9T 11T 9T-base 9T-base
with
Vdd/2
Proposed
adiabatic
SRAM
Twrite 0-1 0.10 0.08 0.09 0.10 0.11 0.25 0.03
Twrite 1-0 0.19 0.16 0.11 0.11 0.09 0.10 0.03
Tread1 0.10 0.09 0.12 0.10 0.09 0.29 0.04
Tread0 0.09 0.24 0.11 0.09 0.08 0.26 0.20
Table 6.1 Delay Comparison

Power Comparison Table
Power 6T 7T 9T 11T 9T-base 9T-base
with
Vdd/2
Proposed
adiabatic
SRAM
Pwrite
0-1
3.495u 3.144u 3.329u 7.340u 0.193m 91.93u 0.821n
Pwrite
1-0
4.166u 5.071u 2.071u 6.736u 0.317m 0.118m 0.767n
Pread1 4.121u 3.099u 4.450u 7.165u 0.228m 1.182u 1.813n
Pread0 3.465u 72.424u 4.930u 7.223u 0.597m 91.93u 1.231n
Phold 6.399u 3.162u 6.242u 9.379u 0.139m 91.93u 5.369n
Table 6.2 Power Comparison Table


7. CONCLUSION
The paper proposes a novel sub-threshold SRAM circuit along with the study
of various SRAM designs in the sub-threshold region at 45nm technology using
MICROWIND simulations and typical corner transistor models. Operating a SRAM
device in sub-threshold requires sufficient writing ability and good static noise margin
for the design. From the results we can see that successful designs perform better
reaults in sub-threshold SRAM proposed model. Thus proposed model of 9T SRAM
cell has the better results than existing systems.


8. FUTURESCOPE
In this proposed system design sub-threshold voltage and adiabatic logic
concepyts to decrease the time delays and energy dissipation. The adiabatic logic used
in this model is partially adiabatic logic. But in future by using fully adiabatic logic
the energy dissipations may be reduce to zero also but the circuit design goes to very
complex and circuit cost also increases.


9. REFERENCES
[1] Wang, A.; Chandrakasan, A.P.; Kosonocky, S.V.; , "Optimal supply and threshold
scaling for subthreshold CMOS circuits ," VLSI, 2002. Proceedings. IEEE Computer
Society Annual ymposium on, vol., no., pp.5-9,2002
[2] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A
Design Perspective, 2nd ed. Pearson Education, Inc., 2003.
[3] Aly, R.E.; Faisal, M.I.; Bayoumi, M.A.; , "Novel 7T sram cell for low power
cache design," SOC Conference, 2005. Proceedings. IEEE International , vol., no.,
pp.171-174, 19-23 Sept. 2005
[4] Calhoun, B.H.; Chandrakasan, A.;, "A 256kb Sub-threshold SRAM in 65nm
CMOS," Solid State Circuits Conference, 2006. ISSCC 2006. Digest of Technical
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APPENDIX
MICROWIND
Introduction to MICROWIND
MICROWIND is a CMOS circuit editor and simulation tool for layout-level
design, running on Microsoft Windows. It has been developed since 1998 through
several versions, and is available as a freeware for educational purpose. In short,
Microwind allows us to draw the masks of the circuit layout and perform analog
simulation.
Role of MICROWIND
It is a CMOS layout and simulation tool for deep submicron designs.
Microwind is used for the testing of layouts. Once tested, the layout is converted into
CIF format for full verification and final assembly of the test-chip. Microwind is also
significantly improved to handle the automatic conversion from Verilog to layout.
The diagram 5 shows the design flow of automatic conversion of verilog code to
layout.

Figure 5.1: Design flow showing conversion of verilog code to layout.


MICROWIND tools are very easy-to-use and truly affordable, with a powerful
range of features and industry-standard file formats. With tool popularity increasing
worldwide our tools proves itself that they are best and most reliable products for IC
design on PC.

MICROWIND Features
MICROWIND supports entire front-end to back-end design flow.
1. For front-end designing, we have DSCH (digital schematic editor) which
posses in-built pattern based simulator for digital circuits. User can also build analog
circuits and convert them into SPICE files and use 3
rd
party simulators like WinSpice
or pSPICE. DSCH can convert the digital circuits into Verilog file which can be
further synthesized for FPGA/CPLD devices of any vendor. The same Verilog file
can be compiled for layout conversion in MICROWIND.
2.The back-end design of circuits is supported by MICROWIND. User can
design digital circuits and compile here using Verilog file. MICROWIND
automatically generates an error free CMOS layout. Although this place-route is not
optimized enough as we do not indulge in omplex place & route algorithms. User can
also create CMOS layout of their own using compile one line Verilog syntax or
custom build the layouts by manual drawing. The CMOS layouts can be verified
using inbuilt mix-signal simulator and analyzed further for DRC, crosstalks, delays,
2D cross section, 3D veiw, etc.
Main Window Screen
The Microwind main screen, shown in Figure 5.2, includes two windows:
1. For the main menu and the layout display, and
2. For the icon menu and the layer palette.
The main layout window features a grid, scaled in lambda () units. The
Lambda unit is fixed to half of the minimum available lithography of the technology

in use, noted as L
min
. For example, the default technology is a CMOS 6-metal layers
65nm technology, consequently lambda is 0.035 m.
The key advantages of the lambda-based system:
1.The ability to simulate the same layout with several technology files.
2.The convenience of having to master only a single set of design rules
(minimum gate length 2 , minimum metal width 3 , etc.)

Figure 5.2: Main screen of micro wind
Micro wind posses many features like inbuilt design rule check,2D
view and 3D view to check the layout, transient analysis , eye diagram
simulation ,analog simulation e.t.c. In addition to this layout can be
automatically converted into CIF format and verilog code.


Design Flow Using MICRO WIND

Figure 5.3: Design flow using micro wind

Schematic editor tools like DSCH are used to write the schematic
of the circuit the schematic (verilog code) is then extracted and can be
converted into layout form using micro wind tool for layout level
simulation or can be directly simulated at the functional level using the
modelsim software. Verilog code can also be directly dumped into FPGA
and implemented. Micro wind is used for layout level simulation and the
layout can be converted into CIF format which is an intermediate format
that defines the set of rules for fabrication and then fabrication process
can be carried out.

MICRO WIND is used for layout level simulation
Using micro wind layout of SRAM is drawn and then it is simulated to verify
its function after testing the layout using microwind fabrication is carried and the
batch production of SRAM is carried out. Layout of SRAM can be tested and
analysed carefully using 3D and 2D views of the microwind tools. Design rules are in

built in this tool which automatically perform design rule check and hence facilitating
us to draw an optimized layout
The layout thus drawn can be simulated in many ways like
1. Transient analysis
2. Transfer curve analysis
3. Eye diagram

Design Rules

Select a Design Rule File
The software can handle various technologies. The process parameters are
stored in files with the appendix '.RUL'. The default technology corresponds to a
generic 8-metal 45-nm CMOS process. The default file is CMOS45n.RUL.

- To select a new foundry, click on File Select Foundry and choose the appropriate
technology in the list.

- To set a specific foundry as the default foundry, click File Properties , 'Set as
Default Technology'.


Figure 5.4 : illustration of design rules using the command Design Rules

Lambda Units
The MICROWIND software works is based on a lambda grid, not on a micro grid.
Consequently, the same layout may be simulated in any CMOS technology. The value
of lambda is half the minimum polysilicon gate length.

N-Well

r101 Minimum well size12
r102 Between wells12
r110 Minimum well area 144

Diffusion

r201 Minimum N+ and P+ diffusion width 4
r202 Between two P+ and N+ diffusions 4
r203 Extra nwell after P+ diffusion : 6
r204: Between N+ diffusion and nwell 6
r205 Border of well after N+ polarization 2
r206 Between N+ and P+ polarization 0
r207 Border of Nwell for P+ polarization 6
r210 Minimum diffusion area 24

Polysilicon/Metal Gate

Starting 45-nm, the polysilicon gate material has been replaced by metal such as NiSi.
We keep the name polysilicon for convenience.

r301 Polysilicon width 2

r302 Polysilicon gate on diffusion 2
r303 Polysilicon gate on diffusion for high voltage MOS 4
r304 Between two polysilicon boxes 3
r305 Polysilicon vs. other diffusion 2
r306 Diffusion after polysilicon 4
r307 Extra gate after polysilicon 3
r310 Minimum surface

2nd Polysilicon/Metal gate Design Rules
r311 Polysilicon2 width 2
r312 Polysilicon2 gate on diffusion 2
r320 Polysilicon2 minimum surface 8


MOS option

rOpt Border of option layer over diff N+ and diff P+ 7

Contact
r401 Contact width 2
r402 Between two contacts 5
r403 Extra diffusion over contact 2
r404 Extra poly over contact 2
r405 Extra metal over contact 2
r406 Distance between contact and poly gate 3
r407 Extra poly2 over contact 2

Metal 1

r501 Metal width 4
r502 Between two metals 4
r510 Minimum surface 16 2

Metal 2

r701 Metal width:: 4
r702 Between two metal 2 4
r710 Minimum surface 16 2


Metal 3

r901 Metal3 width: 4
r902 Between two metal3 : 4

Metal 4
rb01 Metal4 width: 4
rb02Between two metal4 : 4

Metal 5
rd01 Metal5 width: 8
rd02 Between two metal5 : 8

Metal 6
rf01 Metal6 width: 8

rf02 Between two metal6 : 15

Metal 7
rh0 Metal7 width: 8
rh02 Between two metal7 : 15

Metal 8
rj01 Metal8 width: 8
rj02 Between two metal8 : 15

Pads

The rules are presented below in m. In .RUL files, the rules are given in lambda. As
the pad size has an almost constant value in m, each technology gives its own value
in l.


rp01 Pad width: 50 m
rp02 Between two pads: 50 m
rp03 Opening in passivation v.s via : 5m
rp04 Opening in passivation v.s metals: 5m
rp05 Between pad and unrelated active
area :20 m
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